JP2005085237A - Card recognition system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a card recognition system provided with an improved converter which has a simple configuration and can efficiently transfer data. <P>SOLUTION: The card recognition system, in which a non-compliant card which does not comply with standard is provided with a computer, in order to recognize the non-compliant card, which comprises a card adapter for connecting the non-compliant card to a connector for a compliant card which complies with the standard, and a converter for allowing the computer to recognize the non-compliant card connected to the card adapter as a compliant card, the converter including a non-compliant card controlling part, having an I/O for the non-compliant card on the non-compliant card side, is characterized in that the converter has an interface which directly converts the data outputted from the non-compliant card control part to data of the compliant card for outputting the converted data to the computer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention provides, for example, card recognition for enabling a non-compliant card such as a smart card not compliant with the PCMCIA standard to be used in a computer having a connector for a compliant card (so-called PC card) compliant with the PCMCIA. More particularly, the present invention relates to an improvement of a converter portion provided in a card adapter or a computer in the card recognition system so that the non-compliant card can be used as a compliant card.

  For example, a non-compliant card such as a smart card that does not conform to the PCMCIA standard, for example, a smart card having an irregular connector other than the PCMCIA standard (hereinafter referred to as an irregular card or a non-PC card, if necessary) is assigned to the PCMCIA A card recognition system that can be used in a computer having a connector for a compliant card (hereinafter referred to as a standard card or a PC card if necessary) is an adapter for connecting the non-PC card to the PC card connector. And a converter for recognizing a non-PC card connected to the adapter to the computer as a PC card.

The adapter includes an active adapter and a passive adapter (see, for example, Patent Document 1 below).
JP 2001-75746 A

  The active adapter is an adapter incorporating the converter, and in a card recognition system using the active adapter, the computer does not need to have a special circuit for recognizing a non-PC card such as a smart card.

  On the other hand, the passive adapter only converts the arrangement of the signal pins of the smart card for the PC card inside, and does not include a converter. For this reason, in the card recognition system using the passive adapter, a detection unit that detects the connection of the passive adapter for the smart card in the computer and the connection when the passive adapter for the smart card is detected by the detection unit. It is necessary to provide a converter that converts data output from the smart card into data for a PC card.

  The present invention relates to an improvement of the converter. Hereinafter, a configuration and problems of a conventional converter will be described by taking a card recognition system using an active adapter as an example.

  FIG. 9 is a diagram showing the smart card 1 that is a non-PC card, and the computer 3 and the active adapter 10 that constitute the recognition system S3 of the smart card 1.

  The computer 3 includes a CPU 5, a memory 6, a hard disk 7, a PC card controller 8 for recognizing a PC card conforming to PCMCIA, and the PC card controller, which are attached to a chip set 4 having a PCI bus B1. PC card connector 2 connected to 8.

  The smart card active adapter 10 is provided between the contact connector 16 corresponding to the contact terminal surface 1a included in the smart card 1 and the female connector 10b corresponding to the male connector 2 for PC card included in the computer 3. A converter C2 is provided that converts data output from the smart card, which is a PC card, to PC card data and outputs the data to the computer.

  The converter C2 includes a PC card interface 11 that exchanges data with the PC card controller 8 via the connector 2, a CPU 12, RAM 13, ROM 14, and a smart card control unit that exchange data with the interface 11 via the bus B2. 15.

  When the smart card 1 is inserted into the contact connector 16 for smart card, the smart card control unit 15 detects this and transmits it to the CPU 12. The CPU 12 outputs information from the smart card 1 to the PC card controller 8 of the computer 3 via the PC card interface 11.

  The flow of data from the smart card 1 to the computer 3 is as follows. Data from the smart card 1 is temporarily stored in a FIFO 15 a built in the smart card control unit 15. The FIFO 15a functions as a so-called buffer memory that absorbs the difference in data processing speed between the smart card 1 and the PC card. When detecting that the data is stored in the FIFO 15a, the CPU 12 reads the data stored from the FIFO 15a and stores it in the working RAM 13. The CPU 12 informs the PC card controller 8 of the computer 3 that there is data received from the smart card 1 using the interrupt signal to the PC card controller 8 of the computer 3 via the PC card interface 11 and the connector 2, and then executes the RAM 13 in the same procedure. Is output to the PC card controller 8.

  The data stored in the RAM 13 is temporarily stored in the register 11 a built in the PC card interface 11 and then output.

  On the other hand, the data flow from the computer 3 to the smart card 1 is as follows. The host CPU 5 in the computer 3 outputs the data stored in the memory 6 to the connector 2 via the chip set 4, PCI bus B 1, and PC card controller 8. The PC card interface 11 that has received the data via the connector 2 temporarily stores the transmission data in the built-in register 11a. When the CPU 12 detects that the transmission data is stored in the register 11a, the PC 12 receives the transmission data. Data is written into the working RAM 13 via the bus B2. The CPU 12 writes the data written in the RAM 13 to the FIFO 15 a built in the smart card control unit 15. The smart card control unit 15 outputs the data written in the FIFO 15 a to the smart card 1 via the contact connector 16. Note that all the programs executed by the CPU 12 are built in the flash ROM 14.

  The converter C2 included in the conventional smart card active card 10 includes a CPU 12, a work RAM 13, and a flash ROM 14 in order to exchange data between the PC card interface 11 and the smart card control unit 15. There was a problem that the circuit scale was large.

  As described above, the data output from the smart card is stored in the FIFO 15a of the smart card control unit 15, the working RAM 13, and the register 11a of the PC card interface 11 in order in the converter C2. Are output to the computer 3. For this reason, the data transmission efficiency was poor.

  Further, since the flash ROM 14 constituting the converter C2 is manufactured by a process different from a normal CMOS, there is a problem that the number of manufacturing processes is increased and the cost is increased. This is the same even when an EEPROM is used instead of the flash ROM.

  The present invention is provided with an improved converter that eliminates the need for the CPU 12, RAM 13, and ROM 14 from the converter C2, has a simple configuration, for example, a configuration that can be easily made into one chip, and can efficiently transmit data. An object is to provide a card recognition system.

  A first card recognition system according to the present invention includes a non-compliant card that does not comply with a standard, a computer that includes a card controller that performs data transmission and reception with a compliant card that conforms to the standard, and the non-compliant card. In a card recognition system having an adapter for connecting to the computer and recognizing the non-compliant card as a compliant card, the non-compliant card data is converted to the compliant card data between the card controller and the non-compliant card. In order to convert, the non-compliant card control unit having non-compliant card I / O, and the non-compliant card control unit connected to the non-compliant card control unit through a dedicated transmission line and having a non-compliant card I / O interface. It is characterized by that.

  According to a second card recognition system of the present invention, in the first card recognition system, the number of bits of data output from the non-compliant card control unit is set to the non-compliant card control unit or the interface. A circuit for converting the number of bits into the number of bits is provided.

  According to a third card recognition system of the present invention, in any one of the card recognition systems, the non-compliant card control unit has a timing control unit that uniquely performs timing control of signal output in response to a request from a computer. It is characterized by.

  According to a fourth card recognition system of the present invention, in any one of the above card recognition systems, the non-compliant card control unit includes a buffer memory that is equal to or larger than a maximum amount of data output per unit from the non-compliant card. Features.

  According to a fifth card recognition system of the present invention, in any one of the above card recognition systems, the standard is PCMCIA, and the non-compliant card is a smart card.

  According to a sixth card recognition system of the present invention, in any one of the above card recognition systems, the card adapter is an active card adapter incorporating the non-compliant card control unit and the interface.

  According to a seventh card recognition system of the present invention, in the first to fifth card recognition systems, the card adapter is a passive card adapter, and the controller includes a non-compliant card control unit and an interface. .

  An eighth card recognition system of the present invention is a computer including a deformed card having a connector different in shape from a standard card connector provided in the computer, and a card controller for sending and receiving data to and from the standard card; In a card recognition system having an adapter for connecting the irregular card to the computer and recognizing the irregular card as a standard card, the irregular card data is transferred between the irregular card and the card controller. For the conversion to the card, the card control unit having a card I / O for the card, and the interface having the I / O for the standard card connected to the card control unit through a dedicated transmission line. And

  According to a ninth card recognition system of the present invention, in the eighth card recognition system, the number of bits of data output from the variant card control unit to the variant card control unit or the interface is set to the data of the standard card. A circuit for converting the number of bits is provided.

  According to a tenth card recognition system of the present invention, in the eighth or ninth card recognition system, the odd-shaped card control unit includes a timing control unit that independently performs timing control of signal output in response to a request from a computer. It is characterized by having.

  According to an eleventh card recognition system of the present invention, in the eighth to tenth card recognition systems, the odd-shaped card control unit has a buffer memory that is equal to or more than a maximum amount of data output from the odd-numbered card per unit. It is characterized by.

  According to a twelfth card recognition system of the present invention, in the eighth to eleventh card recognition systems, the standard card is a PC card conforming to PCMCIA, and the deformed card is a smart card.

  A thirteenth card recognition system according to the present invention is characterized in that, in the eighth to twelfth card recognition systems, the card adapter is an active card adapter incorporating the odd-shaped card control unit and an interface.

  According to a fourteenth card recognition system of the present invention, in the eighth to twelfth card recognition systems, the card adapter is a passive card adapter, and the controller includes a deformed card control unit and an interface.

  According to a fifteenth card recognition system of the present invention, a non-compliant card that does not comply with a standard, a computer that includes a card controller that performs data transmission and reception with a compliant card that conforms to the standard, and the non-compliant card. In a card recognition system that has an adapter for connecting to the computer and recognizes a non-compliant card that does not comply with the standard, the data of the non-compliant card is transferred between the card controller and the non-compliant card. (Data format such as serial / parallel, data bit number, etc.) including data conversion unit for converting to compliant card data, card interface for outputting output of data conversion unit to computer, and data conversion unit Dedicated to exchange data directly with the card interface Characterized by comprising a sending passage.

  According to a sixteenth card recognition system of the present invention, in the fifteenth card recognition system, the data conversion unit includes a timing control unit that uniquely controls timing of signal output in response to a request from a computer. And

  According to a seventeenth card recognition system of the present invention, in the fifteenth to sixteenth card recognition systems, the data conversion unit has a buffer memory equal to or more than a maximum amount of data output per unit from a non-compliant card. It is characterized by.

  According to an eighteenth card recognition system of the present invention, in the fifteenth to seventeenth card recognition systems, the standard is PCMCIA, and the non-compliant card is a smart card.

  According to a nineteenth card recognition system of the present invention, in the fifteenth to eighteenth card recognition systems, the card adapter is an active card adapter incorporating the data converter and a card interface.

  According to a twentieth card recognition system of the present invention, in the fifteenth to eighteenth card recognition systems, the card adapter is a passive card adapter, and includes a data conversion unit and a card interface in the controller.

  In the first card recognition system of the present invention, by adopting a configuration in which a non-compliant card control unit and an interface are connected by a dedicated transmission path, the non-compliant card control unit and interface are connected to a CPU, ROM, The circuit scale can be reduced as compared with the case of connection via a bus that is also connected to the RAM.

  In the second card recognition system of the present invention, since the types of registers that cause data processing delays are completely removed, the non-compliant card control unit and the interface are connected via a bus connected to the CPU, ROM, and RAM. In addition to the effects obtained when the CPU realizes the contents realized by the software with a dedicated circuit, the processing speed is further increased and the size is reduced by eliminating the registers. be able to.

  In addition, the flash ROM (which is the same in the case of EEPROM) is unnecessary compared to the case where the non-compliant card control unit and the interface are connected via a bus connected to the CPU, ROM, and RAM. It is possible to manufacture together with other processing units, and the manufacturing efficiency can be improved.

  In the third card recognition system of the present invention, by providing a timing control unit that operates independently, it is possible to always perform accurate timing control regarding signal output regardless of the processing speed and operating state of the computer.

  In the fourth card recognition system of the present invention, the buffer memory having the maximum amount of data output per unit time from the non-compliant card is provided, so that the buffer overflow or the like can be performed regardless of the processing speed or operating state of the computer. Trouble can be prevented.

  In the fifth card recognition system of the present invention, a smart card that does not conform to PCMCIA can be recognized as a PC card by a converter having a simple configuration.

  In the sixth card recognition system of the present invention, a smart card that does not comply with PCMCIA does not use a CPU, ROM, and RAM, and an active device incorporating a non-compliant card control unit and an interface connected to each other via a dedicated transmission line. By using a type adapter, it can be recognized as a PC card.

  The seventh card recognition system of the present invention is based on PCMCIA by providing a non-compliant card control unit and an interface connected to each other via a dedicated transmission path without using a CPU, ROM, or RAM on the computer side. A smart card that is not used can be recognized as a PC card by using a simple and small passive adapter.

  In the eighth card recognition system of the present invention, by adopting a configuration in which the control unit and the interface of the odd-shaped card are connected by a dedicated transmission path, the control unit and the interface of the odd-shaped card are connected to the CPU, ROM, and RAM. In addition, the circuit scale can be reduced as compared with the case of connecting via a connected bus.

  In the ninth card recognition system of the present invention, since the types of registers that cause delays in data processing are completely removed, the irregular card control unit and the interface are connected via a bus that is also connected to the CPU, ROM, and RAM. In addition to the effects obtained when the CPU realizes the contents realized by the software with a dedicated circuit, the processing is further speeded up and the size is reduced by eliminating the registers. Can do.

  In addition, the flash ROM (which is the same in the case of the EEPROM) is unnecessary compared to the case where the odd-shaped card control unit and the interface are connected via a bus connected to the CPU, ROM, and RAM. It becomes possible to manufacture together with other processing units, and the manufacturing efficiency can be improved.

  In the tenth card recognition system of the present invention, by providing a timing control unit that operates independently, it is possible to always perform accurate timing control regarding signal output regardless of the processing speed and operation state of the computer.

  In the eleventh card recognition system of the present invention, having a buffer memory exceeding the maximum amount of data output per unit time from the irregular-shaped card, troubles such as buffer overflow can be achieved regardless of the processing speed and operating state of the computer. Occurrence can be prevented.

  In the twelfth card recognition system of the present invention, a smart card having a connector different from a connector conforming to PCMCIA can be recognized as a PC card by a simple converter.

  In the thirteenth card recognition system of the present invention, a smart card that is not compliant with PCMCIA does not use a CPU, ROM, RAM, and is an active type that incorporates an odd-shaped card controller and an interface connected to each other via a dedicated transmission line. By using the adapter, it can be recognized as a PC card.

  In the fourteenth card recognition system of the present invention, the computer side does not use a CPU, a ROM, and a RAM, and is provided with a deformed card control unit and an interface connected to each other through a dedicated transmission line, thereby complying with PCMCIA. A smart card can be recognized as a PC card by using a simple and small passive adapter.

  In the fifteenth card recognition system of the present invention, a data conversion unit that converts data of a non-compliant card into data of a compliant card including data standards (a non-compliant card control unit in the second card recognition system, And a circuit that converts the number of bits of data output from the control unit to the number of bits of data of the compliant card) and a configuration in which the card interface is connected by a dedicated transmission line. Thus, the circuit scale can be reduced as compared with the case where the data conversion unit and the card interface are connected via a bus that is also connected to the CPU, ROM, and RAM. The data standard includes serial / parallel conversion, data bit number conversion, and the like.

  In addition, since registers that cause data processing delays have been completely removed, the CPU is realized by software when the data converter and card interface are connected via a bus that is also connected to the CPU, ROM, and RAM. In addition to the effects obtained when the contents are realized by a dedicated circuit, the processing can be further speeded up and the size can be reduced by eliminating registers.

  Also, compared to the case where the data conversion unit and the card interface are connected via a bus that is also connected to the CPU, ROM, and RAM, the flash ROM (which is the same in the case of the EEPROM) is eliminated. It becomes possible to manufacture together with other processing units, and the manufacturing efficiency can be improved.

  In the sixteenth card recognition system of the present invention, by providing a timing control unit that operates independently, accurate timing control can always be performed with respect to signal output regardless of the processing speed and operating state of the computer.

  In the seventeenth card recognition system of the present invention, the buffer memory having the maximum amount of data output per unit time from the non-compliant card has a buffer overflow or the like regardless of the processing speed or operating state of the computer. Trouble can be prevented.

  In the eighteenth card recognition system of the present invention, a smart card that does not comply with PCMCIA can be recognized as a PC card by a converter having a simple configuration.

  In the nineteenth card recognition system of the present invention, a smart card that does not conform to PCMCIA does not use a CPU, ROM, or RAM, and an active type that incorporates a data conversion unit and a card interface that are connected to each other via a dedicated transmission line. By using the adapter, it can be recognized as a PC card.

  In the twentieth card recognition system of the present invention, the computer side does not use a CPU, a ROM, and a RAM, and is provided with a data conversion unit and a card interface that are connected to each other through a dedicated transmission line, thereby complying with PCMCIA. A smart card can be recognized as a PC card by using a simple and small passive adapter.

(1) Embodiment 1
Embodiments of a card recognition system and a non-compliant card recognition method according to the present invention will be described below with reference to the accompanying drawings. In FIG. 1, an active adapter 50 constituting the card recognition system S1 of the first embodiment is not compliant with PCMCIA, for example, a non-compliant card having a connector with a different shape (hereinafter referred to as a modified card if necessary). 9 as a converter for recognizing a smart card that is a PCMCIA-compliant card (hereinafter referred to as a standard card or a PC card as required) as a smart card that is a PCMCIA-compliant card. The interface 11, CPU 12, RAM 13, and ROM 14 are removed from C2, and instead, a converter C1 having an improved PC card interface 51 is employed.

  Of the components of the converter C1, the same components as those of the conventional converter C2 described with reference to FIG. 9 are denoted by the same reference numerals. Hereinafter, after describing the overall configuration of the card recognition system S1, the configuration and operation of the converter C1 will be described in detail.

  The computer 3 includes a CPU 5, a memory 6, a hard disk 7, and a PC card controller 8 for recognizing a PC card (standard card) compliant with PCMCIA, which are attached to a chipset 4 having a PCI bus B1, and the above A PC card connector 2 connected to the PC card controller 8 is provided.

  An active adapter 50 for a smart card which is a variant card includes a contact connector 16 corresponding to the contact terminal surface 1a included in the smart card 1, and a female connector 10b corresponding to the male connector 2 for PC card included in the computer 3. Are provided with a converter C1 that converts data output from the smart card 1 into data for a PC card and outputs the data to the computer side.

  The converter C1 includes a smart card control unit 15 that is also provided in the conventional converter C2, and an improved PC card interface 51 that is connected to the smart card control unit 15 via a bus B2 that is a dedicated transmission path. It consists of.

  The smart card control unit 15 incorporates a FIFO 15a that functions as a so-called buffer memory that absorbs the difference in data processing speed between the smart card 1 and the PC card.

  The PC card interface 51 converts the data standard of the signal output from the smart card control unit 15 into that of the PC card and outputs it. The data standard usually includes the data format such as serial / parallel, the number of bits of the data, etc., but the PC card interface 51 uses a dedicated circuit (signal conversion unit) as will be described in detail later. 54) is used to adjust the number of bits of data.

  FIG. 2 is a diagram showing the configuration of the PC card interface 51. The PC card interface unit 51 is roughly composed of an interrupt signal converting inverter 52, an address decoder 53, and a signal converting unit 54. The address decoder 53 generates control signals SCCREN [0] to [7] used by the smart card control unit 15. The signal converter 54 converts the number of bits of the smart card data converted into the data for the PC card by the smart card control unit 15 into the number of bits of the data for the PC card.

  The interrupt signal converting inverter 52 inverts the high active interrupt signal SCCINT output from the smart card control unit 15 to the host CPU 5 of the computer 3 when the smart card 1 is connected, and outputs a low active signal RDY / INT. Output as #. Hereinafter, a signal with “#” at the end means that it is Low active.

  The address decoder 53 includes eight registers each assigned a predetermined address, and the value of 26-bit address data A [25: 0] sent from the computer 3 is assigned to the eight registers. If one of the registered addresses corresponds, one of the address data A [[] among the register enable signals SCCREN [0] to [7], which are control signals, is used to designate the address bus of the PC card bus. The signal of the register to which the value of “25: 0] is assigned is switched to the high level.

  FIG. 3 is a diagram showing the configuration of the address decoder 53. As shown in the figure, the address decoder 53 includes eight registers 53a to 53h for storing eight types of 26-bit data set in advance, and 26-bit data and address data stored in the registers 53a to 53h. An exclusive OR (EXOR) with A [25: 0] is obtained, and eight EXOR gates 53i to 53p that output the result as register enable signals SCCREN [0] to [7] are formed.

  The address decoder 53 configured as described above has register enable signals SCCREN [0] to [7] when there are data stored in the eight registers 53a to 53h that match the address data A [25: 0]. ], The corresponding one signal is switched to the High level and output.

Reference is again made to FIG. The signal conversion unit 54 includes two OR gates 55 and 56, eight bidirectional gates 57 [0] to 57 [7], and eight unidirectional gates 57 [8] to 57 [15]. Is done. Note that the eight bidirectional gates 57 [n] (where n is 0 to 7) are tri-state buffers 57 [n] that pass the bit data SCPUD [n] on the smart card side to the computer side with a low level signal input. In contrast, _A is connected in parallel with a tri-state buffer 57 [n] _B that passes the bit data D [n] on the computer side to the smart card side with a high level signal input.

  The eight one-way gates 57 [m] (where m is 8 to 15) are for the upper 8 bits of the 16-bit data D [15: 0] when a low level signal is input. This is a tri-state buffer that outputs "0" data to the computer side as the data of.

  The OR gate 55 is a low level write enable signal when both the write enable signal WE # and the chip enable signal CE # output from the PC card controller 8 of the computer 3 are switched to the low level in accordance with PCMCIA. Signal SCPURW # is output. When the signal WE # or CE # is switched to the high level, the OR gate 55 outputs a high level data read enable signal SCPURW #.

  The OR gate 56 includes eight bidirectional gates 57 [0] to 57 [7] and eight one-way signals when both the chip enable signal CE # and the output enable signal OE # are at a low level. A low level signal is output to the gates 57 [8] to 57 [15]. As a result, the 8-bit data SCPUD [7: 0] on the smart card side is converted to 16-bit data D [15: 0] and output to the computer 3 side.

  When the signal CE # or OE # is switched to the high level, the OR gate 56 converts the high level signal into the eight bidirectional gates 57 [0] to 57 [7] and the eight 1's. Output to the direction gates 57 [8] to 57 [15]. In this case, the upper 8 bits of the 16-bit data D [15: 0] from the computer 3 side are deleted and output to the smart card 1 side as 8-bit data SCPUD [7: 0].

  In the PC card interface 51 improved in this way, the function of the signal conversion unit 54 can efficiently exchange data between the smart card 1 and the computer 3 without using a register. Become.

  FIG. 4 is a diagram illustrating a configuration of the smart card control unit 15. The smart card control unit 15 includes an SCB control unit 20, a FIFO 15a, an RX / ATR control unit 22, a TX control unit 23, a card detection unit 24, and an I / O control unit 25. The smart card control unit 15 has the same configuration as that incorporated in the converter C2 of the active adapter 10 used in the conventional card recognition system shown in FIG. A brief description will be given of the fact that the signal output from the interface 51 is directly input to the smart card control unit 15 and processed.

  An SC_CD # signal indicating whether the smart card 1 is inserted into the contact connector 16 is input to the card detection unit 24. The card detection unit 24 notifies the SCB control unit 20 that a smart card has been detected when the SC_CD # signal is at a low level. Further, the card detection unit 24 outputs an SC_PWR signal that permits power supply to the smart card 1 to a power source (not shown).

  The I / O control unit 25 outputs a reset signal SC_RST of the smart card 1 in accordance with an instruction from the SCB control unit 20 as will be described later. The I / O control unit 25 exchanges the I / O signal SC_I / O and the clock signal SC_CLK with the smart card 1.

  The RX / ATR control unit 22 receives data from the I / O control unit 25 in 1-bit units, converts this into 8-bit data in parallel, and outputs the data to the FIFO 15a. The RX / ATR control unit 22 also specifies an initial ETU (bit transmission time) that specifies the number of clocks required to transmit 1-bit data according to the ATR (initial response information) received from the smart card 1 at the time of initial connection. To decide.

  The TX control unit 23 serially converts 8-bit data from the FIFO 15 a into 1-bit unit data, and then outputs the data to the I / O control unit 25. The TX control unit 23 is also connected to the control unit 20.

  The FIFO 15a, which functions as a so-called buffer memory that absorbs the difference in data processing speed between the smart card 1 and the PC card, has a total of eight FIFOs (for eight words) that can store 8-bit data. RX / ATR control The 8-bit data input from the unit 22 is output to a data bus (not shown) called SCBDB, or the 8-bit data input from the SCBDB and stored in one of the eight FIFOs is transmitted to the TX control unit. To 23. The SCBDB is also connected to the SCB control unit 20.

  As described above, in the card recognition system according to the first embodiment, the configuration of the converter provided in the active type adapter is greatly simplified, and the types of registers that cause data processing delay (the conventional type shown in FIG. 9). Since the working RAM 13 provided in the converter C2 and the register 11a) of the PC card interface 11 are completely removed, the contents realized by the CPU 12 in the conventional converter C2 shown in FIG. In addition to the effects obtained when implemented with a circuit, it is possible to further speed up the processing and reduce the size by eliminating the type of registers.

  Further, by removing the flash ROM (which is the same in the case of the EEPROM) from the conventional converter C2 shown in FIG. 9, it becomes possible to manufacture together with other processing units, and the manufacturing efficiency can be improved. .

(2) Embodiment 2
In the card recognition system S1 according to the first embodiment, the improved converter C1 is provided inside the active type adapter 50. However, the card recognition system of the present invention is not limited to the form using the active type adapter 50. You may employ | adopt the form using a passive type adapter. In this case, the improved converter C1 is used as a converter built in the computer.

  FIG. 5 is a diagram showing a configuration of the card identification system S2 using the passive adapter 80. As shown in FIG. The passive adapter 80 includes a contact connector 80a corresponding to the contact terminal surface 1a of the smart card 1 and a female connector 80b for a PC card, and internally converts the pin wiring of the smart card 1 to the corresponding PC card. It is well known.

  The computer 9 includes a CPU 5, a memory 6, a hard disk 7, and a PC card controller 70 for recognizing a PC card conforming to PCMCIA, which are attached to the chipset 4 including the PCI bus B 1, and the PC card controller 70. And the PC card connector 2 connected to the PC card.

  The configuration of the PC card controller 70 will be described below. The PC card detection unit 71 determines whether the card inserted into the connector 2 is a PC card conforming to PCMCIA or a smart card passive adapter 80.

  The multiplexer 74 performs bus switching based on the detection result of the PC card detection unit 71. When the card connected to the connector 2 is a PC card, the multiplexer 74 connects the PC card control unit 72 and the connector 2 to each other. When the card connected to 2 is the smart card passive adapter 80, the connector 2 and the converter C1 are connected.

  The converter C1 is connected to the PC card control unit 72. That is, when the connected card is the smart card passive adapter 80, the converter C1 is interposed between the connector 2 and the PC card control unit 72, and the data from the smart card 1 is converted to the PC card compliant with PCMCIA. Then, the converted data is output to the PC card control unit 72. The output of the PC card control unit 72 is transmitted to the chipset 4 via the PCI interface 73 and the PCI bus B1.

  The power switch 76 supplies the power supply voltage Vcc to the card connected via the connector 2 when a high level PWR signal or SC_PWR signal is output from the PC card control unit 72 or the converter C1.

  Also in the card recognition system using the passive adapter 80, by using the improved converter C1 in the computer 9, the circuit scale can be reduced and the data transmission efficiency in the converter can be improved.

(3) Improved example (Embodiment 3)
By providing the improved converter C1, it is possible to reduce the circuit scale by removing the CPU, the ROM, and the RAM that have conventionally formed the converter C2 as shown in FIG. The timing control relating to output is performed by the computer 3. When the host CPU 5 is a multi-task type that processes a plurality of tasks in parallel, when executing an application that requires high processing capacity (so-called heavy), or when executing a number of applications simultaneously, It becomes difficult to perform precise timing control. For example, it becomes difficult to perform timing control when reading and writing data and strict timing control such as a reset period. As a result, it is difficult to always satisfy the EMV standard that the reset period must be a period (about 10 ms to 11.25 ms) in which a clock signal having a frequency of about 4 MHz is cycled 40000 to 45000 times.

  Therefore, as an improved example (third embodiment) of the converter C1 used in the card recognition systems S1 and S2 of the first and second embodiments, as shown in FIG. 6, instead of the smart card control unit 15 constituting the converter C1. In addition, a smart card control unit 60 including an I / O control unit 62 incorporating a large capacity FIFO 61 as a buffer memory and a reset control unit 66 operating independently as a timing control unit was prepared. As a result, it is possible to reliably read and write data from the smart card 1, and it is possible to strictly control the reset period, specifically, to control the reset period that satisfies the EMV standard. Furthermore, it is possible to cope with various timing controls by changing the setting of the reset control unit 66 (setting value of a register 68 described later) from the host CPU 5.

  FIG. 6 is a diagram illustrating a configuration of the improved smart card control unit 60. The same components as the smart card control unit 15 are denoted by the same reference numerals. As described above, in the smart card control unit 60, compared to the smart card control unit 15, the FIFO 61 capable of holding a large number of words (260) and the I / O control unit incorporating the reset control unit 66. 62 is provided.

  First, the FIFO 61 capable of storing 260 words will be described. The FIFO 15a included in the smart card control unit 15 shown in FIG. 4 can hold 8-bit data for only 8 words. In the smart card protocol, up to 260 bytes of data are continuously transmitted and received as block data. For example, when the data reception speed of the host CPU 5 is lower than the data output speed from the smart card 1, the FIFO 15a overflows (so-called buffer overflow) and the received data cannot be read accurately. On the other hand, when the data receiving speed from the FIFO 15a of the smart card 1 is faster than the data writing speed from the host CPU 5 to the FIFO 15a, the data transmission to the smart card 1 is performed intermittently. 1 erroneously recognizes the amount of block data.

  Therefore, instead of the FIFO 15a, a large-capacity FIFO 61 that can store 8-bit data of 260 words, which is the maximum number of bytes that can be transferred from the smart card 1 at one time, is prepared, and writing of data to the FIFO 61 is completed. After that, it was possible to read or write data to the smart card 1 or the computer 9 to solve the above inconvenience.

  Subsequently, the I / O control unit 62 including the reset control unit 66 will be described. FIG. 7 is a diagram illustrating a configuration within the I / O control unit 62. The I / O control unit 62 is obtained by adding an AND gate 65 and a reset control unit 66 to the conventional I / O control unit 25 shown in FIG. Note that components not related to the reset control are omitted.

  A high level signal (for example, power supply voltage Vcc) is input to the data input terminal of the latch circuit 63. When the reset output enable signal SCRSTOE # switches to Low, the one-way gate (tri-state buffer) 64 is turned on and a High level signal output from the latch circuit 63 is output to the smart card 1 as the reset signal SC_RST. The The reset clear signal SCRSTCLR # is input to the timing signal input terminal of the flip-flop 63, and switches the output of the flip-flop 63 after reset to the high level again.

  The reset control unit 66 holds a 16-bit counter 67 that starts counting in response to an input of a low-level signal ACTEND # that means the end of the activation process output from the SCB control unit, and a 16-bit count value. And a comparator 69 that compares the count value output from the counter 67 with the count value held in the register 68 and outputs a low-level reset end signal RSTEND when they match. .

  When the reset control unit 66 configured as described above receives a signal ACTEND # indicating the end of the activation process from the host CPU 5, it counts a preset number of clocks (for example, 41000) and then ends the reset period. A level reset end signal RSTEND is output.

  The reset end signal RSTEND output from the comparator 69 of the reset control unit 66 is input to one signal input terminal of the 2-input AND gate 65. The remaining signal input terminal of the AND gate 65 receives the reset set signal SCRSSET # that has been input to the I / O control unit.

  In the above configuration, the AND gate 65 sets the reset signal to the low level when one of the reset set signal SCRSSET # and the reset end signal RSTEND, which has been conventionally input to the I / O control unit, becomes low. The held latch circuit 63 is reset.

  Note that the setting value of the 16-bit register 68 of the reset control unit 66 can be changed from the host CPU 5 so as to satisfy a reset period of 40000 clocks or less according to a standard other than the EMV standard, for example, ISO 7816. be able to.

  FIG. 8 is a time chart showing an activation process and a reset period that are first executed by the smart card control unit 60 when the smart card 1 is connected. The card detection unit 24 detects that the smart card 1 has been inserted into the contact connector 16 (contact connector 80a in the case of the passive adapter 80) before the timing T1 by switching the SC_DC # signal to the low level, This is notified to the SCB control unit 20. The SCB control unit 20 outputs a high level interrupt signal SCCINT to the host CPU 5. The interrupt signal SCCINT is inverted in the PC card interface unit 51 and then sent to the PC card controller 8, the chipset 4, and the host CPU 5 as the PC card interrupt signal RDY / INT #.

  Receiving the low level interrupt signal RDY / INT #, the host CPU 5 executes the activation process according to the following procedure in order to start communication with the smart card 1. First, at timing T1, the host CPU 5 controls the SC_RST, SC_CLK, and SC_I by controlling the I / O control unit 62 via the PC card interface 51 and the SCB control unit 20 in the smart card control unit 15. The / O terminal is switched from the high impedance state to the low level.

  Since a pull-up resistor required by the standard is connected between the smart card control unit 15 and the smart card 1, SC_I / O is at a high level even in a high impedance state.

  At the timing T2, the host CPU 5 controls the card detection unit 24 via the PC card interface 51 and the SCB control unit 20 in the smart card control unit 15, and switches the SC_PWR terminal to the high level for the card. The power switch (see switch 76 in FIG. 5) is turned on, and power supply to the SC_VCC terminal is started.

  At timing T3, the host CPU 5 controls the I / O control unit 62 via the PC card interface 51 and the SCB control unit 20 in the smart card control unit 15, and sets the SC_I / O terminal to the high impedance state. Set to receive mode.

  At timing T4, the host CPU 5 controls the I / O control unit 62 via the PC card interface 51 and the SCB control unit 20 in the smart card control unit 15, and starts supplying a clock signal from the SC_CLK terminal. . This completes the activation process. The SCB control unit 20 outputs an activation end signal ACTEND # to the reset control unit 66 along with the output of the clock signal.

  Upon receiving the low-level activation end signal ACTEND #, the reset control unit 66 switches the SC_RST terminal to the high level at timing T5 after the predetermined reset period has elapsed, and ends the reset period. The host CPU 5 waits for an ATR (initial response signal) signal to be sent from the smart card 1 via the I / O control unit 62 or the like.

  As described above, by adopting the I / O control unit 62 including the reset control unit 66 that operates independently as the timing control unit, the improved converter C1 is provided, so that the strict timing control of the signal output can be performed. The problem of being unable to do so was solved.

It is a figure which shows the structure of the card | curd recognition system which concerns on Embodiment 1. FIG. It is a figure which shows the structure of a PC card interface. It is a figure which shows the structure of an address decoder. It is a figure which shows the structure of a smart card control part. It is a figure which shows the structure of the card | curd recognition system which concerns on Embodiment 2. FIG. It is a figure which shows the structure of the smart card control part used with the card recognition system of an example of improvement. It is a figure which shows the structure of an I / O control part. It is a figure which shows the time chart at the time of the activation process execution at the time of smart card connection. It is a figure which shows the structure of the conventional card | curd recognition system.

Explanation of symbols

1 smart card, 4 chipset, 5 host CPU, 6 memory, 7 hard disk, 8 PC card controller, 10, 50 active adapter, 11, 51 PC card interface, 15 smart card controller, 53 address decoder.

Claims (20)

A non-compliant card that does not comply with the standard, a computer that has a card controller for transmitting and receiving data to and from the compliant card that conforms to the standard, and an adapter that connects the non-compliant card to the computer In the card recognition system that recognizes the non-compliant card as a compliant card,
A non-compliant card control unit having an I / O for a non-compliant card for converting non-compliant card data into compliant card data between the card controller and the non-compliant card, and the non-compliant card controller. And a dedicated transmission line and an interface having I / O for a compliant card.   2. The circuit according to claim 1, wherein the non-compliant card control unit or the interface includes a circuit that converts the number of bits of data output from the non-compliant card control unit into the number of bits of data of the compliant card. The card recognition system described.   3. The card recognition system according to claim 1, wherein the non-compliant card control unit includes a timing control unit that independently performs timing control of signal output in response to a request from a computer.   The card recognition system according to any one of claims 1 to 3, wherein the non-compliant card control unit has a buffer memory that is equal to or larger than a maximum amount of data output from the non-compliant card per unit.   5. The card recognition system according to claim 1, wherein the standard is PCMCIA, and the non-compliant card is a smart card.   6. The card recognition system according to claim 1, wherein the card adapter is an active card adapter that includes the non-compliant card control unit and an interface.   The card recognition system according to any one of claims 1 to 6, wherein the card adapter is a passive card adapter, and the card controller includes the non-compliant card control unit and an interface. A variant card having a connector different in shape from a standard card connector provided in the computer, a computer including a card controller for sending and receiving data to and from the standard card, and the variant card for connecting the variant card to the computer In a card recognition system having an adapter and recognizing the irregular card as a standard card,
In order to convert the irregular card data into the standard card data between the irregular card and the card controller, the irregular card control unit having an irregular card I / O, and the irregular card control unit and a dedicated transmission line And an interface having an I / O for a standard card.   9. The circuit according to claim 8, further comprising a circuit that converts the number of bits of data output from the variant card control unit to the number of bits of data of a standard card in the variant card control unit or the interface. Card recognition system.   10. The card recognition system according to claim 8, wherein the odd-shaped card control unit includes a timing control unit that independently performs timing control of signal output in response to a request from a computer.   11. The card recognition system according to claim 8, wherein the odd-shaped card control unit has a buffer memory that is equal to or larger than a maximum amount of data output from the odd-numbered card per unit.   12. The card recognition system according to claim 8, wherein the standard card is a PC card conforming to PCMCIA, and the deformed card is a smart card.   The card recognition system according to any one of claims 8 to 12, wherein the card adapter is an active card adapter incorporating the odd-shaped card control unit and an interface.   14. The card recognition system according to claim 8, wherein the card adapter is a passive card adapter, and the card controller includes the deformed card and an interface. A non-compliant card that does not comply with the standard, a computer that includes a card controller for data transmission and reception with a compliant card that conforms to the standard, and an adapter for connecting the non-compliant card to the computer In a card recognition system that recognizes non-compliant cards that do not comply with the standard,
A data converter for converting non-compliant card data to compliant card data including data standards between the card controller and the non-compliant card; and a card interface for outputting the output of the data converter to a computer; A card recognition system comprising a dedicated transmission path for directly exchanging data between the data converter and the card interface.   16. The card recognition system according to claim 15, wherein the data conversion unit includes a timing control unit that uniquely performs signal output timing control in response to a request from a computer.   17. The card recognition system according to claim 15, wherein the data conversion unit has a buffer memory equal to or more than a maximum amount of data output per unit from a non-compliant card.   The card recognition system according to any one of claims 15 to 17, wherein the standard is PCMCIA, and the non-compliant card is a smart card.   The card recognition system according to any one of claims 15 to 18, wherein the card adapter is an active card adapter incorporating the data converter and a card interface. The card recognition system according to any one of claims 15 to 19, wherein the card adapter is a passive card adapter, and the controller includes the data conversion unit and a card interface.

Images