JP2005079462A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent deterioration of a characteristic of a semiconductor device having a power transistor. <P>SOLUTION: A barrier conductor film 22 as a TiW film and a seed film 23 as a Ni film are sequentially formed on an insulating film 16 having contact grooves 17 to 19 therein, a conductive film 25 is formed by depositing a Ni film by plating using a mask on the seed film 23, and areas of the seed film 23 and the barrier conductor film 22 having the conductive film 25 not present thereon are sequentially etched to form wiring films 26 to 28. Subsequently, silicon nitride film 31 and a polyimide resin film 32 are sequentially deposited on a semiconductor substrate 1, an opening 33 is made in the wiring film 28, and the opening 33 is buried by solder past printing to form a bump electrode 41 to be electrically connected with the wiring layer 28. Thereafter, A strap electrode 42 having a width of about 1 mm or more in a direction crossing a current path during driving operation of a power MISFET is connected to the bump electrode 41. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device having a power transistor.

For example, a plurality of electrically isolated conductive paths, a MOSFET chip having a gate electrode and a source electrode fixed on a desired conductive path, and a metal connection plate for connecting the drain electrode of the MOSFET chip to the desired conductive path By adopting a MOSFET mounting structure that includes a MOSFET chip and an insulating resin that integrally supports the conductive path, the bonding wire is eliminated and the source electrode is directly fixed to the conductive path, thereby reducing the on-resistance. There is a technology for realizing (see, for example, Patent Document 1).
JP 2002-76195 A

  Transistors for large power applications that can handle a power of several watts or more are called power transistors, and various structures have been studied.

  The present inventors have studied a technique for mounting a semiconductor chip (hereinafter simply referred to as a chip) on which a power transistor is formed on a mounting substrate, and the contents thereof are as follows.

  That is, as means for mounting the chip on which the power transistor is formed on the mounting substrate, for example, a bonding pad formed on the surface of the chip using a wire formed from Al (aluminum) and a bonding formed on the surface of the mounting substrate There is a means for bonding the pad. When such a wire is used, an elongated wire extends between the two bonding pads, and there is a problem that the electric resistance of the wire increases.

  In addition, by adopting the bonding means using an elongated wire as described above, it becomes difficult for heat to flow in the wire, so that it is difficult for heat generated in the chip to escape from the chip surface to the outside of the chip. . As described above, since the power transistor is used for high power, a high voltage such as about 1200 V is applied to the wire whose electrical resistance is large, and a large current such as about 200 A flows. Therefore, a large amount of heat is generated, and it becomes difficult for the heat generated in the chip to escape from the chip surface to the outside of the chip. That is, when the bonding means using the wire is employed, there is a problem that the thermal resistance of the chip increases. If the heat generated in the chip cannot be sufficiently released from the chip surface to the outside of the chip, there is a concern that the characteristics of the power transistor will deteriorate.

  Further, when the wire is used, the parasitic inductance of the wire is increased. When the power transistor is used as an element for driving a motor of an automobile, for example, a counter electromotive force acts on the power transistor when the automobile is decelerated. At this time, if the parasitic inductance of the wire is large, a large voltage is applied to the power transistor, and there is a problem that the power transistor is destroyed due to overvoltage.

  In addition, when the power transistor is used as, for example, an element for driving a motor of an automobile, vibration during driving of the automobile is applied to the chip and the wire. Therefore, there is a problem that physical damage that causes the wire to be detached from the chip occurs.

  An object of the present invention is to provide a technique capable of preventing deterioration of characteristics of a semiconductor device having a power transistor.

  Another object of the present invention is to provide a technique capable of preventing physical damage of a semiconductor device having a power transistor.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

That is, the semiconductor device of the present invention is
A plurality of first semiconductor elements formed on the main surface of the semiconductor substrate;
A first electrode formed on a main surface of the semiconductor substrate and electrically connected to the first semiconductor element;
A plate-like electrode connected to the first electrode at the top of the first electrode;
The first electrode includes a base electrode and a bump electrode formed in a first semiconductor substrate region on the base electrode,
The bump electrode is made of solder.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
(A) forming a plurality of first semiconductor elements on a main surface of a semiconductor substrate;
(B) forming a first electrode electrically connected to the first semiconductor element on a main surface of the semiconductor substrate;
(C) connecting a plate electrode to the first electrode;
Including
The step (b)
(B1) forming a base electrode electrically connected to the plurality of first semiconductor elements on the main surface of the semiconductor substrate;
(B2) forming a first metal film in a first semiconductor substrate region on the base electrode;
(B3) forming a bump electrode on the first metal film;
(B4) heat-treating the semiconductor substrate, and forming an alloy layer of the first metal film, the base electrode, and the bump electrode between the base electrode and the bump electrode;
Including
The bump electrode is formed from solder.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
(1) It is possible to prevent deterioration of characteristics of a semiconductor device having a power transistor.
(2) Physical damage of a semiconductor device having a power transistor can be prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the drawings used for the description of the following embodiments, hatching may be given even in plan views for easy understanding of the structure.

(Embodiment 1)
The semiconductor device of the first embodiment has, for example, an n-channel trench gate type power MISFET (power device). Such a semiconductor device according to the first embodiment will be described according to the manufacturing process with reference to FIGS.

First, as shown in FIG. 1, an n-type conductivity type is formed on the surface of an n ⁺ type single crystal silicon substrate 1A doped with an n-type conductivity type impurity (for example, As (arsenic)) at a high concentration. A semiconductor substrate (hereinafter simply referred to as a substrate) 1 is prepared by epitaxially growing an n ⁻ type single crystal silicon layer 1B doped with an impurity (for example, As). Subsequently, the silicon oxide film 3 is formed by, for example, thermally oxidizing the surface of the substrate 1.

Next, a silicon nitride film (not shown) patterned by photolithography is formed on the silicon oxide film 3. Subsequently, using the silicon nitride film as a mask, an impurity having a p-type conductivity (for example, P (boron)) is implanted into the n ⁻ -type single crystal silicon layer 1B. Subsequently, the substrate 1 is subjected to heat treatment to diffuse the p-type conductivity impurity, and the p-type well 5 is formed. At this time, the field insulating film 6 is formed on the surface of the substrate 1 in the region without the silicon nitride film. This field insulating film 6 is an element isolation region, and a region partitioned by this region is an element formation region (active (first semiconductor substrate region)). Thereafter, the silicon nitride film is removed by cleaning the substrate 1 using hydrofluoric acid and cleaning the substrate 1 using hot phosphoric acid.

Next, as shown in FIG. 2, impurity ions (for example, B (boron)) having a p-type (second conductivity type) conductivity type using a photoresist film patterned by a photolithography technique as a mask are n ⁻ -type single. Introduced into the crystalline silicon layer 1B. Next, the substrate 1 is subjected to a heat treatment to diffuse the impurity ions to form the p ⁻ type semiconductor region 7. The p ⁻ type semiconductor region 7 becomes a channel layer of the power MISFET after the power MISFET is formed.

Subsequently, impurity ions (for example, As) having n-type conductivity are introduced into the n ⁻ -type single crystal silicon layer 1B using a photoresist film patterned by photolithography as a mask. Next, the substrate 1 is subjected to heat treatment to diffuse the impurity ions, thereby forming an n ⁺ type semiconductor region 8. A part of the n ⁺ type semiconductor region 8 becomes a source region of the power MISFET after the power MISFET is formed. Further, another part of the n ⁺ type semiconductor region 8 is formed on the outer periphery of the chip in a plane when the substrate 1 is divided into individual semiconductor chips (hereinafter simply referred to as chips) to protect the power MISFET element. It has the function to do.

  Next, as shown in FIG. 3, the silicon oxide film 3 and the substrate 1 are etched using a photoresist film patterned by a photolithography technique as a mask to form a groove 10. In the first embodiment, the groove 10 is a mesh-like pattern extending in a square, hexagonal or octagonal shape on the plane, or a stripe-like pattern extending in the same direction. Subsequently, a thermal oxide film 11 is formed on the bottom and side walls of the groove 10 by performing a heat treatment on the substrate 1. This thermal oxide film 11 becomes a gate insulating film of the power MISFET.

Next, for example, a polycrystalline silicon film doped with P is deposited on the silicon oxide film 3 including the inside of the trench 10, and the trench 10 is filled with the polycrystalline silicon film. At this time, a polycrystalline silicon film is formed in layers on the silicon oxide film 3 on the p-type well 5. Subsequently, the polycrystalline silicon film is etched using the photoresist film patterned by the photolithography technique as a mask, and the polycrystalline silicon film is left in the groove 10 to form the gate electrode 12 of the power MISFET in the groove 10. To do. At this time, the polycrystalline silicon pattern 13 is formed by leaving the polycrystalline silicon film on the silicon oxide film 3 and the field insulating film 6 in the outer peripheral portion of the chip region (not shown). A part of the polycrystalline silicon pattern 13 and the gate electrode 12 are electrically connected in a region not shown in FIG. Through the steps so far, the power MISFET (first semiconductor element) is formed with the n ⁺ type single crystal silicon substrate 1A and the n ⁻ type single crystal silicon layer 1B as the drain region and the n ⁺ type semiconductor region 8 as the source region. be able to.

Next, as shown in FIG. 4, for example, after depositing a PSG (Phospho Silicate Glass) film on the substrate 1, an SOG (Spin On Glass) film is applied on the PSG film to thereby form the PSG film and the SOG film. An insulating film 16 made of a film is formed. Subsequently, the insulating film 16 and the substrate 1 are etched using a photoresist film patterned by a photolithography technique as a mask to form contact grooves 17 and 18. The contact groove 17 is formed between the adjacent gate electrodes 12 so as to penetrate the n ⁺ type semiconductor region 8 which becomes the source region of the power MISFET. At this time, the insulating film 16 on the polycrystalline silicon pattern 13 is also patterned, and a contact groove 19 reaching the polycrystalline silicon pattern 13 is formed.

Next, by introducing, for example, BF ₂ (boron difluoride) as impurity ions having p-type conductivity from the bottoms of the contact grooves 17 and 18, p ⁺ that covers the bottoms of the contact grooves 17 and 18 is formed. A type semiconductor region 20 is formed. Thus, the contact trench 17 is formed, impurity ions are introduced from the contact trenches 17 and 18 using the insulating film 16 as a mask, and the p ⁺ type semiconductor region 20 is provided in a self-aligned manner at the bottom of the contact trenches 17 and 18. Thus, for example, the mask alignment margin can be reduced, so that miniaturization between adjacent gate electrodes 12 can be achieved. The p ⁺ type semiconductor region 20 is used to make an ohmic contact with the p ⁻ type semiconductor region 7 at the bottom of the contact groove 17 in a wiring formed in a later step.

  Next, as illustrated in FIG. 5, a barrier conductor film 22 is formed on the insulating film 16 including the inside of the contact grooves 17 to 19. The barrier conductor film 22 can be formed by performing a heat treatment on the substrate 1 after thinly depositing a TiW (titanium tungsten) film by sputtering, for example. Subsequently, a seed film 23 for forming wiring on the substrate 1 is deposited on the barrier conductor film 22 by a plating method in a later step. The seed film 23 can be formed by depositing a thin Ni (nickel) film by, for example, a sputtering method.

  Next, as shown in FIG. 6, a photoresist film 24 is formed on the substrate 1. Subsequently, the photoresist film 24 is patterned by a photolithography technique. Next, a conductive film 25 is formed by depositing a Ni film in a region where the photoresist film 24 does not exist on the seed film 23 by plating.

Next, as shown in FIG. 7, after removing the photoresist film 24, the seed film 23 and the barrier conductor film 22 in a region where the conductive film 25 does not exist on the plane are sequentially etched. Thereby, wirings 26, 27, and 28 including the conductive film 25, the seed film 23, and the barrier conductor film 22 are formed. The wiring 27 is a gate wiring that is electrically connected to the gate electrode 12 through the polycrystalline silicon pattern 13. The wiring 26 is arranged on the outer periphery (second semiconductor substrate region) of the chip in a plane after the substrate 1 is divided into individual chips, and is electrically connected to the n ⁺ type semiconductor region 8 formed on the outer periphery of the chip. When the power MISFET is driven, it is kept at the same potential as the drain. Further, in a region not shown in FIG. 7, a gate pad that is made of the conductive film 25, the seed film 23, and the barrier conductor film 22 and that is electrically connected to the wiring 27 that becomes the gate wiring is formed.

  Next, as shown in FIG. 8, a silicon nitride film (first insulating film, second insulating film) 31 is deposited on the substrate 1 by, for example, plasma CVD. Subsequently, a polyimide resin film (second insulating film) 32 is deposited on the silicon nitride film 31. In the first embodiment, the polyimide resin film 32 may be either photosensitive or non-photosensitive.

  Subsequently, the polyimide resin film 32 and the silicon nitride film 31 are sequentially etched using a photoresist film patterned by photolithography as a mask, and an opening (base electrode, first base electrode) 28 serving as a source electrode (opening ( A first opening 33 is formed, and the polyimide resin film 32 and the silicon nitride film 31 are left in the other region (second semiconductor substrate region). To do. The planar shape of the opening 33 will be described later in the subsequent process. At this time, an opening is also formed on the gate pad in a region not shown in FIG. In the first embodiment, the silicon nitride film 31 covers part of the wiring 28 after the opening 33 is formed. Thereby, it is possible to prevent the wiring 28 from being peeled from the substrate 1.

  Next, as shown in FIG. 9, a thin Au (gold) film (first metal film) 35 is deposited by plating on the surfaces of the wiring 28 and the gate pad that appear at the bottom of the opening 33. In a later process, a bump electrode that is electrically connected to the wiring 28 is formed on the wiring 28, and the barrier film 22, the conductive film 25 including the seed film 23, and the Au film 35 are formed by the processes described so far. A bump base film 36 can be formed. That is, the wiring 28 can have both a function as a source electrode (wiring) and a function as a bump base film. Further, by forming the Au film 35, it is possible to prevent the surface of the conductive film 25 forming the wiring 28 from being oxidized before the bump electrode is formed.

Next, after protecting the surface of the substrate 1 with a tape or the like, the back surface of the n ⁺ type single crystal silicon substrate 1A is ground with the protective surface on the lower side. Subsequently, as a conductive film, for example, a Ti (titanium) film 37, a Ni film 38, and an Au film 39 are sequentially deposited on the back surface of the n ⁺ type single crystal silicon substrate 1A to form a laminated film thereof. This laminated film becomes a lead electrode (drain electrode) 40 in the drain region (n ⁺ type single crystal silicon substrate 1A and n ⁻ type single crystal silicon layer 1B).

Next, as shown in FIG. 10, it is made of, for example, Ag (silver), Sn (tin) and Cu (copper) using a metal mask (not shown) patterned in accordance with the planar pattern of the opening 33. A solder paste is printed, the opening 33 is embedded, and a bump electrode (first bump electrode) 41 having a thickness of about 150 μm that is electrically connected to the wiring 28 is formed. The bump electrode 41 and the wiring 28 serve as a source electrode (first electrode) that is electrically connected to the n ⁺ type semiconductor region 8 serving as the source region of the power MISFET. At the time of printing the solder paste, heat of about 300 ° C. or less is applied to the substrate 1. Due to this heat, an alloy layer of Sn included in the solder paste and Ni that forms the conductive film 25 (not shown) is formed at the interface between the bump electrode 41 and the bump base film 36 (conductive film 25). Is formed. Thereby, the connection between the bump electrode 41 and the bump base film 36 can be strengthened. Further, the Au film 35 diffuses into the bump electrode 41 and the conductive film 25 due to heat during the solder paste printing. Thereafter, the substrate 1 in a wafer state is diced along, for example, divided regions, and divided into individual chips.

  Here, FIGS. 11 to 13 are plan views of the chip CHP formed by dividing the substrate 1. In the polyimide resin film 32, other openings are formed in addition to the openings 33, and a gate pad GP that is electrically connected to the gate electrode 12 appears in the lower part of the openings. As shown in FIGS. 11 to 13, in the first embodiment, the planar pattern of the bump electrode 41 (opening 33) is rectangular (see FIG. 11), stripe (FIG. 12), or matrix (FIG. 13). Can be exemplified. According to experiments conducted by the present inventors, the planar pattern of the bump electrode 41 is in the order of matrix, stripe, and rectangle, so that the solder paste is easily detached from the metal mask during solder paste printing. The fact that the solder paste is easily detached from the metal mask means that the openings 33 are easily filled with the solder paste. Therefore, the plane pattern of the bump electrode 41 is the pattern of the metal mask in the order of matrix, stripe, and rectangle. The street bump electrode 41 can be easily made.

According to the first embodiment in which the bump electrode 41 is formed by the above-described means, the bump electrode is connected to the source electrode (wiring 28) electrically connected to the source region (n ⁺ type semiconductor region 8) of the power MISFET. A function as a base film (bump base film 36) in forming 41 can be provided. As a result, it is not necessary to form a bump underlayer on the source electrode (wiring 28), so that the number of manufacturing steps of the semiconductor device of the first embodiment can be reduced. As a result, the manufacturing cost of the semiconductor device according to the first embodiment can be reduced.

  Next, a strap electrode (plate electrode) 42 (see FIG. 10) formed by bending a Cu plate having a thickness of about 0.2 mm is connected to the bump electrode 41. At this time, the strap electrode 42 can be connected by once melting the bump electrode 41 formed of solder by heating. Further, since the bump electrode 41 is formed of solder, for example, a new soldering step between the bump electrode 41 and the strap electrode 42 when the strap electrode 42 is connected can be omitted. In the first embodiment, the width of the strap electrode 42 is set to about 1 mm or more in the direction (first direction) intersecting the current path during driving of the power MISFET, for example, about 6.5 mm.

  Next, as shown in FIGS. 14 to 16, a lead frame having leads 44G, 44S, 44D and a base plate 44B is prepared. The leads 44G, 44S, 44D and the base plate 44B are made of Cu, for example, and the leads 44D and the base plate 44B are electrically connected. 15 is a cross-sectional view corresponding to the line AA in FIG. 14, and FIG. 16 is a cross-sectional view corresponding to the line BB in FIG.

  Next, the lead electrode 40 (see FIG. 10) formed on the back surface of the chip CHP is connected to a predetermined position of the base plate 44B by using, for example, solder 45 formed of Sn and Sb (antimony), and the strap electrode 42 is connected to the lead 44S. Thereby, the lead electrode 40 and the lead 44D are electrically connected, and the strap electrode 42 and the lead 44S are electrically connected. Subsequently, the gate pad GP and the lead 44G are electrically connected by a wire 46 formed of, for example, Al (aluminum).

  Next, as shown in FIGS. 17 to 19, the chip CHP (including the strap electrode 42 and the wire 46) and the lead frame are sealed with the mold resin 47 to manufacture the semiconductor device of the first embodiment. . In this sealing step, sealing is performed so that the ends of the leads 44G, 44S, and 44D come out of the mold resin 47.

According to the first embodiment described above, the source region (n ⁺ type semiconductor region 8 (see FIG. 10)) of the power MISFET and the lead 44S (see FIGS. 14 and 15) are connected to the strap electrode 42 (see FIGS. 14 and 15). 15)). Accordingly, when a wire similar to the wire 46 (see FIG. 14) electrically connecting the gate pad GP (see FIG. 14) and the lead 44G (see FIG. 14) is used instead of the strap electrode 42, In comparison, the electrical resistance between the source region and the lead 44S can be greatly reduced.

  Further, when a wire is used instead of the strap electrode 42, the cross-sectional area of the wire in the direction intersecting the current path is smaller than that of the strap electrode 42. Becomes difficult to flow. For this reason, it becomes difficult for heat generated in the chip CHP (see FIG. 14) to be released from the surface of the chip CHP to the outside of the chip CHP by driving the power MISFET. Further, since the power MISFET is used for high power, a high voltage such as about 1200 V is applied to a wire having a larger electric resistance than the strap electrode 42, and a large current such as about 200 A flows. For this reason, a large amount of heat is generated from the wire, and it is difficult for the heat generated in the chip CHP to escape from the surface of the chip CHP to the outside of the chip CHP. Therefore, when a wire is used instead of the strap electrode 42, there is a concern that the thermal resistance of the chip CHP increases. Further, when the heat generated in the chip CHP cannot be sufficiently released from the surface of the chip CHP to the outside of the chip CHP, there is a concern that the characteristics of the power MISFET are deteriorated. On the other hand, when the strap electrode 42 having a sufficiently large cross-sectional area in the direction intersecting the current path as compared with the wire is used, heat can be relatively easily flowed. Moreover, since the electric resistance of the strap electrode 42 is smaller than that of the wire, it is relatively difficult to generate heat. Thereby, when the strap electrode 42 of the first embodiment is used, it is possible to prevent an increase in the thermal resistance of the chip CHP. As a result, it is possible to prevent deterioration of the characteristics of the power MISFET.

  Further, when the chip CHP of the first embodiment in which the power MISFET is formed is used, for example, for driving an automobile motor, a counter electromotive force acts on the power MISFET when the automobile is decelerated. Here, when a wire is used instead of the strap electrode 42, since the parasitic inductance of the wire increases, a large voltage is applied to the power MISFET by the action of the counter electromotive force, and the power MISFET is destroyed by the overvoltage. I am worried about it. On the other hand, when the strap electrode 42 of the first embodiment is used, the parasitic inductance of the strap electrode 42 can be relatively reduced, so that such a problem can be prevented from occurring.

  Further, when the chip CHP of the first embodiment in which the power MISFET is formed is used for driving an automobile motor, for example, vibration during driving of the automobile is applied to the chip CHP and the lead frame. For this reason, when a wire is used instead of the strap electrode 42, there is a concern that physical damage may occur such that the wire is detached from the chip CHP or the lead 44S. On the other hand, when the strap electrode 42 of the first embodiment is used, the contact area with the bump electrode 41 (see FIG. 10 and FIG. 14) can be sufficiently increased as compared with the case where a wire is used. In addition, the connection strength with the bump electrode 41 can be greatly improved. As a result, it is possible to prevent physical damage that is a concern when using wires.

(Embodiment 2)
Next, the semiconductor device of the second embodiment will be described with reference to FIGS. 20 and 21 according to the manufacturing process.

  In the second embodiment, the conductive film 25 (see FIG. 7) in the first embodiment is formed of a laminated film of a Cu film and a Ni film for the purpose of reducing electrical resistance. In this case, by using the polyimide resin film 32 (see FIG. 8) as a photosensitive polyimide resin film, the Cu forming the conductive film 25 diffuses into the polyimide resin film 32 and the polyimide resin film 32 is altered. Can be prevented. However, in the case where the facility for forming the photosensitive polyimide resin film is not provided and only the non-photosensitive polyimide resin film can be formed, the semiconductor device of the second embodiment as described below can be used. Such a problem can be prevented by the manufacturing process.

  That is, the manufacturing process of the semiconductor device of the second embodiment is the same up to the step of depositing the barrier conductor film 22 (see FIG. 5) described in the first embodiment. Thereafter, as shown in FIG. 20, on the barrier conductor film 22, for example, Cr (chromium film) having a film thickness of about 0.075 μm and Cu film having a film thickness of about 0.25 μm are sequentially deposited by sputtering. A film 22 is formed. Subsequently, a photoresist film (not shown in FIG. 20) similar to the photoresist film 24 shown in the first embodiment is formed on the substrate 1. Next, a conductive film 25 is formed by sequentially depositing a Cu film having a thickness of about 3 μm and a Ni film having a thickness of about 1.5 μm in a region where the photoresist film does not exist on the seed film 23 by plating. . Next, after removing the photoresist film, the seed film 23 and the barrier conductor film 22 in a region where the conductive film 25 does not exist on the plane are sequentially etched, so that the conductive film 25, the seed film 23, and the barrier conductor film 22 are removed. Wirings 26, 27, and 28 are formed. Next, a Ni film (first thin film) 25A is formed on the surfaces of the wirings 26, 27, and 28 by electroless plating.

  Next, as shown in FIG. 21, the silicon nitride film 31 and the polyimide resin film 32 (non-photosensitive polyimide resin in the second embodiment) are performed by the same process as that described in the first embodiment with reference to FIG. Film). Next, the polyimide resin film 32 and the silicon nitride film 31 are sequentially etched using a photoresist film patterned by a photolithography technique as a mask to form an opening 33 on the wiring 28 that is a source electrode. The planar pattern of the opening 33 in the second embodiment is the same as that in the first embodiment.

  As described above, by covering the surfaces of the wirings 26, 27, and 28 with the Ni film 25A, the Ni film 25A functions as a barrier layer, and Cu diffuses from the conductive film 25 to the polyimide resin film 32. Can be prevented. Thereby, even when the polyimide resin film 32 is formed from a non-photosensitive polyimide resin film, it is possible to prevent a problem that the polyimide resin film 32 is deteriorated due to diffusion of Cu.

  Thereafter, the semiconductor device of the second embodiment is manufactured through the same steps as those described in the first embodiment with reference to FIGS. 9 to 19.

  According to the second embodiment as described above, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
Next, the semiconductor device according to the third embodiment will be described with reference to FIGS.

  The semiconductor device of the third embodiment is a three-phase inverter used for driving a motor, for example. FIG. 22 is a circuit diagram of a principal part of the three-phase inverter.

  The three-phase inverter circuit shown in FIG. 22 includes a bridge circuit BC, a chopper circuit CPC, an inverter circuit IVC, and the like. The bridge circuit BC is formed from a plurality of diodes D1. The chopper circuit CPC is formed from a power transistor Tr1, a reactor L1, a diode D2, and a capacitor C2. The inverter circuit IVC is formed of a plurality of n-channel IGBTs (Insulated Gate Bipolar Transistors) Tr2, a diode D3, and the like. The output from the AC power supply is first rectified by the bridge circuit BC, then smoothed by the capacitor C1, and then the output voltage of the inverter is adjusted by changing the voltage of the capacitor C2 by the chopper circuit CPC.

  FIG. 23 is a plan view of the module IVM in which the inverter circuit IVC is formed. As shown in FIG. 23, a plurality of metal plates 52 and metal plates 53 are formed on the wiring board 51. On each metal plate 52, an IGBT chip (first semiconductor chip) 54 on which the n-channel IGBT (power device) Tr2 is formed and a diode chip (second semiconductor chip) on which a diode (power device) D3 is formed. ) 55 is arranged. The IGBT chip 54 and the diode chip 55 have n-channels formed inside the IGBT chip 54 and the diode chip 55 by connecting respective back electrodes (not shown in FIG. 23) to the metal plate 52. The electrical connection between the type IGBT Tr2 and the diode D3 and the metal plate 52 is realized. The back electrode of the IGBT chip 54 is a collector electrode that is electrically connected to the collector of the n-channel IGBT Tr2, and the back electrode of the diode chip 55 is a cathode electrode of the diode D3.

  Bump electrodes (not shown in FIG. 23) similar to the bump electrodes 41 (see FIGS. 10 to 16) described in the first embodiment are provided on the tops of the IGBT chip 54 and the diode chip 55, respectively. A strap electrode (plate electrode, first plate electrode, second plate electrode) similar to the strap electrode 42 described in the first embodiment (see FIGS. 10 to 16) is formed on the bump electrode. One end of 56 is connected. The other end of the strap electrode 56 is connected to a metal plate 52 or a metal plate 53 on which another IGBT chip 54 and a diode chip 55 are arranged. In addition, a strap electrode (plate electrode) 57 for electrically connecting to a circuit other than the module IVM is connected to one of the metal plates 52. As the strap electrode 57, the same one as the strap electrode 56 can be used.

  FIG. 24 is a cross-sectional view of the main part of the IGBT chip 54.

As shown in FIG. 24, in the IGBT chip 54 of the third embodiment, as a semiconductor substrate (first semiconductor substrate) 1C, an impurity having a p-type conductivity (for example, B) is doped at a high concentration, for example. The n ⁺ type single crystal silicon layer 1E doped with an impurity having an n type conductivity (for example, As) at a high concentration on the surface of the p ⁺⁺ type single crystal silicon substrate 1D and the first embodiment described above The same n ⁻ type single crystal silicon layer 1B as that of the n ⁻ type single crystal silicon layer 1B is sequentially epitaxially grown. In the third embodiment, the impurity concentration of n ⁺ type single crystal silicon layer 1E is set to be lower than that of p ⁺⁺ type single crystal silicon substrate 1D and higher than that of n ⁻ type single crystal silicon layer 1B. The structure other than the semiconductor substrate 1C is the same as that of the first embodiment. In the IGBT chip 54, the n channel is formed by using the p ⁺⁺ type single crystal silicon substrate 1D as a collector and the n ⁺ type semiconductor region 8 as an emitter. A type IGBT (first semiconductor element) Tr2 is formed.

  Next, the diode chip 55 will be described according to the manufacturing process with reference to FIGS.

First, as shown in FIG. 25, an n-type conductivity is formed on the surface of an n ⁺ -type single crystal silicon substrate 61A doped with an n-type impurity (for example, As or P (phosphorus)) at a high concentration. A semiconductor substrate (hereinafter simply referred to as a substrate) 61 is prepared by epitaxially growing an n ⁻ -type single crystal silicon layer 61B doped with an impurity having a type (for example, As or P). Next, heat treatment is performed on the substrate 61 to form a silicon oxide film 62 on the surface of the n ⁻ -type single crystal silicon layer 61B.

Next, as shown in FIG. 26, the silicon oxide film 62 is selectively removed by etching using a photoresist film (not shown) patterned by a photolithography technique as a mask, so that an n ⁻ type single crystal silicon layer 61B is obtained. Is formed. Next, using the silicon oxide film 62 as a mask, an impurity having a p-type conductivity (for example, B) is introduced into the n ⁻ -type single crystal silicon layer 61B using an ion implantation method or the like, and heat treatment is performed as necessary. . Thereby, the p-type diffusion layer 64 is formed. In this way, the diode (first semiconductor element) D3 formed from the PN junction of the p-type diffusion layer 64 and the n ⁻ -type single crystal silicon layer 61B is formed.

  Next, as shown in FIG. 27, an oxide film 65 is formed on the exposed surface of the p-type diffusion layer 64 by using a thermal oxidation method. Next, a silicon oxide film is deposited on the substrate 61, and a PSG (Phospho Silicate Glass) film is deposited on the surface of the silicon oxide film by, for example, a CVD method, thereby forming a surface protective film 66 composed of the silicon oxide film and the PSG film. Form.

  Subsequently, the surface protective film 66 and the oxide film 65 are selectively removed by etching using a photoresist film (not shown) patterned by a photolithography technique as a mask, and an opening 67 is formed. At this time, the p-type diffusion layer 64 is exposed at the bottom of the opening 67. Subsequently, a barrier conductor film 68 is formed on the substrate 61 (surface protective film 66) including the inside of the opening 67. The barrier conductor film 68 can be formed by performing a heat treatment on the substrate 61 after a thin TiW (titanium tungsten) film is deposited by sputtering, for example. Subsequently, a seed film 69 for forming an anode base electrode on the substrate 61 is deposited on the barrier conductor film 68 by a plating method in a later step. The seed film 69 can be formed by depositing a thin Ni film by, for example, a sputtering method. Next, a photoresist film (not shown) is formed on the substrate 1. Subsequently, the photoresist film is patterned by a photolithography technique. Next, a conductive film 70 is formed by depositing a Ni film in a region where the photoresist film does not exist on the seed film 69 by plating. Next, after removing the photoresist film, the seed film 69 and the barrier conductor film 68 in a region where the conductive film 70 does not exist on the plane are sequentially etched. Thereby, an anode base electrode (second base electrode) 71 composed of the conductive film 70, the seed film 69 and the barrier conductor film 68 and electrically connected to the p-type diffusion layer 64 is formed.

  Next, as shown in FIG. 28, a silicon nitride film (first insulating film, second insulating film) 72 is deposited on the substrate 61 by plasma CVD, for example. Subsequently, a polyimide resin film (second insulating film) 73 is deposited on the silicon nitride film 72. In the third embodiment, the polyimide resin film 73 may be either photosensitive or non-photosensitive.

  Subsequently, the polyimide resin film 73 and the silicon nitride film 72 are sequentially etched using a photoresist film patterned by photolithography as a mask, and openings (first semiconductor substrate region and third semiconductor substrate region) are formed on the anode base electrode 71. , First opening) 74 is formed. In the third embodiment, it can be exemplified that the planar shape of the opening 74 is the same as that of the opening 33 (see FIGS. 11 to 13) described in the first embodiment. In the third embodiment, the silicon nitride film 72 covers a part of the anode base electrode 71 after the opening 74 is formed. Thereby, it is possible to prevent the anode base electrode 71 from being peeled off from the substrate 61.

  Next, a thin Au film (first metal film) 75 is deposited on the surface of the anode base electrode 71 appearing at the bottom of the opening 74 by plating. In a later step, a bump electrode that is electrically connected to the anode base electrode 71 is formed on the anode base electrode 71. By the steps so far, the conductive film 70 including the barrier conductor film 68 and the seed film 69, and Au A bump base film 76 made of the film 75 can be formed. That is, the bump base film 76 can also have a function as the anode base electrode 71. Further, by forming the Au film 75, it is possible to prevent the surface of the conductive film 70 forming the anode base electrode 71 from being oxidized before the bump electrode is formed.

Next, after protecting the surface of the substrate 61 with a tape or the like, the back surface of the n ⁺ type single crystal silicon substrate 61A is ground with the protective surface on the lower side. Subsequently, as a conductive film, for example, a Ti film 77, a Ni film 78, and an Au film 79 are sequentially deposited on the back surface of the n ⁺ type single crystal silicon substrate 61A to form a laminated film thereof. This laminated film becomes a cathode electrode (back electrode) 80.

  Next, as shown in FIG. 29, a solder paste made of, for example, Ag, Sn, and Cu is printed using a metal mask (not shown) patterned in accordance with the planar pattern of the opening 74, and the opening 74. A bump electrode (second bump electrode) 81 is formed so as to be electrically connected to the anode base electrode 71. The bump electrode 81 and the anode base electrode 71 serve as anode electrodes (first electrode and second electrode) that are electrically connected to the p-type diffusion layer 64 that is the p-type region of the diode D3. At the time of printing the solder paste, heat of about 300 ° C. or less is applied to the substrate 61. Due to this heat, an alloy layer of Sn included in the solder paste and Ni forming the conductive film 70 (not shown) is formed at the interface between the bump electrode 81 and the bump base film 76 (conductive film 70). Is formed. Thereby, the connection between the bump electrode 81 and the bump base film 76 can be strengthened. Further, the Au film 75 diffuses into the bump electrode 81 and the conductive film 70 due to heat during the solder paste printing. Thereafter, the substrate 61 in a wafer state is diced along, for example, divided regions, and divided into individual diode chips 55.

  According to the third embodiment in which the bump electrode 81 is formed by the above-described means, the anode base electrode 71 can have a function as a base film (bump base film 76) when the bump electrode 81 is formed. it can. This eliminates the need to form a new bump base film on the anode base electrode 71, thereby reducing the number of manufacturing steps of the semiconductor device of the third embodiment. As a result, it is possible to reduce the manufacturing cost of the semiconductor device of the third embodiment.

  Next, a strap electrode (second plate electrode) 56 similar to the strap electrode 42 (see FIG. 10) described in the first embodiment is connected to the bump electrode 81 to manufacture the diode chip 55. Similar to the first embodiment, at this time, the strap electrode 56 can be connected by melting the bump electrode 81 formed of solder once by heating. Since the bump electrode 81 is made of solder, for example, a new soldering step can be omitted between the bump electrode 81 and the strap electrode 56 when the strap electrode 56 is connected.

  Also in the diode chip 55 of the third embodiment as described above, it is possible to obtain the same effect as the chip CHP (for example, see FIG. 14) in which the power MISFET described in the first embodiment is formed. .

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the case where the silicon nitride film is formed so as to cover a part of the bump base electrode in order to prevent the peeling of the bump base film from the substrate has been described. However, instead of the silicon nitride film, a silicon oxide film is used. Alternatively, a silicon oxynitride film may be used.

  In the above embodiment, the bump electrode is formed by printing a solder paste made of Ag, Sn, and Cu. However, the bump electrode may be formed by printing a solder paste made of Sn and Pb (lead).

  The semiconductor device of the present invention can be applied to, for example, a motor driving module mounted on an automobile.

It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; It is a top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing in the position along the AA line in FIG. It is sectional drawing in the position along the BB line in FIG. It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing in the position along the AA line in FIG. It is sectional drawing in the position along the BB line in FIG. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; It is a principal part circuit diagram of the three-phase inverter which is a semiconductor device of Embodiment 3 of this invention. It is a principal part top view of the module in which the three-phase inverter which is a semiconductor device of Embodiment 3 of this invention was formed. It is principal part sectional drawing of the IGBT chip | tip which the semiconductor device of Embodiment 3 of this invention has. It is principal part sectional drawing explaining the manufacturing method of the diode chip which the semiconductor device of Embodiment 3 of this invention has. FIG. 26 is an essential part cross sectional view of the diode chip during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the diode chip during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the diode chip during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the diode chip during a manufacturing step following FIG. 28;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A n ⁺ type | mold single crystal silicon substrate 1B n < ^- > type | mold single crystal silicon layer 1C Semiconductor substrate (1st semiconductor substrate)
1D p ⁺⁺ type single crystal silicon substrate 1E n ⁺ type single crystal silicon layer 3 silicon oxide film 5 p type well 6 field insulating film 7 p ⁻ type semiconductor region 8 n ⁺ type semiconductor region 10 groove 11 thermal oxide film 12 gate electrode 13 Polycrystalline silicon pattern 16 Insulating film 17-19 Contact groove 20 p ⁺ type semiconductor region 22 Barrier conductor film 23 Seed film 24 Photoresist film 25 Conductive film 25A Ni film (first thin film)
26, 27 wiring 28 wiring (base electrode, first base electrode)
31 Silicon nitride film (first insulating film, second insulating film)
32 Polyimide resin film (second insulating film)
33 opening (first opening)
35 Au film (first metal film)
36 Bump foundation film 37 Ti film 38 Ni film 39 Au film 40 Lead electrode 41 Bump electrode (first bump electrode)
42 Strap electrode (plate electrode)
44B Base plates 44D, 44G, 44S Lead 45 Solder 46 Wire 47 Mold resin 51 Wiring substrate 52, 53 Metal plate 54 IGBT chip (first semiconductor chip)
55 Diode chip (second semiconductor chip)
56 Strap electrode (plate electrode, first plate electrode, second plate electrode)
57 Strap electrode (plate electrode)
61 semiconductor substrate 61A n ⁺ type single crystal silicon substrate 61B n ⁻ type single crystal silicon layer 62 silicon oxide film 63 opening 64 p type diffusion layer 65 oxide film 66 surface protective film 67 opening 68 barrier conductor film 69 seed film 70 conductive Film 71 Anode base electrode (second base electrode)
72 Silicon nitride film (first insulating film, second insulating film)
73 Polyimide resin film (second insulating film)
74 opening (first semiconductor substrate region, third semiconductor substrate region, first opening)
75 Au film (first metal film)
76 Bump underlayer film 77 Ti film 78 Ni film 79 Au film 80 Cathode electrode 81 Bump electrode (second bump electrode)
BC Bridge circuit C1, C2 Capacitance CPC Chopper circuit CHP Chip D1, D2 Diode D3 Diode (power device)
GP gate pad IVC inverter circuit IVM module L1 reactor Tr1 power transistor Tr2 n-channel IGBT (power device)

Claims (21)

A plurality of first semiconductor elements formed on the main surface of the semiconductor substrate;
A first electrode formed on a main surface of the semiconductor substrate and electrically connected to the first semiconductor element;
A semiconductor device having a plate-like electrode connected to the first electrode above the first electrode,
The first electrode includes a base electrode and a bump electrode formed in a first semiconductor substrate region on the base electrode,
The base electrode electrically connects the plurality of first semiconductor elements to each other,
The semiconductor device according to claim 1, wherein the bump electrode is made of solder. The semiconductor device according to claim 1,
The semiconductor substrate is formed from the first semiconductor substrate region and the second semiconductor substrate region,
The first semiconductor element is formed in the first semiconductor substrate region;
A semiconductor device, wherein a wiring of the same layer as the base electrode is formed in the second semiconductor substrate region. The semiconductor device according to claim 2,
The semiconductor device, wherein the second semiconductor substrate region arranged along the periphery of the base electrode in a plane is covered with a first insulating film. The semiconductor device according to claim 3.
The semiconductor device, wherein the first insulating film includes a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The semiconductor device according to claim 1,
A width of the plate electrode is 1 mm or more in a first direction intersecting a current path in the plate electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the base electrode contains nickel as a main component. The semiconductor device according to claim 1,
An alloy layer of the base electrode and the bump electrode is formed between the base electrode and the bump electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of first semiconductor elements form a power device. The semiconductor device according to claim 8.
The power device is a MISFET,
The source region of the MISFET is formed near the surface of the semiconductor substrate,
The drain region of the MISFET is formed near the back surface of the semiconductor substrate,
The semiconductor device, wherein the base electrode is electrically connected to the source region. The semiconductor device according to claim 8.
A second insulating film is formed on the base electrode;
The semiconductor device according to claim 1, wherein a first opening reaching the base electrode is formed in the second insulating film in the first semiconductor substrate region. The semiconductor device according to claim 10.
The semiconductor device according to claim 1, wherein the first opening has a planar stripe shape. The semiconductor device according to claim 10.
The semiconductor device according to claim 1, wherein the first opening has a planar matrix shape. The semiconductor device according to claim 10.
The first semiconductor element is a transistor;
One said 1st electrode is electrically connected with the said some 1st semiconductor element, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
The base electrode includes copper;
A second insulating film is formed on the base electrode;
The second insulating film is mainly composed of a non-photosensitive polyimide resin,
A first opening reaching the base electrode is formed in the second insulating film in the first semiconductor substrate region,
A semiconductor device, wherein a first thin film that prevents diffusion of the copper into the second insulating film is formed on a surface of the base electrode. A diode element formed on the main surface of the semiconductor substrate;
A second electrode formed on the main surface of the semiconductor substrate and electrically connected to the diode element;
A semiconductor device having a plate-like electrode connected to the second electrode above the second electrode,
The second electrode includes a base electrode and a bump electrode formed in a third semiconductor substrate region on the base electrode,
The semiconductor device according to claim 1, wherein the bump electrode is made of solder. The semiconductor device according to claim 15, wherein
A second insulating film is formed on the base electrode;
A semiconductor device, wherein a first opening reaching the base electrode is formed in the second insulating film in the third semiconductor substrate region. A semiconductor device having a module in which a first semiconductor chip including a power transistor and a second semiconductor chip on which a diode is formed are electrically connected on a wiring board,
The first semiconductor chip includes a plurality of transistor elements formed on a main surface of a first semiconductor substrate;
A first electrode formed on a main surface of the first semiconductor substrate and electrically connected to the transistor element;
A first plate-like electrode connected to the first electrode at the top of the first electrode;
The first electrode includes a first base electrode and a first bump electrode formed in a first semiconductor substrate region on the first base electrode,
The first base electrode electrically connects the plurality of transistor elements to each other,
The second semiconductor chip includes a diode element formed on a main surface of a second semiconductor substrate;
A second electrode formed on a main surface of the second semiconductor substrate and electrically connected to the diode element;
A second plate-like electrode connected to the second electrode on the second electrode;
The second electrode includes a second base electrode and a second bump electrode formed in a third semiconductor substrate region on the second base electrode,
The semiconductor device according to claim 1, wherein the first bump electrode and the second bump electrode are made of solder. (A) forming a plurality of first semiconductor elements on a main surface of a semiconductor substrate;
(B) forming a first electrode electrically connected to the first semiconductor element on a main surface of the semiconductor substrate;
(C) connecting a plate electrode to the first electrode;
Including
The step (b)
(B1) forming a base electrode electrically connected to the plurality of first semiconductor elements on the main surface of the semiconductor substrate;
(B2) forming a first metal film in a first semiconductor substrate region on the base electrode;
(B3) forming a bump electrode on the first metal film;
(B4) heat-treating the semiconductor substrate, and forming an alloy layer of the first metal film, the base electrode, and the bump electrode between the base electrode and the bump electrode;
Including
The method of manufacturing a semiconductor device, wherein the bump electrode is formed of solder. The method of manufacturing a semiconductor device according to claim 18.
The method for manufacturing a semiconductor device, wherein the heat treatment in the step (b4) is performed at 300 ° C. or lower. The method of manufacturing a semiconductor device according to claim 18.
The method of manufacturing a semiconductor device, wherein the base electrode is formed mainly of nickel. The method of manufacturing a semiconductor device according to claim 18.
The method of manufacturing a semiconductor device, wherein the first metal film is formed using gold as a main component.

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