JP2005063275A - Integrated circuit layout device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit layout device and method capable of accurately analyzing crosstalks at the time of P&R (Place & Routing) in a higher hierarchy and preventing occurrence of crosstalks with a minimum area penalty. <P>SOLUTION: This device comprises a library reading section 101, a design rule reading section 102, a net list reading section 103, a boundary recognition section 104 recognizing a boundary wire of a block in a lower layer, and a lower layer recognition section 105 recognizing in an upper layer the boundary wire of the simplified lower layer block. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an integrated circuit layout apparatus and method for laying out an integrated circuit such as an IC or LSI, and more particularly to an integrated circuit layout apparatus and method for reducing the occurrence of interlayer crosstalk.

  Conventionally, when an LSI or the like is laid out, an automatic placement and routing method is used in which the layout (layout) of wiring is automatically determined using CAD or the like.

  In the automatic placement and routing method, in order to analyze and correct the crosstalk, the coupling capacity of the affected or giving side wiring is analyzed to take measures against noise and delay.

  As countermeasures, (1) spacing is provided so as not to be affected by other wirings (the wiring interval is widened), and (2) GND wiring is inserted between problematic wirings for shielding. (3) Various methods have been devised, such as adjusting the driving ability of the Agressor or Victim line. As an example of such a method, there is a “layout verification apparatus” disclosed in Patent Document 1.

  In the case of flat layout as in the invention described in Patent Document 1, there is no problem with the conventional method, but attention should be paid to lower layer wiring recognition and the like when the hierarchical layout is reached.

As a related art related to the present invention, there is a “semiconductor device” disclosed in Patent Document 2. The invention described in Patent Document 2 avoids the occurrence of crosstalk in the upper layer by providing a wiring prohibited area in advance in the lower layer block when the hierarchical layout is performed.
JP 2003-044540 A JP 2002-270775 A

  However, since the invention described in Patent Document 2 does not consider actual wiring when constructing a lower hierarchy, a wiring prohibited area is set even for an area that is not necessary.

  Hierarchical layout has larger layout restrictions than planar layout, such as the need to set a channel region. Therefore, when an integrated circuit is laid out according to the invention described in Patent Document 1, the chip size increases, and the integrated circuit The manufacturing cost will be high.

  SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an integrated circuit layout apparatus capable of accurately analyzing crosstalk during P & R (Place & Routing) in an upper layer and preventing occurrence of crosstalk with a minimum area penalty. It aims to provide a method.

  In order to achieve the above object, according to a first aspect of the present invention, there is provided a device for laying out a wiring pattern of an integrated circuit having a laminated structure, and reading means for reading a library and rules for laying out the wiring pattern. Means for reading a netlist, boundary recognition means for recognizing a boundary wiring of a lower layer block, and means for recognizing a simplified boundary wiring of a lower layer block in an upper layer. An integrated circuit layout apparatus is provided.

  In the first aspect of the present invention, when the lower layer block is any one of RAM, ROM, CPU, PLL, and I / O cell, the boundary recognition means preferably recognizes these boundaries.

  Further, in the first aspect of the present invention described above, in the lower layer block, the spacing measuring means for measuring the spacing with the boundary, and the block can be shielded based on the output of the spacing measuring means. In the case where shielding is possible in the block, it is preferable to perform shielding in the block and permit wiring in an upper layer.

  In order to achieve the above object, according to a second aspect of the present invention, there is provided a method for laying out a wiring pattern of an integrated circuit having a laminated structure, the step of reading a netlist, the step of reading a library, and the wiring pattern A step of reading a rule for laying out a layout, a step of performing placement and routing on a lower layer, a boundary recognition step of recognizing a boundary wiring of a block placed and routed on the lower layer, and a recognition in the boundary recognition step Storing the shape data based on the boundary wiring in the storage means, setting the wiring prohibited area in the shape data stored in the storage means, and storing the data in the storage means, and in the upper hierarchy A layout method of an integrated circuit, comprising: a step of performing placement and routing while avoiding a wiring prohibited area It is intended to provide.

  In the second aspect of the present invention, when the lower layer block is any of RAM, ROM, CPU, PLL, and I / O cell, it is preferable to recognize these boundaries in the boundary recognition step.

  In the second aspect of the present invention, in the lower layer block, the spacing with the boundary is measured to determine whether the block can be shielded, and the block can be shielded. In some cases, it is preferable to perform shielding in the block and allow wiring in the upper layer.

  In order to achieve the above object, according to a third aspect of the present invention, there is provided a method for laying out a wiring pattern of an integrated circuit having a laminated structure, the step of reading a netlist, the step of reading a library, and the wiring pattern A step of reading a rule for laying out the layout, and then, a placement and routing step for placing and routing the lowermost layer, a boundary recognition step for recognizing the border wiring of the placed and routed block, and the boundary recognition A storage step of storing in the storage means the shape data based on the boundary wiring recognized in the step, and an interference prevention area setting step of setting a wiring prohibited area in the shape data stored in the storage means and storing in the storage means After that, for the layers other than the lowest layer, the wiring set in the layer lower than that layer After performing the interference prevention area recognition step for recognizing the stop area and performing placement and routing in the placement and routing step while avoiding the recognized wiring prohibition area in the interference prevention area recognition step, from the boundary recognition step to the interference prevention area setting step The present invention provides a method for laying out an integrated circuit, which is characterized in that a series of operations of performing the steps are performed in order from the lower layer.

  In the third aspect of the present invention, when the arranged and wired block is any of RAM, ROM, CPU, PLL, and I / O cell, it is preferable to recognize these boundaries in the boundary recognition step.

  Further, in the third aspect of the present invention, on the basis of the spacing measurement step for measuring the spacing with the boundary in the arranged and routed block, and the output of the spacing measurement step, after the storing step, And determining whether or not shielding is possible in the block. When shielding is possible in the placed and routed block, in the interference prevention area setting step, a wiring prohibited area is set in the block. It is preferable to perform shielding instead.

  According to the present invention, it is possible to provide an integrated circuit layout apparatus and method capable of preventing the occurrence of crosstalk with a minimum area penalty.

The present invention makes it possible to accurately and rapidly analyze crosstalk at the time of P & R in an upper hierarchy by recognizing the boundary wiring of a lower hierarchy block at the time of hierarchical layout. This prevents the occurrence of crosstalk violations with a minimum area penalty even during hierarchical layout.
Hereinafter, preferred embodiments of the present invention will be described.

FIG. 1 shows a configuration of an integrated circuit layout apparatus according to the present invention. The integrated circuit layout device 100 includes a library reading unit 101, a design rule reading unit 102, a netlist reading unit 103, a boundary recognition unit 104, a lower layer recognition unit 105, a control unit 106, and a database 107.
The library reading unit 101 does not show information registered as a unit (inverter, flip-flop, NAND, etc.) for designing an integrated circuit for standard cells, I / O cells, RAM, ROM, CPU, PLL, etc. Information recording means (HDD, information recording medium reader, etc.). The design rule reading unit 102 acquires a rule for laying out the wiring pattern from an information recording unit (not shown). The net list reading unit 103 acquires a net list expressing circuit diagram data in a text format from an information recording unit (not shown). The boundary recognition unit 104 detects and recognizes the wiring arranged at the block boundary. The lower layer recognition unit 105 determines whether or not crosstalk occurs with a lower layer wiring pattern. The control unit 106 controls the operation of each unit of the integrated circuit layout device 100 to execute a process for laying out the integrated circuit. The database 107 stores information necessary for laying out the wiring pattern of the integrated circuit.

FIG. 2 shows an example of a preferred operation of the integrated circuit layout apparatus 100.
First, the control unit 106 reads the net list created by the designer into the integrated circuit layout device 100 using the layout reading unit 103 (step S1). Assuming a hierarchical layout, the top net may be read as the net list, or the net list of only the lower hierarchy may be read.

Next, the control unit 106 reads the design rule of the process to be actually used into the integrated circuit layout device 100 using the design rule reading unit 102. Further, the control unit 106 reads the library of the hard macro such as the standard cell, I / O cell, and RAM into the integrated circuit layout device 100 using the library reading unit 101 (step S2).
Next, the control unit 106 executes placement and routing of the lower layer block (step S3).
The placement and routing here is created based on the prior art so that no crosstalk violation occurs in the block.

  Next, after the block placement and routing is completed, the control unit 106 extracts all the wirings related to the boundary using the boundary recognition unit 104 (step S4). As a method for extracting wiring related to the boundary, a plurality of methods can be applied. For example, all of those having coupling capacitance when higher-level wiring runs in parallel along the boundary are extracted.

  In this case, as shown in FIG. 3, the case where the signal line in the block affects the signal line outside the block and the case where the signal line in the block is influenced by the signal line outside the block are considered. . Of course, the extraction is performed in consideration of the wiring layer of the block. The extraction target may be set like a design rule, or may be sequentially analyzed at the time of extraction.

  Next, the control part 106 preserve | saves the extracted content in the database 107 (step S5). In the database 107, a portion not related to the crosstalk with the upper wiring in the block is completely hollowed out, and data indicating a shape like a donut model is saved, so that the data amount is reduced and the upper layer is saved. Analyzes and corrections are speeded up.

  Next, the control unit 106 sets a wiring prohibited area for the area indicated by the information stored in the database 107 in step S5 (step S6). Here, the wiring layer of the internal block is recognized, and the minimum area penalty is set so that there is no influence of coupling even in the wiring prohibited area. An example of this is shown in FIG.

  Thereafter, placement and routing are performed in the upper hierarchy based on the information stored in the database in step S6 (step S7). At this point, since an appropriate wiring prohibition area is already set at the boundary with the hierarchical block, the control unit 106 recognizes the wiring prohibition area set in the lower layer using the lower layer recognition unit 105. Therefore, the technique according to the conventional technique can be applied.

  With the above procedure, in automatic placement and routing with a lower hierarchy, it is possible to take measures against crosstalk in consideration of the boundary with the lower hierarchy during layout of the upper hierarchy, and automatic placement with accurate and high-speed crosstalk countermeasures Wiring becomes possible.

  As described above, according to the present invention, the boundary wiring of the lower layer block is recognized at the time of the hierarchical layout, so that the crosstalk can be accurately and quickly analyzed at the time of P & R in the upper layer, the area penalty can be reduced, and the minimum Can be improved. As a result, the wiring can be laid out without causing a crosstalk violation even in the hierarchical layout.

In addition, the said Example is an example of the suitable implementation of this invention, and this invention is not limited to this.
For example, the present invention is applicable even if the lower layer block is a hard macro or I / O. Further, if there is a shieldable area between the line related to the boundary and the boundary, the wiring prohibited area may not be set by performing shielding within this block. In this case, the area penalty can be further reduced. For shielding, a method of widening the interval between the extracted wiring and the boundary, or a method of arranging a ground line between the extracted wiring and the boundary can be applied.
As described above, the present invention can be variously modified.

It is a figure which shows the structure of the integrated circuit layout apparatus which concerns on this invention. 4 is a flowchart showing a flow of operation of the integrated circuit layout device according to the present invention. It is a figure which shows the example of the wiring to extract. It is a figure which shows the example of a setting of a wiring prohibition area | region.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Integrated circuit layout apparatus 101 Library reading part 102 Design rule reading part 103 Net list reading part 104 Boundary recognition part 105 Lower layer recognition part 106 Control part 107 Database

Claims (9)

An apparatus for laying out a wiring pattern of an integrated circuit having a laminated structure,
Means to load the library,
Means for reading the rules for laying out the wiring pattern;
Means to read the netlist,
Boundary recognition means for recognizing the boundary wiring of the lower layer block;
Means for recognizing the simplified lower layer block boundary wiring in the upper layer;
An integrated circuit layout apparatus comprising:   2. The integrated circuit layout according to claim 1, wherein when the lower layer block is one of a RAM, a ROM, a CPU, a PLL, and an I / O cell, the boundary recognition means recognizes these boundaries. apparatus. A spacing measuring means for measuring a spacing with a boundary in the lower layer block;
Means for determining whether or not shielding is possible in the block based on the output of the spacing measuring means;
3. The integrated circuit layout device according to claim 1, wherein if the block can be shielded, shielding is performed in the block and wiring in the upper layer is permitted. A method of laying out a wiring pattern of an integrated circuit having a laminated structure,
Reading the netlist,
Loading the library,
Reading the rules for laying out the wiring pattern;
Performing placement and routing for the lower layer;
A boundary recognition step for recognizing the boundary wiring of blocks placed and routed in the lower layer;
Storing shape data based on the boundary wiring recognized in the boundary recognition step in a storage means;
An interference prevention area setting step for setting a wiring prohibited area in the shape data stored in the storage means and storing the wiring prohibited area in the storage means;
And a step of performing placement and routing while avoiding the wiring prohibition region in an upper layer.   5. The integrated circuit according to claim 4, wherein when the lower layer block is one of a RAM, a ROM, a CPU, a PLL, and an I / O cell, the boundary is recognized in the boundary recognition step. Layout method. In the lower block, measure the spacing with the boundary to determine whether shielding is possible in the block;
6. The integrated circuit layout method according to claim 4, wherein if the block can be shielded, shielding is performed in the block and wiring in the upper layer is permitted. A method of laying out a wiring pattern of an integrated circuit having a laminated structure,
Reading the netlist,
Loading the library,
Read the rules for laying out the wiring pattern,
Then, for the lowest layer,
A placement and routing step for placement and routing;
A boundary recognition step for recognizing the boundary wiring of the placed and routed block;
A storage step of storing, in a storage means, shape data based on the boundary wiring recognized in the boundary recognition step;
Setting a wiring prohibition area in the shape data stored in the storage means, and performing an interference prevention area setting step of storing in the storage means;
After that, about the hierarchy other than the lowest layer,
An interference prevention area recognition step for recognizing a wiring inhibition area set in a hierarchy lower than that hierarchy is executed, and in the placement and routing step, placement and routing is performed while avoiding the recognized wiring inhibition area in the interference prevention area recognition step. A method for laying out an integrated circuit, wherein a series of operations of performing each step from the boundary recognition step to the interference prevention region setting step is performed in order from the lower layer.   8. The integrated circuit according to claim 7, wherein when the arranged and wired block is any one of a RAM, a ROM, a CPU, a PLL, and an I / O cell, the boundary is recognized in the boundary recognition step. Layout method. After the storing step, a spacing measuring step for measuring a spacing with a boundary in the placed and routed block;
Determining whether shielding is possible in the block based on the output of the spacing measurement step;
9. If shielding is possible in the arranged and wired block, in the interference preventing area setting step, shielding is performed instead of setting the wiring prohibited area in the block. An integrated circuit layout method as described.

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