JP2005050088A - High speed dual system controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high speed dual system controller whose control cycle is extremely short(about 10msec) for continuously using internal data under an arithmetic operation from a main system to a slave system or counter data as they are, and for smoothly switching the dual systems without causing the fluctuation of a command value in the controller. <P>SOLUTION: This high speed dual system controller 10 is provided with main system and slave system control units 12 and 13 and a main/slave selecting module 20 for selecting any of those control units. The main and slave system control units 12 and 13 are provided with a dual port memory 14 and a control arithmetic unit 15, respectively. The main system and slave system dual port memories 14 are made to share control data in a real time. Also, the main and slave system control arithmetic units 15 are made to perform the same control arithmetic operation on the basis of the control data of its own dual port memory. Furthermore, the abnormality of the main system/slave systems can be quickly monitored and decided by a main/slave selection module 20, and when any of those systems is abnormal, the normal system is switched to the main system. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a high-speed dual system control apparatus that includes a main system and a subordinate control apparatus, and immediately switches to the other control apparatus when an abnormality occurs and continues control. The present invention relates to a gas turbine control device.

  In order to increase the reliability of the control device, a multiplex system control device including a plurality of control devices has been conventionally proposed (for example, Patent Documents 1 to 4).

  As shown in FIG. 3, the “operational abnormality monitoring system” of Patent Document 1 is a transmittable pulse generating circuit that outputs a pulse signal when a main central processing unit 51 can transmit in a dual central processing unit. 55, a main serial transmission line 54 that is connected to the central processing unit and transmits a transmission signal, a transmission enable notification line 58 that is connected to the digital output unit 56 and transmits a transmittable signal, and an input pulse signal And a plurality of local processing devices 53 having a pulse monitoring circuit 57 for monitoring the abnormality of the main central processing unit 51.

  The “triple fault tolerant system data changing method” of Patent Document 2 includes, as shown in FIG. 4, first to third units 61, 61, 63 connected in parallel, and a period is changed from an input / output unit 64 of each unit. In the triple fault tolerant system in which the plant data of each system inputted in the system is computed by the control computation unit 65, the computation result of each system is majority processed and periodically output to the operation system of the plant. Are connected to each other by a data change motivation signal line 66, and after each unit receives change data from an external man-machine interference fence 67, all units are connected via the synchronization signal line 66. A synchronization signal is output to 61, 62, 63, all units are synchronized, and the control data is changed by the change data.

  As shown in FIG. 5, the “backup apparatus and method” of Patent Document 3 has a built-in disk device 73 in each of the current machine 71 and the spare machine 72. Also, a shared disk device 74 is provided, and the same content as that of the built-in disk device is written to make a duplex configuration. The current organic reads from the built-in disk device with a short access time, and writes the result of message processing and takeover information to the shared disk and its own built-in disk. When a failure occurs in the active machine, the spare machine takes over the contents of the failed active machine by reading the takeover information from the shared disk device. Further, the spare machine copies the contents of the shared disk device to its own internal disk device.

  As shown in FIG. 6, “Redundant Control Memory Redundancy Method” of Patent Document 3 is a system in which a failure occurs in the hardware circuit group 83 of the active control device 81 during diagnosis of the standby control device 82. Then, the occurrence of this failure is detected by the failure monitoring circuit 84, and a failure detection signal and an alarm are generated from the failure monitoring circuit 84, respectively. The alarm input to the CPU 85 is received as a mate alarm by the CPU 86, and the diagnosis of the control device 82 is stopped based on the control of the CPU 86. The output signal of the external gate 87 to which the failure detection signal is input switches the copy memory selection circuit 88 to select the output storage data of the test memory circuit 89. As a result, data stored in the control memory 90 during normal operation of the control device 81 written in the test memory circuit 89 is read out and written in the control memory 91.

Japanese Patent No. 3324355 (Japanese Patent Laid-Open No. 9-084156) JP 2000-66912 A JP-A-6-175788 JP-A-8-305594

In the conventional multiplex system control device described above, a plurality of control devices are provided with different storage devices, but there is a problem that at least several hundred msec or more is required to synchronize data in each storage device. It was.
That is, in a control device such as a gas turbine that operates at high speed, the control cycle is as short as about 10 msec, and even when switching from the main system to the sub system in this control cycle, internal data and counter data being calculated in the control device Can be used as they are, and the command value does not change and needs to be switched smoothly.
However, in the conventional multiplex system control device described above, the slave control device receives the normal operation signal from the master system control device, and when this is cut off, the control is switched to the slave control device. Cannot be used in a time shorter than the control cycle (about 10 msec), and there is a problem that this requirement cannot be satisfied.

  The present invention has been developed to solve such problems. That is, the object of the present invention is to use the internal data and the counter data being calculated from the master system to the slave system as they are in a control apparatus having a very short control cycle (about 10 msec). It is an object of the present invention to provide a high-speed dual system control device that can be switched smoothly without fluctuation in value.

According to the present invention, there is provided a high-speed dual system control device including a master system and a slave control unit, and a master / slave selection module for selecting one of the control units,
The master and slave control units each have a dual port memory and a control arithmetic unit,
The master and slave dual port memories share control data in real time,
The master and slave control operation units perform the same control operation based on the control data of their dual port memory,
A high-speed dual system controller characterized by monitoring and judging main / subordinate abnormalities at high speed with the master / subordinate selection module, and switching to the main one when both are abnormal. Provided.

  According to a preferred embodiment of the present invention, each of the dual port memories has a self-system memory area and another system memory area, and one self-system memory area and the other system memory area are connected by an optical cable. The data in the system memory area is overwritten in the other system memory area at intervals shorter than the control cycle.

  The master control arithmetic unit reads the control data from its own memory area, overwrites the control data in its own memory area, and the slave control arithmetic unit reads the control data from its own slave memory area. It is preferable to overwrite the control data in the own memory area.

According to the configuration of the present invention described above, the master and slave dual port memories share the control data in real time, so if any one of them is abnormal, the normal one is switched to the master. Internal data and counter data being calculated from the system to the slave system can be used as they are.
In addition, each dual port memory has its own memory area and other memory area. One own memory area and the other other memory area are connected by an optical cable, and the data in the own memory area is transferred from the control cycle. Since the other system memory area is overwritten at a short interval (for example, several μsec), the control data in the other system memory area can always be held in the main system control data, and the control data can be shared substantially in real time.

Therefore, the following effects can be obtained by the apparatus of the present invention.
(1) When the slave control unit is stopped and restarted, the same control calculation as that of the master system can be performed in a short time (for example, several μsec).
(2) When a part of the input of the main system is defective, the input data of the sub system can be used.
(3) The determination of normal operation can be strengthened by using data other than the normal operation signal.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In each figure, common portions are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a schematic diagram of a high-speed dual system controller of the present invention. In this figure, a high-speed dual system control apparatus 10 according to the present invention includes a main and subordinate control units 12 and 13, and a main and slave selection module 20 that selects one of the control units 12 and 13.
The high-speed dual system control device 10 is a control device such as a gas turbine that operates at high speed, for example, and receives data such as temperature, flow rate, pressure, and the like from a plurality of sensors (not shown), and an actuator 1 (control valve, etc.) It is a dual system gas turbine control device adapted to control. In the case of a gas turbine control device, the control cycle is about 10 msec.

  In FIG. 1, the high-speed dual system control apparatus 10 of the present invention further includes two selectors 4. The outputs of the two control units 12 and 13 are input in parallel to each selector 4 and output to the same actuator 1 respectively. Further, the two selectors 4 are controlled by the master / slave selection module 14 so as to select and output only one of the outputs of the two control units 12 and 13.

  The master / slave selection module 20 monitors and determines the abnormality of the two control units 12 and 13 of the master system and the slave system at a high speed, and when one of them is abnormal, switches the normal one to the master system. Therefore, the main system and the slave system are reversed by this switching. For example, in FIG. 1, if 12 is the master system and 13 is the slave system, 12 is the slave system and 13 is the master system after switching. In the following description, 12 is the main system and 13 is the subordinate system.

  In FIG. 1, the main and subordinate control units 12 and 13 each have a dual port memory 14 and a control arithmetic unit 15 (CPU). The master and slave dual port memories 14 share control data in real time. Further, the master and slave control arithmetic units 15 perform the same control calculation based on the control data of their own dual port memory 14.

FIG. 2 is a block diagram of the high-speed dual system controller 10 of the present invention. As shown in this figure, the dual port memory 14 has a self-system memory area 14a and another system memory area 14b, respectively. The dual port memory 14 is provided on the same substrate.
In addition, one local memory area 14a and the other secondary memory area 14b are connected by two optical cables 16, and data in the local memory area 14a is transmitted at an interval shorter than the control cycle (for example, about 2 μsec, 8 byte transfer). The other memory system area 14b is overwritten.

In the high-speed dual system controller 10 of the present invention, the main control arithmetic unit 12 reads the control data from its own memory area 14a and overwrites the control data in the own memory area 14a. Therefore, when the actuator 1 is controlled by the main control arithmetic unit 12, the actuator can always be controlled with the latest control data.
On the other hand, the secondary control arithmetic unit 13 reads the control data from its own secondary memory area 14b and overwrites the control data in the local memory area 14a. Therefore, when the actuator 1 is controlled by the main control arithmetic unit 12, the latest control data (main system own memory area 14a) can always be held in the sub system other memory area 14b. Control data can be shared in real time.

  For example, in the writing process, the oldest data is determined from the sequence number and the shared data is updated, and in the reading process, the newest data is determined from the sequence number. get. Furthermore, it is preferable to protect the reading during writing by using the writing flag and to ensure the consistency of the write data by checksum.

  In the processing of communication errors, checksum errors and communication errors are monitored at each high-speed control calculation cycle in each board, and self-diagnosis is preferably performed when consecutive occurrences occur (for example, three times). By this self-diagnosis, when the substrate is abnormal, the abnormality signal is output, and when the other substrate is abnormal, the abnormality signal is output.

  In the communication down process, the communication down is monitored at a high-speed control calculation cycle, and an abnormal signal of communication down is output when the communication down occurs several times (for example, three times).

  Each abnormality signal is input to the master / slave selection module 20, and based on this, the abnormality of the two control units 12 and 13 of the master system and the slave system is monitored and judged at high speed, and the normal one is switched to the master system. Do.

As described above, according to the configuration of the present invention, the main and slave dual-port memories 14 share control data in real time. By switching, the internal data and counter data being calculated from the master system to the slave system can be used as they are.
The dual port memory 14 has a self-system memory area 14a and another system memory area 14b, respectively, and one self-system memory area and the other system memory area are connected by an optical cable, and data in the system memory area is stored. Since the other system memory area is overwritten at intervals shorter than the control cycle (for example, several μsec), the control data of the other system memory area of the slave system can always be held in the control data of the main system, and the control data is shared substantially in real time. it can.

  In addition, this invention is not limited to embodiment mentioned above, Of course, it can change variously in the range which does not deviate from the summary of this invention. For example, the present invention is not limited to a gas turbine control device, and can be freely applied to other devices.

It is a schematic diagram of the high-speed dual system control apparatus of this invention. It is a block diagram of the high-speed dual system control apparatus of this invention. 1 is a configuration diagram of Patent Document 1. FIG. It is a block diagram of patent document 2. FIG. It is a block diagram of patent document 3. FIG. It is a block diagram of patent document 4. FIG.

Explanation of symbols

1 Actuator, 4 Selector,
10 High-speed dual system controller, 12, 13 control unit,
14 Dual port memory,
14a own system memory area, 14b other system memory area,
15 control arithmetic unit (CPU),
16 optical cable, 20 master-slave selection module

Claims (3)

A high-speed dual system control device comprising a master system and a slave control unit, and a master / slave selection module for selecting one of the control units,
The master and slave control units each have a dual port memory and a control arithmetic unit,
The master and slave dual port memories share control data in real time,
The master and slave control operation units perform the same control operation based on the control data of their dual port memory,
A high-speed dual system controller characterized in that a master / slave selection module monitors / determines a master / slave abnormality at a high speed, and switches either of the normal ones to the master system if either is abnormal. Each of the dual port memories has its own memory area and another memory area,
One local memory area and the other external memory area are connected by an optical cable, and data in the local memory area is overwritten on the external memory area at intervals shorter than the control cycle. The high-speed dual system control device according to claim 1. The main control arithmetic unit reads control data from its own memory area, overwrites the control data in its own memory area,
3. The high-speed dual system controller according to claim 2, wherein the slave control arithmetic unit reads control data from its own slave memory area and overwrites the control data in the own memory area.

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