JP2005045085A - Method for exposure and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for exposure by which a resist pattern can be obtained with a high aspect ratio. <P>SOLUTION: The method for exposure includes a step of forming a resist 1 which is a photosensitive material on a substrate S in a prescribed thickness, and a step of exposing the resist 1 to light by changing the luminous exposure between a portion P1 of a resist pattern P to be formed and the peripheral section P2 of the resist pattern P at the time of forming a prescribed resist pattern P by exposing the resist 1 to the light. The method also includes a step of leaving the part of the resist 1 corresponding to the portion P1 of the resist pattern P with a sufficient height and, at the same time, slightly leaving the part of the resist 1 corresponding to the peripheral section P2 of the pattern P by developing the exposed resist 1. After the method for exposure, in addition, ion implantation and etching are performed on the substrate S through the resist 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an exposure method for forming a pattern having a predetermined shape by exposure to a photosensitive material formed on a substrate, and a method for manufacturing a semiconductor device.

  Conventionally, a resist made of a polymer resin is used as a mask in an ion implantation process in manufacturing a semiconductor device or a mask in a dry etching process in a semiconductor device or a micromachine. A mask pattern made of these resists is generally formed by using an optical lithography technique. In other words, a resist is spin-coated on the target substrate, the original pattern is exposed and transferred using an exposure device that uses a mercury lamp i-line (wavelength 365 nm) or a KrF excimer laser (wavelength 248 nm) as a light source, and then alkali development is performed. A desired resist pattern is formed by developing with a liquid.

  In the ion implantation process, the resist pattern used as a mask has a thickness sufficient to shield ions implanted into the substrate, and in the dry etching process, the resist pattern has a thickness sufficient to leave the resist when the substrate is etched. There is a need to.

  In recent years, with the fine integration of semiconductor devices, the size of the mask pattern in the ion implantation process has been reduced. Furthermore, formation of deep wells and the like requires high energy ion implantation of MeV class, and a thick resist is necessary to shield them.

  As the semiconductor device is finely integrated, in the dry etching process, only the mask pattern size is reduced while ensuring the thickness of the resist as a conventional mask.

  In addition, for the production of micromachines and optical waveguide chips, it is necessary to dig deeper into the substrate by several μm or more, and even if an inorganic film hard mask is used, the inorganic film must also be sufficiently thick. In order to etch the inorganic film, the resist needs to be sufficiently thick. Since the size of the micromachine and the optical waveguide chip is miniaturized, the two-dimensional size of the pattern is also reduced.

  For these reasons, there is an increasing demand for forming a resist pattern that is two-dimensionally small in size and thick. That is, it is necessary to form a resist with a high aspect ratio. However, in the optical lithography technology, the resist pattern collapses due to the surface tension of the rinsing liquid adhering in the rinsing process after development, or the pattern collapses due to insufficient defocus margin due to pattern miniaturization. It is difficult to form an aspect ratio resist pattern.

  Here, in Patent Document 1, from the viewpoint of preventing the resist from collapsing, the force applied to the resist pattern from the rinse liquid at the time of spin-drying is obtained by vaporizing a rinse liquid for washing away the developer after resist development in a reduced-pressure atmosphere. Techniques for reducing are disclosed.

JP-A-7-142301

  However, in the technique disclosed in Patent Document 1, it is necessary to place the rinse solution in a reduced-pressure atmosphere after resist development, which causes a problem of increasing the number of processing steps.

  The present invention has been made to solve such problems. That is, according to the present invention, when forming a predetermined pattern by exposing the photosensitive material to a predetermined thickness and exposing the photosensitive material to a predetermined thickness, the pattern material to be formed and the peripheral portion of the pattern are exposed. A step of performing exposure by changing the amount; and a step of developing the exposed photosensitive material to leave a photosensitive material corresponding to a pattern portion and a slight amount of a photosensitive material corresponding to a peripheral portion of the pattern. It is an exposure method. In addition, after performing this exposure method, it is also a method for manufacturing a semiconductor device in which ion implantation or etching is performed on the substrate through the remaining pattern.

  In the present invention, when the photosensitive material formed on the substrate is exposed to form a predetermined pattern, the photosensitive material is left slightly in the peripheral portion of the pattern together with the pattern. The remaining light-sensitive material supports the pattern. That is, since the supporting peripheral portion and the predetermined pattern are made of the same material, a high aspect ratio pattern can be formed on the substrate by utilizing these adhesion properties.

  In the present invention, since there is support around the predetermined pattern, for example, a resist pattern having an aspect ratio of 3 or more can be formed without pattern collapse. In addition, since the pattern and its support are made of the same photosensitive material, the subsequent processing is not affected, and the remaining photosensitive material does not have to be removed in a separate process, increasing the number of processes. Can be prevented. This makes it possible to reliably form a high aspect ratio resist pattern that serves as a mask for high energy ion implantation. It is also possible to form a high aspect ratio resist pattern that serves as a mask when dry etching a thick film.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view for explaining an exposure method according to this embodiment. That is, in the exposure method according to the present embodiment, when a predetermined pattern is formed by exposing the resist 1 which is a photosensitive material formed on the substrate S, the pattern portion P1 to be formed and the peripheral portion P2 of the pattern are formed. The exposure is performed by changing the exposure amount, and the resist 1 after the exposure is developed, thereby leaving the resist 1 corresponding to the pattern portion P1, and leaving the resist 1 corresponding to the peripheral portion P2 of the pattern slightly. This is a method of forming a pattern with a high aspect ratio while supporting the resist 1 in the slightly remaining peripheral portion P2.

  Specifically, the resist 1 of the portion P1 to be the pattern is formed thick by adjusting the light transmittance of the portion M1 and the background portion M2 corresponding to the pattern of the reticle M that is the original of the pattern to be formed, and the pattern By thinly forming the resist 1 in the peripheral portion P2, which is the background portion, and forming a resist pattern shape with a base as a whole, the resistance to lateral force due to surface tension during rinsing after development is enhanced. It is characterized by that.

  As an exposure method, first, as shown in FIG. 1A, a negative resist 1 is formed thickly on a substrate S. Next, for example, on a quartz substrate, a reticle M in which a translucent film is formed on a portion other than a desired fine pattern (background portion M2) is prepared, and exposed and transferred to the resist 1 using an exposure apparatus.

  As shown in FIG. 1B, the exposure amount from the portion M1 that becomes the pattern of the reticle M by this exposure transfer is large, and the exposure amount from the background portion M2 is small. Next, the substrate 2 is heated and cooled, and then developed using an alkaline developer, then rinsed with pure water, and the substrate S is dried.

  As a result, as shown in FIG. 1C, a resist pattern P having a high aspect ratio is formed, and the resist 1 is also formed in the background portion P2 of the resist pattern P in a thin state. That is, the resist 1 in the background portion P2 is the basis for the resist pattern P having a high aspect ratio.

  The background portion P2 has a large area in close contact with the substrate S with respect to the width of the resist pattern P and is integrally formed of the same material (resist 1) as the resist pattern P. It becomes very strong. Therefore, after the resist pattern P is formed, it is possible to reliably prevent the pattern from falling down that is likely to occur during the rinsing process.

  FIG. 2 is a diagram showing the relationship between the exposure amount when a negative resist is exposed with a bare glass reticle without a light-shielding film and the thickness of the negative resist formed after development. In this figure, the vertical axis represents the resist film thickness, and the horizontal axis represents the logarithm of the exposure amount. From this relationship, when the exposure amount for the negative resist is small, the negative resist is not crosslinked, and the film thickness after development becomes zero. On the other hand, when the exposure amount for the negative resist is increased, a part of the negative resist is crosslinked, and the film thickness after development is increased. When a certain amount of exposure is reached, the thickness becomes substantially the same as that of the negative resist formed, and even if the amount of exposure is increased further, the film thickness after development does not increase.

  Here, the optimum exposure amount for forming the desired resist pattern P is E0, and the film thickness of the negative resist formed after development is T0. Further, a desired thickness of the negative resist formed on the background portion P2 of the pattern is T1. Then, from the relationship shown in FIG. 2, in order to form a negative resist having a thickness T1, the background portion P2 of the pattern needs to be irradiated with light having an exposure amount E1. As described above, the transmissivity of the translucent film formed on the background portion M2 of the reticle M is Log (T1) / Log (T0). The transmissivity of the semitransparent film is proportional to the thickness of the translucent film and is adjusted by the film thickness.

  By performing exposure using such a reticle M, the exposure amount of the pattern portion P1 and the background portion P2 can be changed, and a resist pattern P having a height is formed in the pattern portion P1, The resist 1 can be left thin in the background portion P2.

  Even if the resist 1 remains thin in the background portion P2 in this way, it remains thin in the high energy ion implantation process in the manufacturing process of the semiconductor device or in the dry etching process of the thick film in the semiconductor device, micromachine, or the like. Since it is not necessary to consider the influence of the resist 1, it is not necessary to remove the resist 1 remaining in the background portion P2 in a separate process. Therefore, an increase in the number of processes as a whole can be prevented.

  The later process is a high energy ion implantation process, and when ions flying at a high energy are injected into a material, the energy is lost immediately before the ions stop. Therefore, even if the resist 1 remains thin in the background portion P2 of the pattern, ions can be implanted to the desired depth of the substrate S without any problem with almost no energy loss.

  In the step of dry etching the thick film, the thin film of the resist 1 in the background portion P2 of the pattern can be removed (breakthrough) at the initial stage of etching. At this time, a part of the upper part of the resist pattern P, which is originally a mask, is also etched, but the amount is small, so that the film to be etched can be etched leaving a sufficient resist film.

  Further, in the reticle M shown in FIG. 1, a semitransparent film is formed on the background portion M2 corresponding to the portion other than the resist pattern P to be formed, and the thin film of the resist 1 is left on the entire background portion P2 after exposure. However, using a reticle M as shown in FIG. 3A, the thin film of resist 1 may be left only in the peripheral portion P3 of the resist pattern P to be formed, as shown in FIG. 3B. .

  In this case, as the reticle M, the transmittance of the portion M1 corresponding to the resist pattern P is set to 100%, for example, and a translucent film is formed on the portion M2 corresponding to the peripheral portion where the thin film of the resist 1 is left. For example, it may be 30%, and the other portion M0 may be shielded with a chromium film or the like (transmittance 0%).

  Examples of the present invention will be described below. The first embodiment is a method of forming a resist mask for performing ion implantation for forming a retrograde n-well in a process of manufacturing a DRAM-embedded CMOS device having a triple well.

  FIG. 4 is a schematic plan view showing the DRAM cell array, in which an N-channel peripheral circuit a2 is arranged around the DRAM cell array a1. A retrograde n-well is formed only in the regions of the DRAM cell array a1 and the peripheral circuit a2. The width of the boundary separating the two regions is 0.5 μm.

  FIG. 5 is a schematic view showing a reticle corresponding to such a DRAM cell array and peripheral circuits. FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along line AA. In this reticle M, a translucent film is formed in a portion M3 corresponding to a portion where ion implantation is performed. The film thickness of the translucent film is obtained from the relationship between the exposure amount and the resist film thickness shown in FIG.

  FIG. 6 is a schematic cross-sectional view for sequentially explaining the exposure method of the first embodiment. First, as shown in FIG. 6A, a negative resist 1 made of a photosensitive material, a bisdiazide compound and a cyclized rubber resin, is applied on a substrate S to a thickness of 2 μm.

  Next, using an i-line reduction type exposure apparatus with an exposure wavelength of 365 nm, pattern exposure transfer is performed via the reticle M shown in FIG. The conditions at that time are NA = 0.6, σ = 0.5, and exposure time 200 sec.

  Further, in the reticle M shown in FIG. 5, the transmittance of the translucent film of the DRAM cell array and the portion M3 which becomes the peripheral circuit region is 30%, and the transmittance of the other regions is 100%. For the quartz substrate constituting the reticle M, a MoSiNO film is used as a translucent film. The film thickness is adjusted so that the transmittance is 30%.

  Next, the exposed substrate S is heated at 130 ° C. for 60 seconds, cooled, developed with a 2.38% TMAH alkaline developer, further rinsed with pure water, and dried. Thereby, the resist 1 having a thickness of 30 nm remains in the portion P2 corresponding to the DRAM cell array and the peripheral circuit as shown in FIG. 6C, and a resist pattern having a thickness of 2 μm can be formed in the other portion P1. become.

  In addition, when a conventional method of using a reticle in which the DRAM cell array and peripheral circuit area are completely shielded from light is used, no resist is formed in the DRAM cell array and peripheral circuit area (dissolves completely in the developer). The resist line pattern (corresponding to the P1 portion in this embodiment) between the cell array and the peripheral circuit region is collapsed during rinsing after development.

Next, 2 × 10 ¹³ (pieces / cm ² ) of 2 MeV phosphorus is implanted using the resist pattern created in this embodiment as a mask and using a high energy ion implantation apparatus. When the substrate S is properly annealed, a retrograde n-well can be formed only in desired regions (DRAM cell array a1 and peripheral circuit a2 shown in FIG. 4).

  In the second embodiment, when a CMOS image sensor having a light receiving portion made of an NMSO type photodiode is formed, a deep P well is formed so that a leak current does not flow from the photodiode to the substrate and other pixels. This is a method of forming a resist mask for high energy ion implantation.

  FIG. 7 is a schematic plan view showing four pixels of the CMOS image sensor. In the figure, reference numeral PD denotes an NMOS photodiode, reference numeral SG denotes a switching gate, and reference numeral FD denotes a floating diffusion.

  Each pixel is separated by element isolation. In FIG. 7, wirings, plugs and the like are omitted. The high energy ion implantation described above requires a resist pattern that masks the photodiode PD.

  FIG. 8 is a schematic diagram showing a reticle for forming a resist pattern applied by high energy ion implantation corresponding to the CMOS image sensor shown in FIG. Here, FIG. 8A is a plan view, and FIG. 8B is a sectional view taken along the line BB in FIG. In this reticle M, the transmittance of the portion M5 corresponding to the photodiode is adjusted to 100%, and the transmittance of the other portion M6 formed with the semitransparent film is adjusted.

  In the second embodiment, the reticle M is exposed to form a thick resist pattern in a portion corresponding to the photodiode, and a thin resist is left in the other portion, so that a high aspect ratio resist is formed. -Configure the pattern.

  First, a negative resist made of a photosensitive material, a bisdiazide compound and a cyclized rubber resin, is applied to a substrate by 6 μm. Then, using an i-line reduction type exposure apparatus having an exposure wavelength of 365 nm, a reticle M pattern as shown in FIG. 8 is exposed and transferred. The conditions at that time are NA = 0.45, σ = 0.5, and exposure time 230 sec.

  In the reticle M shown in FIG. 8, the portion M5 corresponding to the photodiode has a transmittance of 100%, and the other portion M6 has a transmittance of 35%. As the reticle M, a translucent MoSiNO film is formed in a region other than the photodiode using a quartz substrate. The film thickness is adjusted so that the transmittance is 35%.

  Next, the substrate is heated at 130 ° C. for 60 seconds, cooled, developed with a 2.38% TMAH alkaline developer, further rinsed with pure water, and dried. Thereby, a resist pattern P as shown in FIG. 9 can be formed. That is, a resist pattern P of 2 μm × 2 μm and a thickness of 6 μm can be formed in the region corresponding to the photodiode without pattern collapse, and a resist with a thickness of 50 nm remains in the other portion P2.

Next, 1 × 10 ¹² (pieces / cm 2) of 4.5 MeV boron is implanted using the resist pattern P formed by exposure and development as a mask, using a high energy ion implantation apparatus. Thereafter, when the substrate S is appropriately annealed, a deep P well is formed only in the region other than the photodiode.

  A cantilever has been proposed as part of a micromachine system component. Example 3 is a method for creating the arm portion of the cantilever.

  First, as shown in FIG. 10, a silicon oxide layer 12 is formed on a silicon substrate S1, and a silicon film 13 having a thickness of 1 μm is further formed. Furthermore, a negative resist 14 made of a bisdiazide compound, which is a photosensitive material, and a cyclized rubber resin is applied thereon with a thickness of 3 μm.

  Then, using an i-line reduction type exposure apparatus with an exposure wavelength of 365 nm, a pattern is exposed and transferred using a reticle M as shown in the schematic diagram of FIG. FIG. 11A is a plan view of the reticle, and FIG. 11B is a sectional view taken along the line CC of FIG. In this reticle M, the transmittance of the portion M7 corresponding to the arm of the cantilever is set to 100%, and a translucent film is formed in the other portion M8.

  The exposure conditions using this reticle M are NA = 0.5, σ = 0.5, and exposure time 200 sec. In the reticle M shown in FIG. 11, the transmittance of the portion M7 corresponding to the arm of the cantilever is 100%, and the transmittance of the other portion M8 is 30%. The cantilever arm has a length of 10 μm and a width of about 0.7 μm. In the reticle M, a MoSiNO film that is translucent is formed on a quartz substrate at a portion corresponding to M8. The film thickness is adjusted so that the transmittance is 30%.

  Next, after exposing and developing the resist 14, the silicon substrate S1 is heated at 130 ° C. for 60 seconds, cooled, developed with a 2.38% TMAH alkaline developer, further rinsed with pure water, and dried. Thereby, a resist pattern P as shown in FIG. 12 is formed. The resist pattern P does not collapse, and the resist 14 having a thickness of 3 μm remains in the peripheral portion P2. Further, the resist pattern P remains in a state where the resist 14 having a thickness of 40 nm remains.

  Next, as shown in FIG. 13A, the resist 14 is etched back, and the thin film resist in the peripheral portion of the resist pattern P is removed. At this time, the thick resist pattern P is also scraped by 40 nm. For the etching, a parallel plate type etching apparatus is used, and oxygen and argon are used as the gas.

  Subsequently, as shown in FIG. 13B, the silicon film 13 is etched using the resist pattern P as a mask using the same etching apparatus. At this time, hydrogen bromide or oxygen is used as the gas. Then, when the remaining resist 14 is removed using a stripping solution, a cantilever arm made of the silicon film 13 as shown in FIG. 13C can be formed.

  In the embodiments and examples described above, the negative photosensitive material is mainly used as the photosensitive material made of the resist 1, but the present invention can be applied even if a positive photosensitive material is used. In this case, the balance of the exposure amount between the pattern forming portion and its peripheral portion is reversed from that in the negative type. For example, the reticle on the part where the pattern is to be formed is shielded from light (transmittance 0%), and a translucent film is formed on the reticle corresponding to the peripheral part to achieve a transmittance of about 70%. As a result, a resist pattern is formed in the portion with 0% transmittance, and a resist thin film remains in the peripheral portion with a transmittance of about 70%, and the high aspect ratio resist pattern is supported by the resist thin film in the peripheral portion. Will be able to.

It is a schematic cross section explaining the exposure method according to the present embodiment. It is a figure which shows the relationship between the exposure amount and the resist thickness formed after image development. It is a schematic diagram explaining the example of another reticle. It is a schematic plan view which shows a DRAM cell array. FIG. 3 is a schematic diagram showing a reticle corresponding to a DRAM cell array and peripheral circuits. It is a schematic cross section explaining the exposure method of Example 1 in order. FIG. 3 is a schematic plan view showing four pixels of a CMOS image sensor. It is a schematic diagram which shows the reticle applied with a CMOS image sensor. It is a schematic cross section which shows the resist pattern formed. It is a schematic cross section explaining the manufacturing process of a cantilever (the 1). It is a schematic diagram which shows the reticle applied by manufacture of a cantilever. It is a schematic cross section explaining the manufacturing process of a cantilever (the 2). It is a schematic cross section explaining the manufacturing process of a cantilever (the 3).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Resist, M ... Reticle, P ... Resist pattern, S ... Substrate, S1 ... Silicon substrate, 12 ... Silicon oxide layer, 13 ... Silicon film, 14 ... Negative resist

Claims (5)

Forming a photosensitive material with a predetermined thickness on a substrate;
In the exposure of the photosensitive material to form a predetermined pattern, a step of performing exposure by changing the exposure amount between the pattern portion to be formed and the peripheral portion of the pattern;
And developing the photosensitive material after exposure to leave a photosensitive material corresponding to the pattern portion and a slight amount of the photosensitive material corresponding to the peripheral portion of the pattern. . When a negative resist is used as the photosensitive material, exposure is performed with a first exposure amount corresponding to a portion where the pattern is formed, and a first exposure amount which is smaller than the first exposure amount corresponding to a peripheral portion of the pattern. The exposure method according to claim 1, wherein the exposure is performed with an exposure amount of 2. When a positive resist is used as the photosensitive material, exposure is performed with a first exposure amount corresponding to a portion where the pattern is to be formed, and a first exposure amount which is greater than the first exposure amount corresponding to a peripheral portion of the pattern. The exposure method according to claim 1, wherein the exposure is performed with an exposure amount of 2. Forming a photosensitive material with a predetermined thickness on a substrate;
In the exposure of the photosensitive material to form a predetermined pattern, a step of performing exposure by changing the exposure amount between the pattern portion to be formed and the peripheral portion of the pattern;
Developing the photosensitive material after exposure, leaving a photosensitive material corresponding to the pattern portion, and leaving a slight photosensitive material corresponding to the peripheral portion of the pattern; and
By performing ion implantation on the substrate using the photosensitive material after development as a mask, the photosensitive material corresponding to the pattern portion prevents ions from entering the substrate and remains slightly in the peripheral portion of the pattern. A method of manufacturing a semiconductor device, comprising: a step of allowing ions to pass through the photosensitive material and allowing ions to enter the substrate. Forming a photosensitive material with a predetermined thickness on a substrate;
In the exposure of the photosensitive material to form a predetermined pattern, a step of performing exposure by changing the exposure amount between the pattern portion to be formed and the peripheral portion of the pattern;
Developing the photosensitive material after exposure, leaving a photosensitive material corresponding to the pattern portion, and leaving a slight photosensitive material corresponding to the peripheral portion of the pattern; and
Etching of the substrate with the developed photosensitive material as a mask prevents etching of the substrate in the photosensitive material corresponding to the pattern portion, and in the photosensitive material slightly remaining in the peripheral portion of the pattern And a step of etching the substrate at a position corresponding to the portion of the photosensitive material after the etching of the portion of the photosensitive material.

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