JP2005044386A - Semiconductor storage device and microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize an increase of a chip area caused by the addition of an ECC (Error Check and Correct) function. <P>SOLUTION: When a semiconductor storage device includes; a memory mat section (10) in which a plurality of memory mats which are accessed in the largest bit width unit in the valid bit width modifiable according to designation from outside have been arranged and; an indirect peripheral circuit (20) shared with the plurality of memory mats, the indirect peripheral circuit is structured by including an ECC function block circuit (21) for error correction based on a hamming code and a data size alignment circuit (23) which performs data size alignment process according to the valid bit width specified from the outside. A bit configuration of a test mat is reduced by enabling an access to a memory mat with the largest bit width unit in a valid bit width modifiable according to a designation from the outside by setting a data size alignment circuit in a direct peripheral circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an error correction technique in a semiconductor memory device such as an SRAM (Static Random Access Memory), and more particularly to a technique effective when applied to a microcomputer including an SRAM.
[0002]
[Prior art]
In a semiconductor memory device, countermeasures against soft errors due to α rays are important. Soft error caused by alpha rays is a phenomenon that destroys data by alpha rays (He nuclei) contained in cosmic rays and alpha rays emitted from radioactive atoms contained in LSI package resin etc. entering the memory cell. It is.
[0003]
An SRAM, which is an example of a semiconductor memory device, uses a flip-flop circuit as a memory cell memory element, and therefore has a structure that is more resistant to soft errors caused by alpha rays than a DRAM (dynamic random access memory) or the like. It has become. However, the resistance to soft errors due to α rays is decreasing as the memory cell area is reduced to increase the capacity and speed of the SRAM, and the operating voltage is reduced to reduce the power consumption of the system. In some cases, it may be necessary to take measures to improve resistance to soft errors due to α rays. In particular, soft errors due to α rays in control microcomputers mounted on automobiles are items that must be eliminated.
[0004]
A highly reliable industrial computer is devised so as not to cause a failure, and even if a failure occurs, if the failure is mild, the process is continued and preventive maintenance is performed before a serious failure occurs. It is necessary to have. In order to meet such a request, for example, in the case of a memory single bit error, conventionally, the data read by the ECC correction mechanism is corrected and the corrected data is written to the memory, and when a single bit error occurs again at the same memory address, the element It is known that a diagnosis means for determining a failure is provided (for example, see Patent Document 1). Furthermore, a technique is known that makes it possible to diagnose a memory element failure in a general-purpose computer that does not have a special mechanism such as an additional mechanism for writing ECC-corrected data.
[0005]
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2000-207291 (second paragraph, FIG. 6)
[0006]
[Problems to be solved by the invention]
In order to apply the ECC function to the SRAM, an inspection memory mat for storing data (hamming code) for correcting a memory error, an ECC function block for detecting and correcting a hamming code generation and a memory error are required. The inventor of the present invention has examined the application of these to conventional SRAMs, and found that the area of the SRAM module is greatly increased. For example, in the case of an SRAM having a capacity of 16 kbytes (4 kbytes × 4 mats), the configuration of one mat is 1k words × 32 bits. Furthermore, this SRAM has a data size alignment function for changing the data size such as 32-bit input / output as bytes (8 bits), words (16 bits), and long words (32 bits). Therefore, in order to apply the ECC function to this SRAM, an ECC inspection mat is required in units of bytes (8 bits), which is the minimum unit of data size. The ECC check bits required for 8 input / output bits are 4 bits by single bit error correction, and 16 bits are required for 1 mat. Further, the entire module requires 64 bits in a size of 16 bits × 4 mats. For this reason, the area of the SRAM module increases to 1.5 times that when the ECC function is not provided.
[0007]
An object of the present invention is to provide a technique for minimizing an increase in chip area accompanying the addition of an ECC function.
[0008]
Another object of the present invention is to provide a technique for enabling error detection and correction without degrading high speed.
[0009]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0011]
That is, a memory mat portion in which a plurality of memory mats accessed in units of the maximum bit width in an effective bit width that can be changed according to designation from the outside are arranged, and an indirect peripheral circuit shared by the plurality of memory mats A semiconductor memory device is configured. At this time, the indirect peripheral circuit is interposed between the ECC function block circuit for error correction based on the Hamming code, the ECC function block circuit and the external input / output terminal, and has an effective bit width designated from the outside. And a data size alignment circuit for performing a corresponding data size alignment process.
[0012]
According to the above means, by providing the data size alignment circuit in the indirect peripheral circuit, the memory mat can be accessed in units of the maximum bit width in the effective bit width that can be changed according to designation from the outside. In some cases, the bit configuration per mat of the inspection mat can be reduced as compared with the case where the memory mat is accessed in a bit width unit corresponding to byte access, which achieves a reduction in the area of the memory mat portion. To do.
[0013]
In addition, according to external designation of the effective bit width for data input / output, the bit width corresponding to byte access, the bit width corresponding to word access wider than the byte access, the bit width corresponding to long word wider than the word access In the semiconductor memory device that can be changed in three stages, a memory mat portion in which a plurality of memory mats accessed in bit width units corresponding to the long word are arranged, and an indirect peripheral circuit shared by the plurality of memory mats are provided. Provide. At this time, the indirect peripheral circuit is interposed between the ECC function block circuit for error correction based on the Hamming code, the ECC function block circuit and the external input / output terminal, and has an effective bit width designated from the outside. And a data size alignment circuit that performs a corresponding data size alignment process.
[0014]
According to the above means, a memory mat can be accessed in a bit width unit corresponding to a long word, and in this case, the bit configuration per mat of the inspection mat is determined by a bit width unit corresponding to byte access. This can be reduced as compared with the case of accessing, and this achieves a reduction in the area of the memory mat portion.
[0015]
The data size alignment circuit can be configured to allocate storage data of the memory mat to the remaining bits that are not accessed when word access or byte access is designated from the outside.
[0016]
When a data read operation from the memory mat is performed in the first half of the write cycle and a data write operation to the memory mat is performed in the second half of the write cycle, the data size alignment circuit performs word access or byte from the outside. When access is designated, the data read from the memory mat in the first half of the write cycle can be assigned to the remaining bits that are not accessed. At this time, the data read operation from the memory mat is performed in the first half of the write cycle, and the data read operation to the memory mat is performed in the second half of the write cycle. The time required for processing can be reduced as compared with the case where data writing to the memory mat or the inspection mat is performed in separate cycles.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 shows a microcomputer in which the semiconductor memory device according to the present invention is mounted.
[0018]
As shown in FIG. 2, the microcomputer 221 is not particularly limited, but an external interface (I / F) 228 capable of exchanging various signals via an external bus, a CPU (central processing unit) for arithmetic processing 224, a floating point unit (FPU) 223 for executing floating point calculations of mathematical functions, a ROM 226 storing a microprogram executed by the CPU 224, a work area for arithmetic processing by the CPU 224, etc. The SRAM 227 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The external interface 228, the CPU 224, the floating point unit 223, the ROM 226, and the SRAM 227 are coupled by an internal bus 222 so that signals can be exchanged with each other. The internal bus 222 includes an address bus for transmitting address signals, a data bus for transmitting data, and a control bus for transmitting control signals. The SRAM 227 is an example of a semiconductor memory device that can be accessed by the central processing unit in the present invention.
[0019]
FIG. 1 shows a configuration example of the SRAM 227 included in the microcomputer.
[0020]
As shown in FIG. 1, the SRAM 227 is not particularly limited, but has a storage capacity of 16 kbytes (4 kbytes × 4 mats), and includes a memory mat section 10 and an indirect peripheral circuit 20.
[0021]
The memory mat unit 10 includes four RAM units 11, 12, 13, and 14 although not particularly limited. The four RAM units 11, 12, 13, and 14 have the same configuration. The RAM unit 11 includes a column selection circuit 112, a row selection circuit 111, a memory mat 113, an inspection mat 114, and input / output circuits 115 and 116.
[0022]
The memory mat 113 can read and write data in units of 32 bits (bits). The memory mat 113 has a plurality of word lines, a plurality of bit lines arranged so as to intersect with the word lines, and the intersections of the word lines and the bit lines. And a static memory cell arranged. The row selection circuit 113 drives a corresponding word line from the plurality of word lines to a selection level based on the input row address signal. The column selection circuit 112 selectively couples a corresponding bit line to the common line among the plurality of bit lines based on the input column address signal. As a result, data can be read from or written to the memory cell via the input / output circuit 115. The inspection mat 114 can read and write a Hamming code for ECC inspection in units of 6 bits, and includes a plurality of word lines, a plurality of bit lines arranged so as to cross the word lines, and the word lines and the bit lines. And static memory cells arranged at the intersections. The row selection circuit 111 and the column selection circuit 112 are shared by the memory mat 113 and the inspection mat 114. Here, the row selection circuit 111, the column selection circuit 112, and the input / output circuits 115 and 116 are referred to as direct peripheral circuits for the memory mat 113 and the inspection mat.
[0023]
The indirect peripheral circuit 20 includes, but is not limited to, an ECC function block circuit 21, a data latch circuit 22, a data size alignment circuit 23, an input / output control circuit 24, and an I / O bus 25. The ECC function block circuit 21 has an ECC correction function using a Hamming code and is not particularly limited, but generates a 6-bit Hamming code for the check mat 114 from 32-bit input data when writing data to the memory mat 113. A 6-bit hamming code is generated based on the write ECC control function to be performed and the 32-bit output data from the memory mat 113 when data is read from the memory mat 113, and the hamming stored in the test mat 114 A read ECC control function that performs comparison with a code and performs error correction of output data having a 32-bit configuration from the memory mat 113 based on the comparison result. The data latch circuit 22 temporarily holds data output from the data size alignment circuit 23 and data read from the memory mat 113 and error-corrected as necessary by the read ECC control function. The data size alignment circuit 23 performs size alignment processing of data written to the memory mat and data read from the memory mat. The content of this data size alignment is determined by the architecture of the CPU 224. The input / output control circuit 24 controls input / output of various data to / from the internal bus 222.
[0024]
FIG. 3 shows the layout configuration of the SRAM 227.
[0025]
The memory mat portion 10 is divided into two, and the indirect peripheral circuit 20 is laid out therebetween.
[0026]
Next, the Hamming code generated by the ECC function block circuit 21 will be described.
[0027]
As a method for forming an error correction code, there is a Hamming method using a parity check. Here, consider a code string in which an m-bit check code (redundant bit) is added to each k-bit information code and the entire code length is n bits. Assuming that there is an error of 1 bit or less in the n-bit code string, the number of pieces of information represented by the check code is equal to or greater than the number when an error occurs, and the following equation is established.
2 ^m ≧ n + 1 (1)
[0028]
Here, when n = m + k is substituted and arranged, the relationship of the following equation is established between the number of information bits k and the number of check bits m (= n−k).
2 ^m −m ≧ k + 1 (2)
[0029]
A code having an overall code length of n bits, of which information bits are k bits, is referred to as an (n, k) code. FIG. 4 shows an example of a combination (hamming code) of n and k when Expression (2) is established. For example, if the information bit is an 8-bit code sequence (k = 8), 4 check bits (m = 4) are required. Similarly, if the information bit is a 32-bit code string, 6 check bits (m = 6) are required. As described above, the memory mat 113 shown in FIG. 1 can read and write data in units of 32 bits. In this case, since the number of information bits (k) exceeds 26 bits and is 57 bits or less, 6 bits is sufficient as the number of inspection bits (m). Therefore, in the configuration shown in FIG. 1, the test mat 114 and the input / output circuit 116 corresponding thereto can be accessed in units of 6 bits.
[0030]
FIG. 5 shows a list of main external terminals in the SRAM 227 and simple functions for the external terminals.
[0031]
The SRAM 227 is not particularly limited, but includes a CK terminal for capturing a system clock signal, a BUSRDY terminal for capturing a bus ready signal indicating a bus cycle delimiter, an STBY terminal for capturing a hardware / software standby control signal, and read / write. MRWN terminal for capturing control signals, DSIZE [1: 0] terminal for capturing data size alignment signals, IAB [11: 0] terminals for capturing row address signals and column address signals, and data input / output IDB [31: 0] terminal, MSRAM [3: 0] N terminal for capturing a mat selection signal, MSECC [3: 0] N terminal for capturing an ECC mat selection signal, ECCN for capturing an ECC test mode signal Each terminal includes It is coupled to the scan 222. The “H” (high) level of the BUSRDY terminal indicates an interval between bus cycles, and the “L” (low) level of the BUSRDY terminal indicates that the bus cycle is in progress. When the STBY terminal is set to “H” level, a standby state is instructed, and when the STBY terminal is set to “L” level, the SRAM 227 is set to an operating state. A read cycle is designated by setting the MRWN terminal to “H” level, and a write cycle is designated by setting the MRWN terminal to “L” level. Longword access is specified by setting the DSIZE [1: 0] terminal to “L” and “L”, and word access is specified by setting the DSIZE [1: 0] terminal to “L” and “H”. , DSIZE [1: 0] terminals are set to “H” and “H” to designate byte access. Of the IAB [11: 0] terminals, IAB [1: 0] indicates the presence / absence of data access size shift, IAB [3: 2] indicates a column address, and IAB [11: 4] indicates a row address. When the ECCN terminal is set to “H”, ECC disable is specified, and when the ECCN terminal is set to “L”, ECC enable is specified.
[0032]
FIG. 6 shows a specific example of the data size alignment processing performed by the data size alignment circuit 23. In FIG. 6, “*” indicates don't care, logical value “1” indicates a high (H) level, and logical value “0” indicates a low (L) level.
[0033]
When long word access (32-bit access) is specified by setting the DSIZE [1: 0] terminals to logical values “0” and “0”, a 32-bit configuration from the data latch circuit 22 is provided at the time of reading. The data is output to the bus 222 through the IDB [31: 0] terminal via the input / output control circuit 24 in the bit configuration as it is. At the time of writing, the 32-bit data taken from the bus 222 via the IDB [31: 0] terminals is transmitted to the data latch circuit 22 with the bit configuration as it is.
[0034]
The word size (16-bit access) is specified by setting the DSIZE [1: 0] terminal to the logical value “0” or “1”, and the IAB [1: 0] terminal has the logical value “0” or “*”. When the data shift is instructed by the data size, at the time of reading, the data in which the upper 16 bits output from the data latch circuit 22 are valid is shifted to the lower 16 by the upper 16 bits being shifted in the data size alignment circuit 23. After the bits are changed to valid data, they are output to the bus 222 via the IDB [31: 0] terminals. At the time of writing, data in which the lower 16 bits fetched from the bus 222 via the IDB [31: 0] terminal are valid are shifted by the lower 16 bits being shifted in the data size alignment circuit 23. The 16 bits are changed to valid data and then transmitted to the data latch circuit 22.
[0035]
Word access is specified by setting the DSIZE [1: 0] terminal to the logical value “0” “1”, and the data shift is instructed by the logical value “1” “*” at the IAB [1: 0] terminal. Otherwise, at the time of reading, the data in which the upper 16 bits output from the data latch circuit 22 are valid is output to the bus 222 via the IDB [31: 0] terminal as it is. At the time of writing, data in which the lower 16 bits fetched from the bus 222 via the IDB [31: 0] terminals are valid are transmitted to the data latch circuit 22 without being bit-shifted.
[0036]
Byte access is instructed when the DSIZE [1: 0] terminal is set to the logical value “1” or “1”, and data shift is instructed by the IAB [1: 0] terminal to the logical value “0” or “0”. In this case, at the time of reading, the data in which the upper 16 bits (2 bytes) output from the RAM units 11 to 14 are valid is bit-shifted by the data size alignment circuit 23, so that the lower 16 bytes ( 2 bytes) is changed to valid data and then output to the bus 222 via the IDB [31: 0] terminals. The CPU 224 handles any of the lower two bytes of data on the bus 222 as valid data. Further, at the time of writing, byte data in which the 8th to 15th bits taken in from the bus 222 via the IDB [31: 0] terminals are valid are bit-shifted in the data size alignment circuit 23. Then, after the upper 8 bits are changed to valid data, they are transmitted to the RAM units 11-14.
[0037]
Byte access is instructed when the DSIZE [1: 0] terminal is set to the logical value “1” or “1”, and data shift is instructed by the IAB [1: 0] terminal to the logical value “0” or “1”. In this case, at the time of reading, the data in which the upper 16 bits (2 bytes) output from the RAM units 11 to 14 are valid is bit-shifted by the data size alignment circuit 23, so that the lower 16 bytes ( 2 bytes) is changed to valid data and then output to the bus 222 via the IDB [31: 0] terminals. The CPU 224 handles any of the lower two bytes of data on the bus 222 as valid data. At the time of writing, byte data in which the lower 8 bits fetched from the bus 222 via the IDB [31: 0] terminals are made valid are bit-shifted by the data size alignment circuit 23 so that the 16th bit is obtained. The 23rd bit is changed to valid data and then transmitted to the RAM units 11-14.
[0038]
Byte access is instructed when the DSIZE [1: 0] terminal is set to the logical value “1” “1”, and data shift is instructed by the logical value “1” “0” at the IAB [1: 0] terminal Otherwise, at the time of reading, the data in which the lower 16 bits (2 bytes) output from the data latch circuit 22 are valid are used as they are in the data size alignment circuit 23 in the IDB [31: 0] terminals. To the bus 222. The CPU 224 handles any of the lower two bytes of data on the bus 222 as valid data. Further, at the time of writing, byte data in which the 8th to 15th bits taken in from the bus 222 via the IDB [31: 0] terminals are valid are bit-shifted in the data size alignment circuit 23. Without being transmitted to the RAM units 11-14.
[0039]
Byte access is instructed when the DSIZE [1: 0] terminal is set to a logical value “1” or “1”, and data shift is instructed by the IAB [1: 0] terminal to a logical value “1” or “1”. Otherwise, at the time of reading, the data in which the lower 16 bits (2 bytes) output from the data latch circuit 22 are valid are used as they are in the data size alignment circuit 23 in the IDB [31: 0] terminals. To the bus 222. The CPU 224 handles any of the lower two bytes of data on the bus 222 as valid data. At the time of writing, byte data in which the lower 8 bits fetched from the bus 222 via the IDB [31: 0] terminal are valid are not bit-shifted by the data size alignment circuit 23 and are stored in the RAM unit 11. ~ 14.
[0040]
In the above write operation, of the 32-bit data in the data latch circuit 22, bits for which no valid data exists are read out from the memory mat 112 by the data size alignment circuit 23 in the first half of the write cycle. Of the bit-structured data, for bits for which there is no valid data, all the bits (32 bits) are apparently assigned by appropriately assigning the data for the bits to the lower 16 bits in the data stored in the data latch circuit 22. Valid data is synthesized and transmitted to the ECC function block circuit 21.
[0041]
Next, the operation of the SRAM 227 configured as described above will be described.
[0042]
FIG. 7 shows the flow of the ECC operation during the write operation in the SRAM 227. FIG. 9 shows the operation timing of the main part during the write operation of the SRAM 227. In FIG. 9, () indicates an internal signal, and hatching indicates don't care. The STBY terminal is fixed at the “H” level.
[0043]
During the write operation, a read operation from the memory mat 113 is performed in the first half of the write cycle regardless of whether the data size alignment is byte, word, or long word (step S11). In the ECC function block circuit 21, a hamming code is generated based on the data obtained by the read operation, the hamming code is compared with the hamming code read from the inspection mat 114, and the memory It is determined whether or not an error is included in the data read from the mat 113 (step S12). In this determination, if it is determined that “no error is included”, the read data is latched in the data latch circuit 22 (step S13). If it is determined in the error determination in step S12 that “a 1-bit error is included”, the data is corrected after the 1-bit error is corrected by a known error correction technique in ECC (step S17). Is latched by the data latch circuit 22 (step S13).
[0044]
On the other hand, data for writing is transmitted from the bus 222 to the data size alignment circuit 23 via the input / output control circuit 24 (step S14), and data is transferred to a desired bit according to an instruction from the CPU 224 as shown in FIG. Are shifted (step S15). When word access or byte access is designated from the outside, the data of the corresponding bit in the data stored in the data latch circuit 22 is synthesized with the remaining bits that are not accessed (bits that are not valid). As a result (step S16), it is apparently transmitted as 32-bit write data to the ECC function block circuit 21, where a hamming code for the input data of 32 bits is generated (step S17). Then, the 32-bit write data is written to the designated address in the memory mat 113, and the corresponding hamming code is written in the inspection mat 114 (step S18). The writing in step S18 is performed in the latter half of the write cycle. That is, in the write cycle, data is read from the memory mat 113 and the inspection mat 114 in the first half cycle, and writing to the memory mat 113 and the inspection mat 114 is performed in the second half cycle. For example, assuming that the internal two-phase clock signals φ1 and φ2 that are synchronized with the clock signal input from the outside via the CK terminal are generated in the SRAM 227 at the timing shown in FIG. 9, the synchronous signal is synchronized with the clock signal φ1. The data is read from the memory mat 113 and the inspection mat 114, and is written to the memory mat 113 and the inspection mat 114 in synchronization with the clock signal φ2, thereby reading the data from the memory mat 113 and the inspection mat 114. Compared with the case where data reading from the memory mat 113 and the inspection mat 114 is performed in separate cycles, the time required for processing can be shortened.
[0045]
If long word access is specified by the CPU 224, a hamming code may be generated from 32-bit write data fetched via the bus 222. Therefore, the memory mat 113 can be used in the first half cycle of the write cycle. The synthesis process (step S16) using the read data is not performed.
[0046]
FIG. 8 shows a flow of the ECC operation during the read operation in the SRAM 227. FIG. 10 shows the operation timing of the main part during the read operation of the SRAM 227. In FIG. 10, () indicates an internal signal, and hatching indicates don't care. The STBY terminal is fixed at the “H” level.
[0047]
In the read operation, in synchronization with the clock signal φ1 shown in FIG. 10, 32-bit data and a corresponding hamming code are read from the selected memory mat 113 and test mat 114 (S21). The ECC function block circuit 21 generates a hamming code based on the 32-bit data read from the memory mat 113, and the generated hamming code and the hamming code read from the test mat 114. Is compared to determine whether or not an error has occurred (step S22). In this determination, if it is determined that “no error has occurred”, the data is latched in the data latch circuit 22 (step S23). If it is determined in step S22 that “a 1-bit error has occurred”, the error is corrected (step S26), and then the data is latched in the data latch circuit 22. (Step S23). The latched data is transmitted to the data size alignment circuit 23, and data size alignment processing is performed as shown in FIG. 6 according to the designation from the CPU 224 (S24). To the bus 222 (step S25).
[0048]
FIG. 11 shows an SRAM 237 to be compared with the SRAM 227 shown in FIG. The SRAM 237 has a storage capacity of 16 kbytes (4 kbytes × 4 mats), and the configuration of one mat is 1 k words × 32 bits. Furthermore, in this SRAM 237, data size alignment circuits 341 to 344 for changing the data size into 32-bit input / output bytes (8 bits), words (16 bits), and long words (32 bits) are directly connected to peripheral circuits. It is provided as a part. In one RAM unit 11, memory mats (× 8) 301 to 304 capable of reading and writing data in units of 8 bits are provided, and input / output circuits 321 to 324 are provided correspondingly. Corresponding to the memory mats 301 to 314, humming code inspection mats 311 to 314 and corresponding input / output circuits 331 to 334 are provided. Since the minimum unit of the data size is 8 bits, as shown in FIG. 4, this corresponds to the case where the number of information bits (k) is 11, and the number of check bits (m) in that case is 4 bits. Therefore, the inspection mats 311 to 314 and the input / output circuits 331 to 334 corresponding to the inspection mats 311 to 314 can input and output a Hamming code in units of 4 bits (× 4 bits). Therefore, the inspection mat requires 16 bits per mat, and the entire module requires 64 bits for 16 bits × 4 mats. For this reason, the area of the SRAM 237 increases by a factor of 1.5 compared to the case where the ECC function is not provided.
[0049]
On the other hand, in the SRAM 227 having the configuration shown in FIG. 1, the data size alignment circuit is provided in the indirect peripheral circuit 20, and the memory mat 113 is always accessed in units of 32 bits. As a result, the inspection mat corresponding to the memory mat 113 can be composed of 6 bits per mat (see FIG. 4). Thus, since the size of the inspection mat per mat can be reduced, the area of the memory mat portion 10 can be reduced.
[0050]
According to the above example, the following effects can be obtained.
[0051]
(1) Since the data size alignment circuit is provided in the indirect peripheral circuit 20 and access to the memory mat 113 is always performed in units of 32 bits, there are 6 inspection mats corresponding to the memory mat 113 per mat. A bit configuration is sufficient. Since the size of the inspection mat per mat can be reduced in this way, the area of the memory mat portion 10 can be reduced. For example, the SRAM 227 is turned on in a semiconductor integrated circuit such as the microcomputer 221. It is advantageous when chipped.
[0052]
(2) When word access or byte access is designated from the outside, the data size alignment circuit 23 assigns the data stored in the memory mat 113 to the remaining bits that are not accessed, so that the memory mat 113 has a 32-bit unit. Access to the inspection mat 114 in 6-bit units.
[0053]
(3) In the write cycle, data is read from the memory mat 113 and the inspection mat 114 in the first half cycle, and writing to the memory mat 113 and the inspection mat 114 is performed in the second half cycle. Specifically, when the internal two-phase clock signals φ1 and φ2 synchronized with the clock signal input from the outside via the CK terminal are generated in the SRAM 227 at the timing shown in FIG. Data is read from the memory mat 113 and the inspection mat 114 in synchronization with φ1, and writing to the memory mat 113 and the inspection mat 114 is performed in synchronization with the clock signal φ2. Thereby, the time required for processing can be shortened as compared with the case where data reading from the memory mat 113 or the inspection mat 114 and data writing to the memory mat 113 or the inspection mat 114 are performed in different cycles. In other words, data is read from the memory mat in the first half of the write cycle, and data is written to the memory mat in the second half of the write cycle, so that high-speed performance is not deteriorated despite having the ECC function. Error detection and correction can be performed.
[0054]
Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.
[0055]
For example, after correcting a 1-bit error in the data in the ECC function block circuit 21 (steps S17 and S26), the data is written to the memory mat 113 again, read out, and checked again in the ECC function block circuit 21 (step If S12, S22) and error correction (steps S17, S26) are performed, a 2-bit error can be corrected. Therefore, the data reliability can be improved by rewriting the error-corrected data in the memory mat 113.
[0056]
In the above description, the case where the invention made mainly by the present inventor is applied to the SRAM, which is the field of use as the background, has been described. However, the present invention is not limited to this, and a dynamic random access memory is used. (DRAM) can also be applied. The present invention can also be applied to a case where a semiconductor memory is manufactured as a single product.
[0057]
The present invention can be applied on condition that at least a memory mat is provided.
[0058]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0059]
In other words, the bit configuration of the inspection mat is reduced by providing a data size alignment circuit directly in the peripheral circuit and making the memory mat accessible in units of the maximum bit width in the effective bit width that can be changed according to external designation. As a result, an increase in chip area accompanying the addition of the ECC function can be minimized. Further, by reading data from the memory mat in the first half of the write cycle and writing data to the memory mat in the second half of the write cycle, the ECC function can be mounted without degrading high speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of the overall configuration of an SRAM, which is an example of a semiconductor memory device according to the present invention.
FIG. 2 is a block diagram showing an example of the overall configuration of a microcomputer on which the SRAM is mounted.
FIG. 3 is a layout explanatory diagram of main circuit blocks in the SRAM;
FIG. 4 is an explanatory diagram of a Hamming code in the ECC function.
FIG. 5 is an explanatory diagram of main external terminals and functions of the external terminals in the SRAM shown in FIG. 1;
6 is an explanatory diagram of data size alignment processing performed by the data size alignment circuit shown in FIG. 1; FIG.
FIG. 7 is a flowchart of an ECC operation during a write operation of the SRAM.
FIG. 8 is a flowchart of an ECC operation during a read operation of the SRAM.
FIG. 9 is a timing diagram of a write operation in the SRAM.
FIG. 10 is a timing diagram of a read operation in the SRAM.
FIG. 11 is a block diagram illustrating a configuration example of an SRAM to be compared with the SRAM.
[Explanation of symbols]
10 Memory mat
11, 12, 13, 14 RAM section
20 Indirect peripheral circuits
21 ECC function block
22 Data latch circuit
23 Data size alignment circuit
24 I / O control circuit
111 row selection circuit
112 column selection circuit
113 Memory mat
114 Inspection mat
115,116 I / O circuit
221 Microcomputer
222 Bus
223 FPU
224 CPU
226 ROM
227 SRAM
228 External interface

Claims (5)

A semiconductor memory device capable of changing an effective bit width related to data input / output according to an external designation,
A memory mat portion in which a plurality of memory mats that are accessed in units of the maximum bit width in an effective bit width that can be changed according to designation from the outside are arranged;
An indirect peripheral circuit shared by the plurality of memory mats,
The indirect peripheral circuit includes an ECC function block circuit for error correction based on a Hamming code;
A data size alignment circuit which is interposed between the ECC function block circuit and the external input / output terminal and performs data size alignment processing in accordance with an effective bit width designated from the outside. Storage device. The effective bit width related to data input / output is 3 according to the designation from the outside, the bit width corresponding to byte access, the bit width corresponding to word access wider than the byte access, and the bit width corresponding to long word wider than the word access. A semiconductor memory device that can be changed in stages,
A memory mat portion in which a plurality of memory mats accessed in bit width units corresponding to the long word are arranged;
An indirect peripheral circuit shared by the plurality of memory mats,
The indirect peripheral circuit includes an ECC function block circuit for error correction based on a Hamming code;
A data size alignment circuit which is interposed between the ECC function block circuit and the external input / output terminal and performs data size alignment processing in accordance with an effective bit width designated from the outside. Storage device. 3. The semiconductor memory device according to claim 2, wherein said data size alignment circuit allocates storage data of said memory mat for the remaining bits that are not accessed when word access or byte access is designated from the outside. When a data read operation from the memory mat is performed in the first half of the write cycle and a data write operation to the memory mat is performed in the second half of the write cycle, the data size alignment circuit performs word access or byte from the outside. 3. The semiconductor memory device according to claim 2, wherein, when access is designated, the data read from the memory mat is assigned to the remaining bits not accessed in the first half of the write cycle. A microcomputer formed on a single semiconductor substrate, comprising: the semiconductor memory device according to claim 1; and a central processing unit capable of accessing the semiconductor memory device.

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