JP2005031073A - Search method of gps correlated peak signal and system therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To preserve in a memory only a correlated integration value over a critical value by adding an in-phase sample and a quadrature-phase sample values together into one value before a correlatively-integrated sample value is preserved in the memory, and by comparing the added sample value with the critical value. <P>SOLUTION: This system includes a converter for converting a received GPS signal into an in-phase digital signal I and a quadrature-phase digital signal Q, and a correlator for generating an expected code to one tap, correlating the in-phase digital signal I and the quadrature-phase digital signal Q with the expected code, and outputting sampled I value and Q value. The system also includes a filter for filtering the sampled I value and Q value by changed I value and Q value, adding the changed I value and Q value, and outputting it to changed data, a memory for preserving the changed data, a domain conversion part for performing domain conversion to the changed data and outputting the converted value, and a comparison part for comparing a threshold with the converted value in order to determine whether a peak exists in the tap. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to GPS (Global Positioning System), and more particularly, to a GPS receiver and a method related thereto.

The GPS receiver calculates its position by calculating the distance from the satellite using the arrival times of signals transmitted simultaneously from a plurality of GPS satellites. Such satellites transmit satellite position data including pseudo-random codes along with data for clock timing.
Using the received pseudo-random code, the GPS receiver determines a similar range of GPS satellites, and calculates the position of the receiver using data for the similar range, satellite timing, and clock timing. The similar range is a delay time value between local clock signals received from each satellite. In general, GPS signals are received from four or more satellites. The satellite data and signature data for the clock timing are extracted from the GPS signal every time one satellite is detected and tracked. GPS signal detection can be detected for a few seconds and should be received as a strong signal and have a low error rate. The GPS signal includes a high-rate repetitive signal called a pseudorandom (PN) code. The code used for a general product is called C / A (Coarse / Acquisition) and has a binary phase reversal rate of 1.023 MHz, that is, a chipping rate, and 1023 chips are 1 millisecond. It is repeated according to the code period. The code sequence is included in the gold code, and each GPS satellite provides a signal for a unique gold code.

Most GPS receivers use a correlation method to calculate the similarity range. The correlator multiplies the received signal using a stored copy of the gold code that is compatible with its local memory, integrates the calculation result, and uses the correlation value and sampling used as an indicator of the presence of the satellite signal. Get the value. The receiver sequentially adjusts the relative timing of the stored manuscript according to the received signal and observes an output correlation value to determine a time delay between the received signal and a local clock. . First determining whether or not such an output exists is called acquisition. When acquisition occurs, the tracking phase is entered, at which time the local reference timing is adjusted small for high correlation output.
The GPS system uses a plurality of satellites to simultaneously transmit signals to a receiver so that the arrival time difference between the plurality of signals can be measured to determine the position of the receiver. In general, since signals received from different satellites use pseudo-random spreading codes that are almost orthogonal to each other, they are hardly interfered with each other. Such low interference conditions depend on the power magnitude of the received signals that are similar to each other.

To reduce acquisition time, the GPS receiver processes signals received from several satellites in multiple channels. Each channel includes multiple correlation taps used for correlation operations. In general, the data received at each correlation tap is stored in memory. The stored data is correlated through a process. The memory size is proportional to the number of channels and taps. To reduce acquisition time, a memory with sufficient capacity and speed is required. However, as the proportion of memory components occupied by the GPS receiver increases, it becomes more difficult to reduce the size of the GPS receiver.
FIG. 1 is a block diagram showing a configuration of a conventional GPS receiver. A conventional GPS receiver includes an antenna 1, a down converter 2, a local oscillator 3, an A / D converter 4, a receiver channel 5, a receiver processor 6, a navigation processor 7, and a user interface 8. In operation, the antenna 1 receives signals transmitted from a set of satellites in the atmosphere. The down converter 2 mixes a high frequency signal received from the antenna 1 with a local oscillation signal generated by the local oscillator 3 and converts it to an intermediate frequency (hereinafter referred to as IF). The A / D converter 4 converts an IF signal, which is an analog signal, into a digital signal for processing in the receiver channel 5. The IF signal received by the receiver channel 5 is processed by the receiver channel 5, the receiver processor 6 and the navigation processor 7. The receiver channel 5 can be set to have N channels at the time of manufacture. The receiver processor 6 generates a plurality of similar ranges for each satellite and performs a correlation between the in-phase intermediate frequency data I and the quadrature intermediate frequency data Q for each channel. The navigation processor 7 sets a position value using a similar range that is different for each satellite. The user interface 8 is used for displaying position data.

FIG. 2 is a block diagram showing the configuration of one of the N channels of the receiver of FIG.
The digital IF signal received from the A / D converter 4 is provided to an in-phase / quadrature multiplier 10, and an in-phase sine signal generator (sine map) 11 is generated by a carrier numerically controlled oscillator (NCO) 19. And a quadrature phase cosine signal generator (cosine map) 12, or a quadrature phase sine signal generator 11 and an in-phase cosine signal generator 12 are sequentially operated to generate signals. The outputs of the in-phase / quadrature multiplier 10 are the in-phase IF signal of the phase of the sine signal generator 11 and the quadrature IF signal of the phase of the cosine signal generator 12. Further, the phase IF is the quadrature phase IF of the sine signal generator 11 and the phase of the cosine signal generator 12 is the same phase IF signal. The receiver processor 6 generates a numerical code that controls the carrier numerically controlled oscillator 19 in order to generate a Doppler frequency. The receiver processor 6 also generates a clock control signal that is input to a code numerically controlled oscillator 18 in conjunction with a PN code generator 16. A pseudo-random code associated with the satellite is generated by a PN code generator 16. The PN code is shifted by a code shift 17 and output to a plurality of correlators 13. The correlator 13 performs correlation by comparing the phase-shifted PN code with the I data and Q data received from the in-phase / quadrature phase multiplier 10. The I and Q data correlated from the correlator 13 is output to the integrator 14 and integrated. The integrated value, also referred to as a sampling value, is stored in the memory 15. In general, all sampling values sampled for a predetermined time, for example, about 1 millisecond, are stored in the memory 15 for each tap by the integration value 14 in the receiver channel 5. After a predetermined number of samplings, the sampling value is transmitted to the FFT unit 20, and it is determined whether a peak exists for the corresponding tap through high-speed Flier conversion. If a peak is present, the receiver processor 6 calculates a similar range for extracting and capturing the frequency and code value information from the tap.

If it is determined that there is no peak in the sampled tap, the sampling, correlation process, and FTF process are repeated until a tap with a peak is found.
In this process, it can be confirmed that a lot of positive data should be stored in the memory 15 of the receiver. Therefore, a memory having a sufficient capacity is required. Also, since memory data must be accessible, memory access time affects acquisition speed and is therefore an important factor in receiver performance.

As described above, the present invention is for solving the conventional technical problems, and the in-phase sample and the quadrature-phase sample value are added together before storing the correlated and integrated sample values in the memory. It is an object of the present invention to provide a GPS correlation peak signal search method in which a sample value is compared with a critical value and only a correlation integral value equal to or higher than the critical value is stored in a memory.
Another object of the present invention is to provide a system for carrying out the above-described method.

A converter that converts the received GPS signal into an in-phase digital signal I and a quadrature digital signal Q, and an expected code is generated for one tap, and the in-phase digital signal I and the quadrature digital signal Q are converted into the expected code. A correlator that outputs the sampled I and Q values in correlation with each other, and filters the sampled I and Q values to the modified I value and the modified Q value to change the modified I value and Q A filter that adds the values and outputs the change data, a memory that stores the change data, a domain conversion unit that performs domain conversion on the change data and outputs a conversion value, and whether a peak exists in the tap A GPS receiver is provided that includes a threshold value and a comparison unit that compares the converted value to determine.
The sampled I and Q values are changed to have positive values when the current I sample value and the current Q sample value are different in sign from the previous I sample value or Q sample value. .
For example, the changed I value and Q value may be values obtained by dividing each sampled I value and Q value by the same value.

According to one aspect of the invention, the filter delays the sign bit of the sampled I value and Q value and outputs the previous sign value, and compares the sign of the current sampled Q value with the previous sign value. And a pair of sign bit comparators that output a positive value if they are different from each other, and the filter performs an operation of adding the changed I value and the changed Q value including the sign bit. Further includes a vessel.
For example, the domain conversion unit is a high-speed Flier conversion unit. The memory further stores sampled I and Q values of taps identified as having a peak, and the memory can be SRAM or DRAM.

  According to another aspect of the present invention, a converter that converts a received GPS signal of one tap into an in-phase digital signal I and a quadrature digital signal Q, and the in-phase digital signal I and the quadrature digital signal Q are expected. A correlator for outputting a sampled I value and a Q value having a sign bit that correlates with a code to indicate a direction, filtering the sampled I value by filtering at least one sampled I value and a sign bit of the Q value And a filter that determines whether or not there is a potential peak of the tap based on the number of direction changes in the sign bit of the Q value and the sampled I of the tap that is determined to have the potential peak. A domain conversion unit that performs domain conversion on the data derived from the value and the Q value and outputs a conversion value; GPS receiver including a comparator for comparing the converted value to a threshold is provided to determine click is present. A memory is provided for storing data derived from the sampled I and Q values of taps determined to have potential peaks, which may be SRAM or DRAM.

  For example, the data is derived from a sampled I value, Q value, which is a signed I value added to a resigned Q value, and the sampled I value and Q value are the current I sample value or When the current Q sample value is different in sign from the previous I sample value or Q sample value, it is filtered with a positive value. The filtered I value and Q value may be values obtained by dividing each sampled I value and Q value by the same value. The filter delays the sign bit of the sampled I value and the Q value and outputs a previous sign value and the sign of the current sampled Q value is different from the previous sign value; It includes a pair of single bit comparators that output positive values.

  Receiving a GPS signal from one or more satellites; converting the received GPS signal into an in-phase digital signal I and a quadrature digital signal Q; generating an expectation code to generate the in-phase digital signal I; Correlating the orthogonal moving digital signal Q with the expected code and outputting the sampled I value and Q value, and filtering the sampled I value and Q value with the modified I value and the modified Q value Adding the changed I value and the changed Q value and outputting the changed data; storing the changed data in a memory; and performing domain conversion on the changed data to obtain a converted value. For determining position, comprising: outputting and comparing a threshold value and the transformed value to determine whether a peak exists in the tap PS signal processing method is also provided. The sampled I value or Q value is changed so that the current I sample value or current Q sample value has a negative value when the immediately preceding I sample value or Q sample value are different in sign from each other. be able to. The changed I value and the changed Q value are values obtained by dividing each sampled I value and Q value by the same value, and the reduced value is reduced by 1/2. Value. The filtering step includes outputting the previous sign value by delaying the sign bit of the sampled I value and Q value, and if the sign of the current sampled Q value is different from the previous sign value, Outputting a negative value. The method may further include adding the changed I value and the changed Q value including a sign bit.

The GPS signal processing method may further include storing the sampled I and Q values of taps identified as having a peak in the memory.
A step of converting a GPS signal received by the tap into an in-phase digital signal I and a quadrature digital signal Q, and a sign bit for indicating a direction by correlating the in-phase digital signal I and the quadrature digital signal Q with an expected code. Outputting sampled I and Q values and filtering at least one sampled I value and Q value sign bit to a number of direction changes of the sampled I value and Q value sign bits. Based on whether or not a potential peak exists in a tap, and performs domain conversion on data derived from the I and Q values of the tap determined to have a potential peak and outputs the converted value And further comparing the threshold value with the transformed value to determine if a peak is present at the tap. The law is provided.

  The GPS signal processing method may further include, for example, storing data derived from sampled I and Q values of taps determined to have potential peaks in a memory.

  According to another aspect of the invention, outputting the sampled I and Q values having sign bits indicating the direction by correlating the in-phase digital signal I and the quadrature digital signal Q with the expected code, and at least Filter the sign bit of one sampled I value and Q value, and determine whether there is a potential peak in the tap based on the number of direction changes of the sampled I value and Q value sign bit. Determining, performing domain conversion on data derived from the sampled I and Q values of taps determined to have potential peaks, and outputting converted values, and peaking at the taps Comparing the threshold value with the converted value to determine whether the signal exists, and performing a GPS signal processing method by the process. Program storage device is provided with a storage code that can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Similar or equivalent parts have been given similar reference numbers to simplify the description.

  FIG. 3 is a block diagram showing a configuration of a GPS receiver according to an embodiment of the present invention.

  The operation of the components of the receiver illustrated in FIG. 3 is the same as that of FIG. The filter 30 is configured to receive the sampling values I and Q output from the integrator 14. According to at least one embodiment of the present invention, the filter 30 changes the sampled I and Q values so that a data set reduced from the sampled values is selected and stored in the memory 15. . According to another embodiment of the present invention, the filter 30 extracts a correlation characteristic from the sampled I value and Q value, and selectively stores the I value and the Q value, or performs a screen process thereof. Change. The sampling I and Q values of taps determined not to have a peak are discarded and are not stored in the memory. The process of processing the stored data by the FFT unit 20 to determine whether there is a peak tap reduces the power consumption because the reduced data set and the required memory 15 capacity are reduced. The physical size of 15 is also reduced and is more efficient.

  FIG. 4 is a block diagram illustrating the configuration of the filter of FIG. 3 according to an embodiment of the present invention. The sampled I value and Q value output from the integrator 14 are input to the pair of delay elements 23 and 24 and the sign bit comparison units 25 and 26. In order to describe an embodiment of the present invention, the sampled I and Q values are 16-bit values and the sampling period is 1 millisecond. Each sample frame has 16 samples. Of course, other numbers of bits, other sampling periods, and other sampling frames can be used without departing from the spirit of the present invention.

  As shown in FIG. 4, each 16-bit data obtained by adding one sign bit to the sampled I value and Q value is input to one of the n taps of the filter 30. The circuit for tap 0 is shown in FIG. The sign bit is input to the delay element 23 that delays the sign bit by one clock before being input to the sign bit comparison unit 25. The sign bit comparison unit 25 compares the sign value of the previously sampled I data with the sign value of the current sampled I data. The sign bit comparison unit 25 outputs a logical value 0 indicating a positive value when the current sign bit is different from the previous sign bit. The delay element 24 and the sign bit comparator 26 perform the above-described operation on the sampled Q data. The sign (or direction) of the I data and Q data sampled in this way is changed according to the direction of the sampling data according to time. The changed I data and Q data are input to the adder 27, and the changed I data and Q data including the sign bit are added thereto. The added data is “variation data”. According to this embodiment, 16 pieces of change data added from the changed I data and Q data are output for storage in the memory 15. The stored data is subjected to Fourier transform by the FFT unit 20 to determine whether an actual peak value exists in the corresponding tap. The sign bit comparison units 25 and 26 can be implemented using, for example, a negative exclusive OR (XNOR). It is obvious that the sign bit comparison unit can be implemented using exclusive OR (XOR), and in this case, the comparison value is a negative value (logic “1”). When the current sample value and the previous sample value have the same sign using XNOR or have different signs using XOR, the counter 28 counts a logic “1” number. If no peak is formed at this tap, the process described above is repeated for the next tap.

  FIG. 5 is a block diagram illustrating the configuration of the filter of FIG. 3 according to another embodiment of the present invention. Referring to FIG. 5, every time a negative result is obtained through addition of the changed I data and Q data of the adder 27, a logic “1” signal is output to the counter 28 to count the tap. Increase. The counter 28 is set to 0 before data sampling of each tap. Completing a sampled frame, for example, 16 samples, the final count value is compared to a preset threshold of logic circuit 29. If the count value is larger than a preset threshold value, such as 12 out of 16, for example, the data of tap 0 is determined as a potential peak value. At this time, the sampled I value and Q value of the unknown tap are stored in the memory 15. The stored data is processed by the FFT unit 20 and the receiver process 6 to determine whether a peak exists in the tap. If the count value of any tap is not larger than the preset threshold value, the sampled I value, Q value, changed I data, Q data, and change data are stored in the memory 15. Not. This data is discarded.

  FIG. 6 is a block diagram illustrating the configuration of the filter of FIG. 3 according to another embodiment of the present invention. Referring to FIG. 6, not the sampling I value and Q value, but the change data output from the adder 27 is determined by the logic circuit 29 as a count value larger than a preset threshold value and output to the memory 15. Is done.

According to this embodiment, the change data of potential peak taps is stored and processed by the FFT unit 20 and the receiver process 6. Thus, the data set stored in the memory 15 is smaller than the data set of the sampling I value and Q value output from the integrator 14.
Table 1 shows an example of data received from a tap according to an embodiment of the present invention and a process of processing the data by a filter 20.

  In Table 1, 16 I sample values and Q sample values output from the integrator 14 and input to the filter 30 are illustrated in the I column and the Q column. The changed I and Q values are shown in the I 'and Q' columns, respectively. As shown here, the sign of each sample value has a positive value when a sign change occurs between the current I sample value, the Q sample value and the previous I sample value, and the Q sample value. The I sample value is changed by the delay element 23 and the sign bit comparison unit 25, and the Q sample value is changed by the delay element 24 and the sign bit comparison unit 26. The changed I sample value and Q sample value are added by an adder 27 to output a change value. Such summation is shown in the column indicated by the change value (I ′ + Q ′) in Table 1. The adder 27 adds the values of I ′ and Q ′ in consideration of the signs of the I ′ value and the Q ′ value. Each time a negative value is output from the adder 27, the counter value of the counter 28 is increased. As shown in the “Count Value” column of Table 1, the count value of the data of this tap is 7 out of 16 sample frames. This means that there are seven negative values of the sum of the changed I ′ and Q ′ sample values. Table 1 illustrates data for taps that do not have a peak.

  Those skilled in the art will recognize that in order for the tap peak to exist, the I value and the Q value appear as two cluster forms: a cluster corresponding to the I sample value and a cluster corresponding to the Q sample value. FIG. 7 illustrates the sampled I and Q values swinging in the other direction as the zero axis. Those skilled in the art can see that this unknown tap has no peak with reference to the graph illustrated in FIG.

  According to an embodiment of the present invention, as shown in Table 1, the count value is a value obtained by measuring the number of times the sampled I value and Q value are changed around 0 as an axis. Therefore, of the 16 data sets, 7 count values are not clustered apart from the 0 axis, but are understood as data sets having data points that swing around the 0 axis in the other direction. Can be done. Of the 16 taps, 7 taps are judged as taps having no peak and can be discarded.

  Table 2 illustrates sampled I and Q values for taps with peaks. As shown in Table 2, as for the sampled I value and Q value, all 16 samples are clustered in the same direction. Further, since the direction of the I sample value and the Q sample value hardly changes or does not change at all, the sampling I value and Q value (I ′ and Q ′) changed by the filter shown in FIG. ) Is changed so that 16 samples always have a negative sign. Therefore, the output (I '+ Q') of the adder 27 has a larger negative value clustered on the zero axis. Since each change value (I ′ + Q ′) is a negative value, the counter counts 16 times and has 16 as a count value. This is recognized as a tap with a peak.

  FIG. 8 is a graph showing the I sample values and Q sample values shown in Table 2.

  Referring to Table 2, it can be seen that there are two data clusters for I sample values and Q sample values. According to the embodiment of the present invention, the change value (I ′ + Q ′) is stored in the memory 15 to determine whether a peak exists in a specific tap, and the stored change value is processed by the FFT unit 20. Search for the presence of a peak. Whether or not there is a peak can be determined by comparing the change value converted by the FFT unit 20 with a predetermined value that defines the presence of the peak. If it is determined that a peak exists in the tap, the frequency, code value, and phase offset are extracted from the sampled I value and Q value, and a similar range is calculated. Alternatively, in order to further reduce the data set, the sampled I value and Q value are multiplied by 1/2, 1/4, etc. by the fraction multiplier before passing through the filter, and the filter 30 and the FFT unit 20 Can be processed. The multiplier (not shown) may be constituted by a part of the filter 30 or may be formed between the integrator 14 and the filter 30.

  FIG. 9 is a flowchart illustrating a process of processing data received from a tap according to an exemplary embodiment of the present invention to determine whether a peak exists. As shown, the receiver according to this embodiment of the present invention receives an I value and a Q value from a tap (step 71). The N samples (sampled values) of the integrated correlation value are output to the filter 30 (step 72). According to this example, N is 16 and the integration period is 1 millisecond. The sampled I and Q values are received by the filter 30 (step 73). The sampled I and Q values are changed to have a positive value when a sign change occurs between the current I sample value, the Q sample value and the previous I sample value, and the Q sample value ( Step 74). The changed I value and Q value are added by the adder 27 (step 75). When N I values and Q values are sampled (step 76), the modified I value and Q value (change values) are stored in the memory 15 (step 77). The stored data is processed by the FFT unit 20 (step 78), and the FFT-transformed value is compared with a given threshold value to determine whether the maximum value is a peak value. (Step 79). Thereafter, if the value is the maximum value as the phase offset of the code numerically controlled oscillator 18, the I value and the Q value are stored (step 80). Thereafter, it is determined whether or not a peak exists (step 81). If there is a peak, the navigation processor 7 calculates the similarity range, phase offset, etc. (step 83). If no peak exists, the next search frequency and code delay value are set (step 82), and the process is repeated again from step 71.

  According to another embodiment of the present invention, the count value of the count 28 and the count values of Tables 1 and 2 of FIG. If a peak is present at the tap, the count value approximates the number of samples and the number of sampled I and Q values. In this embodiment, the peak tap count value must be close to 16. Therefore, for example, when the threshold value is set to 14 and the count value is larger than 14, it is determined that a peak exists in the current tap. According to this embodiment, the sampled I value and Q value are stored in the memory 15 for processing. It is determined that no peak exists in the I sample value and Q sample value of the tap having a count value smaller than the threshold value, and the corresponding I sample value and Q sample value are not stored in the memory 15. Such I sample values and Q sample values are not used for the acquisition operation and are discarded.

  FIG. 10 illustrates an example of a processing process according to the present embodiment. As shown, the receiver receives an I value and a Q value from the tap (step 91). N samples (sampled values) of the integrated correlation value are output to the filter 30. The sampled I and Q values are received by the filter 30 (step 93). The sampled I and Q values are changed to have positive values when a sign change occurs between the current I sample value, the Q sample value and the previous I sample value, and the Q sample value. (Step 94). The changed I value and Q value are added by the adder 27 (step 95). When each of the N I and Q values are sampled (step 96), the count value is compared to the current threshold value of logic circuit 29 (step 97). If the count value is greater than or equal to the current threshold value, it is determined that the unknown tap has a potential peak. In such a case, the sampled I and Q values are stored in the memory 15 (step 98). The stored data is processed by the FFT unit 20 (step 99), and the FFT-transformed value is compared with a given peak threshold value to determine whether a peak exists in the tap ( Step 100). Thereafter, it is determined whether or not a peak exists (step 110). If a peak is present, post processing is performed to calculate the similarity range, phase offset, etc. (step 120). If there is no peak, the next search frequency and code delay value are set (step 130), and the process is repeated from step 91.

  FIG. 11 illustrates an example of a processing process according to the present embodiment. As shown, the receiver according to this embodiment of the present invention receives an I value and a Q value from a tap (step 211). According to this embodiment, N is 16 and the integration period is 1 millisecond. The sampled I and Q values are received by the filter 30 (step 213).

  The sampled I and Q values are changed to have a positive value when a sign change occurs between the current I sample value, the Q sample value and the previous I sample value, and the Q sample value ( Step 214). The changed I value and Q value are added by the adder 27 (step 215). When each of the N I and Q values are sampled (step 216), the count value is compared with the current threshold value of the logic circuit 29 (step 217). If the count value is greater than or equal to the current threshold value, it is determined that the unknown tap has a potential peak. In such a case, the added I value and Q value are stored in the memory 15 (step 218). The stored data is processed by the FFT unit 20 (step 219), and the FFT transformed value is compared with a given peak threshold value to determine whether a peak exists in the tap ( Step 220). If the value is the maximum value as the phase offset of the code numerically controlled oscillator 18, the I value and the Q value are stored (step 221). Thereafter, it is determined whether or not a peak exists (step 222). If there is a peak, post-processing is performed to calculate the similarity range, phase offset, etc. (step 223). If no peak exists, the next search frequency and code delay value are set (step 224), and the process is repeated from step 211 again.

  As described above, according to another embodiment of the present invention using the filter 30 and the counter 28, the count value is used to determine whether a potential peak exists at an unknown tap. If it is determined that the tap has a potential peak, the converted value (I '+ Q') is stored in memory instead of storing the sampled I and Q values as in the previous embodiment. 15 is stored. The stored data is then processed by the FFT unit 20 to determine whether a peak exists at the tap. According to this embodiment, the sampled I and Q values and the converted value (I ′ + Q ′) of the taps determined to have no potential peak are not stored in the memory 15 or processed. The memory 15 is a semiconductor memory, for example, SRAM or DRAM.

  In order to further reduce the data set stored in the memory 15, the sampled I and Q values are multiplied by 1/2, 1/4, etc. by the fractional multiplier before passing through the filter 30, and the value is obtained. Can be reduced. The multiplier / shifter (not shown) may be implemented before the value is input to the adder 27 of FIG.

  Table 3 shows the sampled I and Q values, the reduced I value, the Q value, the converted value (I1 / 2 + Q1 / 2), and the count value of the tap having the peak.

  FIG. 12 is a graph showing change data values of taps (Table 1) where peak values are present and taps (Table 3) where peak values are not present. Referring to this, it can be seen that taps having peaks tend to crowd away from the zero axis, and taps without peaks tend to swing around the zero axis in the other direction.

  A person skilled in the art having ordinary knowledge according to the present invention, in the above embodiment, the filter is constituted by a circuit. You already know that you can embody the function of a filter. The storage device is, for example, a flash memory or a ROM.

  As described above, in the present invention, before storing the correlation-integrated sample value in the memory, the in-phase sample value and the quadrature sample value are added together, and the added sample value is set as the critical value. In comparison, only the correlation integral value above the critical value is stored in the memory, so that the memory storage capacity can be reduced, and the hardware load is reduced by reducing the processor and memory access count for correlation peak search. It can be reduced to improve the capture speed.

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to the embodiments, and as long as it has ordinary knowledge in the technical field to which the present invention belongs, without departing from the spirit and spirit of the present invention, The present invention can be modified or changed.

It is a block diagram which shows the structure of the conventional GPS receiver. It is a block diagram which shows the structure of one channel among N channels of the receiver of FIG. It is a block diagram which shows the structure of the GPS receiver by one Example of this invention. FIG. 4 is a block diagram illustrating a configuration of the filter of FIG. 3 according to an embodiment of the present invention. FIG. 4 is a block diagram illustrating a configuration of the filter of FIG. 3 according to another embodiment of the present invention. FIG. 4 is a block diagram illustrating a configuration of the filter of FIG. 3 according to still another embodiment of the present invention. 2 is a diagram illustrating 16 I sample values and Q sample values presented in Table 1. FIG. 6 is a diagram illustrating 16 I sample values and Q sample values presented in Table 2. FIG. FIG. 5 is a flowchart illustrating a GPS signal processing process according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating a GPS signal processing process according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating a GPS signal processing process according to an embodiment of the present invention. It is a graph which shows the value of the change data with respect to the tap (Table 1) and peak (Table 3) which a peak value does not exist.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Multiplier 13 Correlator 14 Integrator 15 Memory 20 FTF part 25 Sign bit comparison part 27 Adder 30 Filter

Claims (35)

A converter that converts the received GPS signal into an in-phase digital signal I and a quadrature digital signal Q;
A correlator for generating an expected code for one tap and correlating the in-phase digital signal I and the quadrature digital signal Q with the expected code to output a sampled 1 value and Q value;
A filter for filtering the sampled I value and Q value with the changed I value and the changed Q value and adding the changed I value and Q value to output change data;
A memory for storing the change data;
A domain conversion unit that performs domain conversion on the change data and outputs a conversion value;
A comparator for comparing a threshold value and the converted value to determine whether a peak exists in the tap;
A GPS receiver comprising:   The sampled I and Q values are changed to have a positive value when the current I sample value or the current Q sample value is different in sign from the previous I sample value or Q sample value. The GPS receiver according to claim 1   2. The GPS receiver according to claim 1, wherein the changed I value and the changed Q value are values obtained by dividing each sampled I value and Q value by the same value. .   4. The GPS receiver according to claim 3, wherein the reduced value is a value reduced by 1/2. The filter includes a pair of delay elements for delaying the sign bit of the sampled I value and Q value and outputting the previous sign value;
The method of claim 1, further comprising: a pair of single bit comparison units that output a positive value when the signs of the current sampled I value and Q value are different from each other compared to the previous sign value. GPS receiver.   6. The GPS receiver according to claim 5, wherein the filter further includes an adder for performing an operation of adding the changed I value and Q value including a sign bit.   The GPS receiver according to claim 1, wherein the domain conversion unit is a fast Fourier transform unit.   The GPS receiver of claim 1, wherein the memory further stores sampled I and Q values of taps identified as having a peak.   The GPS receiver according to claim 1, wherein the memory is SRAM or DRAM. A converter that converts the received GPS signal of one tap into an in-phase digital signal I and a quadrature digital signal Q;
A correlator for outputting sampled I and Q values having sign bits that correlate the in-phase digital signal I and the quadrature digital signal Q with an expected code to indicate a direction;
Whether at least one sampled I value and Q value sign bit is filtered and whether there is a potential peak in the tap based on the number of direction changes of the sampled I value and Q value sign bits. A filter to judge,
A domain conversion unit that performs domain conversion on the data derived from the sampled I and Q values of the taps determined to have potential peaks and outputs the converted value;
A comparator for comparing a threshold value and the converted value to determine whether a peak exists in the tap;
A GPS receiver comprising:   11. The GPS of claim 10, further comprising a memory for storing data derived from the sampled I and Q values of taps determined to have potential peaks. Receiving machine.   The GPS receiver according to claim 11, wherein the memory is a SARM or a DRAM.   11. The GPS receiver according to claim 10, wherein the data is derived from the sampled I value and Q value by adding the sign-changed I value to the sign-changed Q value.   The sampled I value or Q value is filtered to have a positive value when the current I sample value or current Q sample value is different in sign from the previous I sample value or Q sample value. The GPS receiver according to claim 10.   15. The GPS receiver according to claim 14, wherein the filtered I value and Q value are values obtained by dividing each sampled I value and Q value by the same value. The filter is
A pair of delay elements that delay the sampled I and Q sign bits and output the previous sign value;
The method of claim 10, further comprising: a pair of single bit comparators that output positive values when the signs of the current sampled I and Q values are different from each other by comparing the previous sign values. GPS receiver. Receiving GPS signals from one or more satellites;
Converting the received GPS signal into an in-phase digital signal I and a quadrature digital signal Q;
Generating an expected code and correlating the in-phase digital signal I and the quadrature digital signal Q with the expected code and outputting sampled I and Q values;
Filtering the sampled I value and Q value with the changed I value and the changed Q value, and adding the changed I value and Q value to output change data;
Storing the change data in a memory;
Performing domain transformation on the change data and outputting a transformation value;
Comparing a threshold value and the converted value to determine if a peak is present in the tap;
A GPS signal processing method for determining a position, comprising:   The sampled I or Q value is changed to have a negative value when the current I sample value or current Q sample is different in sign from the immediately preceding I sample value or Q sample value. The GPS signal processing method according to claim 17, wherein:   The GPS signal processing according to claim 17, wherein the changed I value and the changed Q value are values obtained by dividing each sampled I value and Q value by the same value. Method.   The GPS signal processing method according to claim 19, wherein the reduced value is reduced by 1/2. The filtering step includes
Delaying the sign bit of the sampled I and Q values and outputting the previous sign value;
18. The GPS signal processing method according to claim 17, further comprising: outputting a negative value when a sign of a current sampled I value and Q value is different from each other when compared with the previous sign value. . The filtering step includes
The GPS signal processing method according to claim 17, further comprising a step of adding the changed I value and Q value including a sign bit.   The GPS signal processing method according to claim 17, wherein the domain transform is a fast Fourier transform unit.   The GPS signal processing method further includes storing the sampled I and Q values of taps identified as having peaks in the memory and not storing other sampled I and Q values that are not. The GPS signal processing method according to claim 17, wherein: Converting the GPS signal received at the tap into an in-phase digital signal I and a quadrature digital signal Q;
Correlating said in-phase digital signal I and quadrature-phase digital signal Q with an expected code to output sampled I and Q values having sign bits indicating direction;
Filter at least one sampled I-value and Q-value sign bit and determine whether a potential peak exists in the tap based on the number of direction changes of the sampled I-value and Q-value sign bits. And the stage of
Performing a domain transformation on the data derived from the sampled I and Q values of the taps determined to have potential peaks and outputting a transformed value;
Comparing a threshold value with the variable value to determine if a peak exists in the tap;
A GPS signal processing method comprising:   26. The method of claim 25, wherein the GPS signal processing method further includes storing data derived from sampled I and Q values of taps determined to have potential peaks in a memory. GPS signal processing method.   27. The GPS signal processing method according to claim 26, wherein the memory is SRAM or DRAM.   26. The GPS signal processing method according to claim 25, wherein the data is derived from the sampled I value and Q value by adding the sign-changed I value to the sign-changed Q value.   The sampled I and Q values are filtered to have a positive value if the current I sample value or the current Q sample value is different in sign from the previous I sample value and Q sample value. 26. The GPS signal processing method according to claim 25.   26. The GPS signal processing method according to claim 25, wherein the filtered I value and Q value are values obtained by dividing each sampled I value and Q value by the same value. The filtering step includes
Delaying the sign bit of the sampled I and Q values and outputting the previous sign value;
26. The GPS signal processing method according to claim 25, further comprising: outputting a positive value if a sign of a current sampled I value and Q value is different from each other when compared with the previous sign value. . Correlating the in-phase digital signal I and the quadrature digital signal Q with an expected code and outputting sampled I and Q values having sign bits to indicate direction;
Filter at least one sampled I-value and Q-value sign bit and determine whether a potential peak exists in the tap based on the number of direction changes of the sampled I-value and Q-value sign bits. And the stage of
Performing a domain transformation on the data derived from the sampled I and Q values of the taps determined to have potential peaks and outputting a transformed value;
Comparing a threshold value and the converted value to determine if a peak is present in the tap;
A program storage device having a storage code capable of implementing a GPS signal processing method including a process by a process.   The program according to claim 32, wherein the GPS signal processing method further comprises storing in memory a data derived from the sampled I and Q values of taps determined to have potential peaks. Storage device.   34. The program storage device according to claim 33, wherein said memory is SRAM or DRAM.   The program storage device according to claim 32, wherein the program storage device is a flash memory or a ROM (ROM).

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