JP2005018317A - Transaction failure recessing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow the processing of the failure of transaction to be transferred through a bus to have a means adaptive to the transaction failure processing of an operating system. <P>SOLUTION: This transaction failure processing system is provided with: an input buffer 11 for receiving the transaction of a processor bus; and a transaction processing deciding part 15 for selecting failure processing according to transaction classification and failure classification. This transaction failure processing system is further provided with: a transaction converting part 16 for transmitting transaction to a transmission destination without converting it when no failure is detected in the transaction, and transmitting the transaction to the transmission destination by converting it according to the transaction failure processing when any failure is detected in the transaction; a transmission destination output buffer 17 for transmitting the non-converted transaction without any failure and the converted transaction to a transmission destination; and a transmission origin output buffer 18 for converting the failure processing result by using the transaction converting part and returning the conversion result to the transmission origin. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a failure processing system for transactions transferred via a bus, and more particularly, a transaction that is configured by an integrated circuit including a storage circuit mounted on a chipset and can be adapted to transaction failure processing adopted by a predetermined operating system. The present invention relates to a failure handling system.
[0002]
[Prior art]
The CPU, interface unit, and memory are connected to the chipset including the bus control function, and a dedicated operation mode is provided to enable use of some operating system functions including the chipset. The system has been launched faster than it was. In normal startup, it takes time to set up data that can be resumed by waking up various devices. In the start-up in the dedicated operation mode, the operation mode can be shifted to a specific access in a short time such as data reference, and the start-up time is shortened. This is because the bus control and memory control functions mounted on the chipset are kept active, so that wakeup and data resetting are not required. That is, by placing the chipset in an active state, some functions of the operating system are maintained in an active state by an integrated circuit (for example, Patent Document 1).
[0003]
In a system including a processor to which a device is connected, a mapping register for assigning an address and a range in the processor address space of the device is assigned to the device, and by changing the mapping register, an address at which the output of the device selection signal becomes valid There is a configuration that can be changed. Therefore, the configuration is integrated into an integrated circuit and mounted on a chip set. As a result, the address allocation and the occupied space for the device are not fixed but can be made adaptable (for example, Patent Document 2).
[0004]
A computer system having an accelerated graphics port (AGP) bus device and a core logic chipset that functions as a bridge between a host processor and computer system memory, with graphic address remapping to the chipset A table (GART table) is placed to remap the virtual address referenced by the AGP device to the physical address of the graphic information in the memory of the computer system. By controlling the GART table with software, the address of the physical memory can be arbitrarily changed (for example, Patent Document 3).
[0005]
[Patent Document 1]
JP 2002-132393 A (paragraphs 0037 and 0042, FIG. 1)
[Patent Document 2]
JP 11-272600 A (paragraphs 0017, 0030, 0031)
[Patent Document 3]
JP 11-167523 A (paragraph 0026, FIG. 13)
[0006]
[Problems to be solved by the invention]
In an information processing apparatus based on the Intel architecture, a plurality of operating systems such as Windows (registered trademark), Linux, and Unix can operate. Normal functions such as system startup and application running are within the Intel architecture, and thus do not hinder the operation of the above operating system.
[0007]
However, in recent years, operating system vendors have enhanced fault handling functions, but the trend of specification is unclear, and specifications are not being developed in the Intel architecture and other de facto standards. In such an industry situation, if the information processing apparatus is developed after waiting for the determination of the failure processing specification of the operating system, the timing of bringing the information processing apparatus to the market is delayed, and the business chance is reduced. On the other hand, if an information processing device (especially LSI) is developed before the failure handling specifications of the operating system are finalized, the risk of re-creation increases, and if it is re-created, additional development costs are incurred and business performance is impaired. It is. Therefore, in order for the information processing apparatus to flexibly adapt to failure processing of a plurality of operating systems, circuit design that makes the operating system adaptable to an integrated circuit is one of the solutions.
[0008]
Therefore, for failure processing of transactions that are transferred on the bus, depending on the transaction type specified in advance (read request, write request, read and write request completion report) and the failure type, when a failure occurs and when a failure occurs The hardware that can be adapted by changing the failure processing of subsequent transaction failures is integrated into an integrated circuit and mounted on the chipset. By performing setting control by initialization, the information processing apparatus is provided with means for adapting to failure processing of transaction failures that differ for each operating system.
[0009]
An object of the present invention relates to a transaction failure of a transaction transferred via a bus, and includes an integration including a storage circuit that can be set for an operating system that applies the handling of failure processing according to the transaction type and the failure type. The purpose is to provide a circuit that is mounted on a chip set and has adaptability to cope with failure processing of a plurality of operating systems.
[0010]
[Means for Solving the Problems]
Therefore, in the transaction failure processing system for detecting a failure of the transaction and processing the failure with respect to the transaction transferred from the transmission source to the transmission destination via the bus according to the present invention, the input buffer for receiving the transaction from the via bus A transaction processing unit that determines a transaction type and a failure type of the transaction in the input buffer, selects a failure process for a transaction failure in an operating system to be applied, and selects a failure process corresponding to the same transaction type thereafter; In the determination of the transaction processing unit, when there is no transaction failure, the transaction of the input buffer is not converted, and when there is a transaction failure, the transaction A destination that sends a transaction conversion unit that performs the conversion determined by the transaction failure processing and a transaction that is not converted by the transaction conversion processing unit or a transaction that is converted by the transaction conversion unit to the destination An output buffer and a transmission source output buffer that converts the response by the transaction conversion unit and sends it back to the transmission source.
[0011]
Further, the transaction processing unit includes a transaction type determination unit that determines a transaction type of the input buffer, a failure detection unit that detects whether a failure has occurred in the transaction of the input buffer, and a failure type, According to the type and the failure type, there is a first failure processing table that refers to the transaction failure that has occurred for the first time, and a second failure processing table that refers to the transaction type stored in the failure history. A failure processing designation unit and a transaction failure history are stored, the first failure processing table or the second failure processing table is selected and referred to by the history, and a failure is determined based on the transaction type and the failure type. A transaction process determination unit for selecting a process, and Characterized in that it.
[0012]
Further, the transaction is classified into a read request, a write request, a read request completion report, and a write request completion report, and the transaction itself has a header part and a data part, The header portion includes a type code indicating a transaction type, a transmission source code indicating a transmission source, and a transmission destination code indicating a transmission destination. The data portion includes data to be processed and a check code for the data. , Including.
[0013]
Further, the transaction failure is classified as a failure type including a header error and a data error, and the header error is determined as a header error when the type code and the transmission source code and the transmission destination code are illegal codes. When the data error is an error detected by the check code, it is determined that the data error is a data error.
[0014]
Further, the transaction failure processing system is constituted by an integrated circuit including a memory circuit mounted on a chip set, and can be initialized.
[0015]
Further, the first failure processing table is configured by an integrated circuit including a storage circuit mounted on a chipset, and includes assumed failure processing for transaction failures of a plurality of applicable operating systems, the transaction type, and the failure type. A failure processing selector employed by a predetermined operating system is initially set in the cell in a table including a combination of cells.
[0016]
Further, the second failure processing table is composed of an integrated circuit including a storage circuit mounted on a chipset, and includes assumed failure processing for transaction failures of a plurality of applicable operating systems, the transaction type, and the failure type. In the table composed of the combination of cells, a selector is initially set in the cell for failure processing for an existing transaction failure adopted by a predetermined operating system.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described with reference to the drawings. Referring to FIG. 1 showing an embodiment of the present invention, it is possible to change failure processing selected in a combination of a transaction type and a failure type for a transaction failure mounted on a chip set (not shown). Transaction processing unit 10 that can be processed, an input buffer 11 that receives a transaction from the outside such as a processor bus (not shown), and a transaction processing unit 10 that selects a failure processing designated for the transaction failure and converts the transaction A conversion unit 16, an output buffer 17 connected to a PCI bus or the like for transmitting the converted transaction to the transmission destination, and an output buffer 18 connected to a processor bus or the like for returning the converted transaction to the transmission source.
[0018]
The transaction processing unit 10 includes a transaction type determination unit 12 that determines the transaction type of a transaction received from the input buffer 11, a failure detection unit 13 that detects a failure type of the transaction received from the input buffer 11, a transaction type and a failure type The failure processing designation unit 14 having the first failure processing table 141 and the second failure processing table 142 for designating the failure processing corresponding to the transaction type, the transaction type of the transaction type determination unit 12, and the failure of the failure detection unit 13 The type and the history of whether the transaction failure has occurred for the first time or whether the transaction failure has occurred before are stored, and the first failure processing table 141 or the second failure processing table 142 is stored according to the history. Browse and select It includes a transaction processing determination unit 15 to select harm process, the.
[0019]
Referring to FIG. 2, the configuration of a transaction will be described. The transaction 20 indicates transfer data that is input from the outside such as a processor bus and output to the outside such as a PCI bus through the transaction processing unit 10, and includes a header 21 and data The header 21 includes a transaction type 211, a transmission source 212, a transmission destination 213, and a check code 214. The data 22 includes the data itself 221 and its check code 222. Including.
[0020]
Further, when the transaction type 211 of FIG. 3 is used as the transaction type 211, a read request (with data reply), a write request (with completion report), a write request (without completion report), a completion report with data, And no data completion report.
[0021]
Furthermore, the error type is roughly divided into a case where there is an error in the header 21 and a case where there is an error in data when the failure type 1412 of FIG. 3 is used. A header error indicates an illegal code of an item included in the header, and a data error indicates an error detected by a check code.
Further, the transaction failure includes a transaction failure of a type determined by combining a header error header error and a data error with respect to one of the transaction types when the transaction type 1411 and the failure type 1412 of FIG. 3 are used. .
[0022]
The first failure processing table 141 will be described with reference to FIG. 3. The first failure processing table 141 is applied to failure processing for a transaction failure that has occurred for the first time. This table is composed of cells 1413 to 1420 in which failure processing adopted by a plurality of operating systems assumed to be applied to combinations of transaction types and failure types. In addition, there are failure processing that can be selected and failure processing that cannot be selected for transaction failures. For failure processing that cannot be selected, a non-selectable identifier is set in advance, and for selectable failure processing, a selectable identifier is set in advance. A selector is set in the corresponding selectable cell, and the first failure processing table 141 is individualized.
The second failure processing table 142 will be described with reference to FIG. 4. The second failure processing table 142 is applied to a transaction of a transaction type stored in the transaction failure history, and a transaction of a predetermined operating system. Ensure consistency in fault handling for faults. The second failure processing table 142 is a table having cells 1422 to 1429 in which failure processing adopted by a plurality of operating systems assumed to be applied to the transaction types stored in the history is arranged. Further, there are failure processing that can be selected and transaction processing that cannot be selected for the transaction type. For failure processing that cannot be selected, a non-selectable identifier is set in advance, and for selectable failure processing, a selectable identifier is set in advance. A selector is set in the corresponding selectable cell, and the second failure processing table 142 is individualized. That is, the transaction type that caused the transaction failure is subjected to consistent failure processing after being registered in the history.
[0023]
Next, the operation of this embodiment will be described. The transaction 20 is supplied from the outside such as a processor bus, and is first stored in the input buffer 11 that can temporarily hold the transaction 20. The input buffer 11 is connected to the transaction type determination unit 12 and the failure detection unit 103. The transaction type determination unit 12 interprets the type 211 of the transaction 20 held in the input buffer 11, reads a request (with data reply), a write request (with completion report), a write request (without completion report), It is classified into a completion report with data and a completion report without data. In addition, this classification result is transmitted to the transaction processing determination unit 15.
[0024]
The failure detection unit 13 determines whether or not a failure has occurred in the transaction held in the input buffer 11, and if a failure has occurred, determines the failure type of a header error or a data error. Also, the failure type result is transmitted to the transaction process determination unit 15. Since the transaction 20 is roughly divided into one having only the header 21 without the data 22 and one having the data 22 and the header 21, the failure type 1412 is also classified into two failure types, header error and data error. Can be divided roughly.
[0025]
The failure processing designation unit 14 selects the failure processing of the transaction in which the failure has occurred for the first time and the transaction after the failure has occurred, by combining the transaction type and the failure type. For failure handling that is applied to a plurality of operating systems applied to a transaction failure, forward of the failure header (forward indicates an operation for sending a transaction to a transmission destination) 1413 and data forward with an error (data is an error) If the correction code is included, the error correction code indicating that an error has occurred is replaced with the data, and if the data is not with the error correction code but with parity, the parity bit is inverted and there is no transaction without a header. Therefore, data with an error is always transmitted as a header and a set and transferred to the transmission destination) 1414, an error header response (response indicates an operation for returning a transaction to the transmission source) 1415, an all-one data response 1416, , With error Data response (error attached how the data is the same as the error with data forward) and 1417, and discard 1418, non-conversion forward (the transaction nothing directly forward without) and 1419, or, as the non-conversion response 1420, there is. One of the failure processes described above is selected and transmitted to the transaction process determination unit 15.
[0026]
The transaction process determination unit 15 determines the transaction failure process based on the combination of the transaction type 1411, the failure type 1412, and the failure processes 1413 to 1420. The failure processing table 141 is a list of failure processing for the transaction failure that has occurred for the first time (the transaction itself becomes a failure). The failure processing table 142 is a list of failure processing 1422 to 1429 for the transaction type 1421 stored in the failure history after the occurrence of a transaction failure.
[0027]
The failure processing table 141 and the failure processing table 142 indicate specific failure processing to the transaction processing determination unit 15. For example, if the header of the read request has an error (header error) and the failure processing table 141 has selected an error header response, the failure processing specification unit 14 notifies the transaction processing determination unit 105 of the selection, and transaction processing The determination unit 105 instructs the transaction conversion unit 16 to convert the transaction into an error header response. Further, the transaction process determination unit 15 has a function of storing a transaction failure as a history, and can distinguish whether the transaction failure has occurred for the first time or the transaction failure has already been stored in the history. For example, if the selection from the failure processing designation unit 14 is abandoned for a write request with a completion report after the occurrence of a transaction failure, the transaction processing determination unit 105 discards the corresponding transaction in the transaction conversion unit 106 (forward) Alternatively, it is instructed not to make a response and to discard the transaction in the transaction processing unit 10).
[0028]
The transaction conversion unit 16 converts the transaction stored in the input buffer 11 according to the selection of the transaction processing determination unit 15 and processes one of forward, response, and discard. In the case of forwarding, the converted transaction is stored in the output buffer 17 and finally sent to the transmission destination. When responding, the transaction is sent to the output buffer 18, and finally the transaction is returned to the transmission source.
[0029]
Next, a specific example will be described with reference to the failure processing table 143 of FIG. 5 and the failure processing table 144 of FIG. 6 in which the failure processing table 141 and the failure processing table 142 of this embodiment are individualized by selectors. To do. The selection of failure processing for a transaction failure that occurs for the first time at initialization is set in the cell of the failure processing table 143 and individualized for a predetermined operating system.
When read request is header error; data all 1 response.
Completion report and write request when header error; no conversion response.
When a write request with a completion report is a data error; data forward with error.
No completion report When write request is header error; Discarded.
No completion report When write request is data error; data forward with error.
When the completion report with data is a header error;
When the completion report with data is a data error; data forward with error.
When no data complete report is header error; discarded.
[0030]
When initializing fault processing for a transaction fault after the occurrence of the fault, a selector is set in the cell of the fault processing table 144 and individualized for a predetermined operating system. For transactions stored in the transaction failure history, consistent failure processing by transaction type is adopted.
When a read request is made; data all 1 response.
When there is a completion report and a write request; no conversion response.
When a write request with no completion report is made;
When reporting completion with data;
When reporting no data completion;
[0031]
A specific operation will be described with reference to the failure processing table 143 and the failure processing table 144. The transaction 20 is first stored in the input buffer 11. The transaction type of the transaction 20 stored in the input buffer 11 is determined by the transaction type determination unit 12. In parallel with this, the failure detection unit 13 determines whether a failure has occurred and whether it is a header error or a data error. When the transaction 20 stored in the input buffer 11 is a read request and a header error, the transaction process determination unit 15 includes a transaction type determination unit 12, a failure detection unit 13, and a failure process table 143 of the failure process specification unit 14. To convert the transaction into a data all 1 response.
[0032]
The determination result is transmitted to the transaction conversion unit 16, and the transaction conversion unit 16 converts the read request stored in the input buffer 11 into a data all 1 response in accordance with this instruction and stores it in the output buffer 18. Finally, a data all 1 response is returned from the output buffer 18 to the transmission source. If there is no failure in the read request of the transaction 20 stored in the input buffer 11, the transaction conversion unit 16 does not perform conversion, but stores it in the output buffer 17 as it is and sends it to the transmission destination. Since the transaction processing determination unit 15 stores that the transaction failure has occurred after the failure occurs, the transaction processing is performed according to the failure processing table 144 stored in the failure processing designation unit 14. The read request is set in the data all 1 response 1445, the write request with end report is set in the no-conversion response 1447, and the selector is set, so the response is returned to the transmission source. The write request without completion report, the completion report with data, and the completion report without data are all discarded 1447.
[0033]
Even when a failure occurs in a transaction other than a read request, the failure processing of the transaction is performed according to the failure processing table 144 at the time of failure occurrence set in the failure processing designation unit 14 described above. Regardless of the type of transaction in which a failure has occurred, after the failure occurs, the transaction 20 stored in the input buffer 11 is subjected to failure processing according to the failure processing table 144 after the failure has occurred. If the selector set in the failure processing specification unit 14 is changed, the transaction processing unit 10 can flexibly adapt to the failure processing for the transaction failure of the operating system to which the transaction occurs when the failure occurs and after the failure occurs.
[0034]
【The invention's effect】
The effect of the present invention is that an error processing adapted to a transaction failure of an operating system is integrated into an LSI such as an information processing apparatus in an integrated circuit, so that a difference in the failure processing specification of a transaction failure for each operating system or a delay in specification determination As a result, the development risk of LSI and operating system can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a transaction failure processing system.
FIG. 2 is a diagram illustrating an example of a transaction configuration.
FIG. 3 is a diagram illustrating a configuration of a first failure processing table.
FIG. 4 is a diagram illustrating a configuration of a second failure processing table.
FIG. 5 is a diagram individualizing a first failure processing table.
FIG. 6 is a diagram individualizing a second failure processing table.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Transaction processing part 11 Input buffer 12 Transaction type determination part 13 Failure detection part 14 Failure process designation | designated part 15 Transaction process determination part 16 Transaction conversion part 17 Output buffer

Claims (7)

In a transaction failure processing system that detects a failure of the transaction and handles the failure for a transaction that is transferred from the source to the destination via the bus,
An input buffer that receives transactions from the transit bus,
A transaction processing unit that determines a transaction type and a failure type of the transaction in the input buffer, selects a failure process for a transaction failure in the operating system to be applied, and selects a failure process corresponding to the same transaction type thereafter;
In the determination of the transaction processing unit, when there is no transaction failure, the transaction of the input buffer is not converted, and when there is a transaction failure, the transaction is discarded or converted as determined by the transaction failure processing. And
A destination output buffer that transmits a transaction that is not converted by the transaction conversion processing unit, or a transaction that is converted by the transaction conversion unit, to a destination;
A source output buffer that converts the response in the transaction conversion unit and sends it back to the source;
A transaction failure processing system comprising: The transaction processing unit
A transaction type determination unit for determining the transaction type of the input buffer;
A failure detection unit for detecting whether a failure has occurred in the transaction of the input buffer and a failure type;
In accordance with the transaction type and the failure type, a first failure processing table that is referred to for a transaction failure that has occurred for the first time, and a second failure processing table that is referenced to the transaction type stored in the failure history, A fault handling designation unit having
Transaction processing for storing transaction failure history, selecting and referring to the first failure processing table or the second failure processing table based on the history, and selecting failure processing based on transaction type and failure type A determination unit;
The transaction failure processing system according to claim 1, further comprising: The transaction is
Read request, write request, read request completion report, and write request completion report are classified as types,
The transaction itself is
A header portion and a data portion;
The header part is
Including a type code indicating a transaction type, a source code indicating a source, and a destination code indicating a destination,
The data part is
3. The transaction failure processing system according to claim 1, further comprising: data to be processed and a check code for the data. The transaction failure is
Header error and data error are fault types,
The header error is
When the type code and the transmission source code and the transmission destination code are illegal codes, it is determined as a header error,
The data error is
3. The transaction failure adaptive processing system according to claim 1, wherein when the error is detected by the check code, it is determined as a data error. The transaction failure processing system includes:
3. An adaptive processing system capable of dealing with transaction failures according to claim 1, wherein the adaptive processing system comprises an integrated circuit including a memory circuit mounted on a chip set and can be initialized. The first failure processing table is:
An integrated circuit including a storage circuit mounted on a chipset is configured, and a table including a combination of assumed failure processing for transaction failures of a plurality of applicable operating systems, the transaction type, and the failure type is predetermined. 3. The transaction failure processing system according to claim 2, wherein a failure processing selector adopted by the operating system is initialized in the cell. The second failure processing table is
It is composed of an integrated circuit including a memory circuit mounted on a chip set, and a table including a combination of assumed failure processing for a transaction failure of a plurality of applicable operating systems, the transaction type, and the failure type is predetermined. 3. The transaction fault processing system according to claim 2, wherein a selector is initially set in the cell for fault processing for an existing transaction fault adopted by said operating system.

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