JP2005017725A - Display device and image signal processing method for the image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device that can reduce the circuit scale, mount area, and price of an image signal processing circuit, decrease the number of output signals to a data driver IC, and more preferably perform excellent high-speed data transfer, and to provide an image signal processing method for the display device. <P>SOLUTION: The display device is equipped with: an image signal processing part 1 which processes an image signal; and a display part which displays an image according to the image signal which has been processed by the image signal processing part 1. Further, the display device is equipped: with a frame rate conversion processing part 4 which performs frame rate conversion; and an array conversion processing part 6 which converts the frame-rate converted image signal to an array corresponding to the display part. This display device is equipped with frame memories 11 to 14 having a plurality of memory areas 21 to 28 which can be individually read and written. This display device performs write processing by using the array conversion processing part 6 to a memory area where a read operation by the frame rate conversion processing part 4 has been completed, and thus the frame rate conversion processing part 4 and array conversion processing part 6 share the frame memory. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device and an image signal processing method for a display device.
[0002]
[Prior art]
For example, a surface discharge type plasma display device includes two glass substrates, and each of the two glass substrates has a row electrode (scanning electrode and common electrode) extending in the row direction and a column direction. An extending column electrode (data electrode) is provided. A dielectric layer and a protective layer are provided on the row electrode of the glass substrate on which the row electrode is provided, and a dielectric layer and a phosphor layer are provided on the column electrode on the glass substrate on which the column electrode is provided. Is provided. Furthermore, a partition is provided between each column electrode, and two glass substrates are arranged opposite to each other with a small space by the partition, and a discharge gas is sealed in a plurality of cells partitioned by the partition and arranged in a matrix. Thus, a planar plasma display panel having a matrix structure is formed.
[0003]
In this plasma display panel, the row electrode and the column electrode are separately driven to generate plasma discharge in the discharge gas in the cell at the intersection of the driven row electrode and column electrode. The fluorescent material provided on the column electrode is excited to emit light. In the case of a display panel that performs color display, each column electrode is composed of electrodes using phosphors of R (red), G (green), and B (blue), and each color electrode is provided for each column. By individually driving each, color display can be performed.
[0004]
In this case, as a driving method of each electrode, as a row electrode, for example, an X electrode provided in common in each row and a Y electrode provided in each row are alternately arranged, and the X electrode and the Y electrode are arranged. An AC (alternating current) driving method is generally used in which a voltage pulse is alternately applied between them to cause a discharge whose polarity is reversed every half cycle.
[0005]
In such an AC-driven plasma display panel (AC-PDP), once a discharge occurs between the electrodes of each cell, electrons and ions generated in the discharge space accumulate on the dielectric layer and become wall charges. Is formed. In a cell in which wall charges are formed, discharge at a low voltage is possible by the action of the electric field of the wall charges, and discharge can be maintained by inverting this low voltage every half cycle. This function is called a memory function, and a discharge maintained at a low applied voltage by this function is called a sustain discharge.
[0006]
In order to perform gradation display of an image in AC-ADP, a sub-frame display method for dividing an image signal of one frame period into a plurality of sub-frames and controlling the time (number of times) to emit light by sustain discharge for each sub-frame. Is taken. Specifically, for example, a sustain discharge period that increases at a power of 2 is assigned to each subframe while resetting every frame. As a result, a cell having a larger number of sustain discharges emits light brighter, so that gradation display can be performed.
[0007]
The configuration of the AC color PDP apparatus and the configuration and operation of a data driver IC that finally receives display data as a digital signal from an image signal processing circuit (described later) and supplies it to the plasma display panel will be described below.
[0008]
FIG. 14 is a block diagram showing the configuration of a general AC type color PDP apparatus, FIG. 15 is a diagram showing the configuration of the data driver IC, and FIG. 16 is a timing chart showing the display data input format of the data driver IC.
[0009]
As shown in FIG. 14, the AC type color PDP apparatus 100 includes a plurality of data driver ICs 101, an AC type plasma display panel (AC-PDP) 102, a plurality of scan driver ICs 103, an image signal processing circuit 104, and a drive. A signal generation circuit 105 and a high voltage drive circuit 106 are provided.
[0010]
Among them, the data driver IC 101 receives a predetermined number (n) of serial display data signals corresponding to the total number L of column electrodes from the image signal processing circuit 104 and receives a parallel latch control signal from the drive signal generation circuit 105. Accordingly, a data signal is output in parallel to each column electrode for each scanning period.
[0011]
The AC-PDP 102 is an AC driving type plasma display panel that performs driving by a sub-frame display method using a memory function, and sequentially arranges K rows of electrodes and electrodes corresponding to three colors of R, G, and B. The electrode arrangement is such that column electrodes (data electrodes) arranged in L rows are arranged in a matrix.
[0012]
The scan driver IC 103 sequentially outputs scan signals to the K row electrode in response to the row drive signal from the drive signal generation circuit 105.
[0013]
The image signal processing circuit 104 converts an image signal corresponding to three colors of R, G, and B into a serial display data signal that is a data array received by the data driver IC 101, and the serial display data signal is converted into a subframe display method. Is output to the data driver IC 101 in synchronization with this timing.
[0014]
The drive signal generation circuit 105 generates a row drive signal and a column drive signal according to a predetermined sequence of a subframe display method for each frame in accordance with a vertical synchronization signal included in image data detected by a vertical synchronization signal detection circuit (not shown). Is supplied to the data driver IC 101 and the scan driver IC 103.
[0015]
The high voltage drive circuit 106 supplies high voltage power to each data driver IC 101 and scan driver IC 103 in accordance with the drive signal from the drive signal generation circuit 105.
[0016]
As shown in FIG. 15, the data driver IC 101 includes a shift register circuit 111 composed of n stages of shift registers, a parallel latch circuit 112 for n circuits, and n output control logic gate circuits G1, G2, G3. , Gn and n high-voltage CMOS (Complementary Metal Oxide Semiconductor) drivers B1, B2, B3, B4,..., Bn.
[0017]
Among these, the shift register circuit 111 shifts and inputs the serial display data signal D <b> 1 input from the image signal processing circuit 104 for each scanning period in accordance with the shift clock signal SCK from the drive signal generation circuit 105.
[0018]
The parallel latch circuit 112 latches the output from the n-stage shift register of the shift register circuit 111 according to the parallel latch control signal LE from the drive signal generation circuit 105.
[0019]
The output control logic gate circuits G1, G2, G3, G4,..., Gn correspond to the parallel input signals Q1, Q2, Q3, Q4 from the parallel latch circuit 112 in response to the output control signal OE from the drive signal generation circuit 105. ,..., Qn are output in parallel for each scanning period.
[0020]
High-voltage CMOS drivers B1, B2, B3, B4,..., Bn are connected in parallel from the output control logic gate circuits G1, G2, G3, G4,. The input signals Q1, Q2, Q3, Q4,..., Qn are converted into data signals O1, O2, O3, O4,.
[0021]
As an example of the display data input form of the data driver IC 101, FIG. 16 shows the case of 1-bit data input.
[0022]
In the case of 1-bit data input, when the input data D1 is repeatedly arranged in the order of R, G, and B, the shift register circuit 111 is sequentially shifted at every rising edge of the shift clock signal SCK and shifted to the end. At the falling edge of the parallel latch control signal LE, it is latched in parallel by the parallel latch circuit 112, and one bit at a time, like serial display data signals On, On-1, On-2,..., O3, O2, O1. Is output.
[0023]
In this case, since the high level of the parallel input signal Q is converted to the high voltage power supply voltage Vd and the low level is converted to 0 V and output, the high voltage power supply voltage Vd is applied to the data electrode (column electrode) according to the parallel input signal Q. When applied, a discharge occurs in a cell at the intersection with the scanned row electrode, and display data is written to the panel.
[0024]
In the sub-frame period, display data transfer-data electrode output-cell writing is repeated for the number of lines necessary for display, and then discharge is emitted for the number corresponding to the brightness of the image in the sustain period. For example, an image of one frame input as an 8-bit image signal for each RGB color has a subframe period for each bit within one frame period, and displays the gradation of the image as a whole.
[0025]
Next, the circuit configuration and operation of the image signal processing circuit 104 will be described. FIG. 17 is a block diagram showing a configuration example of the image signal processing circuit 104 of the conventional color PDP apparatus.
[0026]
As shown in FIG. 17, the image signal processing circuit 104 includes a resolution conversion circuit 1041, an inverse γ correction circuit 1042, a frame rate conversion circuit 1043, a subframe data conversion circuit 1044, a data array conversion circuit 1045, and a subframe data read circuit 1046. It has.
[0027]
The image signal input to the color PDP device passes through a resolution conversion circuit 1041 based on 8-bit parallel signal processing, an inverse γ correction circuit 1042, and a frame rate conversion circuit 1043, and is a signal processing circuit unique to the latter half of the PDP. It always passes through the frame data conversion circuit 1044 and the data array conversion circuit 1045, and the display data is serially transferred to the data driver IC 101 in accordance with the timing of the subframe display method.
[0028]
The individual circuits in the image signal processing circuit 104 function as follows.
[0029]
First, the resolution conversion circuit 1041 will be described with reference to FIGS. Here, for the sake of simplicity, an example will be described in which resolution conversion is performed such that the number of scanning lines of an image signal is increased from 240 to 480, for example.
[0030]
As shown in FIG. 18, in order to double the number of scanning lines, a scanning line L103 is newly added at an intermediate position between the scanning lines L101 and L102 that are vertically adjacent on the display screen. Here, the scanning line L103 is a scanning line having the image characteristics of both the upper and lower scanning lines L101 and L102. Therefore, average data obtained by adding the pixel data in the image signals of the upper and lower scanning lines L101 and L102 and dividing by 2 is assigned to the pixel data corresponding to the scanning line L103.
[0031]
When the image signals of the upper and lower scanning lines L101 and L102 are added in this way, it is necessary to simultaneously obtain the corresponding image signal of the upper scanning line L101 during the period when the image signal of the lower scanning line L102 is input. is there. For this purpose, for example, as shown in FIG. 19, it is preferable to provide a line memory 1041a as a delay line for delaying the image signal exactly by one scanning period. Further, an adder 1041b for adding signals, a bit shift circuit 1041c for dividing by 2, a write side for outputting to the image signal processing circuit in the next stage as a continuous scan line after the addition of the scan line, and a read side Two lines of line memories 1041d and 1041e are provided.
[0032]
Here, since the resolution conversion circuit 1041 converts the input signal into a signal having twice as many scanning lines as the input signal, the scanning line period is halved when the frame rate does not change, for example, at 60 Hz. Accordingly, the line memory 1041e for two lines operates with the cycle of the read clock as half the clock cycle of the input image signal.
[0033]
Next, the inverse γ correction circuit 1042 will be described with reference to FIG.
[0034]
In general, an image signal such as a broadcast image signal is output with a characteristic called γ correction added to the display characteristic of a display device using a cathode ray tube. In a color PDP device or the like, unlike the case of a cathode ray tube, since the image signal level and the displayed brightness are in a substantially proportional relationship, when the input image signal is displayed as it is, the originally dark portion of the image is displayed brighter and is not displayed. Natural image display. For this reason, the image signal processing circuit 104 of the plasma display apparatus performs correction to cancel the γ correction added to the image signal. This correction is performed by the inverse γ correction circuit 1042, and for example, the inverse γ correction is performed with the conversion characteristics as shown in FIG. When such inverse γ correction is realized by digital signal processing, as shown in FIG. 20A, ROM data is generally given conversion characteristics and the ROM 1042a is used as a lookup table.
[0035]
Next, the frame rate conversion circuit 1043 will be described with reference to FIGS.
[0036]
In general, the frame rate (vertical frequency) of an image signal input to a color PDP device or the like is not limited to one type. For example, in addition to 60 Hz, an image signal of 50 Hz or 75 Hz exists.
[0037]
Of course, it is possible to perform the display operation of the color PDP apparatus by preparing an operation mode for each frame rate of the input image signal. However, in order to operate a high-speed and complicated plasma display driving circuit composed of a high-voltage circuit, the color PDP apparatus If the frame rate can be unified at the display operation stage, display performance, power consumption, circuit cost, etc. can often be optimized. For this reason, a frame rate conversion circuit 1043 may be mounted on the image signal processing circuit 104 to unify the frame rate at the display operation stage. Here, for the sake of simplicity, an example will be described in which, for example, an input image signal of 75 Hz is converted to 60 Hz as shown in FIG.
[0038]
There are various types of frame rate conversion circuit 1043. In the case of the example of FIG. 21, the ratio of two frequencies (75:60) is 5: 4, so one frame is removed for every five frames of the input signal image. Then, frame rate conversion that connects images (5 frames to 4 frames) is good.
[0039]
Here, the frame-excluded frame (frame drop frame) image is simply discarded (because it is not distributed to the previous and next frames), so the motion may look awkward in moving images, but the previous and next frames are not processed. It will not be a blurred image.
[0040]
FIG. 22 shows a configuration example of the frame rate conversion circuit 1043.
[0041]
The frame rate conversion circuit 1043 of this example includes a frame memory 1043a having a capacity of several frames in order to absorb a time difference due to a difference in input / output rates and connect the image signals before and after frame removal without interruption. For example, when converting from 75 Hz to 60 Hz, the frame memory 1043a for three frames is provided.
[0042]
In frame rate conversion, input image signals are sequentially written in these frame memories 1043a, and image signals are read from the frame memory 1043a that has been written at a speed corresponding to 60 Hz after frame rate conversion. Here, since the speed on the reading side is slower than that on the writing side, the interval from writing to reading gradually increases. At the timing when there are two frame memories 1043a that have been written but have not been read, the reading side skips reading of the next frame memory 1043a and shifts to reading of the next frame memory 1043a. As a result, overflow on the writing side is prevented and frame removal of one frame occurs. In this way, a continuous image signal with a reduced frame rate from 75 Hz to 60 Hz is obtained.
[0043]
Next, the subframe transform coding circuit 1044 will be described with reference to FIG.
[0044]
In a color PDP apparatus, one frame period is divided into small periods called subframes, each subframe displays a gradation of a specific bit of an image signal by controlling the number of times of light emission, and the subframe of each bit is temporally displayed in one frame. All the gradations of the image signal are displayed in the series. In this case, the 8-bit image signal may be allocated to the 8-bit subframe as it is. However, in order to improve the display image quality, the image data is converted from the binary format data to other formats and is redundant. There is a method of assigning to each subframe with a larger number of bits. A conversion coding method is generally a method in which ROM data has conversion characteristics and ROM 1044a is used as a look-up table, as in the case of inverse γ correction. FIG. 23 shows an example in which subframe conversion coding is performed from a 4-bit signal to a 5-bit signal for simplicity.
[0045]
Next, the data array conversion circuit 1045 will be described with reference to FIGS.
[0046]
Unlike the conventional image display using a cathode ray tube or the like, the sub-frame display method as described above in the color PDP apparatus emits pulses for the number of times corresponding to the bit weight during the sub-frame period for each bit of the image signal. The subframes are arranged in time series to display the image signal.
[0047]
For this reason, a general 8-bit parallel signal as digital signal processing is not suitable as display data for the subframe display method, and as shown in FIG. 24, a display data format finally transferred to the data driver IC 101, that is, It is necessary to convert the array into a serial display data signal (perform data rearrangement).
[0048]
This process is performed by the data array conversion circuit 1045. As an example of the data array conversion circuit 1045, as shown in FIG. 25, two frame memories 1045a and the number of image signal lines arranged before writing to the frame memory are used. There is a configuration comprising the line memory 1045b.
[0049]
The two frame memories 1045a provide a function of storing an image signal to be written into a grouped area in the memory for each bit, and a specific bit data in the stored image signal is read according to the timing of the subframe display method. The functions are alternately handled (double buffer operation is performed).
[0050]
In addition, as shown in FIG. 26, a line memory is used to create data to be written to the frame memory, and an image signal for one scanning period is divided and parallelized in accordance with the number of outputs of the data driver IC 101. Each bit data is arranged in time series and written to the frame memory.
[0051]
The reason why the data array conversion circuit 1045 requires a frame memory is that the input image signal is a time-series signal composed of scanning lines throughout the frame period, whereas in the sub-frame display method, it is specified within the sub-frame. This is because it is necessary to read out and output from the first scanning line data to the last scanning line data for each bit, so that one frame is required as a buffer.
[0052]
[Problems to be solved by the invention]
Incidentally, the image signal processing circuit 104 in the conventional PDP apparatus includes a frame memory 1043a dedicated to the frame rate conversion circuit 1043 and a frame memory 1045a dedicated to the data array conversion circuit 1045. The reason why the conventional image signal processing circuit 104 needs to include the frame memory 1043a and the frame memory 1045a as described above is as follows.
[0053]
In the conventional image signal processing circuit 104, the resolution conversion circuit 1041, the inverse γ correction circuit 1042, and the frame rate conversion circuit 1043 that precede the data array conversion circuit 1045 perform parallel signal processing of 8-bit RGB colors. It has become. For this reason, the frame rate conversion circuit 1043 includes a frame memory 1043a for parallel processing.
[0054]
By the way, in the image signal processing circuit 104 of the color PDP, as shown in FIG. 24, one frame period is divided into a plurality of subframe periods, and each subframe performs discharge light emission by a single bit brightness. Since the sub-frame display method is employed in which the discharge light emission of each bit data is added by the afterimage effect of the human eye and the image is displayed throughout the period, it is necessary to rearrange the arrangement of the image signals. Further, in the color PDP, as many data driver ICs 101 as the number of outputs are connected to the data electrodes, the image area is divided in units of the number of outputs of the data driver IC 101, and the display data is simultaneously displayed to each data driver IC 101. Must be transferred.
[0055]
That is, the data array conversion circuit 1045 performs a process of arranging the data in time series for each bit and converting the display data to be transferred to each data driver IC 101 at the same time. A frame memory 1045a is provided as a buffer memory for storing data.
[0056]
The data stored in the frame memory 1045a has a storage area (address) in the frame memory for each bit as shown in FIG. 27 (b) for the purpose of outputting all data of a specific bit during the subframe period. It is divided and stored in an array 271 that is parallelized with the number of outputs of the data driver IC 101 as a unit. Here, for the sake of simplicity, FIG. 27 shows a case where the entire number of horizontal pixels on the display screen is assigned to the four data driver ICs 101. However, in practice, for example, the assignment is made to 32 data driver ICs 101. Accordingly, only 32 arrays 271 shown in FIG. 27B are stored in the frame memory 1045a.
[0057]
Here, the data stored in the frame memory 1045a is not a bitmap type memory mapping that has been conventionally used in image signal processing (similar in relative arrangement to the screen display of the image signal), but 8-bit parallel. Not suitable for signal processing.
[0058]
Therefore, when adding or subtracting normal image signal processing in the frame array data array conversion frame memory, an 8-bit parallel signal cannot be read out all at the same time. However, high-speed reading of specific bit data corresponding to the subframe display method is not possible.
[0059]
Therefore, the data array conversion frame memory 1045a should be shared with the frame memory 1043a used in normal 8-bit parallel signal processing (data is stored in the bitmap format as shown in FIG. 27A). Is difficult, and is dedicated to the data array conversion circuit 1045.
[0060]
As a result, conventionally, as shown in FIG. 17, the data array conversion frame memory 1043a has one frame for each of the writing side and the reading side (double buffer system). The memory 1043a and the frame memory 1045a for parallel processing require a total of 5 frames of memory.
[0061]
For this reason, there is a problem that the circuit scale and mounting area of the image signal processing circuit 104 are large and cost is high.
[0062]
In addition, since the number of frame memories is large as described above, it is necessary to divide the LSI constituting the image signal processing circuit 104 into a plurality of parts because of the number of terminals.
[0063]
Therefore, the conventional image signal processing circuit 104 has an 8-bit parallel signal processing block 104A (FIG. 17) including a resolution conversion circuit 1041, an inverse γ correction circuit 1042, and a frame rate conversion circuit 1043, for example, as shown in FIG. Signal processing board 251 and data array conversion board 252 forming data array conversion block 104B (FIG. 17) including SF conversion circuit 1044, data array conversion circuit 1045, and SF readout circuit 1046 ( Chip).
[0064]
In addition, since the number of frame memory input / output signal terminals and the number of display data output terminals to the data driver IC 101 in the image signal processing circuit 104 are large, the LSI package constituting the image signal processing circuit 104 has a large number of pins, resulting in high costs. There was also.
[0065]
The data driver IC 101 to which display data is transferred from the image signal processing circuit 104 is arranged along the long side of the color PDP. For example, in the case of a color PDP having 1024 horizontal pixels, a data driver having 96 outputs is provided. If the IC 101 is used, the number of necessary data driver ICs is 3 (colors) × 1024/96 = 32 (pieces). Therefore, display data corresponding to each data driver IC 101 is quickly and reliably transmitted from the image signal processing circuit 104 in one place on the apparatus to as many as 32 data driver ICs 101 in a wide range at a common timing. Technology to transfer (send) is required.
[0066]
The need to transfer data at high speed is increasing as the number of outputs of the data driver IC 101 increases due to cost reduction and the scan time (display data transfer period) tends to decrease for improving brightness. .
[0067]
For example, when the data driver IC 101 with 96 outputs is used, when the scanning time for one line is set to 2 microseconds in the scanning period, the data transfer rate is obtained when a signal is transferred to one data driver IC with one signal line. Is 96/2 = 48 mega / second (48 MHz).
[0068]
An interval of, for example, about 1 meter is assumed from the image signal processing circuit 104 on the transmission side to the data driver IC 101 on the reception side, but the above-described data transfer rate is very high as a signal on the transmission line having this length. It has become a thing.
[0069]
Conventionally, for example, data transfer using a CMOS signal with 5 V amplitude or 3.3 V amplitude is employed. However, in such data transfer using a CMOS signal, the difference in the number of stages of buffer ICs inserted for relaying is used. In addition, there is a problem that the clock and data skew (timing difference) is likely to increase due to the time difference due to the difference in the length of the signal line itself, and high-speed data transfer is difficult.
[0070]
The present invention has been made to solve the above-described problems, and can reduce the circuit scale, mounting area, and price of the image signal processing circuit, and can reduce the number of output signals to the data driver IC. More preferably, it is an object of the present invention to provide a display device and a display device image signal processing method capable of suitably executing high-speed data transfer.
[0071]
[Means for Solving the Problems]
In order to solve the above problems, a display device of the present invention includes an image signal processing unit that processes an input image signal, a display unit that displays an image based on an image signal processed by the image signal processing unit, The image signal processing unit includes a frame that performs frame rate conversion by repeatedly writing an image signal to a frame memory and periodically skipping and reading the written image signal. A rate conversion processing unit, an array conversion processing unit that converts the image signal subjected to frame rate conversion by the frame rate conversion processing unit into an array corresponding to the display unit, and writes the converted image signal into a frame memory; A frame memory having a plurality of possible memory areas, and writing by the array conversion processing unit The frame rate is shared by the frame rate conversion processing unit and the array conversion processing unit by sequentially performing processing on the memory region of which the reading by the frame rate conversion processing unit is completed. It is said.
[0072]
In the display device of the present invention, the process of reading out the image signal from each memory area of the frame memory by the frame rate conversion processing unit and the process of writing to the memory area by the array conversion processing unit are performed within one frame period. It is preferable to be completed.
[0073]
In the display device of the present invention, following the reading by the frame rate conversion processing unit from one memory area of the memory area of the frame memory, writing by the array conversion processing unit to the one memory area is performed. It is preferable that
[0074]
Alternatively, in the display device of the present invention, in the memory area of the frame memory, in parallel with reading by the frame rate conversion processing unit from one memory area, writing by the array conversion processing unit to another memory area is performed. It is also preferable to do so.
[0075]
The display device of the present invention further includes a transfer processing unit that transfers the image signal written in the frame memory by the array conversion processing unit to the display unit, and each memory area of the frame memory includes a plurality of small areas. The array conversion processing unit writes image signals corresponding to a predetermined number of scanning lines in the display unit in a small area of each memory region according to a display order, while the transfer processing unit has the same display It is preferable that the image signals in the order are read from the small areas of the respective memory areas, and these image signals are synchronized and transferred to the display unit.
[0076]
Furthermore, in the display device of the present invention, it is preferable that the frame rate conversion processing unit and the array conversion processing unit are provided on the same chip.
[0077]
In this case, it is preferable that the chip further includes a frame memory.
[0078]
In the display device of the present invention, it is also preferable to use a low-amplitude differential signal when transferring the image signal after the array conversion to the display unit.
[0079]
Moreover, it is preferable that the display apparatus of this invention is a plasma display apparatus provided with a plasma display module as the said display part.
[0080]
Also, an image signal processing method for a display device according to the present invention is an image signal processing method for a display device that processes an input image signal and displays an image based on the processed image signal. A frame rate conversion step of performing frame rate conversion by repeating writing to the memory and periodically skipping and reading out the written image signal, and the frame rate conversion in the frame rate conversion step An array conversion step of arraying image signals into an array corresponding to a display unit and writing the image signals to a frame memory, and having a plurality of memory areas that can be individually read and written in the array conversion step By performing on the memory area of the frame memory that has been read in the frame rate conversion process, It is characterized by sharing the frame memory and the frame rate conversion process to the sequence conversion step.
[0081]
In the image signal processing method for a display device of the present invention, a process of reading an image signal from each memory area of a frame memory by the frame rate conversion processing unit and a process of writing to each memory area by the array conversion processing unit. It is preferable to complete within one frame period.
[0082]
In the image signal processing method for a display device of the present invention, the array conversion processing unit for the one memory area is read out from the memory area of the frame memory by the frame rate conversion processing unit. It is also preferable to perform writing according to.
[0083]
Alternatively, in the image signal processing method for a display device of the present invention, the array conversion with respect to another memory area is performed in parallel with the reading by the frame rate conversion processing unit from one memory area of the memory area of the frame memory. It is also preferable to perform writing by the processing unit.
[0084]
In the image signal processing method for a display device of the present invention, each memory area of the frame memory includes a plurality of small areas, and in the array conversion step, a predetermined area in the display unit of the display apparatus is assigned to each small area of each memory area. Image signals corresponding to several scanning lines are written in accordance with the display order, and among the image signals written in the array conversion step, the image signals in the same display order are read from the small areas of each memory area, and these images are read. It is preferable to synchronize the signals and transfer them to the display unit.
[0085]
According to the display device and the image signal processing method for a display device of the present invention, the frame rate conversion processing unit includes a frame memory having a plurality of memory areas that can be individually read and written, and writing by the array conversion processing unit. Since the frame memory is shared by the frame rate conversion processing unit and the array conversion processing unit by performing the reading on the memory area in which reading by (1) is completed, for example, four frame memories are sufficient.
[0086]
As a result, the number of components can be reduced, and the circuit scale, mounting area, power consumption, and price of the image signal processing unit can be reduced. In addition, it is possible to reduce the price by promoting integration of image signal processing units, sharing between models, and standardization.
[0087]
Furthermore, since the number of frame memory input / output signal terminals and the number of display data output terminals to the data driver in the image signal processing unit are reduced, integration of LSIs constituting the image signal processing unit is facilitated. For this reason, the image signal processing circuit 104 having a configuration as shown in FIG. 25 in the conventional case can be constituted by an integrated image signal processing circuit 1 as shown in FIG. In other words, the image signal processing circuit can be made into a one-chip LSI, and in addition to the reduction of the mounting area, the cost can be reduced by sharing the LSI, components and circuits and mass production.
[0088]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment mode, a plasma display device as an example of the display device according to the present invention will be described.
[0089]
Of the constituent elements described in the present embodiment, constituent elements that are the same as those in the prior art may be assigned the same reference numerals and descriptions thereof may be omitted.
[0090]
The plasma display device according to the present embodiment is a sub-frame type display device configured to display one frame period by displaying a plurality of sub-frame periods in time series, and is input. An image signal processing circuit (image signal processing unit) 1 (FIG. 1) for processing an image signal to be processed, and a plasma display panel (plasma display module, which displays an image based on an image signal processed by the image signal processing circuit 1 Display unit).
[0091]
As shown in FIG. 1, an image signal processing circuit 1 includes a resolution conversion circuit 2 that performs resolution conversion on an input image signal, and an inverse γ correction circuit 3 that performs reverse γ correction on the image signal after resolution conversion. A frame rate conversion circuit (frame rate conversion processing unit) 4 that performs frame rate conversion on the image signal after inverse γ correction, and a subframe conversion coding circuit 5 that performs subframe conversion on the image signal after frame rate conversion. A data array conversion circuit (array conversion processing unit) 6 that performs data array conversion (array conversion) on the image signal after subframe conversion, and SF readout that reads the image signal after data array conversion and outputs it to the data driver IC A circuit 7 and a plurality of frame memories 11, 12, 13, and 14 are provided.
[0092]
Of these, the resolution conversion circuit 2, the inverse γ correction circuit 3, and the subframe conversion coding circuit 5 are, for example, the resolution conversion circuit 1041, the inverse γ correction circuit 1042, and the subframe conversion coding circuit 1044 described in the related art, respectively. It has the same configuration.
[0093]
Similarly to the frame rate conversion circuit 1043 described in the prior art, the frame rate conversion circuit 4 writes the image signal to the frame memories 11 to 14 and skips the written image signal periodically. Frame rate conversion is performed by repeating reading and reading.
[0094]
Further, the data array conversion circuit 6 converts the image signal whose frame rate has been converted by the frame rate conversion circuit 4 into an array corresponding to the plasma display panel and writes it in the frame memories 11 to 14.
[0095]
As shown in FIG. 2, for example, each of the frame memories 11 to 14 has a plurality of (for example, eight in this embodiment) memory areas 21, 22, 23, 24, 25, which can be individually read and written. 26, 27, 28. In FIG. 2, for the sake of simplicity, only the memory area allocated to one data driver IC 101 is shown (in the present embodiment, for example, 8), but actually, for example, 32 frame memories are provided. It is assumed that a memory area corresponding to the data driver IC 101 is allocated.
[0096]
Further, each of the memory areas 21 to 28 is divided into a plurality of small areas 31, 32, 33, 34, 35, 36, 37, and 38 as shown in FIG.
[0097]
Each of the frame memories 11 to 14 functions in the same manner. However, each of the frame memories 11 to 14 is replaced every frame period and assumes one of four functions. The four functions are a function used for writing an image signal by the frame conversion circuit 4, a function for maintaining a storage state of the image signal written by the frame conversion circuit 4, and a reading and array conversion circuit by the frame conversion circuit 4. 6 is a function provided for rewriting by 6, and a function provided for reading by the subframe reading circuit 7. That is, for example, in a frame period in which an image signal is written to the frame memory 11 by the frame conversion circuit 4, the frame memory 12 stores the image signal written by the frame conversion circuit 4 in the previous frame period. The frame memory 13 is used for reading by the frame conversion circuit 4 and the rewriting by the array conversion circuit 6, and the frame memory 14 is used for reading by the sub-frame reading circuit 7. In the next frame period, the frame memory 13 14, the image signal is written by the frame conversion circuit 4, the frame memory 11 maintains the storage state of the image signal written in the previous frame period by the frame conversion circuit 4, and the frame memory 12 Reading by circuit 4 and rewriting by array conversion circuit 6 Subjected to wear, as such a frame memory 13 is subjected to reading by the sub-frame reading circuit 7, functions that each frame memory 11 through 14 plays are so switched cyclically. Therefore, for the sake of simplicity, the following description will be made simply by referring to the “frame memories” without specifying the frame memories 11 to 14.
[0098]
Next, referring to FIG. 4, a process performed on an image signal (for example, an 8-bit image signal in the present embodiment) input to the image signal processing circuit (image signal processing unit) 1. The flow will be described.
[0099]
That is, first, resolution conversion is performed by the resolution conversion circuit 2 in step S1, and inverse γ correction is performed by the inverse γ correction circuit 3 in the subsequent step S2.
[0100]
Subsequently, in step S3, the frame rate conversion circuit 4 writes the frame memory. Here, the frame rate conversion circuit 4 performs writing in a normal bitmap format as in the prior art. As a result, as shown in FIG. 5A, the frame memory is in a state of storing a bitmap format image signal.
[0101]
The image signal written in this way is also subjected to frame rate conversion, for example, by skipping reading at a rate of once per five writes (see the prior art).
[0102]
The image signal whose reading is not skipped is read from the frame memory by the frame rate conversion circuit 4 in the subsequent step S4.
[0103]
Further, this image signal is subjected to subframe conversion by the subframe conversion coding circuit 5 (step S5), subsequently, data array conversion is performed by the data array conversion circuit 6 (step S6), and it is rewritten in the frame memory (step S6). S7).
[0104]
Here, as shown in FIG. 5B, writing to the frame memory is sequentially performed on the memory area where reading by the frame rate conversion circuit has been completed, and as a result of sequentially writing in this manner, FIG. As shown in (c), the image signals after the array conversion are written in the memory areas 21 to 28 of the frame memory. The writing of the image signal after the array conversion will be described in detail in each embodiment described later.
[0105]
In addition, the image signals after the array conversion written in the frame memory in this way are read by the sub-frame reading circuit 7 (step S8) and output to the corresponding data driver IC 101 (step S9). The display based on is performed on the plasma display panel.
[0106]
According to the present embodiment, a plurality of frame memories 11 to 14 having a plurality of memory areas 21 to 28 that can be individually read and written are provided, and writing by the data array conversion circuit 6 is performed by the frame rate conversion circuit 4. The frame rate can be shared by the frame rate conversion circuit 4 and the data array conversion circuit 6 by performing the process on the memory area for which the reading is completed.
[0107]
Hereinafter, examples of preferred embodiments will be described in detail.
[0108]
[First Embodiment]
As shown in FIG. 6, the image signal processing circuit 10 of the plasma display device according to the first embodiment includes data (image signal) writing to the frame memories 11 to 14 and the frame memory in addition to the configuration of FIG. 1. A frame memory control circuit 8 for controlling data reading from 11 to 14 is provided. In the case of the first embodiment, for example, the resolution conversion circuit 2, the inverse γ correction circuit 3, the frame rate conversion circuit 4, the subframe conversion coding circuit 5, the data array conversion circuit 6, the SF read circuit 7, and the frame memory control. While the circuit 8 is provided in one LSI (same chip) 10A, each of the frame memories 11 to 14 is configured externally to the LSI 10A.
[0109]
In the case of the first embodiment, reading from the frame memory by the frame rate conversion circuit 4 in step S4 and writing to the frame memory by the data array conversion circuit 6 in step S7 are performed by a read modify write operation.
[0110]
That is, out of the plurality of memory areas 21 to 28 included in one frame memory, after the frame rate conversion circuit 4 reads from the one memory area, the data array conversion circuit 6 writes to the one memory area. . By sequentially executing such reading and writing on each memory area of one frame memory, the image signal for one frame after the array conversion is written in the one frame memory. .
[0111]
Next, with reference to FIG. 7, the process from step S3 to step S9 in FIG. 4 will be described in detail. Here, for the sake of simplicity, it is assumed that the frame memory has four memory areas (memory areas 21 to 24) and that each memory area has four small areas (small areas 31 to 34). Do.
[0112]
First, the process of step S3 in FIG. 4 is a process of writing bitmap-format parallel processing data to the frame memory, as shown by step S11 in FIG. 7, and is performed within one frame period. That is, in the 8-bit parallel signal processing, the image signal is stored in a normal bitmap format. As a result of this processing, as shown in step S12 in FIG. 7, the frame memory is in a state of storing parallel processing data.
[0113]
Next, the process of step S4 in FIG. 4 is a process of reading an image signal from the frame memory for subframe conversion, and the process of step S7 in FIG. 4 is the process of reading the image signal after subframe conversion and array conversion into the frame memory. Is a process of writing to
[0114]
For this processing, read-modify-write is applied in which data is written after reading by one memory access. The write data here is not data that has been subjected to subframe conversion and array conversion on the data read by the same memory access, but was read before that and subjected to subframe conversion and array conversion. It is data. This is because the subframe conversion and array conversion to data immediately after reading are not in time for writing in the same memory access. If rewriting is performed in this manner, the relative position of the image signal in the frame memory is shifted, but since there is no collision between reading and writing of data, there is no problem in subsequent processing.
[0115]
More specifically, as shown in step S13 in FIG. 7, these processes are performed by first reading out an image signal from the memory area 21 of the frame memory (step S13a), and then subframe conversion and conversion into the memory area 21. The image signal after the array conversion is written by overwriting (step S13b), and thereafter the image signal reading from the memory area 22 (step S13c) → the writing of the image signal to the memory area 22 (step S13d) → the memory area 23 The image signal is read out, the image signal is written into the memory area 23, the image signal is read out from the memory area 24, and the image signal is written into the memory area 24. As a result, as shown in step S13e in FIG. 7, the frame memory stores an image signal for one frame after the array conversion.
[0116]
Here, for simplicity, for example, as shown in FIG. 8, one frame period is formed by four subframes (SF1, SF2, SF3, and SF4), and an image for one screen in the display screen G of the plasma display panel. Assume that signals are allocated to the four data driver ICs 101 (the entire number of horizontal pixels are allocated to the four data driver ICs 101). In this case, for example, the memory area 21 corresponds to ¼ of all the horizontal pixels on the scanning line L1 corresponding to a predetermined number of uppermost stages on the display screen G (for example, ¼ of the vertical width of the display screen G). Write the image signal corresponding to the minute. Similarly, an image signal corresponding to one-fourth of all the horizontal pixels on the scanning line L2 for a predetermined number of subsequent stages in the display screen G is written in the memory area 22, and in the memory area 23 in the display screen G. Further, an image signal corresponding to ¼ of all the horizontal pixels in the predetermined number of scanning lines L3 in the next stage is written, and the predetermined number of scanning lines L4 in the lowermost stage in the display screen G are written in the memory area 24. Write the corresponding image signal.
[0117]
In more detail, the image signal is written here in accordance with the display order for each of the small areas 31 to 34 corresponding to a predetermined number of scanning lines on the display screen G of the plasma display panel. Is repeated periodically for each memory area. That is, for example, the image signal of the first subframe (SF1) in the display order is written in each small area 31, and the image signal in the second subframe (SF2) is written in each small area 32, for example. For example, an image signal in the third subframe (SF3) is written in each small area 33, and an image signal in the fourth subframe (SF4) is written in each small area 34, for example.
[0118]
Note that the process of step S13 in FIG. 7 is executed within one frame period. In other words, the process of reading the image signal from each memory area of one frame memory by the frame rate conversion circuit 4 and the process of writing to each memory area by the data array conversion circuit 6 are completed within one frame period.
[0119]
Next, as a result of performing the processing in step S13, the memory contents of the frame memory in which the image signals after the array conversion are stored (step S13e) are read by the SF reading circuit 7 and output to the data driver IC 101. (Step S14 in FIG. 7).
[0120]
As shown in FIG. 7, this read / output process is a process of reading and outputting the memory contents of the small area 31 of each memory area 21 to 24 (step S14a), and the memory of the small area 32 of each memory area 21 to 24. A process of reading and outputting the contents (step S14b), a process of reading and outputting the memory contents of the small area 33 in each of the memory areas 21 to 24 (step S14c), and the memory contents of the small area 34 of each of the memory areas 21 to 24 This is performed by performing the process of reading and outputting (step S14d) in this order. Here, the processing of step S14a to step S14d is performed by designating and reading out addresses that are each skipped (for example, every three in FIG. 7).
[0121]
That is, the SF readout circuit 7 as a transfer processing unit for transferring the image signal written in the frame memory to the plasma display panel (in practice, for example, the data driver IC 101 in the vicinity of the plasma display panel) A signal (that is, an image signal of a bit corresponding to a subframe scanning period) is read from a small area of each memory area, and these image signals are synchronized and transferred to the plasma display panel.
[0122]
Further, as a result of performing the processing of step S14a to step S14d in this way, SF1, SF2, SF3, and SF4 are displayed in order as shown in FIG. 8A, and the display of SF1 to SF4 is collectively displayed. A one-frame display is formed.
[0123]
Furthermore, the processing from step S11 is repeatedly performed on the frame memory that has undergone the processing of step S14.
[0124]
As described above, in this embodiment, the 8-bit parallel signal processing and the data array conversion processing are cyclically executed by the pipeline processing in the signal processing order.
[0125]
As described above, according to the plasma display device of the present embodiment, a frame having a plurality of memory areas 21 to 28 that can be individually read and written (memory areas 21 to 24 are shown in FIG. 7 for simplicity). The memory 11 to 14 are provided, and writing by the data array conversion processing circuit 6 is performed on the memory area where the reading by the frame rate conversion circuit 4 is completed, so that the frame rate conversion circuit 4 and the data array conversion circuit 6 Since the memories 11 to 14 are shared, that is, in the 8-bit parallel signal processing, the image signal is stored in a normal bitmap format, and in the subsequent data array conversion processing, the data storage area is stored for a predetermined number of lines. The memory address is allocated and stored so that it is divided into small areas and data can be read out bit by bit. Since the small areas 31 to 38 (the small areas 31 to 34 are simply shown in FIG. 7) are periodically arranged as a body, the same frame is stored in the memory area after the frame rate conversion data of 8-bit parallel signal processing is read. Data that has undergone data array conversion within the period can be rewritten.
[0126]
In addition, by reading the bit data designated for each subframe period from the frame memory and transferring it as display data to the data driver IC 101 according to the subframe display method in the next frame period in which the data after the array conversion is written. The same image display as in the conventional case is possible.
[0127]
That is, a specific bit address is stored in a memory address having a predetermined number of scanning lines (for a predetermined number of lines) as a cycle. Only bit data can be obtained over the entire frame, and by outputting this specific bit data to the data driver IC 101, image display can be suitably executed.
[0128]
Therefore, in the image signal processing circuit 10, the frame memories necessary for the frame rate conversion process and the data array conversion process are the frame memory used for the process of step S11 in FIG. 7, the frame memory used for the process of step S12, A total of four frame memories, that is, the frame memory used for the process of step S13 and the frame memory used for the process of step S14 are sufficient. That is, it is possible to reduce the memory for one frame by sharing the frame memory that has conventionally been necessary on the writing side of the data array conversion processing.
[0129]
As a result, the number of components can be reduced, and the circuit scale, mounting area, and price of the image signal processing circuit 10 can be reduced. In addition, it is possible to reduce the price by promoting integration of the image signal processing circuit 10, sharing between models, and standardization.
[0130]
Furthermore, since the number of frame memory input / output signal terminals and the number of display data output terminals to the data driver IC 101 in the image signal processing circuit 10 are reduced, LSI integration is facilitated. For this reason, the image signal processing circuit 104 having the configuration shown in FIG. 25 in the conventional case can be configured by an integrated image signal processing circuit 10 as shown in FIG. 6, for example. That is, the image signal processing circuit 10 can be made into a one-chip LSI, and in addition to the reduction of the mounting area, the cost can be reduced by sharing the LSI, components and circuits and mass production.
[0131]
[Second Embodiment]
As shown in FIG. 9, the LSI 20A constituting the image signal processing circuit 20 of the plasma display device according to the second embodiment is the same as the LSI 10A in the first embodiment (FIG. 6; each frame memory 11-14 is externally connected). In contrast, the frame memories 11 to 14 are provided.
[0132]
As described above, since the frame memories 11 to 14 are built in the LSI 20A, there is no need to assign input / output signals to the memory areas 21 to 28 to the terminals of the LSI package, and the number of signal terminals of the LSI 20A is insufficient. Since this is alleviated, the integration of LSIs can be further improved.
[0133]
In the present embodiment, the frame memory control circuit 8 can individually access and read / write in parallel the memory areas 21 to 24 of the frame memories 11 to 14. Then, as shown in FIG. 10, while reading 8-bit parallel data in one memory area (for example, memory area 23), rewriting to the previous memory area (for example, memory area 22) that has already been read is performed. Execute. That is, in the memory area of the frame memory, the data array conversion circuit 6 writes to the other memory area in parallel with the reading by the frame rate conversion circuit 4 from one memory area.
[0134]
That is, more specifically, step S15 shown in FIG. 11 is performed instead of step S13 shown in FIG. That is, first, an image signal is read from the memory area 21 (step S15a), and then the image signal after subframe conversion and array conversion is written to the memory area 21 while reading the image signal from the memory area 22 (step S15b). Hereinafter, the process of writing the image signal after the subframe conversion and the array conversion to the memory area 22 while reading the image signal from the memory area 23 in order (step S15c), and reading the image signal from the memory area 24 to the memory area 23 in order. Performs a process of writing the image signal after the subframe conversion and the array conversion, and a process of writing the image signal after the subframe conversion and the array conversion in the memory area 24. As a result, as in the case of the first embodiment described above, the frame memory is in a state in which the image signals for one frame after the array conversion are stored (step S13d).
[0135]
Thus, unlike the case of the first embodiment, the second embodiment does not use the read-modify-write operation, so that the read / write operation can be performed without increasing the data rate during memory access. There is an advantage that the memory control is not complicated.
[0136]
In the second embodiment, for example, a high-speed serial interface 19 (FIG. 9) such as LVDS (low amplitude differential signal) is used to transfer an image signal from the image signal processing circuit 20 to the data driver IC 101.
[0137]
That is, in order to reduce the number of signal terminals of the LSI 20A, the image signal transferred to the data driver IC 101 is subjected to parallel / serial conversion by the parallel / serial conversion circuit 9 (FIG. 9), and then the LVDS signal is output by the LVDS output circuit 19 (FIG. 9). This is received by the conversion circuit 50 (FIG. 12; constituted by, for example, an LVDS receiver with a serial / parallel conversion function) in the vicinity of the data driver IC 101, converted into a CMOS signal again, and further converted into a serial / parallel signal. The data is supplied to each data driver IC 101.
[0138]
In this way, by performing data transfer from the LSI 20A to the vicinity of the data driver IC 101 using the LVDS signal, high-speed data transfer can be suitably performed, and the number of signal lines, power consumption, and timing conditions are alleviated. This can be realized, and LSI integration can be more suitably achieved.
[0139]
[Third Embodiment]
In the third embodiment, an example will be described in which display with any number of display pixels among a plurality of types of display pixels can be selected and executed.
[0140]
Setting (selection) of the number of display pixels is performed, for example, by inputting setting data or mode setting bits from outside the LSI constituting the image signal processing circuit.
[0141]
Further, it is assumed that the resolution conversion circuit 2 can select any one of a plurality of types of resolution conversion algorithms. Each of the frame memories 11 to 14 has a capacity capable of storing an image signal corresponding to the maximum number of display pixels among the settable memories, and is configured to perform addressing to a memory corresponding to a specific set pixel. Need to be.
[0142]
According to the present embodiment, since a common LSI can be used for image signal processing even if the number of display pixels is different, the printed circuit board is shared, the parts are shared, the development period is shortened, and the cost is reduced due to the mass production effect. Can be achieved.
[0143]
[Fourth Embodiment]
In the fourth embodiment, an example will be described in which a function that bypasses one or both of the resolution conversion process and the inverse γ correction process in the previous stage of image signal processing can be selected as necessary.
[0144]
That is, as shown in FIG. 13, the image signal processing circuit in the plasma display device of the fourth embodiment has a function of executing both resolution conversion processing and inverse γ correction (FIG. 13A), resolution conversion processing, and Of the inverse γ correction, the resolution conversion process is bypassed and only the inverse γ correction is executed (FIG. 13B), and the resolution conversion process and the inverse γ correction are both bypassed (FIG. 13C). Any one of the functions can be selectively executed. Therefore, by selecting any one of these functions as necessary, unnecessary processing can be omitted and various image signal input modes can be handled.
[0145]
In the above embodiment, only the example in which the present invention is applied to the plasma display device has been described. However, the present invention is not limited to this, and other matrix display devices that display image signals by a subframe sequence are also described. The image signal processing circuit can be integrated.
[0146]
In the above description, the frame rate conversion circuit 4 and the data array conversion circuit 6 share the frame memory. However, this frame memory may be shared by the resolution conversion circuit 2 as well.
[0147]
【The invention's effect】
According to the present invention, a frame memory having a plurality of memory areas that can be individually read and written is provided, and writing by the array conversion processing unit is performed on a memory area that has been read by the frame rate conversion processing unit. Thus, the frame rate conversion processing unit and the array conversion processing unit share the frame memory, so that for example, four frame memories are sufficient.
[0148]
As a result, the number of components can be reduced, and the circuit scale, mounting area, power consumption, and price of the image signal processing unit can be reduced. In addition, it is possible to reduce the price by promoting integration of image signal processing units, sharing between models, and standardization.
[0149]
Furthermore, since the number of frame memory input / output signal terminals and the number of display data output terminals to the data driver in the image signal processing unit are reduced, integration of LSIs constituting the image signal processing unit is facilitated, and as a result, a color PDP device This has the effect of further reducing the cost of the entire system, shortening the development period by sharing circuits, facilitating model development, and reducing power consumption, and further promoting the spread of color PDP devices.
[0150]
Also, by transferring data from the image signal processing unit to the display unit with a low-amplitude differential signal, the number of signal lines can be reduced, power consumption can be reduced, and timing conditions can be relaxed, making LSI integration more suitable. You can get none.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of an image signal processing circuit of a display device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a frame memory.
FIG. 3 is a diagram showing a more detailed configuration of a frame memory.
FIG. 4 is a flowchart for explaining a flow of processing performed by an image signal processing circuit.
FIG. 5 is a diagram for explaining reading from the frame memory by the frame rate conversion circuit and writing to the frame memory by the data array conversion circuit;
FIG. 6 is a block diagram showing an image signal processing circuit of the display device according to the first embodiment.
FIG. 7 is a diagram for explaining a flow of reading from and writing to the frame memory in the case of the first embodiment.
FIG. 8 is a diagram for explaining the correspondence between the data written in the frame memory after the array conversion and the display position on the display screen.
FIG. 9 is a block diagram showing an image signal processing circuit of a display device according to a second embodiment.
FIG. 10 is a diagram for explaining reading from the frame memory by the frame rate conversion circuit and writing to the frame memory by the data array conversion circuit in the case of the second embodiment.
FIG. 11 is a diagram for explaining a flow of reading from and writing to a frame memory in the case of the second embodiment.
FIG. 12 is a schematic diagram showing an overall configuration of a display device according to a second embodiment.
FIG. 13 is a diagram for explaining processing when a plurality of types of processing by the image signal processing circuit can be selected.
FIG. 14 is a block diagram showing a configuration of a general AC color plasma display device.
FIG. 15 is a conceptual diagram showing a configuration of a data driver IC.
FIG. 16 is a timing chart showing a display data input format of the data driver IC.
FIG. 17 is a block diagram illustrating a configuration example of an image signal processing circuit of a conventional color plasma display device.
FIG. 18 is a diagram for explaining the operation of a resolution conversion circuit;
FIG. 19 is a block diagram illustrating a configuration of a resolution conversion circuit.
20A and 20B are diagrams for explaining an inverse γ correction circuit, in which (a) shows the configuration of the inverse γ correction circuit, and (b) shows an example of conversion characteristics of the inverse γ correction circuit.
FIG. 21 is a diagram for explaining the operation of the frame rate conversion circuit;
FIG. 22 is a block diagram showing a configuration of a frame rate conversion circuit.
FIG. 23 is a block diagram illustrating a configuration of a subframe conversion coding circuit.
FIG. 24 is a diagram for explaining the operation of the data array conversion circuit;
FIG. 25 is a block diagram showing a configuration of a data array conversion circuit.
FIG. 26 is a block diagram showing a configuration of an in-line processing circuit in the data array conversion circuit.
27A is a diagram for explaining a conventional 8-bit parallel processing frame memory, and FIG. 27B is a diagram for explaining a conventional data array conversion frame memory. FIG.
FIG. 28 is a schematic diagram showing an overall configuration of a conventional display device.
[Explanation of symbols]
1 Image signal processing circuit (image signal processing unit)
11, 12, 13, 14 frame memory
21, 22, 23, 24, 25, 26, 27, 28 Memory area
31, 32, 33, 34, 35, 36, 37, 38 Small area
4 Frame rate conversion circuit (frame rate conversion processor)
6 Data array conversion circuit (array conversion processor)
7 Subframe readout circuit (transfer processing unit)
10A LSI (chip)
20A LSI (chip)

Claims (14)

In a display device comprising: an image signal processing unit that processes an input image signal; and a display unit that displays an image based on an image signal processed by the image signal processing unit.
The image signal processor is
A frame rate conversion processing unit that performs frame rate conversion by repeatedly writing the image signal to the frame memory and periodically skipping and reading the written image signal;
An array conversion processing unit that converts the image signal subjected to frame rate conversion by the frame rate conversion processing unit into an array corresponding to the display unit and writes the image signal in a frame memory;
A frame memory having a plurality of memory areas that can be individually read and written;
With
The frame rate conversion processing unit and the array conversion processing unit are sequentially written in the memory area of the frame memory that has been read by the frame rate conversion processing unit. A display device characterized by sharing a frame memory. A process of reading an image signal from each memory area of the frame memory by the frame rate conversion processing unit and a process of writing to each memory area by the array conversion processing unit are completed within one frame period. The display device according to claim 1. The frame conversion processing unit reads from the memory area of the frame memory by the frame rate conversion processing unit, and then writes to the one memory area by the array conversion processing unit. Item 3. The display device according to Item 1 or 2. The array conversion processing unit performs writing to another memory area in parallel with reading by the frame rate conversion processing unit from one memory area of the memory area of the frame memory. Item 3. The display device according to Item 1 or 2. A transfer processing unit that transfers the image signal written in the frame memory by the array conversion processing unit to the display unit;
Each memory area of the frame memory consists of multiple small areas,
The array conversion processing unit
While writing the image signals corresponding to the predetermined number of scanning lines in the display unit in accordance with the display order for the small areas of each memory area,
5. The transfer processing unit according to claim 1, wherein the transfer processing unit reads image signals having the same display order from the small areas of the respective memory areas, and transfers the image signals to the display unit in synchronization with each other. The display device according to one item. The display device according to claim 1, wherein the frame rate conversion processing unit and the array conversion processing unit are provided on the same chip. The display device according to claim 6, wherein the chip further includes each frame memory. 8. The display device according to claim 1, wherein a low-amplitude differential signal is used when the image signal after the array conversion is transferred to the display unit. 9. The display device according to claim 1, wherein the display device is a plasma display device including a plasma display module as the display unit. In an image signal processing method for a display device that processes an input image signal and displays an image based on the processed image signal,
A frame rate conversion step of performing frame rate conversion by repeating writing the image signal to the frame memory and periodically skipping and reading the written image signal;
An array conversion step in which the image signal subjected to frame rate conversion in the frame rate conversion step is converted into an array corresponding to a display unit and written in a frame memory;
With
Writing in the array conversion process is performed on a memory area of the frame memory having a plurality of memory areas that can be individually read and written, and having been read in the frame rate conversion process. A frame memory is shared by the frame rate conversion step and the array conversion step. The process of reading an image signal from each memory area of the frame memory by the frame rate conversion processing unit and the process of writing to the memory area by the array conversion processing unit are completed within one frame period. Item 11. The image signal processing method for a display device according to Item 10. 11. The frame conversion processing unit performs writing to the one memory area following the reading by the frame rate conversion processing unit from one of the memory areas of the frame memory. 11. A display device image signal processing method according to 11. 11. The writing by the array conversion processing unit to another memory region is performed in parallel with the reading by the frame rate conversion processing unit from one memory region of the memory area of the frame memory. 11. A display device image signal processing method according to 11. Each memory area of the frame memory consists of multiple small areas,
In the array conversion step, image signals corresponding to a predetermined number of scanning lines in the display unit of the display device are written in a display order in a small area of each memory area,
Among the image signals written in the array conversion step, image signals having the same display order are read out from the small areas of the respective memory areas, and these image signals are synchronized and transferred to the display unit. The image signal processing method for a display device according to any one of claims 10 to 13.

Images