JP2005005516A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve write characteristic of a nonvolatile memory cell, to improve reliability of a gate insulating film of an field effect transistor included in a logic circuit, and also to provide a method of manufacturing the semiconductor device which can reduce the number of processes and improve reliability. <P>SOLUTION: After a gate insulating film 7, a polysilicon film 8, a silicon oxide film 9, and a silicon nitride film 10 are sequentially formed on a semiconductor substrate 1; these films are left only on the nonvolatile memory cell forming region using the photolithography and etching technologies. Subsequently, a gate insulating film 13a is formed with an ISSG oxide method, and simultaneously a silicon oxide film 14 is formed on the silicon nitride film 10 of the nonvolatile memory cell forming region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device in which a rewritable nonvolatile memory cell including a first field effect transistor for a memory and a circuit including a second field effect transistor are formed, and a manufacturing method thereof. It is related to effective technology.
[0002]
[Prior art]
Conventionally, there is a semiconductor device in which a memory, a peripheral circuit for driving the memory, and a logic circuit are mixedly mounted on the same semiconductor chip (semiconductor substrate).
[0003]
The memory formed in this semiconductor device includes a volatile memory that keeps storing only when the power is on, and a non-volatile memory that does not lose its memory even when the power is turned off. In addition, there is an EEPROM (Electrically Erasable Programmable Read Only Memory) capable of writing and erasing information. These memories, such as a volatile memory and a non-volatile memory, have a configuration in which a large number of memory cells are arranged two-dimensionally in units of memory cells that store 1-bit information.
[0004]
In the field effect transistor of the nonvolatile memory cell included in the above-described EEPROM, a floating gate electrode is provided on a channel formation region of a semiconductor substrate via a gate insulating film, and an interlayer insulating film is provided on the floating gate electrode. The control gate electrode is provided. In such a configuration, the threshold voltage of the control gate electrode changes depending on whether charges are accumulated in the floating gate electrode. Then, by utilizing this change in threshold voltage, the nonvolatile memory cell stores 1-bit information.
[0005]
In a field effect transistor of a nonvolatile memory cell that stores information according to the presence or absence of charges accumulated in the floating gate electrode, information is lost if the charges accumulated in the floating gate electrode leak to the control gate electrode. Therefore, in order to prevent the loss of information, an interlayer insulating film is provided between the floating gate electrode and the control gate electrode. This interlayer insulating film is formed by sequentially stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film. It is formed of a three-layered film (ONO film). Actually, in order to prevent the upper silicon oxide film from being scraped off by cleaning or the like in the subsequent process, a four-layer film (ONON film) in which a silicon nitride film is laminated as a protective film on the upper silicon oxide film. Is formed.
[0006]
On the semiconductor chip, in addition to the above-described nonvolatile memory cells, there are field effect transistors included in peripheral circuits and logic circuits for driving the nonvolatile memory cells, which are formed as shown below, for example. The
[0007]
As a first method, a gate insulating film, a conductor film (a film to be processed into a floating gate electrode in a later process), and a four-layer stacked film (ONON film) are sequentially formed in a nonvolatile memory cell formation region, There is a method of forming a gate insulating film of a field effect transistor of a peripheral circuit or a logic circuit. That is, there is a method of forming a four-layer film and gate insulating films of field effect transistors of peripheral circuits and logic circuits in separate steps.
[0008]
As a second method, a gate insulating film of a nonvolatile memory cell, a conductor film to be a floating gate electrode, and a three-layer laminated film (ONO film) are sequentially formed on the conductor film. There is a method of forming a gate insulating film of a peripheral circuit at the same time as forming (see, for example, Patent Document 1).
[0009]
[Patent Document 1]
JP-A-9-107086 (page 6, FIGS. 10 to 11)
[0010]
[Problems to be solved by the invention]
However, in the first method described above, since the silicon nitride film as the protective film is formed on the three-layered laminated film (ONO film), the floating gate electrode and the silicon nitride film corresponding to the thickness of the silicon nitride film are formed. The capacitance value between the control gate electrodes is reduced. Therefore, the voltage of the floating gate electrode at the time of writing becomes relatively low, which makes it difficult to improve the writing characteristics. Further, since a four-layered film (ONON film) is formed, there is a problem that the number of manufacturing steps increases.
[0011]
In the second method described above, the silicon oxide film on the upper part of the three-layered film (ONO film) is formed by the CVD (Chemical Vapor Deposition) method, and the gate insulating film of the field effect transistor in the peripheral circuit is formed by the CVD method. Or it forms by the method which combined CVD method and thermal oxidation method. Therefore, the gate insulating film of the field effect transistor of the peripheral circuit has a problem that the reliability is inferior in terms of insulation resistance or the like as compared with the gate insulating film formed by the thermal oxidation method as in the prior art.
[0012]
An object of the present invention is to provide a semiconductor device in which a nonvolatile memory cell including a first field effect transistor for memory and a circuit including a second field effect transistor are formed in different regions of a semiconductor substrate, or a first for a nonvolatile memory. In a semiconductor device in which a first field effect transistor and a second field effect transistor for a microcomputer are formed on the same semiconductor substrate, the write characteristics of the first field effect transistor are improved and the gate insulating film of the second field effect transistor is improved. An object is to provide a semiconductor device capable of improving reliability.
[0013]
Another object of the present invention is to provide a method for manufacturing a semiconductor device in which a nonvolatile memory cell including a first field effect transistor for memory and a circuit including a second field effect transistor are formed in different regions of a semiconductor substrate, or In a method of manufacturing a semiconductor device in which a first field effect transistor for a nonvolatile memory and a second field effect transistor for a microcomputer are formed on the same semiconductor substrate, the number of steps can be reduced and reliability can be improved. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a film.
[0014]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0015]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0016]
A semiconductor device of the present invention is a semiconductor device in which a rewritable nonvolatile memory cell including a first field effect transistor for memory and a circuit including a second field effect transistor are formed in different regions on a semiconductor substrate, The first field effect transistor includes: (a) a first gate insulating film formed on the semiconductor substrate; (b) a floating gate electrode formed on the first gate insulating film; and (c) the floating gate. A first insulating film formed on the gate electrode; (d) a second insulating film formed on the first insulating film; and (e) a third insulating film formed on the second insulating film; (F) a first gate electrode formed on the third insulating film, and the second field effect transistor includes: (g) a second gate insulating film formed on the semiconductor substrate; h) The second gate A second gate electrode formed on the film, wherein the third insulating film and the second gate insulating film reduce the pressure from an atmospheric pressure, and supply hydrogen gas and oxygen gas to the semiconductor. It is formed by reacting on a substrate.
[0017]
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method in which a rewritable nonvolatile memory cell including a first field effect transistor for memory and a circuit including a second field effect transistor are formed in different regions of a semiconductor substrate. A method for manufacturing an apparatus, comprising: (a) forming a first gate insulating film of the first field effect transistor on the semiconductor substrate; and (b) forming a first conductor film on the first gate insulating film. (C) forming a first insulating film on the first conductive film; (d) forming a second insulating film on the first insulating film; and (e) the first insulating film. (2) forming a patterned resist film on the insulating film; and (f) etching using the resist film as a mask, the first conductor film, the first insulating film, and the first insulating film only in the formation region of the nonvolatile memory cell. 2 Insulating film And (g) removing the first gate insulating film formed on the semiconductor substrate, leaving only the first gate insulating film formed in the formation region of the nonvolatile memory cell, (H) forming a third insulating film on the second insulating film and forming a second gate insulating film of the second field effect transistor on the semiconductor substrate, and the step (h) includes: The third insulating film and the second gate insulating film are formed by reacting hydrogen gas and oxygen gas on the semiconductor substrate in a state where the pressure is reduced from atmospheric pressure. is there.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0019]
In this embodiment, the present invention is applied to a semiconductor device in which a rewritable nonvolatile memory and a logic circuit are mixedly mounted on a semiconductor chip. That is, in this embodiment, the present invention is applied to a semiconductor device including a logic circuit, a rewritable nonvolatile memory cell, and a peripheral circuit for driving the nonvolatile memory cell.
[0020]
FIG. 1 shows a MIS transistor (second field effect transistor) Q formed in different regions on a semiconductor substrate (semiconductor chip) 1. ₁ ~ Q ₃ , Field effect transistor (first field effect transistor) Q ₄ It is sectional drawing which showed a part of wiring. FIG. 1 shows a 1.8 V MIS (Metal Insulator Semiconductor) transistor formation region, a 3.3 V MIS transistor formation region, and an HV (High Voltage) MIS transistor formation region in order from the left region on the semiconductor substrate 1. The rightmost region shows the rewritable nonvolatile memory cell formation region.
[0021]
That is, in FIG. 1, the MIS transistor Q formed in the leftmost region. ₁ Is a MIS transistor that operates at the lowest power and at a high speed. A MIS transistor having a high operating voltage and a high withstand voltage is formed toward the right side region, and a nonvolatile memory cell is formed on the right side. .
[0022]
In each region of the semiconductor substrate 1, element isolation regions 2 for isolating elements are formed. In each active region isolated by the element isolation region 2, p-type wells 3, 4, 5, 6 are formed. Has been. That is, the p-type well 3 is formed in the 1.8V MIS transistor formation region, and the p-type well 4 is formed in the 3.3V MIS transistor formation region. Similarly, a p-type well 5 is formed in the HV MIS transistor formation region, and a p-type well 6 is formed in the nonvolatile memory cell formation region.
[0023]
Next, on the p-type well 3, a 1.8V MIS transistor Q operating at high speed with low breakdown voltage. ₁ MIS transistor Q is formed on p-type well 4. ₁ 3.3V MIS transistor Q with higher breakdown voltage ₂ Is formed. Similarly, on the p-type well 5, a 3.3V MIS transistor Q ₂ Higher withstand voltage HV (for example, 5V) MIS transistor Q ₃ And the field effect transistor Q is formed on the p-type well 6. ₄ Is formed.
[0024]
On the semiconductor substrate 1, a circuit, a logic circuit, a nonvolatile memory cell, a peripheral circuit for driving the nonvolatile memory cell, and the like constituting a microcomputer arranged in parallel with the nonvolatile memory are formed. For example, the MIS transistor Q described above may be used as a logic circuit that performs processing such as comparison and determination, and a circuit that constitutes a microcomputer. ₁ ~ Q ₃ It is included. In other words, the logic circuit and the circuit constituting the microcomputer have a MIS transistor Q of about 1.8V system having a relatively low operating voltage. ₁ HV transistor MIS transistor Q with relatively high breakdown voltage ₃ A wide range of transistors are used.
[0025]
Peripheral circuits that drive nonvolatile memory cells include, for example, a booster circuit that generates a voltage several times higher than the power supply voltage, a booster clock circuit, a voltage clamp circuit, a column decoder that selects rows and columns of the nonvolatile memory cell array, There are a row decoder, a column latch circuit, a WELL control circuit, etc., and these circuits are HV transistor MIS transistors Q having a relatively high breakdown voltage. ₃ It is composed of
[0026]
Non-volatile memory cells include field effect transistors Q ₄ A non-volatile memory cell array in which the non-volatile memory cells are two-dimensionally arranged is formed on the semiconductor substrate 1.
[0027]
Next, the MIS transistor Q shown in FIG. ₁ ~ Q ₃ And field effect transistor Q ₄ The configuration of will be described.
[0028]
First, MIS transistor Q ₁ Has the following configuration. That is, a gate insulating film (second gate insulating film) 13c is formed on the p-type well 3 formed in the semiconductor substrate 1, and a gate electrode (second gate electrode) 21 is formed on the gate insulating film 13c. Is formed. The gate electrode 21 is formed of, for example, a polysilicon film 19 and a cobalt silicide film 43 formed on the polysilicon film 19 in order to reduce resistance. The film formed on the polysilicon film 19 for reducing the resistance is not limited to the cobalt silicide film 43, and may be a titanium silicide film or a nickel silicide film, for example.
[0029]
The gate insulating film 13c is a silicon oxide film having a thickness of about 4.2 nm formed by using an ISSG oxidation (In-Situ Steam Generated Oxidation) method. The ISSG oxidation method will be described in a manufacturing method described later. In brief, by reacting hydrogen gas and oxygen gas on the semiconductor substrate 1 while the semiconductor substrate 1 is heated while reducing the pressure from atmospheric pressure, This is a method of forming a silicon oxide film.
[0030]
According to the ISSG oxidation method, a highly reliable film can be formed by the reduction action of hydrogen. That is, a film having excellent insulation resistance and a long TDDB (Time Dependent Dielectric Breakdown) life can be formed. Note that the reason why the gate insulating film is as thin as about 4.2 nm is to form a transistor with low breakdown voltage and high speed.
[0031]
On the side wall of the gate electrode 21, the MIS transistor Q ₁ A sidewall 34 is formed in order to make the source region and drain region of the semiconductor layer have an LDD (Lightly Doped Drain) structure, and a low-concentration n-type impurity which is a semiconductor region is formed in the p-type well 3 below the sidewall 34. Diffusion regions 26 and 27 are formed. High-concentration n-type impurity diffusion regions 35 and 36, which are semiconductor regions, are formed outside the low-concentration n-type impurity diffusion regions 26 and 27, and a cobalt silicide film 43 is formed in the upper portion to reduce resistance. Has been.
[0032]
The low-concentration n-type impurity diffusion region 26, the high-concentration n-type impurity diffusion region 35, and the cobalt silicide film 43 constitute the MIS transistor Q. ₁ Source region is formed, and the low concentration n-type impurity diffusion region 27, the high concentration n-type impurity diffusion region 36 and the cobalt silicide film 43 are used to form the MIS transistor Q. ₁ The drain region is formed.
[0033]
Next, the MIS transistor Q ₂ The configuration of will be described. MIS transistor Q ₂ The configuration of the MIS transistor Q ₁ The structure is substantially the same as that of FIG. 1, and the major difference is the thickness of the gate insulating film.
[0034]
In FIG. 1, the MIS transistor Q ₂ First, a gate insulating film (second gate insulating film) 17 formed on the p-type well 4 in the semiconductor substrate 1, and a gate electrode (second gate electrode) 22 formed on the gate insulating film 17, have. The gate electrode 22 is formed of a polysilicon film 19 and a cobalt silicide film 43 formed on the polysilicon film 19 in order to reduce resistance.
[0035]
The gate insulating film 17 is formed of a silicon oxide film using an ISSG oxidation method and has a thickness of about 8 nm. MIS transistor Q ₁ Since the oxide film formed by the ISSG oxidation method is a highly reliable film as described in the structure of MIS transistor Q, ₂ However, it is possible to improve the insulation resistance of the gate insulating film 17, in other words, to improve the TDDB life. The film thickness of the gate insulating film 17 is such that the MIS transistor Q ₁ The MIS transistor Q is thicker than the gate insulating film 13c. ₁ The operating voltage of the MIS transistor Q is about 1.8V. ₂ This is because the operating voltage is about 3.3V. That is, the MIS transistor Q ₂ MIS transistor Q ₁ This is because a relatively high breakdown voltage is required.
[0036]
Furthermore, the MIS transistor Q ₂ Are the side wall 34 formed on the side wall of the gate electrode 22, the low concentration n-type impurity diffusion regions 28 and 29, which are semiconductor regions, formed in the p-type well 4 below the side wall 34, and the semiconductor region. There are certain high-concentration n-type impurity diffusion regions 37 and 38, and a cobalt silicide film 43 is formed above the high-concentration n-type impurity diffusion regions 37 and 38 in order to reduce the resistance.
[0037]
The low-concentration n-type impurity diffusion region 28, the high-concentration n-type impurity diffusion region 37, and the cobalt silicide film 43 constitute the MIS transistor Q. ₂ Source region is formed, and the low concentration n-type impurity diffusion region 29, the high concentration n-type impurity diffusion region 38 and the cobalt silicide film 43 are used to form the MIS transistor Q. ₂ The drain region is formed.
[0038]
Next, the MIS transistor Q ₃ The configuration of will be described. MIS transistor Q ₃ The configuration of the MIS transistor Q ₁ , Q ₂ The structure is substantially the same as that of FIG. 1, and the major difference is the thickness of the gate insulating film.
[0039]
In FIG. 1, the MIS transistor Q ₃ Has a gate insulating film (second gate insulating film) 18 formed on the p-type well 5 in the semiconductor substrate 1 and a gate electrode (second gate electrode) 23 formed on the gate insulating film 18. Yes. The gate electrode 23 is formed of a polysilicon film 19 and a cobalt silicide film 43 formed on the polysilicon film 19 for resistance reduction.
[0040]
The gate insulating film 18 is formed of a silicon oxide film using an ISSG oxidation method and has a thickness of about 19 nm. Since the silicon oxide film formed using the ISSG oxidation method as described above is a highly reliable film, it is possible to improve the insulation resistance of the gate insulating film 18, that is, improve the TDDB life. The film thickness of the gate insulating film 18 is MIS transistor Q. ₁ , Q ₂ Thicker than MIS transistor Q ₃ The operating voltage of MIS transistor Q ₁ , Q ₂ This is because a relatively high breakdown voltage is required.
[0041]
Furthermore, the MIS transistor Q ₃ Includes a sidewall 34 formed on the side wall of the gate electrode 23, low-concentration n-type impurity diffusion regions 30 and 31 which are semiconductor regions, and high-concentration n-type impurity diffusion regions 39 and 40 which are semiconductor regions. A cobalt silicide film 43 is formed above the high-concentration n-type impurity diffusion regions 39 and 40 in order to reduce the resistance.
[0042]
The low-concentration n-type impurity diffusion region 30, the high-concentration n-type impurity diffusion region 39, and the cobalt silicide film 43 constitute the MIS transistor Q. ₃ Source region is formed, and the low concentration n-type impurity diffusion region 31, the high concentration n-type impurity diffusion region 40, and the cobalt silicide film 43 are used to form the MIS transistor Q. ₃ The drain region is formed.
[0043]
Next, the field effect transistor Q ₄ The configuration of will be described. In FIG. 1, a field effect transistor Q ₄ Has the following configuration. That is, a gate insulating film (first gate insulating film) 7 is formed on the p-type well 6 of the semiconductor substrate 1, and a floating gate electrode 25 for accumulating charges is formed on the gate insulating film 7.
[0044]
On the floating gate electrode 25, a laminated film (ONO film) composed of a silicon oxide film (first insulating film) 9, a silicon nitride film (second insulating film) 10, and a silicon oxide film (third insulating film) 14 is sequentially formed. A control gate electrode (first gate electrode) 24 is formed on the silicon oxide film 14. The control gate electrode 24 is formed of a cobalt silicide film 43 formed on the polysilicon film 19 and the polysilicon film 19 in order to reduce resistance.
[0045]
Side walls 34 are formed on the side walls of the floating gate electrode 25, the silicon oxide film 9, the silicon nitride film 10, the silicon oxide film 14, and the control gate electrode 24, and a semiconductor is formed in the p-type well 6 below the side wall 34. Low-concentration n-type impurity diffusion regions 32 and 33 are formed as regions.
[0046]
High-concentration n-type impurity diffusion regions 41 and 42, which are semiconductor regions, are formed outside the low-concentration n-type impurity diffusion regions 32 and 33. On the high-concentration n-type impurity diffusion regions 41 and 42, A cobalt silicide film 43 is formed to reduce the resistance. A source region is formed from the low-concentration n-type impurity diffusion region 32, the high-concentration n-type impurity diffusion region 41, and the cobalt silicide film 43, and the low-concentration n-type impurity diffusion region 33, the high-concentration n-type impurity diffusion region 42, and cobalt. A drain region is formed from the silicide film 43.
[0047]
Field effect transistor Q configured as described above. ₄ The gate insulating film 7 is made of, for example, a silicon oxide film, and has a function as a tunnel insulating film in addition to a normal function. For example, field effect transistor Q ₄ Performs storage and erasure of data by injecting electrons from the semiconductor substrate 1 to the floating gate electrode 25 through the gate insulating film 7 and discharging electrons accumulated in the floating gate electrode 25 to the semiconductor substrate 1. . Therefore, it can be seen that the gate insulating film 7 functions as a tunnel insulating film when data is stored or erased.
[0048]
The floating gate electrode 25 is provided for accumulating charges contributing to data storage, and is formed of, for example, a polysilicon film. Depending on whether or not charges are accumulated in the floating gate electrode 25, the voltage at which the channel is formed, that is, the threshold voltage changes. Field effect transistor Q ₄ Stores one-bit information by utilizing the change in the threshold voltage.
[0049]
The silicon oxide film 9, the silicon nitride film 10, and the silicon oxide film 14 have a function of preventing charges accumulated in the floating gate electrode 25 from leaking to the control gate electrode 24. Therefore, these films are required to have excellent insulation resistance.
[0050]
Further, it is desirable that the total thickness of the silicon oxide film 9, the silicon nitride film 10, and the silicon oxide film 14 be as thin as possible without reducing the insulation resistance. This is because when the film thickness is large, the capacitance between the control gate electrode 24 and the floating gate electrode 25 decreases, and when a write voltage is applied to the control gate electrode 24, the potential of the floating gate electrode 25 becomes relatively low. That is, during the write operation, for example, electrons are injected from the source region in the semiconductor substrate 1 into the floating gate electrode 25. At this time, the higher the potential of the floating gate electrode 25 is, the higher the potential of the floating gate electrode 25 is. This is because the injection is facilitated and the speed at which electrons are injected is improved. Thus, from the viewpoint of improving the writing characteristics and the writing speed, it is desirable that the total film thickness of the silicon oxide film 9, the silicon nitride film 10, and the silicon oxide film 14 is small. The actual film thickness of the silicon oxide film 9 is, for example, about 6.5 nm, and the film thickness of the silicon nitride film 10 is, for example, about 6.8 nm. The film thickness of the silicon oxide film 14 is, for example, about 5.0 nm.
[0051]
The silicon oxide film 9 is formed using, for example, a thermal oxidation method or a CVD (Chemical Vapor Deposition) method, and the silicon nitride film 10 is formed by, for example, a CVD method. On the other hand, the silicon oxide film 14 formed on the silicon nitride film 10 is formed by the ISSG oxidation method.
[0052]
Since the silicon nitride film 10 has oxidation resistance, a silicon oxide film cannot be formed on the silicon nitride film 10 using a thermal oxidation method. Therefore, normally, a silicon oxide film is formed on the silicon nitride film 10 using the CVD method.
[0053]
Although the surface of the silicon nitride film 10 is considerably rough and has defects, the formation of the silicon oxide film using the CVD method cannot improve this state and the film quality of the silicon oxide film is also reliable. I can't say that. Therefore, at present, it cannot be said that the leakage current from the floating gate electrode 25 to the control gate electrode 24 is sufficiently prevented.
[0054]
Therefore, in the semiconductor device in the present embodiment, the silicon oxide film 14 is formed on the silicon nitride film 10 by using the ISSG oxidation method. As described above, the ISSG oxidation method is a method of forming the silicon oxide film 14 by reacting hydrogen gas and oxygen gas on the semiconductor substrate 1 while the semiconductor substrate 1 is heated while reducing the pressure from atmospheric pressure. It is. According to this ISSG oxidation method, the silicon nitride film 10 can be strongly oxidized, and the reliable silicon oxide film 14 can be formed while recovering the irregularities and defects on the surface of the silicon nitride film 10. Here, the silicon oxide film 14 formed by the ISSG oxidation method is used for the MIS transistor Q as described in the manufacturing method described later. ₁ ~ Q ₃ The gate insulating films 13c, 17 and 18 are formed in the process of forming the gate insulating films 13c, 17 and 18.
[0055]
Hereinafter, it will be described with reference to FIGS. 2 and 3 that the silicon nitride film 10 can be strongly oxidized by the ISSG oxidation method.
[0056]
FIG. 2 is a graph showing changes in the thickness (oxidation amount) of a silicon oxide film when a silicon oxide film is formed on silicon and when a silicon oxide film is formed on a silicon nitride film. In FIG. 2, the horizontal axis indicates the film thickness (Si oxidation amount) (nm) of the silicon oxide film formed on the silicon, and the vertical axis indicates the film of the silicon oxide film formed on the silicon nitride film. Thickness (SiN oxidation amount) (nm) is shown.
[0057]
The triangle mark in FIG. 2 shows the case where a silicon oxide film is formed on the silicon and the silicon nitride film by a normal steam oxidation method, and the rhombus mark is about 4 times closer to the silicon by the ISSG oxidation method. This shows a case where a silicon oxide film is formed on a silicon nitride film on which a .3 nm silicon oxide film is formed. Square marks indicate the case where a silicon oxide film is formed on the silicon and the silicon nitride film by the ISSG oxidation method.
[0058]
As shown in FIG. 2, in a normal steam oxidation method (triangle mark), a silicon oxide film is formed on silicon, but a silicon oxide film is hardly formed on the silicon nitride film, and a silicon nitride film is formed. It can be seen that has oxidation resistance. Specifically, a silicon oxide film having a thickness of about 7.7 nm is formed on silicon, whereas only a silicon oxide film having a thickness of about 0.5 nm is formed on the silicon nitride film.
[0059]
Next, it can be seen that when the ISSG oxidation method is used (square marks), a silicon oxide film is formed on the silicon and a silicon oxide film is also formed on the silicon nitride film. Then, as the thickness of the silicon oxide film formed on the silicon increases, the thickness of the silicon oxide film formed on the silicon nitride film also increases, and there is a predetermined linear relationship between them. Recognize. Specifically, when the thickness of the silicon oxide film on the silicon is about 2.9 nm, the thickness of the silicon oxide film on the silicon nitride film is about 1.7 nm. It can be seen that when the thickness of the silicon oxide film on the silicon increases to about 17 nm, the thickness of the silicon oxide film on the silicon nitride film also increases to about 11 nm. Therefore, it can be seen that according to the ISSG oxidation method, unlike a normal steam oxidation method, a silicon oxide film can be sufficiently formed on the silicon nitride film.
[0060]
Next, when a silicon oxide film is formed on the silicon nitride film formed on the silicon and silicon nitride film having a thickness of about 4.3 nm using the ISSG oxidation method (diamond mark), the silicon oxide film is similarly formed on the silicon. It can be seen that a silicon oxide film is also formed on the silicon nitride film. However, the thickness of the silicon oxide film to be formed is larger in the silicon nitride film in which nothing is initially formed than in the silicon nitride film in which the silicon oxide film of about 4.3 nm is formed from the beginning. .
[0061]
Next, FIG. 3 shows the relationship between the erosion amount of the silicon nitride film and the film thickness (Si oxidation amount) of the silicon oxide film formed on the silicon when the silicon oxide film is formed on the silicon nitride film. It is the shown graph.
[0062]
In FIG. 3, the horizontal axis indicates the film thickness (Si oxidation amount) (nm) of the silicon oxide film formed on the silicon, and the vertical axis indicates the case where the silicon oxide film is formed on the silicon nitride film. The erosion amount (nm) of the silicon nitride film is shown. The number on the vertical axis indicates the amount of erosion of the silicon nitride film, and indicates that the amount of erosion increases toward the bottom. 2 and 3 are common to the horizontal axes. Further, the plots of triangle marks, square marks, and rhombus marks in FIG. 3 indicate the same conditions as in FIG.
[0063]
In the case of a normal steam oxidation method (triangle mark), a silicon oxide film is formed on silicon, but a silicon oxide film is hardly formed on the silicon nitride film (see FIG. 2). Therefore, as can be seen from FIG. 3, it can be seen that there is almost no erosion amount of the silicon nitride film. Specifically, a silicon oxide film having a thickness of about 7.8 nm is formed on silicon, whereas only a silicon oxide film having a thickness of about 0.5 nm is formed on the silicon nitride film. It can be seen that the amount of erosion of the film is also about 0.5 nm.
[0064]
Next, since the horizontal axis of FIG. 2 and the horizontal axis of FIG. 3 are common, the relationship between the vertical axis of FIG. 2 and the vertical axis of FIG. 3 will be described. That is, the relationship between the thickness of the silicon oxide film formed on the silicon nitride film (vertical axis in FIG. 2) and the amount of erosion of the silicon nitride film (vertical axis in FIG. 3) will be described.
[0065]
When a silicon oxide film is formed on the silicon nitride film by using the ISSG oxidation method (square mark), the erosion of the silicon nitride film is increased as the thickness of the silicon oxide film formed on the silicon nitride film is increased. It can be seen that there is a predetermined linear relationship that the amount also increases. More specifically, when a silicon oxide film having a thickness of about 1.8 nm is formed on the silicon nitride film (see the vertical axis in FIG. 2), the erosion amount of the silicon nitride film is about 1.2 nm ( (See vertical axis in FIG. 3). When a silicon oxide film having a thickness of about 11 nm is formed on the silicon nitride film, the amount of erosion of the silicon nitride film is about 7 nm. Accordingly, the silicon oxide film having a thickness of about 11 nm is formed of a silicon oxide film having a thickness of about 7 nm that is eroded by the silicon nitride film and a silicon oxide film having a thickness of about 4 nm that is deposited on the silicon nitride film. I understand that.
[0066]
This shows that the silicon oxide film formed by the ISSG oxidation method is deposited while eroding the silicon nitride film as the base. Therefore, according to the ISSG oxidation method, it is possible to recover defects existing in the silicon nitride film while eroding unevenness on the surface of the silicon nitride film.
[0067]
Similarly, when a silicon oxide film is formed on the silicon nitride film on which a silicon oxide film of about 4.3 nm from the beginning is formed by using the ISSG oxidation method (diamond mark), the oxidation formed on the silicon nitride film is also performed. It can be seen that the erosion amount of the silicon nitride film increases as the thickness of the silicon film increases.
[0068]
Next, a method for manufacturing a semiconductor device in the present embodiment will be described.
[0069]
First, as shown in FIG. 4, for example, a semiconductor substrate 1 in which p-type impurities are introduced into single crystal silicon is prepared. Examples of the p-type impurity include boron and boron fluoride. Next, an element isolation region 2 is formed in each region of the main surface of the semiconductor substrate 1. That is, the element isolation regions 2 are formed in the 1.8V MIS transistor formation region, the 3.3V MIS transistor formation region, the HV MIS transistor formation region, and the nonvolatile memory cell formation region, respectively.
[0070]
The element isolation region 2 is provided to electrically isolate each element so as not to adversely influence each other such as interference, and is formed by, for example, a LOCOS (Local Oxidation Of Silicon) method or an STI (Shallow Trench Isolation) method. be able to. FIG. 4 shows an element isolation region 2 formed by the STI method in which a shallow groove is dug in the main surface of the semiconductor substrate 1 and a silicon oxide film is buried in the groove. According to the STI method, the isolation width can be reduced and the depth of the element isolation region 2 can be increased as compared with the LOCOS method, so that high integration of elements can be achieved.
[0071]
Next, p-type wells 3, 4, 5, 6 are formed in the active region of the semiconductor substrate 1 separated by the element isolation region 2. The p-type wells 3 to 6 are formed by introducing p-type impurities such as boron and boron fluoride into the active region of the semiconductor substrate 1 using, for example, a photolithography technique and an ion implantation method. In order to activate the introduced boron or boron fluoride, heat treatment is performed after the introduction.
[0072]
Subsequently, as shown in FIG. 5, a gate insulating film (first gate insulating film) 7 is formed on the entire main surface (element formation surface) of the semiconductor substrate 1. The gate insulating film 7 is made of, for example, a silicon oxide film, and can be formed by, for example, a thermal oxidation method.
[0073]
Then, a polysilicon film (first conductor film) 8 which is a conductor film is formed on the gate insulating film 7. For the polysilicon film 8, for example, a CVD method for depositing the polysilicon film 8 by thermally decomposing silane gas in nitrogen gas can be used.
[0074]
Next, a silicon oxide film (first insulating film) 9 is formed on the polysilicon film 8. The silicon oxide film 9 can be formed by, for example, a thermal oxidation method or a CVD method using silane gas and oxygen gas, and the film thickness is, for example, about 6.5 nm. Subsequently, a silicon nitride film (second insulating film) 10 is formed on the silicon oxide film 9. The silicon nitride film 10 can be formed using, for example, a CVD method in which silane gas and ammonia gas are reacted in a gas phase. After the silicon nitride film 10 is formed, annealing (crimping) is performed, and a thin silicon oxide film 11 is formed on the silicon nitride film 10. This annealing is performed for the purpose of eliminating defects such as pinholes generated in the silicon nitride film 10.
[0075]
Subsequently, after applying a photosensitive resist film 12 on the thin silicon oxide film 11, exposure and development are performed and patterning is performed. The patterning is performed so that the resist film 12 remains only in the nonvolatile memory cell formation region. That is, the resist film 12 formed on the 1.8V MIS transistor formation region, the 3.3V MIS transistor formation region, and the HV MIS transistor formation region is removed.
[0076]
Next, as shown in FIG. 6, the patterned resist film 12 is formed on the 1.8V MIS transistor formation region, 3.3V MIS transistor formation region, and HV MIS transistor formation region by etching using the resist film 12 as a mask. The thin silicon oxide film 11, silicon nitride film 10, silicon oxide film 9 and polysilicon film 8 are removed.
[0077]
Subsequently, after removing the patterned resist film 12, as shown in FIG. 7, gates formed in the 1.8V MIS transistor formation region, the 3.3V MIS transistor formation region, and the HV MIS transistor formation region. The insulating film 7 is removed. For example, a buffered hydrofluoric acid solution is used to remove the gate insulating film 7. This buffered hydrofluoric acid solution is a mixed solution consisting of hydrofluoric acid, ammonium fluoride and pure water. Note that when the gate insulating film 7 is removed, the silicon oxide film 11 formed on the silicon nitride film 10 in the nonvolatile memory cell formation region is also removed.
[0078]
The semiconductor substrate 1 subjected to the above-described processing is carried into a heating apparatus as shown in FIG. 8 in order to perform the ISSG oxidation method next.
[0079]
FIG. 8 is a partial cross-sectional view showing a schematic configuration of the processing chamber 100 of the heating apparatus. In FIG. 8, the processing chamber 100 of the heating apparatus has a stage 101, a lamp assembly 102, an introduction port 103a for introducing gas, and an exhaust port 103b for exhausting gas.
[0080]
The stage 101 is for placing the semiconductor substrate 1 loaded from the outside. The lamp assembly 102 is configured to heat the semiconductor substrate 1 disposed on the stage 101, and includes a plurality of lamps 102a.
[0081]
The introduction port 103a is for introducing hydrogen gas and oxygen gas into the processing chamber 100, and the exhaust port 103b is for exhausting reaction gas and the like.
[0082]
Hereinafter, a process of forming an oxide film on the semiconductor substrate 1 in the processing chamber 100 described above will be described.
[0083]
The semiconductor substrate 1 is carried into the processing chamber 100 configured as described above, and is placed on the stage 101. The temperature of the semiconductor substrate 1 is heated to, for example, about 950 ° C. to 1100 ° C. by the plurality of lamps 102a. Subsequently, hydrogen gas and oxygen gas are introduced into the processing chamber 100 from the introduction port 103a. At this time, the pressure in the processing chamber 100 is set to about 10 × 133.3 Pa, for example. The introduced hydrogen gas and oxygen gas react on the semiconductor substrate 1, and a gate insulating film 13a and a silicon oxide film (third insulating film) 14 made of a silicon oxide film are formed on the semiconductor substrate 1 as shown in FIG. It is formed. Here, the mixing ratio of the hydrogen gas and the oxygen gas introduced into the processing chamber 100 is, for example, a ratio of oxygen gas of 98% to 67% with respect to a ratio of hydrogen gas of 2% to 33%.
[0084]
As described above, according to the ISSG oxidation method, the gate insulating film 13a is formed on the 1.8V MIS transistor formation region, the 3.3V MIS transistor formation region, and the HV MIS transistor formation region in the same process, and is nonvolatile. A silicon oxide film 14 can be formed on the silicon nitride film 10 in the memory cell formation region. The reason why the gate insulating film 13a and the silicon oxide film 14 can be formed in the same process is that the silicon oxide film can be formed on the silicon nitride film by the ISSG oxidation method.
[0085]
Next, as shown in FIG. 10, after applying a resist film 15 on the semiconductor substrate 1, the resist film 15 is patterned by exposure and development. The patterning is performed so that the resist film 15 remains on the nonvolatile memory cell formation region and the HV MIS transistor formation region. Then, the gate insulating film 13a formed on the 1.8V MIS transistor formation region and the 3.3V MIS transistor formation region is removed by etching using the patterned resist film 15 as a mask.
[0086]
Subsequently, after removing the resist film 15, the semiconductor substrate 1 is again carried into the processing chamber 100 of the heating apparatus as shown in FIG. 8, and the ISSG oxidation method is performed. As a result, as shown in FIG. 11, the gate insulating film 13b is formed on the semiconductor substrate 1 and the thickness of the silicon oxide film 14 is increased. That is, the gate insulating film 13b is formed on the 1.8V MIS transistor forming region and the 3.3V MIS transistor forming region, and the gate insulating film 13b is formed on the gate insulating film 13a in the HV MIS transistor forming region. Is formed. In addition, the thickness of the silicon oxide film 14 increases in the nonvolatile memory cell formation region. At this time, as described with reference to FIG. 3, the silicon oxide film 14 grows so as to erode the silicon nitride film 10 which is the base, and thus the thickness of the silicon nitride film 10 decreases.
[0087]
Next, as shown in FIG. 12, after a resist film 16 is applied on the element forming surface of the semiconductor substrate 1, the resist film 16 is patterned by exposure and development. The patterning is performed so that the resist film 16 does not remain only in the 1.8V MIS transistor formation region. Then, the gate insulating film 13b formed in the 1.8V MIS transistor formation region is removed by etching using the patterned resist film 16 as a mask.
[0088]
Subsequently, after removing the resist film 16, the semiconductor substrate 1 is again carried into the processing chamber 100 of the heating apparatus shown in FIG. 8, and the ISSG oxidation method is performed. As a result, as shown in FIG. 13, the gate insulating film 13 c is formed on the semiconductor substrate 1 and the thickness of the silicon oxide film 14 is increased. That is, the gate insulating film (second gate insulating film) 13c is formed in the 1.8V MIS transistor forming region, and the 3.3V MIS transistor forming region is composed of the gate insulating film 13b and the gate insulating film 13c. A gate insulating film (second gate insulating film) 17 is formed.
[0089]
A gate insulating film (second gate insulating film) 18 made of the gate insulating films 13a, 13b, and 13c is formed in the HV MIS transistor formation region. In the nonvolatile memory cell formation region, the film thickness of the silicon oxide film 14 increases, while the film thickness of the eroded silicon nitride film 10 decreases.
[0090]
In this manner, gate insulating films having different thicknesses can be formed in the 1.8V MIS transistor forming region, the 3.3V MIS transistor forming region, and the HV MIS transistor forming region, respectively, and the nonvolatile memory cell is formed. In the region, the silicon oxide film 14 can be formed on the silicon nitride film 10. Therefore, a laminated film (ONO film) made of the silicon oxide film 9, the silicon nitride film 10, and the silicon oxide film 14 can be formed on the polysilicon film 8 in the nonvolatile memory cell formation region.
[0091]
According to the method of manufacturing a semiconductor device in the present embodiment, in the process of forming the gate insulating film of the MIS transistor used for the logic circuit and the peripheral circuit, the silicon nitride film 10 formed on the nonvolatile memory cell formation region is formed. Then, the silicon oxide film 14 can be formed. In other words, in the process of forming the silicon oxide film 14 on the ON film made of the silicon oxide film 9 and the silicon nitride film 10 formed in the nonvolatile memory cell formation region, the MIS transistor used for the logic circuit and the peripheral circuit. The gate insulating film can be formed. Therefore, the number of processes can be reduced as compared with conventional processes, and the cost of manufactured products can be reduced.
[0092]
In other words, in the conventional process, after forming a stacked film (ONO film) of a silicon oxide film, a silicon nitride film, and a silicon oxide film on the polysilicon film, the uppermost silicon oxide film of the stacked film is protected. A silicon nitride film was formed. That is, a laminated film (ONON film) composed of four layers is formed on the polysilicon film. Then, the gate insulating film of the MIS transistor used for the logic circuit and the peripheral circuit is formed in a state where the laminated film composed of four layers is formed on the nonvolatile memory cell forming region.
[0093]
On the other hand, in the method of manufacturing a semiconductor device in the present embodiment, a laminated film (ON film) made of the silicon oxide film 9 and the silicon nitride film 10 is formed on the polysilicon film. Then, using the ISSG oxidation method, a silicon oxide film 14 is formed on the silicon nitride film 10 to form a laminated film (ONO film), and a gate insulating film of a MIS transistor used for a logic circuit or a peripheral circuit. Is forming. For this reason, according to the method for manufacturing a semiconductor device in the present embodiment, a laminated film (ON film) consisting of two layers is formed without forming a laminated film (ONON film) consisting of four layers, and the ON film. The number of steps can be reduced in that the gate oxide film of the MIS transistor used for the logic circuit and the peripheral circuit is formed while the silicon oxide film 14 is formed on the upper portion of the silicon oxide film.
[0094]
Furthermore, according to the manufacturing method of the semiconductor device in the present embodiment, the silicon oxide film 14 is formed on the silicon nitride film 10 by the ISSG oxidation method. Accordingly, the reliability of the silicon oxide film 14 itself is high and the surface irregularities and defects of the silicon nitride film 10 can be recovered. Therefore, the silicon oxide film 14 is more reliable than the case where the CVD method is used. A film can be formed. Similarly, since the gate insulating film of the MIS transistor used in the logic circuit and the peripheral circuit also uses the ISSG oxidation method, the insulation resistance is higher than the CVD method or the film combining the CVD method and the thermal oxidation method. And a film having a long TDDB life can be formed. As described above, the method for manufacturing a semiconductor device in this embodiment can form a highly reliable film while reducing the number of steps.
[0095]
In this embodiment, the ISSG oxidation method is used when any of the gate insulating films 13a, 13b, and 13c is formed. Therefore, each time the gate insulating films 13a, 13b, and 13c are sequentially formed, the film thickness of the silicon oxide film 14 formed on the silicon nitride film 10 is increased to, for example, a predetermined film thickness A. However, the film thickness of the silicon oxide film 14 can be reduced from A. That is, not all of the gate insulating films 13a, 13b, and 13c are formed by the ISSG oxidation method, but, for example, a thermal oxidation method is used to form the gate insulating film 13a, and the gate insulating films 13b and 13c are formed. Performs the ISSG oxidation method. By doing so, the film thickness of the silicon oxide film 14 can be made thinner than A. This is because the silicon oxide film 14 cannot be grown on the silicon nitride film 10 by the thermal oxidation method. In this case, the silicon oxide film 14 can be grown on the silicon nitride film 10 when the gate insulating films 13b and 13c are formed by the ISSG oxidation method. As described above, the thickness of the silicon oxide film 14 can be reduced by forming any one of the gate insulating films 13a, 13b, and 13c using the thermal oxidation method instead of the ISSG oxidation method.
[0096]
Further, when it is desired to reduce the thickness of the silicon oxide film 14 formed on the silicon nitride film 10, any two of the gate insulating films 13a, 13b, and 13c may be formed using a thermal oxidation method. .
[0097]
As described above, the thickness of the silicon oxide film 14 formed on the silicon nitride film 10 can be adjusted by appropriately changing the formation method of the gate insulating films 13a, 13b, and 13c. In other words, since the silicon oxide film 14 grows by eroding the silicon nitride film 10 according to the ISSG oxidation method, the thickness of the silicon nitride film 10 is changed by changing the formation method of the gate insulating films 13a, 13b, and 13c. It can be said that can be adjusted.
[0098]
Next, a process after forming the gate insulating film 13c, the gate insulating film 17, and the gate insulating film 18 and forming the silicon oxide film 14 on the silicon nitride film 10 in the nonvolatile memory cell formation region will be described.
[0099]
As shown in FIG. 14, a polysilicon film (second conductor film) 19 that is a conductor film is formed on the element formation surface of the semiconductor substrate 1. The polysilicon film 19 can be formed by, for example, a CVD method in which silane gas is thermally decomposed in nitrogen gas. Note that a conductive impurity such as phosphorus is added during the growth of the polysilicon film 19 or after the growth in order to reduce the resistance.
[0100]
Subsequently, a silicon oxide film 20 a is formed on the polysilicon film 19. The silicon oxide film 20a can be formed by, for example, a plasma CVD method. And after apply | coating the resist film 20 on the silicon oxide film 20a, it patterns by exposing and developing. The patterning is performed so that the resist film 20 remains in the region where the gate electrode is to be formed.
[0101]
Next, the silicon oxide film 20a is patterned by etching using the patterned resist film 20 as a mask. Thereafter, as shown in FIG. 15, the polysilicon film 19 is similarly etched to form gate electrodes (second gate electrodes) 21, 22, 23 and a control gate electrode (first gate electrode) 24.
[0102]
Subsequently, after the 1.8V MIS transistor formation region, the 3.3V MIS transistor formation region, and the HV MIS transistor formation region are covered with a resist film, the silicon oxide film 20a (hard mask) and the control gate electrode 24 are masked. The etched silicon oxide film 14, silicon nitride film 10, silicon oxide film 9 and polysilicon film 8 are patterned. Then, as shown in FIG. 16, a floating gate electrode 25 made of the polysilicon film 8 is formed under the control gate electrode 24 through the silicon oxide film 14, the silicon nitride film 10, and the silicon oxide film 9.
[0103]
Subsequently, after removing the resist film covering the 1.8V MIS transistor formation region, the 3.3V MIS transistor formation region, and the HV MIS transistor formation region, the gate electrodes 21 to 23 and the control gate electrode 24 are formed. The formed silicon oxide film 20a is removed.
[0104]
Next, as shown in FIG. 17, low-concentration n-type impurity diffusion regions 26 and 27, which are semiconductor regions, are formed on both sides of the gate electrode 21 using a photolithography technique and an ion implantation method. The low-concentration n-type impurity diffusion regions 26 and 27 can be formed by introducing a n-type impurity such as phosphorus or arsenic and then performing a heat treatment for activating the introduced impurity.
[0105]
Similarly, low-concentration n-type impurity diffusion regions 28 and 29 that are semiconductor regions are formed on both sides of the gate electrode 22, and low-concentration n-type impurity diffusion regions 30 and 31 that are semiconductor regions are formed on both sides of the gate electrode 23. Form. Further, low-concentration n-type impurity diffusion regions 32 and 33 which are semiconductor regions are formed on both sides of the control gate electrode 24.
[0106]
Subsequently, a silicon oxide film is deposited on the element formation surface of the semiconductor substrate 1 by using, for example, a CVD method. Then, as shown in FIG. 18, the deposited silicon oxide film is anisotropically etched to form side walls 34 on the side walls of the gate electrodes 21 to 23 and the control gate electrode 24 (including the floating gate electrode 25). .
[0107]
Next, as shown in FIG. 18, a high-concentration n-type impurity diffusion region 35, which is a semiconductor region, is formed on both sides of the sidewall 34 formed on the sidewall of the gate electrode 21 by using a photolithography technique and an ion implantation method. , 36 are formed. The high-concentration n-type impurity diffusion regions 35 and 36 are formed by performing a heat treatment for activating the n-type impurity after introducing an n-type impurity such as phosphorus or arsenic. The concentration of the n-type impurity introduced into the high-concentration n-type impurity diffusion regions 35 and 36 is introduced higher than the concentration of the low-concentration n-type impurity diffusion regions 26 and 27.
[0108]
Similarly, high-concentration n-type impurity diffusion regions 37 and 38 that are semiconductor regions are formed on both sides of the sidewall 34 formed on the sidewall of the gate electrode 22, and the sidewall formed on the sidewall of the gate electrode 23 is formed. High-concentration n-type impurity diffusion regions 39 and 40 that are semiconductor regions are formed on both sides of 34. Further, high-concentration n-type impurity diffusion regions 41 and 42 that are semiconductor regions are formed on both sides of the sidewall 34 formed on the sidewall of the control gate electrode 24 (including the floating gate electrode 25).
[0109]
Next, a cobalt film is formed on the element formation surface of the semiconductor substrate 1. The cobalt film can be formed by, for example, a sputtering method or a CVD method. Subsequently, a heat treatment is performed on the semiconductor substrate 1 to form a cobalt silicide film 43 on the high concentration n-type impurity diffusion regions 35 to 42, the gate electrodes 21 to 23 and the control gate electrode 24. The cobalt silicide film 43 is formed for reducing the resistance. Thereafter, the unreacted cobalt film is removed. In this embodiment, the cobalt silicide film 43 is used. However, the present invention is not limited to this. For example, a titanium silicide film or a nickel silicide film may be used.
[0110]
In this way, the n-type MIS transistor Q is formed in the 1.8V MIS transistor formation region. ₁ 3.3 n-type MIS transistor Q in the 3.3V MIS transistor formation region ₂ N-type MIS transistor Q in the HV MIS transistor formation region ₃ Can be formed. The field effect transistor Q is formed in the non-volatile memory cell formation region. ₄ Can be formed.
[0111]
Next, the wiring process will be described.
[0112]
First, as shown in FIG. 1, the MIS transistor Q ₁ ~ Q ₃ And field effect transistor Q ₄ A silicon oxide film 44 is formed on the element formation surface of the semiconductor substrate 1 on which is formed. The silicon oxide film 44 can be formed using, for example, a CVD method.
[0113]
Subsequently, the surface of the formed silicon oxide film 44 is planarized. The surface is planarized by, for example, polishing the surface by a CMP (Chemical Mechanical Polishing) method.
[0114]
Next, the connection hole 50 is formed in the silicon oxide film 44 using a photolithography technique and an etching technique. The connection hole 50 is connected to the MIS transistor Q. ₁ ~ Q ₃ Of the field effect transistor Q and the source region and the drain region. ₄ It is formed so as to penetrate to the drain region.
[0115]
Subsequently, a titanium / titanium nitride film 51 a is formed on the entire surface of the element formation surface of the semiconductor substrate 1. The titanium / titanium nitride film 51 a can be formed using, for example, a sputtering method, and is also formed on the inner wall and the bottom surface of the connection hole 50. This titanium / titanium nitride film 51a has a function of preventing the tungsten buried in the connection hole 50 from diffusing into silicon in a process described later.
[0116]
Thereafter, a tungsten film 51b is formed so as to fill the connection hole 50 on the titanium / titanium nitride film 51a. The tungsten film 51b can be formed using, for example, a CVD method. Then, by using, for example, a CMP method, the unnecessary titanium / titanium nitride film 51a and the tungsten film 51b formed outside the inside of the connection hole 50 are removed, and the plug 51 is formed.
[0117]
Next, a titanium / titanium nitride film 52a, an aluminum film 52b, and a titanium / titanium nitride film 52c are sequentially formed on the silicon oxide film 44 and the plug 51. These films can be formed using, for example, a sputtering method. Thereafter, using the photolithography technique and the etching technique, the above-described film is patterned to form the wiring 52.
[0118]
In this way, the first layer wiring can be formed. Subsequent multilayer wiring is formed in the same manner, but description thereof is omitted in this specification.
[0119]
According to the method for manufacturing a semiconductor device in the present embodiment, the number of steps can be reduced as described above, and a highly reliable film can be formed.
[0120]
Further, the field effect transistor Q included in the semiconductor device of the present embodiment. ₄ In this case, since the silicon oxide film 14 is formed by the ISSG oxidation method capable of forming a high-quality silicon oxide film and recovering defects in the underlying silicon nitride film, the insulation resistance can be improved. Therefore, the field effect transistor Q ₄ The data retention characteristics can be improved.
[0121]
Further, the insulating film between the control gate electrode 24 and the floating gate electrode 25 is formed by an ONO film, and the silicon oxide film 14 is formed by an ISSG oxidation method in which the silicon nitride film 10 is eroded. Therefore, the thickness of the ONO film can be reduced. Therefore, the nonvolatile memory cell (field effect transistor Q ₄ ) Writing speed and writing characteristics can be improved.
[0122]
Further, in the ISSG oxidation method used in the present embodiment, since the silicon oxide film 14 is formed so as to erode the silicon nitride film 10, the silicon nitride film 10 has a thin thickness so that the silicon nitride film 10 cannot be formed by the CVD method. A film 10 can be formed. That is, first, after forming the silicon nitride film 10 by the CVD method, the silicon oxide film 14 is formed so as to erode the silicon nitride film 10 by using the ISSG oxidation method. Thus, the silicon nitride film 10 can be formed so thin that it cannot be formed by the CVD method.
[0123]
The invention made by the present inventor has been specifically described based on the above embodiment, but the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0124]
In the above embodiment, the case where three different types of gate insulating films are formed has been described. However, the present invention is not limited to this, and the present invention is applied to a process of forming three or more types of gate insulating films and an ONO film. Also good.
[0125]
In the above-described embodiment, the case where the n-type MIS transistor is formed in the 1.8V MIS transistor formation region, the 3.3V MIS transistor formation region, and the HV MIS transistor formation region has been described. Instead of this, a p-type MIS transistor may be formed, or an n-type and p-type MIS transistor may be formed.
[0126]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0127]
In a semiconductor device in which a nonvolatile memory cell including a first field effect transistor for memory and a circuit including a second field effect transistor are formed in different regions of a semiconductor substrate, the writing characteristics of the first field effect transistor are improved. In addition, the reliability of the gate insulating film of the second field effect transistor can be improved.
[0128]
Further, in a method for manufacturing a semiconductor device in which a nonvolatile memory cell including a first field effect transistor for memory and a circuit including a second field effect transistor are formed in different regions of a semiconductor substrate, the number of steps can be reduced. In addition, a film with improved reliability can be formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a graph showing the relationship between the thickness of a silicon oxide film formed on silicon (Si oxidation amount) and the thickness of a silicon oxide film formed on a silicon nitride film (SiN oxidation amount). is there.
FIG. 3 is a graph showing the relationship between the erosion amount of a silicon nitride film and the film thickness (Si oxidation amount) of the silicon oxide film formed on silicon when a silicon oxide film is formed on the silicon nitride film. It is.
FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;
FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4;
6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG.
7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG.
FIG. 8 is a partial cross-sectional view showing a processing chamber for using the ISSG oxidation method.
FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 7;
10 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 9; FIG.
FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 10;
12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG.
13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG.
14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG.
15 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 14; FIG.
16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG.
FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 16;
FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 17;
[Explanation of symbols]
1 Semiconductor substrate
2 Device isolation region
3 p-type well
4 p-type well
5 p-type well
6 p-type well
7 Gate insulation film (first gate insulation film)
8 Polysilicon film (first conductor film)
9 Silicon oxide film (first insulating film)
10 Silicon nitride film (second insulating film)
11 Silicon oxide film
12 resist film
13a Gate insulating film
13b Gate insulating film
13c Gate insulating film (second gate insulating film)
14 Silicon oxide film (third insulating film)
15 Resist film
16 resist film
17 Gate insulating film (second gate insulating film)
18 Gate insulating film (second gate insulating film)
19 Polysilicon film (second conductor film)
20 resist film
20a Silicon oxide film
21 Gate electrode (second gate electrode)
22 Gate electrode (second gate electrode)
23 Gate electrode (second gate electrode)
24 Control gate electrode (first gate electrode)
25 Floating gate electrode
26 Low concentration n-type impurity diffusion region
27 Low-concentration n-type impurity diffusion region
28 Low-concentration n-type impurity diffusion region
29 Low-concentration n-type impurity diffusion region
30 Low-concentration n-type impurity diffusion region
31 Low-concentration n-type impurity diffusion region
32 Low-concentration n-type impurity diffusion region
33 Low-concentration n-type impurity diffusion region
34 sidewall
35 High-concentration n-type impurity diffusion region
36 High-concentration n-type impurity diffusion region
37 High-concentration n-type impurity diffusion region
38 High-concentration n-type impurity diffusion region
39 High-concentration n-type impurity diffusion region
40 High-concentration n-type impurity diffusion region
41 High-concentration n-type impurity diffusion region
42 High concentration n-type impurity diffusion region
43 Cobalt silicide film
44 Silicon oxide film
50 Connection hole
51 plug
51a Titanium / titanium nitride film
51b Tungsten film
52 Wiring
52a Titanium / titanium nitride film
52b Aluminum film
52c Titanium / titanium nitride film
100 treatment room
101 stage
102 Lamp assembly
102a lamp
103a inlet
103b Exhaust port
Q ₁ MIS transistor (second field effect transistor)
Q ₂ MIS transistor (second field effect transistor)
Q ₃ MIS transistor (second field effect transistor)
Q ₄ Field effect transistor (first field effect transistor)

Claims (10)

A semiconductor device in which a rewritable nonvolatile memory cell including a first field effect transistor for memory and a circuit including a second field effect transistor are formed in different regions on a semiconductor substrate,
The first field effect transistor is:
(A) a first gate insulating film formed on the semiconductor substrate;
(B) a floating gate electrode formed on the first gate insulating film;
(C) a first insulating film formed on the floating gate electrode;
(D) a second insulating film formed on the first insulating film;
(E) a third insulating film formed on the second insulating film;
(F) having a first gate electrode formed on the third insulating film;
The second field effect transistor is:
(G) a second gate insulating film formed on the semiconductor substrate;
(H) a second gate electrode formed on the second gate insulating film;
The third insulating film and the second gate insulating film are formed by reacting hydrogen gas and oxygen gas on the semiconductor substrate in a state where pressure is reduced from atmospheric pressure. Semiconductor device. The semiconductor device according to claim 1,
The semiconductor device, wherein the third insulating film is formed in the process of forming the second gate insulating film. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the circuit is a logic circuit or a circuit for operating the nonvolatile memory cell. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the circuit is a part of a circuit constituting a microcomputer arranged in parallel with the nonvolatile memory. The semiconductor device according to claim 1,
The semiconductor device, wherein the third insulating film and the second gate insulating film are formed of a silicon oxide film. A method of manufacturing a semiconductor device, wherein a rewritable nonvolatile memory cell including a first field effect transistor for memory and a circuit including a second field effect transistor are formed in different regions of a semiconductor substrate,
(A) forming a first gate insulating film of the first field effect transistor on the semiconductor substrate;
(B) forming a first conductor film on the first gate insulating film;
(C) forming a first insulating film on the first conductor film;
(D) forming a second insulating film on the first insulating film;
(E) forming a patterned resist film on the second insulating film;
(F) leaving the first conductor film, the first insulating film, and the second insulating film only in a formation region of the nonvolatile memory cell by etching using the resist film as a mask;
(G) removing the first gate insulating film formed on the semiconductor substrate, leaving only the first gate insulating film formed in the formation region of the nonvolatile memory cell;
(H) forming a third insulating film on the second insulating film and forming a second gate insulating film of the second field effect transistor on the semiconductor substrate;
In the step (h), the third insulating film and the second gate insulating film are formed by reacting hydrogen gas and oxygen gas on the semiconductor substrate in a state where the pressure is reduced from the atmospheric pressure. A method for manufacturing a semiconductor device. (I) forming a second conductor film on the third insulating film and the second gate insulating film;
(J) forming a first gate electrode of the first field effect transistor on the third insulating film by patterning the second conductor film, and forming the second field effect transistor on the second gate insulating film; Forming a second gate electrode of
(K) By etching using the first gate electrode as a mask, the first conductor film is formed under the first gate electrode through the third insulating film, the second insulating film, and the first insulating film. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming a floating gate electrode. The method of manufacturing a semiconductor device according to claim 6.
The method of manufacturing a semiconductor device, wherein the circuit is a logic circuit or a circuit for operating the nonvolatile memory cell. The method of manufacturing a semiconductor device according to claim 6.
A method of manufacturing a semiconductor device, wherein the circuit is a part of a circuit constituting a microcomputer arranged in parallel with a nonvolatile memory. The method of manufacturing a semiconductor device according to claim 6.
The second insulating film is a silicon nitride film, and the third insulating film is a silicon oxide film;
In the step (h), the silicon oxide film is eroded by reacting the hydrogen gas and the oxygen gas on the semiconductor substrate in a state where the pressure is reduced from the atmospheric pressure. A method of manufacturing a semiconductor device, comprising forming a film and adjusting a film thickness of the silicon nitride film.

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