JP2004355495A - Computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system which does not fall into an abnormal state as a whole even if each function block falls into an abnormal state by realizing function operation/ function stop and an initializing function for each function block in a computer system with a CPU and other function blocks. <P>SOLUTION: Each of the function blocks 120, 130, 140 is refreshed by providing a control signal generation circuit 106 for performing function operation/function stop and initializing control of each of the function blocks 120, 130, 140 and performing processes of function stop/initializing and function operation for each operation of each of the function blocks 120, 130, 140 by software control using the CPU 101. As each of the function blocks 120, 130, 140 can be always started from an initial state when using them by performing the refresh operation, it starts from a normal state at the next time even if it is in an abnormal state at a certain timing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a computer system having a CPU and at least one functional block other than the CPU. In particular, the functional operation / stop and initialization of each functional block can be performed by software control using the CPU. It concerns computer systems.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a computer system having a CPU and at least one functional block other than the CPU, the CPU performs various controls of each functional block via a bidirectional bus.
[0003]
FIG. 3 shows an example of the configuration of a conventional computer system. 3, reference numeral 301 denotes a CPU (central processing unit); 302, a communication block which is one of the functional blocks; 303, another functional block; 304, another functional block; and 305, a bidirectional bus (data, address). etc), 306 are external reset terminals to which an external reset signal is input.
[0004]
For example, when controlling the communication block 302 to realize communication with another device (not shown), the CPU 301 transmits commands such as transmission data and a transmission command to the communication block 302 via the bus 305. . The communication block 302 starts communication with another device based on a command from the CPU 301. With respect to the other functional blocks 303 and 304, the CPU 301 transmits an instruction and performs an operation corresponding to the functional blocks 303 and 304 based on the instruction.
[0005]
When noise or the like is mixed from the outside into the computer system having the CPU 301, the communication block 302, and the function blocks 303 and 304, the computer system falls into an unusual state, and the computer system becomes inoperable. By inputting a reset signal to the external reset terminal 306, the CPU 301, the communication block 302, and the function blocks 303 and 304 are reset at the same time to initialize the entire system, or the CPU 301 is used for a function block in which an abnormality has occurred. Control is performed to initialize only the portion (registers and the like) that can be returned to the initial state by software and return to the normal state.
[0006]
The external reset terminal 306 is also called a hardware reset, and is used even when the power is turned on. By inputting an external reset signal to the external reset terminal 306, a hardware reset can be performed on the CPU 301 and all other functional blocks.
[0007]
As a control method when an abnormality occurs in such a computer system, there is a method using a control method of initializing only a block in which an abnormality has occurred in addition to the above method (for example, see Patent Document 1).
[0008]
[Patent Document 1]
JP-A-5-265596
[Problems to be solved by the invention]
In recent computer systems having a CPU and at least one other functional block, there is a demand for a system in which the whole system does not fall into an abnormal state due to an external influence or the like.
[0010]
In a computer system having a CPU and at least one other functional block, a conventional method uses the following method as a control method when an abnormal state occurs in a functional block other than the CPU due to an external influence or the like. Have been. Monitors the abnormal state of the computer system and, if it detects that an abnormal state has occurred, controls the functional blocks by software and resets it by software, or resets the entire computer system by hardware and resets the computer system. Means for returning the entire system to the initial state or individually performing a software reset on the functional blocks in the abnormal state, and returning only the functional blocks to the initial state and returning.
[0011]
However, the recovery means as described above is a means that functions only when monitoring an abnormal state and detecting that an abnormal state has occurred. Therefore, if an abnormal state cannot be detected, the only means for restoring the system is to reset the entire system by hardware and return the entire system to the initial state.
[0012]
Therefore, an object of the present invention is to provide a computer system capable of ensuring the stability of the entire system in a system having a CPU and at least one other functional block.
[0013]
[Means for Solving the Problems]
A computer system according to the present invention is a system having a CPU and at least one other functional block, in which a functional operation and a functional stop can be controlled for each functional block by software control using the CPU. When stopped, a configuration for initializing the functional block is adopted.
[0014]
As a result, when the operation of each functional block is started by software control using the CPU, it is possible to perform a refresh operation of stopping and initializing only the functional block.
[0015]
Therefore, each functional block can be operated in a state where the functional block is refreshed to the initial state at the start of use. As a result, even if a certain functional block falls into a state where it cannot be put into a normal state due to external noise or the like, when the functional block is used, it is refreshed to the initial state by this refresh operation. Can be secured.
[0016]
The computer system of the present invention includes a CPU, at least one function block whose operation is controlled by the CPU to execute a specific function, a bus connecting the CPU and at least one function block, A control signal generating circuit for providing a function operation signal for operating each function block and a function stop signal for stopping each function block is provided.
[0017]
Each functional block includes a main function circuit, a control register that holds control data that specifies the operation of the main function circuit, and a control register that is provided between the control register and the main function circuit. And a register signal control circuit for selectively inputting data to the main function circuit.
[0018]
The control signal generation circuit described above receives, for example, a function operation instruction or a function stop instruction of each function block connected to the bus and output from the CPU to the bus, and responds to the function operation instruction or function stop instruction of each function block. Then, a function operation signal or a function stop signal is given to each function block.
[0019]
Further, for example, when a function stop command of each functional block is output to the bus, the CPU outputs control data defining the operation of each functional block to the bus, and the control register stores control data output from the CPU. It is configured to store.
[0020]
In addition, the register signal control circuit supplies the initial data of the control register to the main function circuit when a function stop signal is given from the control signal generation circuit, and controls when the function operation signal is given from the control signal generation circuit. The data held in the register is given to the main function circuit.
[0021]
Further, the main function circuit is stopped and initialized when a function stop signal is given from the control signal generation circuit, the initial data of the control register is set, and when the function operation signal is given from the control signal generation circuit. Operates based on the data held in the control register.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing a method for initializing and controlling operation of functional blocks by software control using a CPU in a computer system having a CPU of the present invention and at least one other functional block.
[0023]
The computer system according to the embodiment of the present invention includes a CPU 101, function blocks 120, 130, 140,... Whose operations are controlled by the CPU 101 to execute specific functions, respectively, and functional blocks 120, 130, 140,. , A function signal for operating the function blocks 120, 130, 140,... And a function stop signal for stopping the function blocks, and a bidirectional bus 105. Be composed. The CPU 101 is connected to the function block 120, the function block 130, the function block 140,... And the control signal generation circuit 106 by a bus 105.
[0024]
For example, the function block 120 includes a main function circuit 125 including a logic circuit, a control register 124 that holds control data that specifies the operation of the main function circuit 125, and a function block between the control register 124 and the main function circuit 125. And a register signal control circuit 126 for selectively inputting the data held in the control register 124 and the initial data of the control register to the main function circuit 125. Other functional blocks 130 and 140 have the same configuration.
[0025]
The control signal generation circuit 106 is connected to the bus 105 and receives the function operation command or the function stop command of each of the function blocks 120, 130, 140,... Output from the CPU 101 to the bus 105. A function operation signal or a function stop signal is given to each of the function blocks 120, 130, 140,... In response to the function operation command or the function stop command of 120, 130, 140,.
[0026]
When the CPU 101 outputs the function stop command of each of the function blocks 120, 130, 140,... To the bus 105, the CPU 101 transmits control data that defines the operation of each of the function blocks 120, 130, 140,. The control register 124 is configured to store the control data output from the CPU 101 together with the output to the bus 105.
[0027]
Further, the register signal control circuit 126 supplies the initial data of the control register to the main function circuit 125 when the function stop signal is supplied from the control signal generation circuit 106, and receives the function operation signal from the control signal generation circuit 106. Sometimes, the data held in the control register 124 is given to the main function circuit 125.
[0028]
Further, the main function circuit 125 is stopped and initialized when the function stop signal is given from the control signal generation circuit 106, the initial data of the control register is set, and the function operation signal is given from the control signal generation circuit 106. It operates on the basis of the data held in the control register 124 at the time of occurrence.
[0029]
Hereinafter, embodiments will be described more specifically.
[0030]
When the control signal generation circuit 106 receives an operation command (Enable) / stop command (Disable) for each of the function blocks 120, 130, and 140 from the CPU 101 via the bus 105, the function block 120 via a signal line of the control signal 107. , A function operation signal or a function stop signal for operation (Enable) / disable (Disable) is sent to any or some of the function blocks 130, 140,...
[0031]
The functional block 120, the functional block 130, the functional block 140,... Include a reset input terminal 121, a reset input terminal 131, a reset input terminal 141 to which a hardware reset signal 109 input from the external reset terminal 108 is supplied. .. Are provided with an operation control terminal 122, an operation control terminal 132, an operation control terminal 142,... Which can select operation (Enable) / stop (Disable) of the circuit.
[0032]
When the function block 120, the function block 130, the function block 140,... Receive a function stop signal (operation stop command) from the operation control terminal 122, the operation control terminal 132, the operation control terminal 142,. Are stopped, and the operation is started when a function operation signal (operation start command) is received.
[0033]
Taking the function block A120 as an example, the operation control terminal 120 is connected to a main function circuit 125 other than the control register 124 and a register signal control circuit 126 via a signal line of an internal operation control signal 123, and the main function circuit 125 In addition to controlling the operation (Enable) / stop (Disable), the main function circuit 125 is also initialized at the time of stop.
[0034]
At the time of stop, the control register 124 is operable, and can set and store a set value for the next operation. At this time, the internal operation control signal 123 controls the register signal control circuit 126, so that the register signal control circuit gives an initial value to the main function circuit 125. Thereby, as described above, the main function circuit 125 is initialized.
[0035]
The other functional blocks 130, 140,... Have the same configuration.
[0036]
For example, when using the function block 120, first, the CPU 101 sends an instruction to stop the function block 120 to the control signal generation circuit 106.
[0037]
When receiving the stop (Disable) command of the function block 120 from the CPU 101, the control signal generation circuit 106 sends a stop (Disable) signal to the function block A 120 as the control signal 107.
[0038]
The function block 120 that has received the stop (Disable) signal stops and initializes (refreshes) the main function circuit 125, and at the same time, the CPU 101 stores the control register 124 of the function block 120 as necessary for the operation of the function block 120. Set the appropriate setting value. At this time, the control register 124 and the main function circuit 125 are separated by the register signal control circuit 126, and the set value of the control register 124 does not affect the main function circuit 125. After completing these operations, the CPU 101 sends an operation instruction of the functional block 120 to the control signal generation circuit 106.
[0039]
The function block 120 that has received the operation (Enable) instruction operates the main function circuit 125 with the value set in the control register 124.
[0040]
By performing the above operation every time when each of the functional blocks 120, 130, 140,... Is performed, the entire computer system operates in a constantly refreshed state, and a certain functional block is in a normal state due to external noise or the like. Even if the state becomes impossible, when the functional block is used, the refresh operation is performed to the initial state. Therefore, it is possible to ensure the stability of the entire computer system.
[0041]
Further, since the operation (Enable) / stop (Disable) can be selected in each of the functional blocks 120, 130, 140,..., The functional blocks that have fallen into an abnormal state can be easily separated from the computer system, and the entire computer system can be transferred. It is possible to avoid the effects.
[0042]
Further, in each of the function blocks 120, 130, 140,..., The operation (Enable) / stop (Disable) can be selected. Therefore, when a certain function block is not used, the function block is set to the stop (Disable) state. By doing so, it is also possible to reduce the power consumption of the entire computer system.
[0043]
Hereinafter, an embodiment of the present invention will be described more specifically with reference to FIGS. FIG. 2 shows a specific configuration of the functional block 120 and the control signal generation circuit 106 as an embodiment of the present invention. The following description is an example of the embodiment, and it is easy to understand that other various application examples can be considered.
[0044]
The functional block 120 according to the embodiment includes an AND gate 127 and a logic circuit (for example, a flip-flop or the like) having another arbitrary circuit configuration, and a control signal from the operation control terminal 122 is transmitted to each of the main functional circuits 125. The signal is input to the reset terminal of the logic circuit. The register signal control circuit 126 is constituted by a selector, and selects whether to output the held value of the control register 124 or to output the initial value of the control register 124 according to the level of the internal operation control signal 123.
[0045]
Assuming that the functional block 120 is a serial communication block, at the time of serial communication, the CPU 101 first writes a serial communication block stop command “0” to the control signal generation circuit 106 via the bus 105. Then, the control signal generation circuit 106 outputs “L” as the control signal 107, and the signal is transmitted to the functional block 120 which is a serial communication block. The transmitted signal is transmitted from the operation control terminal 122 to the AND gate A127 as the internal operation control signal 123, and is input to the reset terminal of a logic circuit included in the main function circuit 125 of the serial communication block. Operation stop and initialization, that is, operation stop and initialization of the functional block 120 are performed.
[0046]
At the same time, the internal operation control signal 123 is input to the register signal control circuit 126, and the initial value of the control register 124 is input from the register signal control circuit 126 to the main function circuit 125 of the function block 120.
[0047]
When the function block 120 is stopped in the serial communication block, the CPU 101 writes transmission data / communication settings for operating the function block 120, which is a serial communication block, in the control register 124 in the function block 120. At this point, the initial value of the control register 124 is input to the main function circuit 125 of the function block 120.
[0048]
When the CPU 101 stops and initializes the function block 120 and writes an instruction to the control register 124, the control signal generation circuit 106 sends the operation of the function block (serial communication block) 120 to the control signal generation circuit 106 via the bus 105 in a manner opposite to the above. Write instruction "1". Then, the control signal generation circuit 106 outputs “H” as the control signal 107, and the signal is transmitted to the functional block (serial communication block) 120. The transmitted signal is transmitted from the operation control terminal 122 to the AND gate 127 as the internal operation control signal 123, and the reset state of the reset terminal of the logic circuit included in the main function circuit 125 of the function block 120 is released. The operation of the main function circuit 125 of 120 is performed.
[0049]
At the same time, the internal operation control signal 123 is input to the register signal control circuit 126, and the transmission data / communication settings and the like set in the control register 124 are input from the register signal control circuit 126 to the function block 120 main function circuit 125. .
[0050]
The above example describes a serial communication block, but the same applies to other functional blocks.
[0051]
The above operation is performed each time the operation of each functional block is started, and each functional block is refreshed each time, thereby preventing the entire computer system from falling into an abnormal state.
[0052]
Further, when an abnormality in the function blocks 120, 130, 140,... Has an adverse effect on the entire computer system, the above-described control signal 107 is used for the function blocks 120, 130, and 130. By keeping the blocks 140,... Always stopped, disconnection from the computer system can be performed.
[0053]
Further, even if the function block 120, the function block 130, the function block 140,... Are not used in a certain operation state even in the normal state, the function block 120, the function block 130, By keeping the functional blocks 140,... Always in a stopped state, the functional blocks 120, 130, 130,... Can be stopped, and the power consumption of the entire computer system can be reduced.
[0054]
【The invention's effect】
As described above, according to the present invention, even if a certain functional block enters an abnormal state due to an external influence, only the functional block is initialized each time the functional block is used. Can be avoided.
[0055]
Further, when an abnormal state occurs, it is possible to individually stop and initialize only the functional blocks in the abnormal state, instead of initializing the entire system. In addition, since the function blocks can be individually selected to be stopped or operated, it is easy to stop the function blocks that have fallen into an abnormal state and disconnect them from the computer system. It is also possible to stop unused functional blocks and reduce the power consumption of the entire computer system.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a computer system according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating an example of a detailed configuration of a functional block and a control signal generation circuit in FIG. 1;
FIG. 3 is a block diagram showing a configuration of a conventional computer system.
[Explanation of symbols]
101 CPU
105 Bus 106 Control signal generation circuit 107 Control signal 108 External reset terminal 109 Hardware reset signal 120 Function block 121 Reset input terminal 122 Operation control terminal 123 Internal operation control signal 124 Control register 125 Main function circuit 126 Register signal control circuit 127 AND gate 130 Function block 131 Reset input terminal 132 Operation control terminal 140 Function block 141 Reset input terminal 142 Operation control terminal 301 CPU
302 Communication block 303 Function block 304 Function block 305 Bus 306 External reset terminal

Claims (3)

A CPU, at least one function block whose operation is controlled by the CPU to execute a specific function, a bus connecting the CPU and the at least one function block, and A control signal generation circuit for providing a function operation signal for operating the block and a function stop signal for stopping the function blocks,
Each of the functional blocks includes a main function circuit, a control register that holds control data that defines the operation of the main function circuit, and data that is provided between the control register and the main function circuit and that is held in the control register. And a register signal control circuit for selectively inputting initial data of the control register to the main function circuit. The control signal generation circuit is connected to the bus and receives a function operation command or a function stop command of each of the function blocks output from the CPU to the bus, and receives a function operation command or a function stop command of the function block. 2. The computer system according to claim 1, wherein a function operation signal or a function stop signal is supplied to each of the function blocks in response to the above. The CPU, when outputting a function stop command of each of the functional blocks to the bus, outputs control data defining the operation of each of the functional blocks to the bus,
The control register stores the control data output from the CPU,
The register signal control circuit, when the function stop signal is given from the control signal generation circuit, gives the initial data of the control register to the main function circuit, and the function operation signal is given from the control signal generation circuit. When the data held in the control register is given to the main function circuit,
The main function circuit is stopped and initialized when the function stop signal is supplied from the control signal generation circuit, the initial data of the control register is set, and the function operation signal is supplied from the control signal generation circuit. 3. The computer system according to claim 2, wherein the computer system operates based on data held in the control register when the control register is operated.

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