JP2004350326A - Orthogonal frequency division multiplex modulation/demodulation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an orthogonal frequency division multiplex modulation/demodulation circuit that can multiplex and transmit signals differing in bit rates and QoSs by one FFDM channel. <P>SOLUTION: Input signals are converted into complex parallel signals by serial/parallel convertors 101, 102, and 103, respectively, and subcarriers and modulation schemes are assigned for each channel. The signals are permutated by a randomizer 104, processed by a discrete inverse Fourier transformer 105, converted into serial signals by a parallel/serial converter 106, orthogonally transformed by a transmitter 107, and then outputted from an antenna 115. The signals received by an antenna 116 are orthogonally demodulated by a receiver 108 converted into serial signals by a serial/parallel converter 109 processed by a discrete Fourier transformer 110, returned to their subcarrier order by the randomizer 104, demodulated by parallel/serial converters 112, 113, and 114, and then outputted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an orthogonal frequency division multiplex modulation / demodulation circuit, and more particularly to an orthogonal frequency division multiplex (OFDM) modulation / demodulation circuit for transmitting a plurality of different channels.

  2. Description of the Related Art In recent years, digitization of broadcasting has been promoted, and an OFDM system is to be adopted as a modulation system. The OFDM scheme is also adopted as a modulation scheme in a 5 GHz band wireless LAN (Local Area Network).

  The OFDM method is a method of dividing a transmission signal and modulating each of a very large number of subcarriers for transmission, and is characterized by high frequency use efficiency and resistance to multipath fading. This OFDM method is described in, for example, Japanese Patent Application Laid-Open No. 8-331093 (Patent Document 1).

  FIG. 10 shows a configuration example of a conventional orthogonal frequency division multiplexing modulation / demodulation circuit. The principle of the above-mentioned OFDM method will be described with reference to FIG. First, the transmission signal X is, for example, a digital high-definition broadcast signal, and includes a data signal of 20 Mbps and an overhead (signal for error correction and synchronization control) of 10.72 Mbps. That is, the total is 30.72 Mbps.

  This signal is passed through a serial / parallel converter (S / P) 101 to generate parallel data of 4 × 512 bits, which are further divided into 4 bits, thereby generating a 16-level QAM (Quadrature Amplitude Modulation) baseband signal A. I do.

  The 16-value QAM baseband signal A is complex data having a real part (Re) and an imaginary part (Im), and FIG. 11 shows correspondence between each signal point on a complex plane and an input signal in units of 4 bits.

  As a result, 512 complex AQQAM signals A having a symbol rate of 30.72 / 4/512 Msps = 15 ksps are output. When these 512 complex numbers are applied to a discrete inverse Fourier transformer (IFFT) 105, a conversion result B of 512 pairs is obtained. The result B is converted into a serial signal C by a parallel / serial converter (P / S) 106.

  The real part before the conversion is an I signal and the imaginary part is a Q signal, and is output to the transmitter (TX) 107 at a sampling rate of 15 ksps × 512 = 7.68 Msps. Transmitter 107 orthogonally modulates the I and Q baseband signals and outputs the result from antenna 115.

  FIG. 12 shows an arrangement of subcarriers in a transmission signal. As shown in FIG. 12, the interval between subcarriers is equal to the symbol rate of 15 kHz, and the number of subcarriers is 512. Therefore, the bandwidth is 15 kHz × 512 = 7.68 MHz.

  Next, the configuration of the receiving side will be described. On the receiving side, the high-frequency signal transmitted from the transmitting side is received by the antenna 116, and the receiver (RX) 108 performs quadrature demodulation to generate a baseband signal (I, Q) D. These are sampled at a rate of 7.68 Msps by a serial / parallel converter (S / P) 109 to generate a parallel signal E composed of 512 sets of I (real part) and Q (imaginary part) signals. When this is applied to a discrete Fourier transformer (FFT) 110, 512 complex numbers are obtained.

  These data F represent signal points of the corresponding subcarrier in a complex plane. The corresponding 4-bit (in the case of 16-value QAM) data is reproduced from this signal point, decoded into the original signal Y by the parallel / serial converter (P / S) 112, and output.

As described above, the bit rate to be transmitted in the OFDM scheme is very high, for example, 30.72 Mbps. These are divided into a number of subcarriers and transmitted. When the number of subcarriers is 512 and the modulation method is 16-level QAM, the symbol rate per subcarrier is only 15 ksps. The duration time per symbol is about 67 μsec, which is a value sufficiently large (corresponding to 20 km when converted) as compared with a normal multipath path difference. Therefore, the OFDM scheme has strong resistance to multipath transmission.
Japanese Patent Application Laid-Open No. 8-331093

  The currently planned OFDM systems are based on the premise that each unit is used alone, such as digital television broadcasting and high-speed wireless LAN. However, the OFDM system has a feature that it is inherently resistant to multipath transmission. It is also attractive in other mobile communications.

  Therefore, as a natural consequence, it is considered that there is a demand to use the OFDM method for mobile communication. However, since the OFDM system uses a very large number of subcarriers of several hundreds or more and realizes a very large transmission capacity as a whole, it is not allowed to exclusively use it for only one type of mobile communication. Not done.

  Therefore, it is conceivable to transmit several types of communications, for example, various communications such as digital TV, wireless LAN, the Internet, and a mobile phone, through one OFDM line. These plural types of different communication signals have different bit rates, and the required transmission quality (QoS: Quality of Service) differs depending on the type of information.

  That is, in data communication, there are various transmission speeds (for example, 28.8 kbps, 1.44 Mbps, and 10 Mbps), and the error rate is required to be 10E-6 or less. On the other hand, in voice communication such as telephone, the speed is about 13 kbps, and sufficient quality is obtained even at an error rate of about 10E-3.

  SUMMARY OF THE INVENTION It is an object of the present invention to provide an orthogonal frequency division multiplexing modulation / demodulation circuit capable of solving the above-mentioned problems and multiplexing and transmitting signals having different bit rates and QoS over one OFDM line.

  The orthogonal frequency division multiplexing modulation and demodulation circuit according to the present invention performs communication using a plurality of subcarriers, and is an orthogonal frequency division multiplexing modulation and demodulation circuit for transmitting and receiving a plurality of communication channels, wherein the plurality of subcarriers are divided into a plurality of groups. Each of the divided subcarrier groups is assigned to each of the plurality of communication channels.

  That is, the orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention multiplexes a plurality of communication channels having different bit rates and QoS (Quality of Service) with one OFDM (Orthogonal Frequency Division Multiplex) line and transmits the multiplexed communication channel. To provide a way to:

  In order to realize this, the first orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention performs communication using a plurality of subcarriers, and in the OFDM system for transmitting and receiving a plurality of communication channels, the plurality of subcarriers It is divided into a plurality of groups, and each of the subcarrier groups is assigned to each of the plurality of communication channels.

  The second orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention is characterized in that subcarrier groups are adaptively allocated to individual communication channels.

  The third orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention is characterized in that the modulation scheme applied to each subcarrier group changes according to the QoS (Quality of Service) required for the corresponding communication channel.

  The fourth orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention is characterized in that the transmitting side is provided with means for randomizing the arrangement of subcarriers on the frequency axis, and the receiving side is provided with means for returning the subcarriers to the original state.

  The fifth orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention is characterized in that, if necessary, all subcarriers are allocated to a single channel, and communication of other channels is suspended during that time.

  In the sixth orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention, the above-mentioned changing modulation scheme is BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), QAM (Quadrature Amplitude, etc.). It is characterized in that symbol points on a phase plane are changed according to QoS.

  In the seventh orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention, it is desirable that the transmission power of each subcarrier is uniform, so that the transmission power of each subcarrier is the same regardless of the modulation method. It is characterized in that the peak value of the modulation symbol is determined.

  In the eighth orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention, a specific subcarrier may be suppressed by frequency selective fading. As a means for preventing this, a process of randomizing the position of the subcarrier is performed. It is characterized by being updated for each symbol

  The ninth orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention has means for determining a randomized pattern for each symbol on the transmitting side and transmitting it to the receiving side, and means for synchronizing transmission and reception of the randomized pattern. It is characterized by.

  In the tenth orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention, a means for determining a randomized pattern for each symbol on the transmitting side and transmitting the determined pattern to the receiving side is provided. It is characterized in that a predetermined communication channel and a corresponding subcarrier are allocated.

  An eleventh orthogonal frequency division multiplexing modulation / demodulation circuit according to the present invention is characterized in that a predetermined communication channel and a corresponding subcarrier are excluded from a randomization process.

  With the above configuration and processing operation, the orthogonal frequency division multiplexing modulation / demodulation circuit of the present invention can transmit communication channels having different bit rates and QoS using one OFDM line.

As described above, according to the present invention, in the orthogonal frequency division multiplexing modulation / demodulation circuit that performs communication using a plurality of subcarriers and transmits and receives a plurality of communication channels, each subcarrier divided into a plurality of groups By allocating a carrier group to each of a plurality of communication channels, there is an effect that signals having different bit rates and QoS can be multiplexed and transmitted on one OFDM line.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an orthogonal frequency division multiplexing modulation / demodulation circuit according to one embodiment of the present invention. In FIG. 1, an orthogonal frequency division multiplexing modulation / demodulation circuit according to an embodiment of the present invention includes serial / parallel converters (S / P) 101, 102, 103, a randomizer (Randomize) 104, and a discrete inverse Fourier transformer (IFFT). ) 105, a parallel-to-serial converter (P / S) 106, a transmitting side including a transmitter (TX) 107, a receiver (RX) 108, a serial-to-parallel converter (S / P) 109, It comprises a dynamic Fourier transformer (FFT) 110, a de-randomizer (De-Randomize) 111, and a receiving side including parallel / serial converters (P / S) 112, 113, 114.

  FIG. 2 is a block diagram showing a configuration example of the serial / parallel converter 101 of FIG. 2, the serial-parallel converter 101 includes a shift register 601 and 16-level QAM (Quadrature Amplitude Modulation) generating circuits 602, 603, 604, and 605.

  FIG. 3 is a block diagram showing a configuration example of the serial / parallel converter 102 of FIG. 3, the serial-parallel converter 102 includes a shift register 701 and QPSK (Quadrature Phase Shift Keying) generating circuits 702, 703, 704, and 705.

  4 is a diagram for explaining the randomizer 104 of FIG. 1, FIG. 5 is a diagram for explaining the de-randomizer 111 of FIG. 1, and FIG. 6 shows the operation of the serial-parallel converter 101 of FIG. 7 is a time chart showing the operation of the serial / parallel converter 102 in FIG. 3, and FIG. 8 is a diagram showing symbol points on a complex plane. The operation of the orthogonal frequency division multiplexing modulation / demodulation circuit according to one embodiment of the present invention will be described with reference to FIGS.

  In the orthogonal frequency division multiplexing modulation / demodulation circuit according to one embodiment of the present invention, unlike the conventional orthogonal frequency division multiplexing modulation / demodulation circuit shown in FIG. 10, the transmitting side has a plurality of data inputs X1, X2,. The receiving side also has a plurality of corresponding data outputs Y1, Y2,..., Yn.

  The input signals X1, X2,..., Xn are converted into complex parallel signals A by serial / parallel converters 101, 102, 103, respectively. For example, the input signal X1 has a bit rate of 240 kbps. If the QoS of the input signal X1 is medium, four subcarriers are allocated, and if the modulation method is 16-level QAM, the output of the serial / parallel converter 101 is four of 15 ksps (corresponding to four subcarriers). Becomes a complex number.

  In the serial / parallel converter 101 that generates 16-value QAM, as shown in FIG. 2, data is input to a shift register 601 driven by a clock having a frequency equal to the data rate. The parallel output of the shift register 601 is a set of 4 bits each, and is input to the 16-value QAM generation circuits 602, 603, 604, and 605, respectively, and is captured by a clock (Symbol CLOCK) equal to the symbol rate.

  A symbol point on a complex plane as shown in FIG. 11 is selected according to the fetched 4-bit value, and a real part (Re) and an imaginary part (Im) are output. FIG. 6 shows a timing chart of the operation.

  When the input signal X2 has a bit rate of 120 kbps and a high QoS, four subcarriers are allocated and QPSK having a low error rate is used as a modulation scheme. In this case, the output of the serial / parallel converter 102 is also four complex numbers of 15 ksps (corresponding to four subcarriers).

  In the serial / parallel converter 102, as shown in FIG. 3, data is input to a shift register 701 driven by a clock having a frequency equal to the data rate. The parallel output of the shift register 701 is a set of two bits each, and is input to the QPSK generation circuits 702, 703, 704, and 705, respectively, and is captured by a clock (Symbol CLOCK) equal to the symbol rate.

  A symbol point on the complex plane as shown in FIG. 8 is selected according to the fetched 2-bit value, and a real part (Re) and an imaginary part (Im) are output. FIG. 7 shows a timing chart of the operation.

  Similarly, when the input signal Xn does not have such a high QoS and the bit rate is 90 kbps, if one subcarrier is allocated and the modulation method is 64-level QAM, the output of the serial / parallel converter 103 is one of 15 ksps (1 (Corresponding to one subcarrier).

  As described above, the appropriate modulation scheme and the number of subcarriers to be allocated can be determined from the bit rate and the QoS, and the symbol rate of all subcarriers can be set to the same 15 kHz.

  As described above, subcarriers and modulation schemes are allocated for each communication channel, and a total of 512 complex symbols (symbol rate 15 kbps) are obtained. In this case, if there are not enough communication channels and subcarriers are available, the carrier may be unmodulated, that is, a complex number (0 + j0).

  The order of arrangement of the 512 parallel complex data obtained in this manner is changed by the randomizer 104. This operation is performed for each symbol. In the randomizer 104, as shown in FIG. 4, the order is changed in symbol units by a control signal (for example, 8 bits). If the control signal is 8 bits, 256 kinds of replacement can be performed. In FIG. 4, X510 and X511 are directly connected to Y510 and Y511, but this assumes a control channel.

  The control channel transmits a notification of the symbol synchronization or randomize pattern to the receiving side, and the initial access is easier if the control channel is transmitted without randomization.

  The randomized 512 pieces of parallel complex data A 'are processed by the discrete inverse Fourier transformer 105 to obtain 512 sets of I and Q parallel data B. The result is converted into a serial signal C by the parallel-serial converter 106. The parallel-serial converter 106 outputs the real part before conversion as an I signal and the imaginary part as a Q signal to the transmitter 107 at a sample rate of 15 ksps × 512 = 7.68 Msps. Transmitter 107 quadrature-modulates the I and Q baseband signals and outputs the result from antenna 115.

  FIG. 12 shows an arrangement of subcarriers in a transmission signal. As shown in FIG. 12, the interval between subcarriers is equal to the symbol rate of 15 kHz, and the number of subcarriers is 512. Therefore, the bandwidth is 15 kHz × 512 = 7.68 MHz.

  Next, the operation on the receiving side will be described. On the receiving side, the high-frequency signal transmitted from the transmitting side is received by the antenna 116, and quadrature demodulation is performed by the receiver 108 to generate a baseband signal (I, Q) D. These are sampled at a rate of 7.68 Msps by the serial / parallel converter 109 to generate a parallel signal E composed of 512 sets of I (real part) and Q (imaginary part) signals. When this is applied to the discrete Fourier transformer 110, 512 complex numbers are obtained.

  These data F 'represent the signal points of the corresponding subcarrier on the complex plane. The result is applied to the de-randomizer 111 to restore the order of the subcarriers exchanged by the randomizer 104.

  In the de-randomizer 111, as shown in FIG. 5, the order is changed in units of symbols by a control signal (for example, 8 bits). If the control signal is 8 bits, 256 kinds of replacement can be performed. In FIG. 5, Y510 and Y511 are directly connected to X510 and X511, but this assumes a control channel.

  The control channel transmits a notification of the symbol synchronization or randomize pattern to the receiving side, and the initial access is easier if the control channel is transmitted without randomization.

  The de-randomized result F represents a complex plane signal point of the corresponding subcarrier. Bit data corresponding to the signal point and the modulation scheme of each subcarrier are restored, and the parallel / serial converters 112, 113, and 114 decode and output the original signals Y1, Y2,..., Yn.

  As described above, by performing the processing operation as described above, it is possible to transmit a plurality of communication channels having different bit rates and QoSs through one OFDM line.

  FIG. 9 is a block diagram showing a configuration of an orthogonal frequency division multiplexing modulation / demodulation circuit according to another embodiment of the present invention. FIG. 9 shows the configuration of an orthogonal frequency division multiplexing modulation / demodulation circuit for a single channel.

  That is, an orthogonal frequency division multiplexing modulation / demodulation circuit according to another embodiment of the present invention includes a serial / parallel converter (S / P) 101, a randomizer (Randomize) 104, a discrete inverse Fourier transformer (IFFT) 105, A transmitting side including a serial converter (P / S) 106, a transmitter (TX) 107, a receiver (RX) 108, a serial / parallel converter (S / P) 109, and a discrete Fourier transformer ( An FFT 110, a de-randomizer 111, and a receiving side including a parallel-serial converter (P / S) 112.

  In an orthogonal frequency division multiplexing modulation / demodulation circuit according to another embodiment of the present invention, the main purpose is to transmit a plurality of communication channels having different bit rates and QoS through one OFDM line. However, in some cases, only one communication channel may be preferentially passed.

  For example, when it becomes necessary to relay a digital Hi-Vision TV, it becomes necessary to assign all subcarriers to this. In such a case, it is conceivable to temporarily suspend other low-priority communication channels and use all subcarriers in one priority channel. The multiplex modulation / demodulation circuit has the above configuration.

  As described above, the present invention includes adaptively determining the assignment of the subcarriers and the determination of the modulation scheme according to the priority, the bit rate, and the QoS of the communication channel.

  Further, it is not preferable that a difference occurs in average signal power between subcarriers having different modulation schemes. The present invention includes adjusting the peak value of a symbol so that the average power of all subcarriers becomes uniform.

1 is a block diagram illustrating a configuration of an orthogonal frequency division multiplexing modulation / demodulation circuit according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a serial-parallel converter in FIG. 1. FIG. 2 is a block diagram illustrating a configuration example of a serial-parallel converter in FIG. 1. FIG. 2 is a diagram for explaining the randomizer of FIG. 1. FIG. 2 is a diagram for explaining the delandizer of FIG. 1. 3 is a time chart illustrating an operation of the serial-parallel converter in FIG. 2. 4 is a time chart illustrating an operation of the serial-parallel converter in FIG. 3. FIG. 3 is a diagram illustrating symbol points on a complex plane. FIG. 6 is a block diagram illustrating a configuration of an orthogonal frequency division multiplexing modulation / demodulation circuit according to another embodiment of the present invention. FIG. 11 is a block diagram illustrating a configuration of a conventional orthogonal frequency division multiplexing modulation / demodulation circuit. FIG. 3 is a diagram illustrating a correspondence between each signal point on a complex plane and an input signal in units of 4 bits. FIG. 3 is a diagram illustrating an arrangement of subcarriers in a transmission signal.

Explanation of reference numerals

101, 102, 103 Serial-to-parallel converter 104 Land randomizer 105 Discrete inverse Fourier transformer 106 Parallel-serial converter 107 Transmitter 108 Receiver 109 Serial-parallel converter 110 Discrete Fourier transformer 111 De-randomizer 112, 113, 114 Parallel-serial Converter 601 Shift register 602, 603, 604, 605 16-value QAM generation circuit 701 Shift register 702, 703, 704, 705 QPSK generation circuit

Claims (6)

An orthogonal frequency division multiplexing modulation / demodulation circuit that performs communication using a plurality of subcarriers and transmits and receives a plurality of communication channels,
The plurality of subcarriers are divided into a plurality of groups, so that each subcarrier group is assigned to each of the plurality of communication channels, and the modulation scheme applied to each subcarrier group is required for a corresponding communication channel. To be changed according to the QoS (Quality of Service)
A quadrature frequency division multiplexing modulation / demodulation circuit, wherein a peak value of a modulation symbol is determined so that transmission power of each subcarrier is the same regardless of the modulation scheme. An orthogonal frequency division multiplexing modulation / demodulation circuit that performs communication using a plurality of subcarriers and transmits and receives a plurality of communication channels,
Each of the plurality of subcarriers is divided into a plurality of groups to allocate each subcarrier group to each of the plurality of communication channels,
The transmission side includes means for randomizing the arrangement of the subcarriers on the frequency axis,
The receiving side includes means for restoring a signal in which the arrangement is randomized,
The orthogonal frequency division multiplexing modulation / demodulation circuit, wherein the process of randomizing the position of the subcarrier is updated for each symbol.   3. The orthogonal system according to claim 2, wherein the transmitting side includes means for determining a randomized pattern for each symbol and transmitting the determined randomized pattern to the receiving side, and includes means for synchronizing transmission and reception of the randomized pattern. Frequency division multiplex modulation / demodulation circuit.   4. The orthogonal frequency division multiplexing modulation / demodulation circuit according to claim 3, wherein a predetermined communication channel and a corresponding subcarrier are allocated as means for synchronizing transmission and reception of the randomized pattern.   5. The orthogonal frequency division multiplexing modulation / demodulation circuit according to claim 4, wherein the predetermined communication channel and its corresponding subcarrier are excluded from the randomization process.   The method according to any one of claims 1 to 5, wherein the allocation of the subcarrier groups to the individual communication channels is performed adaptively according to at least a bit rate and a QoS (Quality of Service) of the communication channel. 4. The orthogonal frequency division multiplexing modulation / demodulation circuit according to 1.

Images