JP2004349312A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide memory cells which are markedly reduced in cell area and enable information stored in them to be read out well. <P>SOLUTION: When information held by transistors is read out, a series of operations carried out to read out information for second bit lines connected to the transistors holding information to be read out is identical to the ones carried out for first bit lines other than the first bit lines connected to the transistors holding information to be read out. Therefore, the memory cells holding information to be read out are hardly affected by signals transmitted from the other memory cells or hardly affect the other bit lines, and information stored in the memory cells is accurately read out. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor storage device and a semiconductor integrated circuit including the semiconductor storage device.
[0002]
[Prior art]
FIG. 11 is a schematic plan view of a conventional memory cell, FIG. 12 is a cross-sectional view taken along line AA ′ of the schematic plan view, and FIG. 13 is a circuit diagram of a memory cell array. The memory cell in FIG. 11 is, for example, a flash memory. A gate oxide film 202 is provided on a semiconductor substrate 201, and further has a floating gate 203 serving as a charge retaining film thereon. 204 is an insulating film, 205 is a control gate. 206 is a source region, and 207 is a drain region. 208 is an interlayer insulating film, 209 is a bit line contact, and 210 is a metal wiring serving as a bit line. The threshold voltage of the field effect transistor viewed from the control gate 205 changes depending on the presence or absence of the electric charge in the floating gate 203, and data is read. The operation principle will be described with reference to the cell array diagram of FIG. , Bn are bit lines serving as data lines, which are connected to, for example, the drain region 207 in FIG. 12 of each memory cell, and are the metal wiring 210 in FIG. .., Wm are the word lines and the control gate 205 in FIG. 12, and one memory cell M11 is constituted by a pair of B1 and W1, and in this case, a total of (m × n) Memory cells exist. SL is a source line, which is connected to a source region of each memory cell.
[0003]
[Patent Document 1] JP-A-3-219496
[0004]
[Problems to be solved by the invention]
However, the actual processing dimensions in the present structure also need to consider the processing dimensions of the contacts, and therefore the actual pitch between word lines is 2F or more, which causes an increase in cell area. As described above, in actuality, when the pitch between the contacts or the metal is taken into consideration, the cell area becomes larger than that in the case where the theory is considered. Further, unselected cells M21,..., Mm1 are connected to the bit line B1 of the selected memory cell M11. In each of the unselected cells, the bit line B1 is set to the high level. The source line SL goes low, and the influence of the signal due to the OFF current flowing between the source and drain affects the selected cell. In particular, when the ON / OFF ratio is about three digits, and when m = 1000, the signal read from M11 is affected by the signal from M21,. .
[0005]
[Means for Solving the Problems]
The present invention has been made in view of the above problems, and has as its object to provide a memory cell capable of significantly reducing the cell area and performing good reading.
[0006]
A semiconductor memory device according to a first aspect of the present invention is a semiconductor memory device in which a plurality of transistors having a memory function are arranged on a semiconductor substrate, wherein an element isolation extending in a first direction is provided on a surface of a semiconductor substrate of a first conductivity type. Regions are formed side by side, and active regions extending in a second direction crossing the first direction are defined between adjacent element isolation regions, and a first diffusion region is formed in each of the active regions. A region and a second diffusion region are alternately formed, a channel region is defined between each of the adjacent first diffusion region and the second diffusion region, and a channel region is formed on the semiconductor substrate in the second direction. A plurality of extending word lines are provided so as to pass over a channel region in each of the active regions, and a plurality of first bit lines extending in the first direction on the semiconductor substrate correspond to respective lower portions. First diffusion A plurality of second bit lines extending in the second direction are provided on the semiconductor substrate so as to pass over the second diffusion region, and each of the second bit lines corresponds to the second diffusion region. In a semiconductor memory device connected to a region, when a read operation of a select transistor among the plurality of transistors is to be performed, a second bit line connected to the select transistor is connected to the select transistor. It is characterized in that the same voltage value is applied to a first bit line other than the connected first bit line.
[0007]
According to the above configuration, a memory cell to be read can accurately read retained information without being affected by a signal from another memory cell or affecting other bit lines. Become.
[0008]
Further, the semiconductor memory device of the second invention is
In a semiconductor memory device in which a plurality of transistors having a memory function are arranged on a semiconductor substrate,
Element isolation regions extending in a first direction are formed side by side on a surface of a semiconductor substrate of a first conductivity type, and between adjacent element isolation regions in a second direction intersecting the first direction. An extended active area is defined,
In each of the active regions, first diffusion regions and second diffusion regions are alternately formed,
A channel region is defined between the adjacent first diffusion region and second diffusion region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate so as to pass over a channel region in each of the active regions.
On the semiconductor substrate, a plurality of first bit lines extending in the first direction are respectively connected to first diffusion regions corresponding below, and
A plurality of second bit lines extending in the second direction are provided on the semiconductor substrate so as to pass over the second diffusion region, and are connected to the corresponding second diffusion regions, respectively.
The plurality of second bit lines extending in the second direction are each formed so as to be buried between two word lines.
[0009]
According to the above configuration, since the bit lines are embedded between the word lines, the substantial minimum processing size is determined by the distance between the word lines, and the cell area can be reduced.
[0010]
In one embodiment, the second bit line embedded between the word lines is made of polycrystalline silicon.
[0011]
In the above embodiment, a bit line can be easily formed by CVD used in a normal silicon process.
[0012]
In one embodiment, the second bit line embedded between the word lines has a stacked structure in which polycrystalline silicon and a high melting point metal are provided on the polycrystalline silicon.
[0013]
In the above embodiment, the resistance can be reduced by easily forming the bit line by the silicon process and providing the high melting point metal.
[0014]
In one embodiment, the second bit lines embedded between the word lines are made of tungsten silicide.
[0015]
In the above-described embodiment, a bit line can be easily formed with a low resistance by a normal silicon process, and a good memory cell can be provided.
[0016]
In one embodiment, the transistor having the memory function stores two bits of information with one transistor.
[0017]
In the above embodiment, the cell area per bit can be halved, so that the cell area can be further reduced.
[0018]
In one embodiment, a memory function body is formed on both sides of the word line, and a part or the whole of the memory function body formed on both sides of the word line on the active region has a memory function. It is characterized by. In the above embodiment, the thickness of the gate insulating film can be reduced, and the injected charges do not interfere with each other. Therefore, the element can be easily miniaturized and high integration can be achieved.
[0019]
In one embodiment, the memory function body having the memory function is formed of an insulating film including a silicon nitride film.
[0020]
In the above embodiment, the semiconductor device can be formed by using LPCVD in a silicon process, so that the cell array can be more easily integrated.
[0021]
In one embodiment, the plurality of first bit lines are made of polycrystalline silicon.
[0022]
In the above embodiment, since the first bit line is not made of metal but polycrystalline silicon which is a conductive film, the wiring pitch can be narrowed using a normal silicon process. Since the size can be reduced, a highly integrated memory cell can be provided.
[0023]
In one embodiment, the plurality of first bit lines are formed of a multilayer film of polycrystalline silicon and a refractory metal.
[0024]
In the above embodiment, by providing the high melting point metal on the polycrystalline silicon, it is possible to reduce the resistance of the wiring while keeping the wiring pitch narrow, and it is possible to provide a more highly integrated and favorable memory cell.
[0025]
In one embodiment, the plurality of first bit lines are made of tungsten silicide.
[0026]
In the above embodiment, since the first bit line is formed of tungsten silicide, the wiring pitch can be further narrowed by a normal silicon process, so that the chip area can be further reduced, and high integration can be achieved. Good memory cells can be provided.
[0027]
According to the semiconductor integrated circuit using the semiconductor storage device, further higher integration of the semiconductor integrated circuit can be achieved.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
(Detailed description of one example of a memory element used in the memory cell array of the present invention)
The memory element constituting the semiconductor memory device of the present invention is mainly arranged across a first conductivity type region which is a diffusion region, a second conductivity type region, and a boundary between the first and second conductivity type regions. Or a gate electrode formed on a gate insulating film, a gate electrode formed on the gate insulating film, and both sides of the gate electrode. Memory function body, a source / drain region (diffusion region) disposed on the opposite side of the memory function body from the gate electrode, and a channel region disposed below the gate electrode.
[0029]
This memory element functions as a memory element for storing quaternary or more information by storing binary or more information in one charge holding film, and also has a variable resistance effect by a memory function body. , Also functions as a memory cell having both functions of a selection transistor and a memory transistor. However, this memory element does not necessarily need to store and function quaternary information or more, and may function by storing binary information, for example.
[0030]
The semiconductor device of the present invention is preferably formed on a semiconductor substrate, preferably on a first conductivity type well region formed in the semiconductor substrate.
[0031]
The semiconductor substrate is not particularly limited as long as it is used for a semiconductor device. For example, a bulk substrate made of an element semiconductor such as silicon and germanium, a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe, and GaN. Is mentioned. In addition, as a substrate having a semiconductor layer on its surface, various substrates such as an SOI (Silicon on Insulator) substrate or a multilayer SOI substrate, or a substrate having a semiconductor layer over a glass or plastic substrate may be used. Among them, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor substrate or the semiconductor layer may have a small amount of current flowing therein, but may be single crystal (for example, by epitaxial growth), polycrystalline, or amorphous.
[0032]
An element isolation region is preferably formed on the semiconductor substrate or the semiconductor layer, and elements such as a transistor, a capacitor, and a resistor, a circuit including the elements, a semiconductor device, and an interlayer insulating film are combined to form a single or multiple element. It may be formed in a layer structure. The element isolation region can be formed by various element isolation films such as a LOCOS film, a trench oxide film, and an STI film. The semiconductor substrate may have a P-type or N-type conductivity type, and the semiconductor substrate preferably has at least one well region of a first conductivity type (P-type or N-type). . The impurity concentration of the semiconductor substrate and the well region can be in a range known in the art. Note that when an SOI substrate is used as the semiconductor substrate, a well region may be formed in the surface semiconductor layer, or a body region may be provided below the channel region.
[0033]
The gate insulating film or the insulating film is not particularly limited as long as it is usually used for a semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film; an aluminum oxide film, a titanium oxide film, A single-layer film or a stacked film of a high dielectric film such as a tantalum oxide film or a hafnium oxide film can be used. Among them, a silicon oxide film is preferable. The thickness of the gate insulating film is, for example, about 1 to 20 nm, preferably about 1 to 6 nm. The gate insulating film may be formed only immediately below the gate electrode, or may be formed larger (wider) than the gate electrode.
[0034]
The gate electrode or the electrode is formed on the gate insulating film in a shape usually used for a semiconductor device or a shape having a concave portion at a lower end. Note that a single gate electrode means a gate electrode which is formed as an integral shape without being separated by a single-layer or multilayer conductive film. Further, the gate electrode may have a sidewall insulating film on a sidewall. The gate electrode is not particularly limited as long as it is generally used for a semiconductor device, and a conductive film, for example, a metal such as polysilicon: copper and aluminum: a high melting point metal such as tungsten, titanium, and tantalum: A single-layer film or a laminated film of silicide or the like with a high melting point metal may be used. The gate electrode is preferably formed to have a thickness of, for example, about 50 to 400 nm. Note that a channel region is formed below the gate electrode.
[0035]
The memory function body is configured to include at least a film or a region having a function of retaining charges, having a function of storing and retaining charges, trapping charges, or retaining a charge polarization state. Silicon nitride; silicon; silicate glass containing impurities such as phosphorus and boron; silicon carbide; alumina; high dielectric substances such as hafnium oxide, zirconium oxide, and tantalum oxide; zinc oxide; Body; metal and the like. The memory function body includes, for example, an insulator film including a silicon nitride film; an insulator film including a conductive film or a semiconductor layer therein; an insulator film including one or more conductors or semiconductor dots; It can be formed by a single layer or a laminated structure such as an insulating film including a ferroelectric film in which the state is maintained. Above all, the silicon nitride film has a large hysteresis characteristic due to the presence of many levels for trapping electric charges, and has a long charge retention time and does not cause a problem of charge leakage due to generation of a leak path. Is preferable, and is a material used as a standard in the LSI process.
[0036]
By using an insulating film including an insulating film having a charge holding function, such as a silicon nitride film, as a memory function body, reliability regarding storage and holding can be improved. This is because, since the silicon nitride film is an insulator, even if a charge leaks to a part of the silicon nitride film, the charge of the entire silicon nitride film is not immediately lost. Furthermore, when a plurality of memory elements are arranged, even if the distance between the memory elements is reduced and the adjacent memory function bodies come into contact with each other, the memory function bodies are stored in the respective memory function bodies as in the case where the memory function bodies are made of a conductor. No lost information is lost. Further, the contact plug can be arranged closer to the memory function body, and in some cases, can be arranged so as to overlap with the memory function body, which facilitates miniaturization of the memory element.
[0037]
In order to further increase the reliability of memory retention, the insulating film having a function of retaining charges does not necessarily have to be in the form of a film, and insulators having a function of retaining charges are discretely present in the insulating film. Is preferred. Specifically, it is preferable that the material is dispersed in a dot shape in a material that does not easily retain charge, for example, silicon oxide.
[0038]
In addition, by using an insulator film including a conductive film or a semiconductor layer therein as a memory function body, the amount of charge injected into the conductor or the semiconductor can be freely controlled;
[0039]
Further, by using an insulator film containing one or more conductors or semiconductor dots as a memory function body, writing and erasing by direct tunneling of electric charges can be easily performed, which has an effect of reducing power consumption.
[0040]
Further, a ferroelectric film such as PZT or PLZT whose polarization direction changes by an electric field may be used as the memory function body. In this case, electric charges are substantially generated on the surface of the ferroelectric film due to the polarization, and are maintained in that state. Therefore, a hysteresis characteristic similar to that of a film that is supplied with electric charge from outside the film having a memory function and traps electric charge can be obtained, and the charge retention of the ferroelectric film does not require charge injection from outside the film. Since the hysteresis characteristic can be obtained only by the polarization of the electric charge in the film, there is an effect that writing / erasing can be performed at high speed.
[0041]
That is, it is preferable that the memory function body further include a region that makes it difficult for the charge to escape or a film that has a function of making the charge hard to escape. As a material that functions to make it difficult for electric charge to escape, a silicon oxide film or the like can be given.
[0042]
The charge retaining film included in the memory function body is formed directly or on both sides of the gate electrode via an insulating film, and also directly on the semiconductor substrate (well region, body region, or via the gate insulating film or the insulating film). (Source / drain region or diffusion region). The charge retention films on both sides of the gate electrode are preferably formed so as to cover all or a part of the side wall of the gate electrode directly or via an insulating film. As an application example, when the gate electrode has a concave portion at the lower end, the gate electrode may be formed so as to completely or partially fill the concave portion directly or via an insulating film.
[0043]
The gate electrode is preferably formed only on the side wall of the memory function body, or does not cover the upper part of the memory function body. With such an arrangement, the contact plug can be arranged closer to the gate electrode, so that miniaturization of the memory element is facilitated. Further, a memory element having such a simple arrangement is easy to manufacture and can improve the yield.
[0044]
In the case where a conductive film is used as the charge holding film, the charge holding film is provided with an insulating film interposed therebetween so as not to directly contact the semiconductor substrate (the well region, the body region, the source / drain region, or the diffusion region) or the gate electrode. Is preferred. For example, a stacked structure of a conductive film and an insulating film, a structure in which a conductive film is dispersed in a dot shape or the like in an insulating film, a structure in which a part is arranged in a side wall insulating film formed on a side wall of a gate, and the like are given. .
[0045]
The source / drain regions are arranged on the opposite side of the charge holding film from the gate electrode as diffusion regions of a conductivity type opposite to that of the semiconductor substrate or the well region. The junction between the source / drain region and the semiconductor substrate or the well region preferably has a steep impurity concentration. This is because hot electrons and hot holes are efficiently generated at a low voltage, and a high-speed operation can be performed at a lower voltage. The junction depth of the source / drain regions is not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. Note that in the case where an SOI substrate is used as the semiconductor substrate, the source / drain regions may have a junction depth smaller than the thickness of the surface semiconductor layer; It is preferable to have the following junction depth.
[0046]
The source / drain region may be arranged so as to overlap with the gate electrode end, may be arranged so as to coincide with the gate electrode end, or may be arranged offset from the gate electrode end. You may. In particular, in the case of offset, when a voltage is applied to the gate electrode, the easiness of inversion of the offset region below the charge retaining film greatly changes depending on the amount of charge accumulated in the memory function body, and the memory effect is reduced. It is preferred because it increases and brings about a reduction in the short channel effect. However, if the offset is too much, the drive current between the source and the drain becomes extremely small. Therefore, the offset amount is larger than the thickness of the charge holding film in the direction parallel to the gate length direction, that is, one gate electrode end in the gate length direction. It is preferable that the distance from the nearer source / drain region is shorter. What is particularly important is that at least a part of the charge storage region in the memory function body overlaps with a part of the source / drain region which is a diffusion region. The essence of the memory element constituting the semiconductor memory device of the present invention is that the memory is rewritten by the electric field crossing the memory function body due to the voltage difference between the gate electrode and the source / drain region existing only on the side wall of the memory function body. That's why.
[0047]
The source / drain region may partially extend to a position higher than the surface of the channel region, that is, the lower surface of the gate insulating film. In this case, it is appropriate that a conductive film integrated with the source / drain region is laminated on the source / drain region formed in the semiconductor substrate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-mentioned metals, and high-melting point metals. Among them, polysilicon is preferable. This is because polysilicon has a much higher impurity diffusion rate than a semiconductor substrate, so that it is easy to reduce the junction depth of the source / drain regions in the semiconductor substrate, and it is easy to suppress the short channel effect. . In this case, it is preferable that a part of the source / drain region is disposed so as to sandwich at least a part of the memory function body together with the gate electrode.
[0048]
The memory element of the present invention can be formed by a normal semiconductor process, for example, by a method similar to the method of forming a single-layer or stacked-layer sidewall spacer on the side wall of a gate electrode.
[0049]
Specifically, after forming a gate electrode or an electrode, a single layer including a charge holding film such as a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, and an insulating film / charge holding film / insulating film. A method of forming a film or a laminated film, etching back under appropriate conditions to leave these films in the form of sidewall spacers; forming an insulating film or a charge retaining film, and etching back under appropriate conditions to form a sidewall. A method in which a charge retaining film or an insulating film is formed in the form of a spacer, and then etched back in the same manner to leave a sidewall spacer; a semiconductor substrate including a gate electrode formed of an insulating film material in which a particulate charge retaining material is dispersed A method of applying or depositing on the upper surface and etching back under appropriate conditions to leave the insulating film material in a side wall spacer shape; after forming a gate electrode, forming the single-layer film or the laminated film and forming a mask A method in which patterning and the like using. Before forming a gate electrode or an electrode, a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, an insulating film / charge holding film / insulating film, and the like are formed, and a channel region of these films is formed. An opening is formed in a region to be formed, a gate electrode material film is formed over the entire surface, and the gate electrode material film is patterned into a shape including the opening and larger than the opening.
[0050]
When a memory cell array is configured by arranging the memory elements of the present invention, the best mode of the memory element is, for example, (1) the gate electrodes of a plurality of memory elements have the function of a word line integrally; ▼ A memory function body is formed on both sides of the word line. 3) An insulator, particularly a silicon nitride film, holds electric charges in the memory function body. 4) ONO (Oxide) (Nitride Oxide) film, and the silicon nitride film has a surface substantially parallel to the surface of the gate insulating film. (5) The silicon nitride film in the memory function body is a silicon oxide film with a word line and a channel region. {Circle around (6)} The silicon nitride film and the diffusion layer in the memory function overlap each other, {circle around (7)} the silicon having a surface substantially parallel to the surface of the gate insulating film The thickness of the insulating film separating the nitride film from the channel region or the semiconductor layer is different from the thickness of the gate insulating film. (8) Writing and erasing operations of one memory element are performed by a single word line. ▼ There is no electrode (word line) having a function of assisting the writing and erasing operations on the memory function body. (10) The conductivity type opposite to the conductivity type of the diffusion region is provided immediately below the memory function body in contact with the diffusion region. Having a region with a high impurity concentration. The best mode is the case where all the above requirements are satisfied. However, it is needless to say that all the above requirements need not be satisfied.
[0051]
When a plurality of the above requirements are satisfied, a particularly preferable combination exists. For example, (3) an insulator, particularly a silicon nitride film, holds electric charges in the memory function body, and (9) an electrode (word line) having a function of assisting a write and erase operation on the memory function body. And (6) the case where the insulating film (silicon nitride film) in the memory function body and the diffusion layer overlap. If the insulator holds the electric charge in the memory function body and there is no electrode having a function of assisting the writing and erasing operations on the memory function body, the insulating film ( It has been found that only when the silicon nitride film) and the diffusion layer overlap, the writing operation is performed favorably. That is, it has been found that when the requirements (3) and (9) are satisfied, the requirement (6) must be satisfied.
[0052]
On the other hand, when the electric charge is held in the memory function body by the conductor, the writing operation can be performed even when the conductor in the memory function body and the diffusion layer do not overlap (the conductor in the memory function body). Is to assist writing by capacitive coupling with the writing electrode). In addition, when there was an electrode having a function of assisting the writing and erasing operations on the memory function body, the writing operation could be performed even when the insulating film and the diffusion layer in the memory function body did not overlap. .
[0053]
However, in the case where it is an insulator, not a conductor, that retains electric charges in the memory function body, and there is no electrode having a function of assisting the writing and erasing operations on the memory function body, A very large effect can be obtained.
[0054]
First, the bit line contact can be arranged closer to the memory function body on the side wall of the word line, or even if the distance between the memory elements is short, a plurality of memory function bodies do not interfere with each other and can hold the stored information. This facilitates miniaturization of the memory element. When the charge holding region in the memory function body is a conductor, interference occurs between the charge holding regions as the memory elements approach each other due to capacitive coupling, and storage information cannot be held.
[0055]
When the charge holding region in the memory function body is an insulator (for example, a silicon nitride film), it is not necessary to make the memory function body independent for each memory cell. For example, memory function bodies formed on both sides of one word line shared by a plurality of memory cells do not need to be separated for each memory cell, and memory function bodies formed on both sides of one word line. Can be shared by a plurality of memory cells sharing a word line. Therefore, a photo and etching process for separating the memory function body is not required, and the manufacturing process is simplified. Further, a margin for alignment of a photo and a margin for reducing the thickness of an etching film are not required, so that a margin between memory cells can be reduced.
[0056]
Therefore, as compared with the case where the charge holding region in the memory function body is a conductor (for example, a polycrystalline silicon film), even if formed at the same fine processing level, there is an effect that the memory cell occupation area can be reduced (memory If the charge holding region in the functional body is a conductor, a photo and etching step for separating the memory functional body for each memory cell is required, and a photo alignment margin and an etching film reduction margin are required.
[0057]
Furthermore, since there is no electrode having the function of assisting the writing and erasing operations on the memory function body and the element structure is simple, the number of steps is reduced, the yield is improved, and the transistors forming the logic circuit and the analog circuit are formed. Can be easily combined.
[0058]
Further, as a very important design matter, the case where the charge holding region in the memory function body is an insulator and there is no electrode having a function of assisting the writing and erasing operations on the memory function body (the above two conditions) Is very effective in reducing the cell occupation area, improving the yield by simplifying the manufacturing method, and reducing the cost.) We have found that wrapping allows writing and erasing at very low voltages. Specifically, it was confirmed that the writing and erasing operations were performed at a low voltage of 5 V or less.
[0059]
This function has a very large effect on circuit design. That is, since it is not necessary to generate a high voltage in a chip as in a flash memory, it is possible to omit a charge pumping circuit requiring an enormous occupation area or to reduce the scale. In particular, when a small-capacity memory is incorporated in a logic LSI for adjustment, the occupied area of the memory section is dominated by the occupied area of the peripheral circuit that drives the memory cell rather than the memory cell. Eliminating or reducing the scale of the booster circuit is most effective for reducing the chip size.
[0060]
From the above, it is particularly preferable to satisfy the requirements (3), (9) and (6).
<First embodiment>
FIG. 1 is a schematic plan view of a memory cell array according to a first embodiment of the present invention, and FIGS. 2 to 5 are cross-sectional views taken along lines AA ′, BB ′, CC ′, and DD ′ of the schematic plan views. 6 shows a circuit diagram of the cell array.
[0061]
In this case, the symbol of each memory cell shown in FIG. 6 corresponds to the symbol of a field effect transistor. However, since there is no appropriate symbol for the memory cell used in this embodiment, the memory function using the symbol of the field effect transistor is used. Represents a field effect transistor having
[0062]
In the present embodiment, for example, a memory cell structure as shown in FIG. 2 is shown. For example, a silicon oxide film 102 having a thickness of about 1 nm to 6 nm is formed on a semiconductor substrate 101 as a gate insulating film. Further, a gate electrode 103 made of polycrystalline silicon or a laminated film of polycrystalline silicon and a metal film is provided in a thickness of about 50 to 400 nm. Further, an oxide film 104 is provided over the gate electrode 103. A silicon oxide film 105 having a thickness of about 1 to 20 nm is provided on both sides of the gate insulating film 102 and the gate electrode 103, and a charge retaining film 106 having a thickness of about 2 to 200 nm in the form of a sidewall spacer made of a silicon nitride film is provided. Is provided. The charge holding film 106 made of the silicon nitride film and the silicon oxide film 105 constitute a memory function body. The charge holding film 106 has a function of accumulating charges, and the silicon oxide film 105 has a function of preventing dissipation of the accumulated charges.
[0063]
Source / drain regions 107, 108, 109, and 110 are provided on the semiconductor substrate 101 with the gate electrode 103 interposed therebetween.
[0064]
The end surfaces of the source / drain regions 107, 108, 109, and 110 on the side of the gate electrode 103 are separated from the gate electrode 103 and exist immediately below the charge holding film 106 made of a silicon nitride film.
[0065]
The self-aligned bit line 111 is a line formed of polycrystalline silicon on the semiconductor substrate 101 and is in contact with the source / drain regions 108 and 110. Further, a high melting point metal may be provided on polycrystalline silicon to reduce the resistance. As a forming method, for example, polycrystalline silicon can be deposited on the entire surface and buried in a desired place by using a CMP (Chemical Mechanical Polishing) method. Of course, the forming method is not limited to this method, and any manufacturing method may be used as long as a similar structure can be obtained. Further, if it is a conductive film, a film other than polycrystalline silicon may be used, and a high melting point metal such as tungsten silicide may be used. Further, a silicon oxide film 112 and a silicon nitride film 113 are provided in order to use a SAC (Self-Align-Contact) process. The interlayer insulating film 114 is made of, for example, a BPSG film (Boron-Phosphorus-Silicate-Glass), and the metal wiring 116 is made of, for example, an Al-Si alloy. In the embodiment of the present invention, when the polycrystalline silicon 111 is formed, before the tungsten plug 115 is formed, the polycrystalline silicon serving as the self-aligned bit line is also formed in the region of the tungsten plug 115. It may be removed at the time of formation or the like.
[0066]
In the memory cell of this embodiment, information is written by injecting charge into the charge holding film 106, and a change in threshold value due to the presence or absence of charge in the charge holding film 106, that is, a change in current amount is read. , As a memory. For example, in the memory cell G of FIG. 2, information is written by injecting hot electrons into the charge holding film 106 on the drain 107 side, using the source / drain region 107 as a drain and the source / drain region 108 as a source. In reading, information is read by using the source / drain region 107 as a source and the source / drain region 108 as a drain, judging the presence or absence of electric charge based on the amount of flowing current.
[0067]
Similarly, by injecting a charge into the charge holding film 106 on the side of the source / drain region 108, writing and reading of information can be performed. In this case, the source / drain regions are reversed in each of the above cases. That is, two bits can be operated with one memory cell. Of course, there is no problem even if one memory cell is used for 1-bit operation.
[0068]
In the cell array according to the present invention, as shown in FIG. 6, the first first bit line is denoted by Ba1, the first second bit line is denoted by Bb1, and the memory connected to the first bit line pair is denoted by Ba1. Is M1. In this case, in FIGS. 2 to 4, the first bit lines Ba1, Ba2,..., Ban are self-aligned bit lines 111, the second bit lines are metal wirings 116, and the word lines W1, W2,. , Wm become the gate electrodes 103.
[0069]
In this case, the first bit lines of the memory cells are composed of Ba, Ba2,... In order to connect gates between memory cells, m word lines W1 to Wm are provided so as to intersect the first bit lines Ba1, Ba2,..., Ban. The second bit line is composed of m lines Bb1, Bb2, Bb3,..., Bbm. Therefore, the cell array of FIG. 6 is configured by (mXn) memory cells.
[0070]
For reading of the memory cell, for example, the first bit line Ba1 is set to the low level and the ground state to select M1. In this case, the second bit line Bb1 is at the High level, and for example, 2 V is applied as the power supply voltage VDD. The word line of the selected cell is set to the high level, and a voltage of 2 V is applied to W1 to make the memory transistor M1 conductive. This makes it possible to read 1-bit information from M1. For example, 2V is applied to the first bit lines other than Ba1, which are at least adjacent to Ba1, to have the same potential as the second bit line Bb1. Since the second bit lines Bb2, Bb3,..., Bbm other than Bb1 have the same potential as the first bit line Ba1, in this case, they are set to a low level, for example, to a ground state. Since the word lines W2, W3,..., Wm are Low, the memory transistors of the non-selected cells connected to the first bit line Ba1 are non-conductive. Since the first bit line Ba1 and the second bit lines Bb2,..., Bbm have the same potential, no off-state current flows between the source / drain of these memory cells. That is, since the ON / OFF ratio between the selected memory cell and the non-selected memory cell connected to Ba1 can be made sufficient, the influence of the non-selected memory cell is reduced to reduce the signal of the selected cell. Can be read well.
[0071]
In this case, if the first bit lines other than Ba1 are set to Low, it is also possible to collectively read from all the memory cells connected to the word line W1.
[0072]
Further, the memory cell described in this embodiment can read two bits, and in order to read another bit, the relationship between the first bit line and the second bit line is reversed. You just need to
[0073]
In the case of erasing, the electrons held in the silicon nitride film 103 serving as the charge holding film are extracted from the closer source / drain region through the silicon oxide film 102. For example, consider a case where data is erased from memory cell M1. In this case, it is assumed that charges are drawn from the charge holding region closer to the second bit line. In this case, the first bit line Ba1 applies a forward bias of about Build-in Potential (built-in potential) to the substrate, for example, about -0.7 V to -1.0 V. A voltage of about 3 V to 5 V is applied to the second bit line Bb1. Then, a voltage of about -3 V to -5 V is applied to the word line W1 connected to M1. A first bit line other than Ba1 and at least adjacent to Ba1 is kept at the same potential as the second bit line Bb1, and a second bit line other than Bb1 is placed at the same potential as the first bit line Ba1.
[0074]
By using this method, it is possible to erase one bit at a time, random access is possible, and the product application range is expanded.
In this case, a plurality of necessary memory cells can be erased. The above-mentioned voltage is applied to the first bit line connected to the memory cell to be erased, and the second bit line similarly erased. To the above voltage. In addition, by applying the above voltage to the word line of the memory cell to be erased, the selected memory cell can be erased, and if necessary, all the memory cells can be erased collectively.
[0075]
In this case, a second bit line connected to the memory cell to be read and a first bit line other than the first bit line connected to the selected memory cell, that is, an unselected first bit line Of the same operation, it is possible to read information from a desired memory cell satisfactorily while reducing the cell area.
[0076]
Further, in the present invention, since the self-aligned polycrystalline silicon is used as the first bit line, the gate pitch can be formed at 2F as shown in a region E of FIG. In addition, since two bits of information can be read and written, the cell area per bit can be significantly reduced as compared with a conventional memory cell, and a highly integrated and excellent memory cell array can be provided.
[0077]
In this case, the selection of the bit line formed by self-alignment may be performed by providing a selection transistor.
Of course, in this case, the memory cells used are not limited to the present embodiment, and for example, a memory cell as shown in FIG. 7 may be used. In this case, a silicon nitride film 119 is provided as a charge holding film on the gate insulating film 102, and a silicon oxide film 120 is further provided thereon as an insulating film. Hot carriers are injected into the regions 121 and 122 of the silicon nitride film 119. And performs a charge holding function. In this case, the sidewall may be formed of a normal silicon oxide film 123.
Further, a conventional flash memory may be employed as a memory cell. However, in this case, since one memory cell operates one bit, the cell area per bit is twice as large as that of the memory cell described above.
[0078]
In the present embodiment, the source / drain region is formed in the semiconductor substrate. However, the source / drain region may be formed by providing a low-concentration well region in the semiconductor substrate. In this case, the conductivity type of the well region is opposite to that of the source / drain region, but the conductivity type of the semiconductor substrate does not need to be limited.
[0079]
Further, although the silicon nitride film 106 is provided on the thin silicon oxide film 105 as a sidewall film, the sidewall structure has no problem even if it is a structure other than this embodiment. For example, the influence from the self-aligned bit line 111 is reduced. Therefore, a three-layer structure in which a silicon oxide film is provided on a silicon nitride film, or a three-layer structure or more may be used.
Further, the film thickness, film type, and the like described in the present embodiment are not limited to those described above. Further, the voltage to be applied should be determined optimally according to the film thickness and application to be used, and is not limited to the above-mentioned value.
<Second embodiment>
FIG. 8 is a schematic plan view of the memory cell, FIG. 9 is a cross-sectional view taken along line AA ′ of the schematic plan view in FIG. 8, and FIG. 10 is a circuit diagram of the memory cell array in the present embodiment. In this embodiment, as shown in FIG. 9, instead of the tungsten plug 115 and the metal wiring 116 shown in FIG. 2 of the first embodiment, the wiring is formed by filling with polycrystalline silicon 124 instead of the polysilicon 124. The plurality of polycrystalline silicons are connected to a metal wiring (not shown) of Al-Si or the like via a field effect transistor for performing ON / OFF control. In this case, the metal wiring may be formed on the polycrystalline silicon wiring 125 via an interlayer insulating film, for example. Since the wiring pitch of polycrystalline silicon can be narrower than the metal wiring, the interval between the active regions 118 can be narrowed to the minimum processing size.
[0080]
The memory cell in the embodiment of the present invention forms one block by (3 × m) memory cells including three first bit lines, m second bit lines, and word lines, One end of the source / drain of the field effect transistors Tra1, Tra2, Tra3 and Trb1, Trb2, Trb3 at both ends of the first bit lines Ba1, Ba2, Ba3 of the memory cell array of this one block, respectively, in order to perform ON / OFF control. Are connected. In this case, the polysilicon wiring 125 shown in FIGS. 8 and 9 corresponds to the first bit lines Ba1, Ba2, and Ba3. In this embodiment, three bit lines are used, but there is no problem if the number is increased or decreased as necessary. The memory cell array according to the present embodiment is a field-effect transistor having a memory function. Tra1, Tra2, Tra3, Trb1, Trb2, and Trb3 are used only for performing ON / OFF control. I do not care. However, even in the case of this figure, since there is no appropriate symbol, the same symbol for the field effect transistor is used for both. The other of the source and drain of Tra1, Tra2 and Tra3 is a first metal wiring B1 which is a common metal wiring, and the other of the source and drain of Trb1, Trb2 and Trb3 is a second metal which is also a common metal wiring. It is connected to the wiring B2.
[0081]
An operation example in this case will be described assuming that M1 in the memory cell array is selected and read. The first metal wiring B1 is precharged to High, for example, and the second metal wiring B2 is fixed at Low level. For example, in this case, B1 is precharged to power supply voltage VDD, and B2 is fixed to, for example, 0V. Further, the second bit line Bb1 connected to M1 is fixed to Low, for example, at 0 V, and the other second bit lines Bb2,..., Bbm are fixed to the power supply voltage VDD, for example, at High. Since M1 is selected, VDD is applied as a High level to select the word line W1, and the other word lines W2, W3,..., Wm are not selected.
[0082]
Further, assuming that the field effect transistor Tra1 connected to the first bit line Ba1 is turned on and the threshold value of this field effect transistor is Vth, a voltage of VDD + Vth is applied to the gate of Tra1. Also, Trb1 is turned off. As a result, Ba1 is charged to VDD. The field effect transistors Tr2 and Tr3 connected to B1 are turned off, and the field effect transistors Trb2 and Trb3 connected to B2 are turned on. Thus, Ba2 and Ba3 are fixed at 0V. Subsequently, the metal wiring B1 is changed from a high state (VDD) to a floating state, and by sensing the metal wiring B1 for reading, the information of M1 can be read.
[0083]
Of course, even in this case, a two-bit operation can be performed, and in the case of performing another one-bit operation, the relationship between High and Low may be reversed. Specifically, the first metal wiring B1 is precharged to Low, and the second metal wiring B2 is fixed to High. Trab1, Trab2, and Trb3 are turned on, Trb1, Tra2, and Tra3 are turned off, and the second bit line Bb1 is fixed at the high side, Bb2,..., Bbm is fixed at the low level. Thereafter, by setting the first metal wiring B1 to a floating state and performing sensing, M1 can be read.
[0084]
Also in the present embodiment, at least the bit lines parallel to the word lines connected to the memory cells to be read out have exactly the same operation as the bit lines that intersect the words connected to the unselected memory cells. It is possible to read information from a desired memory cell satisfactorily while reducing the cell area.
[0085]
Further, in the present embodiment, by forming the wiring serving as the first bit line with polycrystalline silicon, the wiring pitch can be narrowed as compared with the case where the wiring is formed with metal wiring, so that the cell area can be reduced. . Further, by connecting a plurality of polycrystalline silicon wirings to metal wirings, the number of metal wirings can be reduced, and the chip area can be reduced even if the pitch of the metal wirings is loosened.
[0086]
Therefore, as shown in a region H in FIG. 8, the area of one memory cell can be set to 4F2, and by operating two bits with one memory cell, the cell area per bit can be increased. Is 2F ² And a significant reduction in size as compared with the conventional memory cell, and it is possible to provide an excellent memory cell array.
[0087]
Of course, in this case, the metal wiring B1 may be fixed and the metal wiring B2 may be sensed. Although a field-effect transistor is used to control ON / OFF, another device may be used as long as it can control ON / OFF satisfactorily.
Further, although a polycrystalline silicon wiring is used as the first bit line, a high melting point metal such as tungsten silicide or a wiring capable of reducing the wiring pitch may be used.
[0088]
The memory cell may be composed of only one block, or may be composed of a necessary number of blocks according to the degree of integration without any problem.
[0089]
Of course, the memory cell used may have the memory structure shown in FIG. 7 or a structure like a flash memory.
[0090]
Further, the film thickness, film type, and the like described in the present embodiment are not limited to those described above. Further, the voltage to be applied should be determined optimally according to the film thickness and application to be used, and is not limited to the above-mentioned value.
[0091]
【The invention's effect】
In the semiconductor memory device of the present invention, good read characteristics can be obtained by making the operations of the unselected first bit line and the second bit line connected to the selected memory cell the same. . Further, by embedding the second bit line between two adjacent word lines, the minimum processing size can be defined by the distance between the word lines, and the cell area can be greatly reduced. . Furthermore, since it is possible to store 2-bit information with one memory cell transistor, it is possible to further reduce the cell area per bit, and to achieve higher integration and higher performance of a memory cell array. It is now possible.
[0092]
Further, by using a high melting point metal such as polycrystalline silicon or tungsten silicide for the first bit line and controlling the memory cell with a normal field effect transistor, the wiring pitch can be narrowed as compared with the case where a normal metal wiring is used. Therefore, the pitch of the metal wiring can be reduced, and the cell area per bit of the memory cell array can be reduced to 2F. ² It became possible to make it much smaller.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a memory cell array according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line AA ′ of the schematic plan view shown in FIG.
FIG. 3 is a sectional view taken along line BB ′ of the schematic plan view shown in FIG. 1;
FIG. 4 is a sectional view taken along line CC ′ of the schematic plan view shown in FIG. 1;
FIG. 5 is a sectional view taken along line DD ′ of the schematic plan view shown in FIG. 1;
FIG. 6 is a circuit diagram of a memory cell array according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of another memory cell array according to the first embodiment of the present invention.
FIG. 8 is a schematic plan view of a memory cell array according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view taken along line AA ′ of the schematic plan view shown in FIG. 8;
FIG. 10 is a circuit diagram of a memory cell array according to a second embodiment of the present invention.
FIG. 11 is a schematic plan view of a conventional memory cell array.
12 is a cross-sectional view taken along line AA ′ of the schematic plan view shown in FIG. 11;
FIG. 13 is a circuit diagram of a conventional memory cell array.
[Explanation of symbols]
101 ... Semiconductor substrate
102, 104, 105, 112: Silicon oxide film
103 ... Gate electrode
106 ... Charge holding film
107, 108, 109, 110 ... source / drain regions
111: Self-aligned bit line
113 ... Silicon nitride film
114 ... Interlayer insulating film
115 ... Tungsten plug
116 ... Metal wiring
117: Element isolation region
118 ... active area

Claims (14)

In a semiconductor memory device in which a plurality of transistors having a memory function are arranged on a semiconductor substrate,
Element isolation regions extending in a first direction are formed side by side on a surface of a semiconductor substrate of a first conductivity type, and between adjacent element isolation regions in a second direction intersecting the first direction. An extended active area is defined,
In each of the active regions, first diffusion regions and second diffusion regions are alternately formed,
A channel region is defined between the adjacent first diffusion region and second diffusion region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate so as to pass over a channel region in each of the active regions.
On the semiconductor substrate, a plurality of first bit lines extending in the first direction are respectively connected to first diffusion regions corresponding below, and
A plurality of second bit lines extending in the second direction are provided on the semiconductor substrate so as to pass over the second diffusion region, and are connected to the corresponding second diffusion regions, respectively.
At the time of a read operation of a select transistor which is to perform a read operation among the plurality of transistors,
A second bit line connected to the selection transistor;
A semiconductor memory device, wherein the same voltage value is applied to a first bit line other than the first bit line connected to the selection transistor. In a semiconductor memory device in which a plurality of transistors having a memory function are arranged on a semiconductor substrate,
Element isolation regions extending in a first direction are formed side by side on a surface of a semiconductor substrate of a first conductivity type, and between adjacent element isolation regions in a second direction intersecting the first direction. An extended active area is defined,
In each of the active regions, first diffusion regions and second diffusion regions are alternately formed,
A channel region is defined between the adjacent first diffusion region and second diffusion region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate so as to pass over a channel region in each of the active regions.
On the semiconductor substrate, a plurality of first bit lines extending in the first direction are respectively connected to first diffusion regions corresponding below, and
A plurality of second bit lines extending in the second direction are provided on the semiconductor substrate so as to pass over the second diffusion region, and are connected to the corresponding second diffusion regions, respectively.
A semiconductor memory device, wherein a plurality of second bit lines extending in the second direction are formed so as to be embedded between two word lines, respectively. 3. The semiconductor memory device according to claim 2, wherein said second bit line embedded between said word lines is made of polycrystalline silicon. 3. The semiconductor memory device according to claim 2, wherein the second bit line embedded between the word lines has a stacked structure in which polycrystalline silicon and a high melting point metal are provided on the polycrystalline silicon. . 3. The semiconductor memory device according to claim 2, wherein the second bit line embedded between the word lines is made of tungsten silicide. 3. The semiconductor memory device according to claim 1, wherein the transistor having the memory function is a single transistor and stores 2-bit information. The memory function body is formed on both sides of the word line, and a part or the whole of the memory function body formed on both sides of the word line on the active region has a memory function, respectively. 3. The semiconductor memory device according to 2. The semiconductor memory device according to claim 7, wherein the memory function body having the memory function is formed of an insulating film including a silicon nitride film. 3. The semiconductor memory device according to claim 1, wherein an insulating film having a memory function is provided on the active region below the word line. 10. The semiconductor memory device according to claim 9, wherein said insulating film having a memory function is a silicon nitride film. 3. The semiconductor memory device according to claim 1, wherein said plurality of first bit lines are made of polycrystalline silicon. 3. The semiconductor memory device according to claim 1, wherein said plurality of first bit lines are formed of a multilayer film of polycrystalline silicon and a refractory metal. 3. The semiconductor memory device according to claim 1, wherein said plurality of first bit lines are made of tungsten silicide. A semiconductor integrated circuit using the semiconductor memory device according to claim 1.

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