JP2004343909A - Power supply circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize power-saving by improving the voltage conversion efficiency of DC/DC conversion. <P>SOLUTION: A switching signal shows a large power mode in a photographing mode requiring large power consumption, and a power-saving mode in a reproduction mode requiring small power consumption; and is inputted to a power supply circuit 62 for executing the DC/DC conversion from a CPU 40. The large power mode and the power-saving mode are switched by a switch 66B corresponding to the switching signal inputted from the CPU 40 at a control unit 66 of the power supply circuit 62. The control unit 66 supplies the power to each part of a digital camera by executing the voltage conversion while executing synchronous rectification operations by driving both of FETs 72H, 72L for controlling and FETs 78H, 78L for synchronous rectification, in each of a step-up circuit 64H and a step-down circuit 64L of a DC/DC converter 64 in the large power mode. However, it supplies the power to each part by executing the voltage conversion by driving only the FETs 72H, 72L for controlling in a state of stopping the synchronous rectification operations by turning OFF the FETs 78 for the synchronous rectification in the power-saving mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power supply circuit and an electronic device, and more particularly to a power supply circuit including a synchronous rectification chopper type DC / DC converter and an electronic device to which the power supply circuit can be applied.
[0002]
[Prior art]
Portable electronic devices such as digital cameras, notebook computers, and PDAs have become widespread. In a portable electronic device, the voltage of an on-board battery is boosted or lowered by a DC / DC converter (DC: Direct Current) to be converted into a desired voltage and supplied to each part of the electronic device.
[0003]
Some DC / DC converters adopt a chopper system that performs voltage conversion by chopper control in which an input DC voltage is intermittently switched by a switching means. This type of DC / DC converter generally includes a rectifying means such as a Schottky barrier diode, but recently, in order to save energy, an FET (Field-effect transistor) is used in parallel with the rectifying means for synchronous rectification. A so-called synchronous rectification method provided with switching means such as a chopper method and a synchronous rectification method is referred to as a synchronous rectification chopper method (see, for example, Patent Document 1).
[0004]
In the synchronous rectification method, when a forward voltage is applied to the rectification means, the switching means for synchronous rectification is turned on to form a path that bypasses the rectification means (path through the switching means for synchronous rectification), and the path is the rectification means By passing a current in the forward direction instead of, power loss in the rectifying means is prevented and power conversion efficiency is improved.
[0005]
Patent Document 2 discloses a drive output for driving each part of an electronic device and a control output used for feedback control in order to reduce power consumption during standby as well as during operation of the electrical device. In order to save power, a technique for stopping the synchronous rectification operation for driving output has been proposed.
[0006]
By the way, in a portable electronic device, for example, a digital camera requires a large amount of power during a shooting operation, but a small amount of power may be required during a playback operation for playing back and displaying a captured image. Power consumption may vary. When the power consumption is small, the power loss for turning on / off the switching means for synchronous rectification relatively increases, and the power conversion efficiency deteriorates by performing synchronous rectification.
[0007]
FIG. 10 shows a graph of voltage conversion efficiency characteristics of a general DC / DC converter. In the graph of FIG. 10, the horizontal axis represents the load current (Load Current), and the vertical axis represents the voltage conversion efficiency (Efficiency).
[0008]
From FIG. 10, the voltage conversion efficiency is higher when synchronous rectification is performed when the load current exceeds the predetermined value Ith, but when the load current is smaller than the predetermined value Ith, it is higher when the synchronous rectification is not performed. I understand.
[0009]
[Patent Document 1]
JP-A-11-220874
[Patent Document 2]
JP 2001-292573 A
[0010]
[Problems to be solved by the invention]
However, the conventional technology described in Patent Document 2 is designed to turn on the drive output in a power supply circuit that performs AC / DC conversion of a commercial power supply (AC) on the assumption that it is used for an installed electronic device such as a printer or a copier. This technique cannot be applied to a device that requires DC / DC conversion, such as a portable electronic device. In addition, the conventional technology stops all drive output during power saving, so it supports switching between operating modes that require high power and operating modes that require less power but require less power. It was not possible to increase the voltage conversion efficiency when power consumption was low.
[0011]
SUMMARY An advantage of some aspects of the invention is that it provides a power supply circuit and an electronic device that can improve the voltage conversion efficiency of DC / DC conversion and save power.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a power supply circuit according to claim 1 is provided for a chopper, and is a switching means for control that is turned on / off to boost or step down an input DC voltage, and the control Synchronous rectification chopper type DC / DC converter provided with synchronous rectification switching means that is turned ON / OFF in synchronization with the switching means for control, ON / OFF of the control switching means and the synchronous rectification switching means A power supply circuit used to supply a DC voltage to the electronic device, and the control unit receives a signal related to power consumption of the electronic device, Based on the input signal, both the switching means for control and the switching means for synchronous rectification are synchronized with each other. Switching means for switching between a first mode for ON / OFF operation and a second mode for turning ON / OFF the switching means for control and turning OFF the switching means for synchronous rectification. It is characterized by.
[0013]
According to the power supply circuit of the first aspect, the DC / DC converter is provided with the switching means for control and the switching means for synchronous rectification, and these switching means can be turned ON / OFF by the control means. Be controlled.
[0014]
In the control means, a first mode in which both the switching means for control and the switching means for synchronous rectification are turned ON / OFF by the switching means according to a signal related to the power consumption of the electronic device, and the switching for control The second mode in which only the means is turned ON / OFF and the synchronous rectification switching means is turned OFF can be switched. That is, voltage conversion by the DC / DC converter is performed with the synchronous rectification operation by the switching means for synchronous rectification being in the first mode and not in the second mode.
[0015]
By providing such switching means in the control means, it is possible to switch between the first mode and the second mode in accordance with the power consumption of the electronic device in which the power supply circuit is used. Is switched to the first mode, the operation of the switching means for synchronous rectification prevents the power loss in the rectifying means, and when the power consumption is low, the mode is switched to the second mode for synchronous rectification. By stopping the operation of the switching means, it is possible to prevent power loss by operating the switching means for synchronous rectification. As a result, the voltage conversion efficiency can be improved as compared with the prior art, and power saving during operation of the power supply circuit can be achieved.
[0016]
In the power supply circuit, as described in claim 2, the signal is input from the outside instructing selection of the first or second mode according to the magnitude of the power consumption. It is a signal, and the switching means may be switched to the mode instructed by the signal.
[0017]
Alternatively, as described in claim 3, the signal is a signal input from the outside representing a current value flowing on a power supply path to the electronic device, and the switching means is a current represented by the signal. When the value is equal to or greater than a predetermined value, the mode may be switched to the first mode, and when the value is less than the predetermined value, the mode may be switched to the second mode.
[0018]
Alternatively, as described in claim 4, the current value provided on the power supply path and flowing on the power supply path is measured, and a signal representing the measured current value is used as the power consumption of the electronic device. A current measuring means for inputting to the switching means as a related signal; the switching means switches to the first mode when the current value represented by the signal is equal to or greater than a predetermined value; When the value is less than the value, the mode may be switched to the second mode.
[0019]
Further, in the above power supply circuit, in order to prevent ripples, as described in claim 5, the control means is configured so that the control switching means is always OFF in the first mode. Preferably, the switching means for synchronous rectification is turned on during the period.
[0020]
An electronic device according to a sixth aspect includes the power supply circuit according to any one of the first to fifth aspects, wherein power is supplied through the power supply circuit.
[0021]
According to the electronic device of the sixth aspect, by using the power supply circuit described above, the voltage conversion efficiency of the DC / DC conversion can be improved as compared with the conventional one, and the power can be saved.
[0022]
In the above electric device, as described in claim 7, in the case of an operation mode in which the power consumption of the electronic device is equal to or higher than a predetermined value, the first mode, the predetermined value In the case of an operation mode that is less than, a signal for instructing the selection of the second mode is generated, and the generated signal is provided with a signal generating means for inputting the generated signal to the switching means as a signal related to power consumption of the electronic device. Also good.
[0023]
Alternatively, as described in claim 8, the current value that is provided on the power supply path from the power supply circuit and flows on the power supply path is measured, and a signal that represents the measured current value is sent to the electronic device. You may make it have the current measurement means input into the said switching means as a signal regarding power consumption.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, an external configuration of the digital camera 10 according to the present embodiment will be described with reference to FIG.
[0025]
In front of the digital camera 10, a lens 12 for forming a subject image, a strobe 14 that emits light to irradiate the subject as necessary during photographing, and a viewfinder used to determine the composition of the subject to be photographed. 16 are provided. Further, on the upper surface of the digital camera 10, a release button (so-called shutter) 18A that is pressed when performing shooting and a power switch 18B are provided.
[0026]
Note that the release button 18A of the digital camera 10 according to the present embodiment is pressed down to an intermediate position (hereinafter referred to as “half-pressed state”) and to a final pressed position beyond the intermediate position. A two-stage pressing operation of a state (hereinafter referred to as a “fully pressed state”) can be detected.
[0027]
In the digital camera 10, after the release button 18A is pressed halfway, an AE (Automatic Exposure) function is activated to set an exposure state (shutter speed, aperture state), and then AF (Auto Focus) is set. , Automatic focusing) function is performed to control focusing, and then exposure (photographing) is performed when the button is fully pressed.
[0028]
On the other hand, on the back of the digital camera 10, the eyepiece of the finder 16 described above, a liquid crystal display (hereinafter referred to as “LCD”) 20 for displaying a photographed subject image, a menu screen, and the like, and photographing are performed. And a mode changeover switch 18C that is slid to be set to any one of a photographing mode that is a mode to be performed and a reproduction mode that is a mode for reproducing the subject image on the LCD 20.
[0029]
Further, on the back of the digital camera 10, there are further provided a cross cursor button 18D and a forced light switch 18E that is pressed to set a forced light mode, which is a mode for forcibly causing the flash 14 to emit light during shooting. It has been.
[0030]
The cross cursor button 18D has a total of five arrow keys indicating four upward, downward, left, and right movement directions in the display area of the LCD 20 and a determination key positioned at the center of the four arrow keys. Consists of two keys.
[0031]
Next, the configuration of the electrical system of the digital camera 10 according to the present embodiment will be described with reference to FIG.
[0032]
The digital camera 10 includes an optical unit 30 including the lens 12 described above, a charge coupled device (hereinafter referred to as “CCD”) 32 disposed behind the optical axis of the lens 12, and an input analog. And an analog signal processing unit 34 that performs various types of analog signal processing on the signal.
[0033]
The digital camera 10 also performs an analog / digital converter (hereinafter referred to as “ADC”) 36 that converts an input analog signal into digital data, and performs various digital signal processing on the input digital data. And a digital signal processing unit 38.
[0034]
The digital signal processing unit 38 has a built-in line buffer with a predetermined capacity, and also performs control to directly store the input digital data in a predetermined area of the memory 44 described later.
[0035]
The output end of the CCD 32 is connected to the input end of the analog signal processing unit 34, the output end of the analog signal processing unit 34 is connected to the input end of the ADC 36, and the output end of the ADC 36 is connected to the input end of the digital signal processing unit 38. . Accordingly, the analog signal indicating the subject image output from the CCD 32 is subjected to predetermined analog signal processing by the analog signal processing unit 34, converted into digital image data by the ADC 36, and then input to the digital signal processing unit 38.
[0036]
On the other hand, the digital camera 10 generates a signal for displaying a subject image, a menu screen or the like on the LCD 20 and supplies the signal to the LCD 20, and a CPU (Central Processing Unit) 42 that controls the operation of the entire digital camera 10. A memory 44 for storing digital image data obtained by photographing, and a memory interface 46 for controlling access to the memory 44 are included.
[0037]
Further, the digital camera 10 includes an external memory interface 50 for enabling the portable memory card 48 to be accessed by the digital camera 10, and a compression / decompression processing circuit 52 for performing compression processing and decompression processing on the digital image data. It is configured to include.
[0038]
In the digital camera 10 of the present embodiment, a VRAM (Video RAM) is used as the memory 44 and a smart media (Smart Media (R)) is used as the memory card 48.
[0039]
The digital signal processing unit 38, the LCD interface 40, the CPU 40, the memory interface 46, the external memory interface 50, and the compression / decompression processing circuit 52 are connected to each other via a system bus BUS. Therefore, the CPU 40 controls the operation of the digital signal processing unit 38 and the compression / decompression processing circuit 52, displays various information via the LCD interface 40 to the LCD 20, the memory interface 46 to the memory 44 and the memory card 48, and the external memory interface. 50 can be accessed each.
[0040]
On the other hand, the digital camera 10 includes a timing generator 54 that mainly generates a timing signal for driving the CCD 32 and supplies the timing signal to the CCD 32, and the driving of the CCD 32 is controlled by the CPU 40 via the timing generator 54.
[0041]
Further, the digital camera 10 is provided with a motor driving unit 56, and driving of a focus adjustment motor, a zoom motor, and an aperture driving motor (not shown) provided in the optical unit 30 is also controlled by the CPU 40 via the motor driving unit 56. The
[0042]
That is, the lens 12 according to the present embodiment has a plurality of lenses, is configured as a zoom lens that can change (magnify) the focal length, and includes a lens driving mechanism (not shown). The lens drive mechanism includes the focus adjustment motor, the zoom motor, and the aperture drive motor, and these motors are each driven by a drive signal supplied from the motor drive unit 56 under the control of the CPU 40.
[0043]
Furthermore, the release button 18A, the power switch 18B, the mode changeover switch 18C, the cross cursor button 18D, and the forced light emission switch 18E (generally referred to as “operation unit 18” in the figure) are connected to the CPU 40. Can always grasp the operation state of the operation unit 18.
[0044]
In addition, the digital camera 10 includes a charging unit 58 that is interposed between the strobe 14 and the CPU 40 and charges power for causing the strobe 14 to emit light under the control of the CPU 40. Further, the strobe 14 is also connected to the CPU 40, and the light emission of the strobe 14 is controlled by the CPU 40.
[0045]
The digital camera 10 can be loaded with a battery 60 such as a battery, and includes a power supply circuit 62 for supplying electric power from the loaded battery 60 to the above-described units (hereinafter referred to as loads).
[0046]
As shown in FIG. 3, the power supply circuit 62 includes a synchronous rectification chopper type DC / DC converter 64 that converts a DC voltage (hereinafter referred to as a battery voltage) supplied from the battery 60 into a predetermined voltage, and a DC / DC converter 64. And an IC chip control unit 66 for controlling the operation. The control unit 66 corresponds to the control means of the present invention.
[0047]
In the present embodiment, the DC / DC converter 64 includes a booster circuit 64H that boosts the battery voltage and a step-down circuit 64L that steps down the battery voltage, and the power supply circuit 62 uses the battery voltage as a drive voltage to drive each part. An example will be described in which two types of voltages, a high voltage and a low voltage, can be supplied. Specifically, a DC voltage of 3.0 to 4.2 V is applied to the DC / DC converter 64 as a battery voltage, and DC voltages of 5 V and 3.3 V are output. Note that the DC / DC converter 64 may include only one of the step-up circuit 64H and the step-down circuit 64L.
[0048]
The step-up circuit 64H and the step-down circuit 64L include an inductance 70 that stores and discharges energy supplied from the battery 60, and a FET (hereinafter referred to as a control FET) 72 that serves as a chopper control switching unit that switches between storage and discharge in the inductance 70, A diode 74 as rectifying means and a capacitor 76 as smoothing means for smoothing and outputting the discharge voltage from the inductance 70 are provided.
[0049]
In FIG. 3, “H” is added to the end of the reference numeral for the member for the booster circuit 64H, and “L” is added to the end of the reference sign for the member for the step-down circuit 64L. .
[0050]
One terminal of the inductance 70H is connected to the battery 60, and the other terminal is branched and connected to the drain of the control FET 72H and the anode of the diode 74H.
[0051]
An N-channel MOS-FET is used as the control FET 72H. In the control FET 72H, the inductance 70H is connected to the drain as described above, and the source is grounded. The gate of the control FET 72H is connected to the control unit 66 so that a control voltage (step-up main signal) from the control unit is supplied.
[0052]
That is, the inductance 70H is grounded via the control FET 72H, and this ground is turned on / off by turning on / off the conduction according to the control voltage supplied to the gate of the control FET 72H. It is like that.
[0053]
A Schottky diode is used as the diode 74H. A load is connected to the cathode side of the diode 74H as an output terminal of the booster circuit 64H. One terminal of the capacitor 76 is connected to the cathode of the diode 74 (the output terminal of the booster circuit 64H), and the other terminal is grounded. That is, the capacitor 76 is connected in parallel with the load.
[0054]
That is, in the booster circuit 64H, when the control FET 72H is ON, the supply energy from the battery 60 is stored in the inductance 70H, and when the control FET 72H is OFF, the stored energy is released from the inductance 70H, thereby obtaining a high voltage. This high voltage is rectified by the diode 74H, smoothed by the capacitor 76, converted into a DC output, and supplied to a load (each part of the digital camera 10).
[0055]
Further, the booster circuit 64H includes an FET (hereinafter, synchronous rectification FET) 78H as a switching means for synchronous rectification. A P-channel MOS-FET is used as the synchronous rectification FET 78H.
[0056]
The FET 78H for synchronous rectification has its source and drain connected to the input / output terminal of the diode 74, and is connected in parallel to the diode 74H. The gate of the synchronous rectification FET 78H is connected to the control unit 66 so that a control voltage (step-up subsignal) is supplied from the control unit 66. The FET 78H for synchronous rectification is turned on / off according to the control voltage supplied to the gate, and when it is turned on, a path bypassing the diode 74H is formed, and a current flows in the forward direction of the diode instead of the diode 74H. That is, the synchronous rectification FET 78H functions as an alternative to the diode 74H when ON.
[0057]
A P-channel MOS-FET is used as the control FET 72L. The source of the control FET 72L is branched and connected to the cathode of the diode 74L and one terminal of the inductance 70L. The drain of the control FET 72L is connected to the cathode of the diode 74H, that is, the output of the booster circuit 64H. The gate of the control FET 72L is connected to the control unit 66 so that a control voltage (step-down main signal) is supplied from the control unit.
[0058]
A Schottky diode is used as the diode 74L. The anode side of the diode 74L is grounded.
[0059]
One terminal of the inductance 70L is connected to the source of the control FET 72L as described above, and each load is connected in series to the other terminal as an output terminal of the step-down circuit 64L. ing. One terminal of the capacitor 76L is connected to the other terminal of the inductance 70L (the output terminal of the step-down circuit 64L), and the other terminal is grounded. That is, the capacitor 76L is connected in parallel with the load.
[0060]
That is, in the step-down circuit 64L, the DC output of the step-up circuit 64H is supplied as an input voltage, and the control FET 72L is turned ON / OFF according to the control voltage supplied to the gate, whereby the DC of the input step-up circuit 64H is supplied. Convert the output to a square wave. As a result, the input voltage is stepped down in terms of time average. By being smoothed by the step-down chopper operation by the inductance 70 and the capacitor 76, it is converted into a DC output and supplied to each load.
[0061]
The step-down circuit 64L includes an FET (hereinafter referred to as synchronous rectification FET) 78L as a switching means for synchronous rectification. For example, an N-channel MOS-FET is used as the synchronous rectification FET 78L.
[0062]
The FET 78L for synchronous rectification is connected in parallel to the diode 74L, with the source and drain connected to the input / output terminal of the diode 74, respectively. The gate of the synchronous rectification FET 78L is connected to the control unit 66 so that the control voltage (step-down sub-signal) from the control unit 66 is supplied. The synchronous rectification FET 78L is turned ON / OFF according to the control voltage supplied to the gate, and when ON, the diode 74L is short-circuited and a current flows in the forward direction of the diode instead of the diode 74L. That is, the synchronous rectification FET 78L functions as an alternative to the diode 74L when ON.
[0063]
In this embodiment, the MOS-FET is used as the switching means (FET 72H, FET 78H, FET 72L, FET 78L). However, the present invention is not limited to this, and for example, a CMOS-FET, a bipolar transistor, etc. Can also be used.
[0064]
In this embodiment, Schottky diodes are used as the rectifying means (diodes 74H and 74L). However, the present invention is not limited to this, and any element having a rectifying action may be used.
[0065]
The control unit 66 generates a step-up main signal, a step-up sub signal, a step-down main signal, and a step-down sub signal in order to drive the FET 72H, FET 78H, FET 72L, and FET 78L of the DC / DC converter 64 ON / OFF, respectively. It has. Each signal (pulse) generated by the signal generator 66A is supplied as the gate voltage of the corresponding FET.
[0066]
The power supply circuit 62 is provided with feedback loops 80H and 80L for returning the DC outputs of the booster circuit 64H and the step-down circuit 64L to the control unit 66. In the control unit 66, the signal generation unit 66A The DC output of the circuit 64H and the DC output of the step-down circuit 64L are detected, and the respective DC outputs are feedback-controlled.
[0067]
Specifically, the control unit 66 generates a pulse having a predetermined frequency as the boost main signal and the step-down main signal. Based on the error between the DC output of the booster circuit 64H and a desired voltage (specifically, 5V), the controller 66 adjusts the duty ratio of the boosted main signal so that the error becomes substantially zero, and the step-down circuit Based on the error between the 64 L DC output and the desired voltage (specifically 3.3 V), the duty ratio of the step-down main signal is adjusted so that the error becomes substantially zero.
[0068]
The control unit 66 generates pulses synchronized with the boost main signal and the step-down main signal as the boost sub-signal and the step-down sub signal. Specifically, the control unit 66 synchronizes with the boost main signal and the step-down main signal so that the synchronous rectification FETs 78H and 78L are turned on when the control FETs 72H and 72L are OFF. A buck sub-signal is generated.
[0069]
The control unit 66 is connected to the power switch 18B, and starts driving when the user operates the power switch 18B to turn on the digital camera 10.
[0070]
Here, in the present embodiment, as shown in FIG. 3, the control unit 66 includes a switching unit 66B as the switching means of the present invention. The switching unit 66B switches whether to drive the synchronous rectification FETs 78H and 78L, that is, whether to perform the synchronous rectification operation. Specifically, in the switching unit 66B, as described above, pulse generation of the boost sub-signal and the step-down sub signal is performed, or stop (duty ratio 0%) is switched. Hereinafter, the case where the synchronous rectification operation corresponding to the first mode of the present invention is performed is referred to as “high power mode”, and the case where the synchronous rectification operation corresponding to the second mode of the present invention is not performed is referred to as “power saving mode”.
[0071]
The switching unit 66B is connected to the CPU 40, and a signal indicating the high power mode or the power saving mode is input from the CPU 40 as a switching signal. Based on this switching signal, switching unit 66B switches between the high power mode and the power saving mode (that is, switching whether or not to perform the synchronous rectification operation).
[0072]
In the present embodiment, the control unit 66 uses a microcomputer chip having a CPU, ROM, ROM, etc., and the functions of the signal generation unit 66A and the switching unit 66B are constructed by executing a program on the CPU, and software control is performed. Thus, each signal is generated as described above. The control unit 66 functions as a switching unit 66B in a circuit configuration used in a conventionally known power supply circuit including an amplifier, a comparator, a triangular wave generator, and the like for amplifying a voltage error as the signal generation unit 66A. It can also be realized by providing a switch circuit or the like.
[0073]
Next, an overall operation at the time of shooting of the digital camera 10 according to the present embodiment will be briefly described.
[0074]
When the digital camera 10 according to the present embodiment is activated by the operation of the power switch 18B and the photographing mode is selected by the mode switch 18C, the CCD 32 first performs imaging through the optical unit 30. The analog signals for R (red), G (green), and B (blue) indicating the subject image are sequentially output to the analog signal processing unit 34. The analog signal processing unit 34 performs analog signal processing such as correlated double sampling processing on the analog signal input from the CCD 32 and sequentially outputs the analog signal to the ADC 36.
[0075]
The ADC 36 converts the R, G, and B analog signals input from the analog signal processing unit 34 into 12-bit R, G, and B signals (digital image data) and sequentially outputs them to the digital signal processing unit 38. To do. The digital signal processing unit 38 accumulates digital image data sequentially input from the ADC 36 in a built-in line buffer and temporarily stores the digital image data directly in a predetermined area of the memory 44.
[0076]
The digital image data stored in a predetermined area of the memory 44 is read by the digital signal processing unit 38 under the control of the CPU 40, and the white balance is adjusted by applying a digital gain according to a predetermined physical quantity. Processing and sharpness processing are performed to generate 8-bit digital image data.
[0077]
The digital signal processing unit 38 performs YC signal processing on the generated 8-bit digital image data to generate a luminance signal Y and chroma signals Cr and Cb (hereinafter referred to as “YC signal”), and the YC signal. Are stored in an area different from the predetermined area of the memory 44.
[0078]
The LCD 20 is configured to display a moving image (through image) obtained by continuous imaging by the CCD 32 and can be used as a finder. When the LCD 20 is used as a finder, the LCD 20 is generated. The YC signals thus output are sequentially output to the LCD 20 via the LCD interface 40. As a result, a through image is displayed on the LCD 20.
[0079]
Here, when the release button 18A is half-pressed by the user, after the AE function is activated and the exposure state is set as described above, the AF function is activated and focus control is performed. Thereafter, when the release button 18A is kept fully pressed, the YC signal obtained by photographing at this time and stored in the memory 44 is converted into a predetermined compression format (this embodiment) by the compression / decompression processing circuit 52. In this case, the digital image data is recorded on the memory card 48 via the external memory interface 50 after being compressed in the JPEG format. When the release button 18A is fully pressed, the strobe 14 is also lit as necessary.
[0080]
When the playback mode is selected by the mode switch 18C, the digital image data to be played back stored in the memory card 48 as described above is read out via the external memory interface 50. The read digital image data is expanded by the compression / expansion processing circuit 52 and then displayed on the LCD 20 via the LCD interface 40.
[0081]
As described above, in the photographing mode, almost all electric systems of the digital camera 10 shown in FIG. 2 are operated, so that the power consumption is large and the load current value exceeds the predetermined value Ith shown in FIG. On the other hand, in the playback mode, the operation of the imaging system, the strobe 14, etc. is unnecessary, so that the power consumption is small and the load current value is less than the predetermined value Ith shown in FIG.
[0082]
Therefore, the CPU 40 selects a high power mode with high power consumption when the shooting mode is selected by the mode changeover switch 18C, and selects a power saving mode with low power consumption when the playback mode is selected. The switching signal shown is output to the power supply circuit 62. This switching signal may be a 1-bit signal such as H level in the high power mode and L level in the power saving mode.
[0083]
Next, the operation of the power supply circuit 62 will be described. FIG. 4 shows the operation of the power supply circuit 62 that is started in response to the user turning on the power switch 18B.
[0084]
That is, when the power switch 18B is operated so that the power switch 18B is turned on, first, in step 100, the control unit 66 causes the boost main signal (see the lower part of the graph in FIG. 5) and the buck main signal (the graph in FIG. 6). The pulse generation of the upper stage is started, and driving of the control FETs 72H and 72L is started.
[0085]
If the switching signal from the CPU 40 indicates the high power mode, the process proceeds from the next step 102 to step 104, where the control unit 66 causes the boost sub-signal (see the upper part of the graph in FIG. 5) and the buck sub-signal (FIG. 6). (See the lower part of the graph), the synchronous rectification FETs 78H and 78L are also driven. Thereafter, until the power switch 18B is turned off by the user, a negative determination is made in the next step 108, and the process returns to step 102.
[0086]
On the other hand, when the switching signal from the CPU 40 indicates the power saving mode, the process proceeds from the next step 102 to step 106, and in the control unit 66, the switching unit 66B causes the boosting sub-signal (see the upper part of the graph in FIG. 7) and stepping down. The pulse generation of the sub signal (see the lower graph of FIG. 8) is stopped, and the driving of the synchronous rectification FETs 78H and 78L is stopped. Thereafter, until the power switch 18B is turned off by the user, a negative determination is made in the next step 108, and the process returns to step 102.
[0087]
When the power switch 18B is turned off by the user, an affirmative determination is made in step 108, and the operation of the power supply circuit 62 in FIG. 4 ends. Thereby, the power supply of the digital camera 10 is turned off. At this time, although not shown in the figure, the power supply circuit 62 waits for a predetermined time required for the power OFF process in the digital camera 10 and then ends the operation.
[0088]
Hereinafter, the operation of the power supply circuit 62 will be specifically described with reference to FIGS.
[0089]
In the high power mode, as shown in FIG. 5, a pulse having a predetermined frequency (lower graph in FIG. 5) is supplied as a boost main signal from the control unit 66 to the boost circuit 64H, and the boost main signal is used as a boost sub signal. When H is at the H level, a pulse (upper graph in FIG. 5) synchronized with the boosted main signal that is always at the H level is supplied. In the booster circuit 64H, the control FET 72H is turned on when the boosted main signal is at the H level, turned off when the boosted main signal is at the L level, and the synchronous rectification FET 78H is turned on when the boosted sub signal is at the L level. OFF when level.
[0090]
Further, as shown in FIG. 6, the step-down circuit 64L is supplied with a pulse having a predetermined frequency (upper graph in FIG. 6) as a step-down main signal, and as a step-down sub signal, the step-down main signal is always at L level. A pulse (lower graph in FIG. 6) synchronized with the step-down main signal is supplied. In the step-down circuit 64L, the control FET 72L is ON when the step-down main signal is L level, and is OFF when the step-down main signal is H level, and the synchronous rectification FET 78H is ON, L when the step-up sub signal is H level. OFF when level.
[0091]
Therefore, in the high power mode, the DC / DC converter 64 performs synchronous rectification while boosting or stepping down and outputting the battery voltage by ON / OFF driving the respective control FETs 72 in the booster circuit 64H and the step-down circuit 64L. When the FET 78 is turned on, the synchronous rectification FET 78 is turned off and the diode 74 functions. However, when the control FET 72 is turned off, the synchronous rectification FET 78 is turned on, and instead of the diode 74, the synchronous rectification FET 78 is turned on. By causing the FET 78 to pass a current (synchronous rectification operation), loss in the diode 74 can be prevented.
[0092]
Here, normally, the maximum value (MAX DUTY) of the boosted main signal and the step-down main signal for turning ON / OFF the control FET 72 is set in advance to a predetermined value (for example, 80 to 90%) less than 100%. Yes. Therefore, as shown in FIGS. 5 and 6, the duty of the boost main signal and step-down main signal is adjusted by feedback control during the periods TH and TL in which the boost main signal and step-down main signal are between MAXDUTY and 100% duty. Even if it is done, it is at a level that always turns off the control FET 72.
[0093]
In the present embodiment, the control unit 66 switches the step-up subsignal and the step-down subsignal to a level at which the synchronous rectification FET 78 is turned on during the periods TH and TL. As a result, it is possible to reliably prevent both the control FET 72 and the synchronous rectification FET 78 from being turned on at the same time, thereby preventing ripples.
[0094]
On the other hand, in the power saving mode, the signal supplied from the control unit 66 to the booster circuit 64H is a pulse similar to that in the high power mode, as shown in FIG. 7, and the boost main signal (lower graph in FIG. 7). However, the boosting sub-signal (upper graph in FIG. 7) is constant at the H level. As shown in FIG. 8, the signal supplied from the control unit 66 to the step-down circuit 64L is a step-down main signal (upper graph in FIG. 8), which is the same pulse as that in the high power mode. The upper part of the graph in FIG. 8 is constant at the L level.
[0095]
Therefore, in the power saving mode, in the booster circuit 64H and the voltage down converter 64L, the control FET 72 is turned on / off in the same manner as in the high power mode to boost or step down the battery voltage and output it. The FET 78 remains OFF and no synchronous rectification operation is performed.
[0096]
As described above, in the present embodiment, the power supply circuit 62 that performs DC / DC conversion from the CPU 40 has the switching signal indicating the high power mode in the shooting mode with high power consumption and the power saving mode in the playback mode with low power consumption. Enter. In the power supply circuit 62, the switching unit 66B switches between the high power mode and the power saving mode in accordance with the switching signal input from the CPU 40, and the control unit 66 controls the DC / DC converter 64 in the high power mode. In each of the step-up circuit 64H and the step-down circuit 64B, both the control FET 72 and the synchronous rectification FET 78 are driven to perform voltage conversion while performing the synchronous rectification operation to supply power to each part of the digital camera. In the power mode, with the synchronous rectification FET 78 turned OFF and the synchronous rectification operation stopped, voltage conversion is performed to supply power to each unit.
[0097]
As a result, the power supply circuit 62 can switch whether or not to perform the synchronous rectification operation according to the power consumption. When the power consumption (load current) is large, the power conversion efficiency is increased by the synchronous rectification operation as in the conventional case. When the power consumption (load current) is small, the power conversion efficiency can be improved by stopping the synchronous rectification operation. Further, by using such a power supply circuit 62, it is possible to save power in the digital camera 10.
[0098]
In the above description, whether or not to perform the synchronous rectification operation is switched in the same manner in the booster circuit 64H and the step-down circuit 64B, but may be switched independently of each other.
[0099]
Further, in the above, based on a switching signal from the outside (specifically, the CPU 40), the switching unit 66B switches between the high power mode and the power saving mode (whether to perform the synchronous rectification operation). Although the circuit 62 has been described, the present invention is not limited to this.
[0100]
For example, as shown in FIG. 9, a current measuring unit 90 for measuring a current is provided in the power supply circuit 62 inside or outside the power supply circuit 62 to the load. The switching operation of the switching unit 66B may be performed. As the current measuring means 90, it is only necessary to measure a DC current. For example, a resistor (a resistance value is preferably small) is used. Needless to say, the switching unit 66B in this case may perform the switching operation depending on whether or not the load current exceeds the predetermined value Ith shown in FIG. The current measuring means 90 may be provided in the power supply circuit 62 or outside the power supply circuit as long as it is on the power supply path.
[0101]
However, if the current measuring unit 90 is provided, a slight voltage drop occurs in the current measuring unit 90, and there is wasteful power consumption that is not related to the operation of the digital camera 10. Therefore, it is preferable to switch whether or not to perform the synchronous rectification operation based on the switching signal from the outside as described above.
[0102]
In the above description, the example in which the present invention is applied to the digital camera 10 has been described. However, the present invention is not limited to this, and can be applied to any electronic device that requires DC / DC conversion. It is.
[0103]
【The invention's effect】
As described above, the present invention has an excellent effect that the voltage conversion efficiency of DC / DC conversion can be improved to save power.
[Brief description of the drawings]
FIG. 1 is an external view of a digital camera according to an embodiment.
FIG. 2 is a block diagram showing a configuration of an electric system of the digital camera according to the present embodiment.
FIG. 3 is a circuit diagram showing a configuration of a power supply circuit according to the present embodiment.
FIG. 4 is a flowchart showing the operation of the power supply circuit according to the present embodiment.
FIG. 5 is a graph showing signal waveform examples of a boost main signal and a boost sub signal in a high power mode in the power supply circuit according to the present embodiment.
FIG. 6 is a graph showing signal waveform examples of a step-down main signal and a step-down sub signal in the high power mode in the power supply circuit according to the present embodiment.
FIG. 7 is a graph showing signal waveform examples of a boost main signal and a boost sub signal in a power saving mode in the power supply circuit according to the present embodiment.
FIG. 8 is a graph showing signal waveform examples of a step-down main signal and a step-down sub signal in the power saving mode in the power supply circuit according to the present embodiment.
FIG. 9 is a circuit diagram showing a configuration of a power supply circuit according to another embodiment.
FIG. 10 is a graph showing voltage conversion efficiency characteristics of a general DC / DC converter.
[Explanation of symbols]
10 Digital camera
18B power switch
18C Mode switch
30 Optical unit
32 CCD
42 CPU
48 memory card
62 Power supply circuit
64 DC / DC converter
64H booster circuit
64L step-down circuit
66 Control unit
66A signal generator
66B switching part
70H, 70L Inductance
72H, 72L Control FET
74H, 74L diode
76H, 76L capacitors
78H, 78L Synchronous rectification FET
90 Current measuring means

Claims (8)

Control switching means provided for the chopper and turned on / off to boost or step down the input DC voltage, and synchronous rectification switching turned on / off in synchronization with the control switching means A synchronous rectification chopper type DC / DC converter comprising means;
Control means for controlling ON / OFF operation of the switching means for control and the switching means for synchronous rectification;
A power supply circuit used to supply a DC voltage to an electronic device,
The control means is
A signal related to the power consumption of the electronic device is input, and on the basis of the input signal, both the control switching unit and the synchronous rectification switching unit are synchronized with each other to perform an ON / OFF operation. Switching means for switching between a first mode and a second mode for turning on and off the control switching means and turning off the synchronous rectification switching means;
A power supply circuit characterized by that. The signal is a signal input from the outside instructing selection of the first or second mode according to the magnitude of the power consumption,
The switching means switches to the mode indicated by the signal;
The power supply circuit according to claim 1. The signal is a signal input from the outside representing a current value flowing on a power supply path to the electronic device,
The switching means switches to the first mode when the current value represented by the signal is equal to or greater than a predetermined value, and switches to the second mode when the current value is less than the predetermined value.
The power supply circuit according to claim 1. Current measuring means provided on a power supply path for measuring a current value flowing on the power supply path and inputting a signal representing the measured current value to the switching means as a signal relating to power consumption of the electronic device. And
The switching means switches to the first mode when the current value represented by the signal is equal to or greater than a predetermined value, and switches to the second mode when the current value is less than the predetermined value.
The power supply circuit according to claim 1. In the first mode, the control means turns on the synchronous rectification switching means in a period in which the control switching means is always turned off.
The power supply circuit according to any one of claims 1 to 4, wherein An electronic apparatus comprising the power supply circuit according to any one of claims 1 to 5, wherein power is supplied through the power supply circuit. Generates a signal instructing selection of the first mode when the power consumption of the electronic device is equal to or higher than a predetermined value, and selecting the second mode when the power mode is lower than the predetermined value. The electronic device according to claim 6, further comprising: a signal generation unit that inputs the generated signal to the switching unit as a signal related to power consumption of the electronic device. A current that is provided on a power supply path from the power supply circuit, measures a current value flowing on the power supply path, and inputs a signal representing the measured current value to the switching unit as a signal related to power consumption of the electronic device The electronic apparatus according to claim 6, further comprising a measuring unit.

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