JP2004342881A - Semiconductor memory, semiconductor device, ic card, portable electronic apparatus, and method for manufacturing semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor memory in which operating speed can be enhanced by bringing a contact and a gate electrode close to each other through a simple arrangement thereby realizing scaling-down, and to provide a semiconductor memory, a semiconductor device, an IC card and a portable electronic apparatus employing it, and a process for fabricating a semiconductor memory. <P>SOLUTION: Coating films 21 and 26 each consisting of an insulator having a function for storing charges are formed to cover the upper surface and the side face of the gate electrode 3 formed on a semiconductor substrate 1 through a gate insulating film 2. A contact 25 formed on the side of the gate electrode 3 through the coating films 21 and 26 is connected electrically with source/drain diffusion regions 13a and 13b. The coating films 21 and 26 are composed of such a material as having a selection ratio to an interlayer insulating film 23 functioning as an etching stop material at the time of etching the interlayer insulating film 23 formed above the coating films 21 and 26 at least on the gate electrode 3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０４７０】
この表１から明らかなように、本実施形態のメモリセルアレイは、ランダムアクセス（１ビット毎の読出しおよび書換え動作）が可能である。このため、一括消去しなければならないデバイスに比較し、アクセス効率を上げることが可能である。また、メモリ状態の一時記憶、一括消去、書込みといったシーケンスも不要となるため制御回路が簡単になるという効果がある。
【０４７１】
上記読出し動作時によれば、あるメモリセルの２ビットの記憶を連続して読み出そうとする場合（例えば、メモリセルＭ２２のメモリ記憶部Ｍ１，Ｍ２を連続して読み出すなど）、近傍のビット線の電位を全て反転しなければならない（上の例ではビット線ＢＬ１〜ＢＬ４の電位を全て反転する）ため、効率が悪い。そのため、後述のように、アドレスデコーダー回路などの工夫を行い、左右のメモリ記憶部（電荷保持部）のアクセスのためのアドレスを離すなどの対策を行うことにより連続して交互に読み出す状態を回避することが好ましい。
【０４７２】
メモリセルＭｉｊ（ｉ＝１，２，３、ｊ＝１，２，３）は、ゲート電極がワード線ＷＬｉ（ｉ＝１，２，３）に、ソース／ドレイン拡散領域の一方が第１のビット線ＢＬ１ｊ（ｊ＝１，２，３）に、ソース／ドレイン拡散領域の他方が第２のビット線ＢＬ２ｊ（ｊ＝１，２，３）に、それぞれ接続されている。
【０４７３】
上記メモリセルアレイの動作は、上述の半導体記憶装置の動作方法に必要な電圧を、特定のワード線および第１および第２のビット線を介して所望のメモリセルに与えればよい。例えば、メモリセルＭ１１のメモリ記憶部（電荷保持部）の一方に書込みを行う場合は、例えば、ワード線ＷＬ１に＋２Ｖを、第１のビット線ＢＬ１１に＋６Ｖを、第２のビット線ＢＬ２１に０Ｖを、それぞれ与えればよい。また、メモリセルＭ１１のメモリ記憶部（電荷保持部）の他方に書込みを行う場合は、例えば、ワード線ＷＬ１に＋２Ｖを、第１のビット線ＢＬ１１に０Ｖを、第２のビット線ＢＬ２１に＋６Ｖを、それぞれ与えればよい。このとき、他の非選択ワード線および非選択ビット線には例えば０Ｖを与えればよい。
【０４７４】
以上の説明より明らかなように、第１９の実施形態のメモリセルアレイは、上記半導体記憶装置を配列して構成されている。上述のように、上記半導体記憶装置は、１つの素子で２ビットの記憶が可能であり、ゲート絶縁膜の薄膜化が可能であるから、微細化が容易である。したがって、上記半導体記憶装置を配列して構成する本実施形態のメモリセルアレイも、微細化が容易となり、製造コストが削減される。
【０４７５】
また、上述のように、上記半導体記憶装置を形成するプロセスは、通常のＣＭＯＳプロセスに非常に近く、従来のＥＥＰＲＯＭなどフローティングゲートを有する不揮発性メモリに比べて非常に簡単に製造することが可能である。したがって、本実施形態のメモリセルアレイの製造も容易であり、さらには論理回路との混載も容易となる。
【０４７６】
【発明の効果】
以上より明らかなように、この発明の半導体記憶装置によれば、層間絶縁膜エッチングは被覆膜に対して選択比の大きいエッチング条件で行って、被覆膜でエッチングをストップすることにより、信頼性が高くかつ製造コストの低い半導体記憶装置を提供することができる。さらに、上記被覆膜により、コンタクトとゲート電極が隔離されて短絡しないので、設計マージンが小さくでき、容易に微細化できる半導体記憶装置を提供することができる。
【０４７７】
また、この発明の半導体装置によれば、メモリ効果の良好な不揮発性の半導体記憶装置と電流駆動能力の高い半導体スイッチング素子が混載することができる。
【０４７８】
また、この発明のＩＣカードによれば、信頼性が高くかつ低コストなＩＣカードを提供することができる。
【０４７９】
また、この発明の携帯電子機器によれば、信頼性が高くかつ低コストな携帯電子機器が提供することができる。
【０４８０】
また、この発明の半導体記憶装置の製造方法によれば、層間絶縁膜エッチングは、被覆膜に対して選択比の大きいエッチング条件で行って、被覆膜でエッチングをストップすることにより、信頼性が高くかつ製造コストの低い半導体記憶装置を提供することができる。
【図面の簡単な説明】
【図１】図１は本発明の第１の実施形態の半導体記憶装置の構造の概要を示す概略断面図である。
【図２】図２は上記第１の実施形態の半導体記憶装置の他の構造の概要を示す概略断面図である。
【図３】図３は本発明の第２の実施形態の半導体記憶装置を用いた半導体記憶装置の製造工程を示す概略断面図である。
【図４】図４は図３に続く上記半導体記憶装置を用いた半導体記憶装置の製造工程を示す概略断面図である。
【図５】図５は本発明の第３の実施形態の半導体記憶装置を用いた半導体記憶装置の製造工程を示す概略断面図である。
【図６】図６は本発明の第４の実施形態の半導体記憶装置を用いた半導体記憶装置の製造工程を示す概略断面図である。
【図７】図７は図６に続く上記半導体記憶装置の製造工程を示す概略断面図である。
【図８】図８は本発明の第５の実施形態の半導体記憶装置を用いた半導体記憶装置の製造工程を示す概略断面図である。
【図９】図９は図８に続く上記半導体記憶装置の製造工程を示す概略断面図である。
【図１０】図１０は本発明の第６の実施形態の半導体記憶装置を用いた半導体記憶装置の製造工程を示す概略断面図である。
【図１１】図１１は図１０に続く上記半導体記憶装置の製造工程を示す概略断面図である。
【図１２】図１２は上記半導体記憶装置の製造工程における分離されたメモリ機能体を示す概略俯瞰図である。
【図１３】図１３は本発明の第７の実施形態の半導体記憶装置のメモリ機能体の構造態様の概要を示す概略断面図である。
【図１４】図１４は本発明の第８の実施形態の半導体記憶装置の製造工程を示す概略断面図である。
【図１５】図１５は本発明の第９の実施形態の半導体記憶装置の構造の概要を示す概略断面図である。
【図１６】図１６は図１５の右側のメモリ機能体周辺部の拡大図である。
【図１７】図１７は上記半導体記憶装置のメモリ機能体のうちシリコン窒化膜のゲート電極と離れた側の端が、ゲート電極から離れた側のメモリ機能体の端と一致していない場合のメモリ機能体周辺部の拡大図である。
【図１８】図１８は上記半導体記憶装置のメモリ機能体の幅を固定してオフセット量を変化させたときのドレイン電流を示す図である。
【図１９】図１９は上記半導体記憶装置の電荷保持膜の上面がゲート絶縁膜上面から等しい距離に位置するように配置されたときのメモリ機能体周辺部の拡大図である。
【図２０】図２０は本発明の第１０の実施形態の半導体記憶装置のメモリ機能体周辺部の拡大図である。
【図２１】図２１は本発明の第１１の実施形態の半導体記憶装置の構造の概要を示す概略断面図である。
【図２２】図２２は本発明の第１２の実施形態の半導体記憶装置の概略断面図である。
【図２３】図２３は本発明の第１３の実施形態の半導体記憶装置の概略断面図である。
【図２４】図２４は本発明の第１４の実施形態の半導体記憶装置の概略断面図である。
【図２５】図２５は本発明の第１５の実施形態の半導体記憶装置の概略断面図である。
【図２６】図２６は本発明の第１６の実施形態の半導体装置の構成図である。
【図２７】図２７は上記半導体装置の製造工程を示す概略断面図である。
【図２８】図２８は図２７に続く上記半導体装置の製造工程を示す概略断面図である。
【図２９】図２９は本発明の第１７の実施形態のＩＣカードを示す概略ブロック図である。
【図３０】図３０は本発明の第１８の実施形態の携帯電子機器を示す概略ブロック図である。
【図３１】図３１（ａ）は本発明の第１９の実施形態の半導体記憶装置のメモリセルアレイの回路図であり、図３１（ｂ）はこのメモリセルアレイの概略平面図である。
【図３２】図３２（ａ）は図３１（ｂ）の切断面線Ｃ−Ｃにおける第１のメモリセルアレイの概略断面図であり、図３２（ｂ）は図３１（ｂ）の切断面線Ｃ−Ｃにおける第１のメモリセルアレイの概略断面図である。
【図３３】図３３は従来の半導体記憶装置としてのフラッシュメモリの装置の構造断面図である。
【符号の説明】
１，１０１，２０１，３０１，４０１，５０１，６０１，８０１，９１１，９８６，１１０１，１４０１…半導体基板
２，１０２，２０２，３０２，４０２，５０２，６０２，８０２，９１４，１１０２，１４０２…ゲート絶縁膜
３，１０３，２０３，３０３，４０３，５０３，６０３，８０３，９１７，１１０３，１４０３…ゲート電極
８，１０８，２０８，３０８，４０８，５０８，６０８，８０８，１１０８…ゲートスタック
１３ａ，１３ｂ，１１３ａ，１１３ｂ，２１３，３１３，４１３，５１３，６１３，８１３，９１２，９１３，１１１３，１４０７…ソース／ドレイン拡散領域
１１６，６１６，７１６，９４３…側壁絶縁体
１１７，９４２…シリコン窒化膜
１８ａ，１８ｂ，２１８ａ，２１８ｂ…電荷保持部
１９…チャネル形成領域
２０，１２０，２２０，９７１…オフセット領域
２１，１２１，２２１，３２１，４２１，５２１，６２１，８２１，１１２１…第１の被覆膜
２３，１２３，２２３，３２３，４２３，５２３，６２３，１１２３，１４４１…層間絶縁膜
２５，１２５，２２５，３２５，４２５，５２５，６２５，１１２５…コンタクト
２６，１２６，２２６，３２６，５２６，６２６，８２６，１１２６…第２の被覆膜
２７，４２７…第３の被覆膜
２８，５２８，６２８，１４０８…素子分離領域
１１１ａ，１１１ｂ，８１１，９６１，９６２，９８１…メモリ機能体
１１２，６１２，７１２…第１の絶縁体
１２２…ゲート電極下領域
２２４，５２４，１１２４…コンタクト孔
６０９…第１絶縁膜
６１７…シリコン窒化膜
６１４…材料（導体等）
６１５，７１５…ポリシリコン
６２９…第２絶縁膜
７１０…シリコンドット
９４１…シリコン酸化膜
９８７…ボディ領域
９８８…埋め込み酸化膜
９９１…Ｐ型高濃度領域
９９２…チャネル領域
１０００…半導体基板
１００１…メモリセルアレイ
１００２…周辺回路
１００３…デコーダ
１００４…Ｉ／Ｏ回路
１００５…制御回路
１００６…アナログ回路
１００７…デコーダ
１００８…読出し回路
１０１１…ＭＰＵ
１０１２…キャッシュＳＲＡＭ
１０１３…ロジック回路
１０１４…アナログ回路
１１０４…論理回路領域
１１０５…メモリ領域
１１０６…ＬＤＤ領域
１１０７…フォトレジスト
１２００Ａ，１２００Ｂ…ＩＣカード
１２０１…ＭＰＵ部
１２０２…演算部
１２０３…制御部
１２０４…データメモリ部
１２０５…ＲＯＭ
１２０６…ＲＡＭ
１２０７…配線
１２０８…コネクト部
１２０９…リーダライタ
１２１０…ＲＦインターフェース部
１２１１…アンテナ部
１３０１…ＭＰＵ部
１３０２…演算部
１３０３…制御部
１３０４…データメモリ部
１３０５…ＲＯＭ
１３０６…ＲＡＭ
１３０７…配線
１３０８…マン・マシンインターフェース部
１３１０…ＲＦ回路部
１３１１…アンテナ部
１４２１…被覆膜
１４３１…コンタクトホール
１４３２…第１層メタル配線
１４３３…ヴィアホール
１４３４…第２層メタル配線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, a semiconductor device, an IC card, a portable electronic device, and a method of manufacturing a semiconductor memory device, and particularly, can be suitably used for an electrically writable and erasable nonvolatile semiconductor device and a method of manufacturing the same. is there.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a semiconductor memory device, there is a flash memory as a memory element which can be electrically written and erased (for example, see Non-Patent Document 1). FIG. 33 shows a sectional view of the structure of the element of this flash memory. As shown in FIG. 33, the element of the flash memory has a floating gate 1506 made of polysilicon on a semiconductor substrate 1501 via a first oxide film 1504, and a second oxide film 1505 on the floating gate 1506. The semiconductor device has a structure in which a pair of source / drain diffusion regions 1502 and 1503 are arranged on the surface of a semiconductor substrate 1501. The control gate 1507 functions as a gate electrode of a field effect transistor (FET) in the flash memory. Further, a first oxide film 1504, a floating gate 1506, and a second oxide film 1505 are arranged between the control gate 1507 and the semiconductor substrate 1501. That is, in the flash memory, by arranging a memory film (floating gate) as a charge holding portion in a gate insulating film portion of the FET, the threshold voltage of the FET changes according to the amount of charge accumulated in the memory film. Memory element having the function of causing
[0003]
[Non-patent document 1]
Fujio Masuzoka, "Flash Memory Technology Handbook", Science Forum, August 15, 1993, P55-58.
[0004]
[Problems to be solved by the invention]
The flash memory having the above structure has a problem of so-called overerasing. That is, the erasing operation in the normal flash memory is to lower the threshold voltage of the FET in the flash memory by extracting electrons (or injecting holes) stored in the floating gate. When the operation is performed excessively, the FET is turned on under the influence of the electric charge held in the floating gate below the gate electrode (that is, the control gate), and a current flows between the source / drain diffusion regions. This phenomenon occurs because the control gate, which is the gate electrode of the FET, and the floating gate, which is the memory film as the memory, are stacked. It is.
[0005]
As a result, a read failure occurs such that the current of the selected memory cell cannot be extracted due to the leak current from the non-selected memory cell during the memory cell array read operation.
[0006]
In the case of the non-volatile memory of the manufacturing method described in Non-Patent Document 1, since a contact to the source / drain diffusion layer is formed, SiO 2 is used. ₂ In the step of etching the film into a contact shape, the surface of the source / drain diffusion layer is roughened, or the etching is performed deeper due to excessive etching, resulting in poor contact or the source / drain diffusion layer and the Si substrate. And short-circuiting sometimes occurred.
[0007]
In addition, when so-called diffusion layer wiring in which connection between source / drain diffusion layers of other cells is performed by extending source / drain diffusion layers is used, parasitic capacitance and resistance of wiring between cells are increased, and operation speed is increased. In practice, the contact is made every few cells with the upper wiring that runs in parallel with the diffusion layer wiring. Therefore, a contact for connecting the source / drain diffusion region and the upper layer is indispensable, and has the same problem as described above.
[0008]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a highly reliable semiconductor memory device and a semiconductor device which can prevent a read failure due to over-erase, and can improve the operation speed by miniaturizing a contact and a gate electrode by using a simple structure. An object of the present invention is to provide a method for manufacturing an IC card, a portable electronic device, and a semiconductor storage device.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor memory device according to a first aspect of the present invention
A gate electrode formed on a semiconductor substrate via a gate insulating film,
A channel formation region arranged at least in a region below the gate electrode of the semiconductor substrate,
A pair of source / drain diffusion regions disposed on both sides of the channel formation region of the semiconductor substrate and having a conductivity type opposite to that of the channel formation region;
An interlayer insulating film formed at least above the gate electrode;
A coating film formed of an insulator having a function of retaining charges formed on the sides of the interlayer insulating film, formed to cover the upper side and the side of the gate electrode;
A contact formed on the side of the gate electrode via the coating film and electrically connected to the source / drain diffusion region;
The coating film is made of a material having a selectivity to the interlayer insulating film so as to function as an etching stop material when etching the interlayer insulating film.
[0010]
According to the semiconductor memory device of the first aspect, the charge holding portion is not formed as a portion that functions as the gate insulating film of the field-effect transistor, but is formed on the side of the gate electrode. The problem of over-erasing and read failures associated therewith is eliminated.
[0011]
In addition, the gate electrode and the contact material can be separated by the above-mentioned coating film, and the coating film can be freely selected from materials different from the ordinary interlayer insulating film, so that the leakage current is reduced while improving the insulation performance. Or the parasitic capacitance can be reduced by using a low dielectric constant material. Therefore, the contact and the gate electrode can be made closer to each other, and the element can be miniaturized.
[0012]
Further, the etching of the interlayer insulating film can be stopped by the coating film. In other words, by stopping the etching with the above-mentioned coating film, it is possible to suppress a contact failure due to etching the semiconductor substrate and a short circuit between the source / drain diffusion region and the semiconductor substrate, thereby providing a highly reliable semiconductor. A storage device can be provided.
[0013]
In addition, since only the above-described coating film can have two functions of a charge holding function and a function of stopping the above-described etching, the steps can be simplified, and a semiconductor memory device with low manufacturing cost can be provided.
[0014]
In addition, since a coating film made of an insulating film is formed above and on the side of the gate electrode, there is no need to provide a large margin for misalignment when designing the contact formation position as in the related art. The area occupied by the element can be reduced, and the manufacturing cost can be reduced.
[0015]
Further, the semiconductor memory device of the second invention is
A gate electrode formed on a semiconductor substrate via a gate insulating film,
A channel formation region arranged at least in a region below the gate electrode of the semiconductor substrate,
A pair of source / drain diffusion regions disposed on both sides of the channel formation region of the semiconductor substrate and having a conductivity type opposite to that of the channel formation region;
A third coating film made of an insulator formed on the gate electrode,
A first coating film made of an insulator having a function of retaining electric charges formed at least on a side of the gate electrode and a side of the third coating film;
An interlayer insulating film formed at least above the third coating film;
A contact formed on the side of the gate electrode via the first coating film and electrically connected to the source / drain diffusion region;
The first coating film is made of a material having a selectivity to the interlayer insulating film so as to function as an etching stop material at the time of etching the interlayer insulating film.
[0016]
According to the semiconductor memory device of the second aspect of the invention, the charge holding portion is not a portion that functions as a gate insulating film of a field effect transistor, but the charge holding portion is formed on the side of the gate electrode. The problem of over-erasure and read failures related thereto is eliminated.
[0017]
In addition, since the gate electrode and the contact material can be separated by the above-mentioned coating film, and the first coating film can be freely selected from materials different from the ordinary interlayer insulating film, the leakage current can be improved while improving the insulation performance. The amount can be reduced, and the parasitic capacitance can be reduced by using a low dielectric constant material. Therefore, the contact and the gate electrode can be made closer to each other, and the element can be miniaturized.
[0018]
Further, the etching of the interlayer insulating film can be stopped by the first coating film. That is, by stopping the etching at the first coating film, it is possible to suppress a contact failure due to etching of the semiconductor substrate and a short circuit between the source / drain diffusion region and the semiconductor substrate, thereby improving reliability. Semiconductor memory device with high reliability can be provided.
[0019]
Further, since only the first coating film can have two functions of a charge holding function and a function of stopping the etching, the process can be simplified, and a semiconductor memory device with low manufacturing cost can be realized. Can be provided.
[0020]
In addition, since the first and third coating films made of an insulating film are formed above and on the side of the gate electrode, the margin for misalignment when designing the contact formation position is increased as in the related art. Since there is no necessity, the area occupied by the element can be reduced, and the manufacturing cost can be reduced.
[0021]
Further, a semiconductor memory device according to a third aspect of the present invention
A gate electrode formed on a semiconductor substrate via a gate insulating film,
A channel formation region arranged at least in a region below the gate electrode of the semiconductor substrate,
A pair of source / drain diffusion regions disposed on both sides of the channel formation region of the semiconductor substrate and having a conductivity type opposite to that of the channel formation region;
A memory function body formed on both sides of the gate electrode and formed of a charge holding portion made of a material having a function of holding charge and a dissipation prevention insulator having a function of preventing dissipation of the charge held in the charge holding portion; ,
An interlayer insulating film formed at least above the gate electrode;
A coating film formed of an insulator formed on the side of the interlayer insulating film, and formed to cover the gate electrode and the memory function body;
A contact formed on the side of the gate electrode via the coating film and electrically connected to the source / drain diffusion region;
The coating film is made of a material having a selectivity to the interlayer insulating film so as to function as an etching stop material when etching the interlayer insulating film.
[0022]
According to the semiconductor memory device of the third aspect, the memory function body is formed not on the gate insulating film portion of the field-effect transistor but on the side of the gate electrode. The problem of read failures associated with this is eliminated.
[0023]
In addition, the gate electrode and the contact material and the memory function body and the contact material can be separated by the coating film, and the coating film can be freely selected from materials different from ordinary interlayer insulating films, so that the insulating performance is improved. In addition, the amount of leakage current can be reduced while the parasitic capacitance can be reduced by using a low dielectric constant material. Therefore, the contact and the gate electrode can be made closer to each other, and the element can be miniaturized.
[0024]
Further, the charge held in the charge holding portion having the function of holding the charge is suppressed by the dissipation prevention insulator having the function of preventing the charge from being dissipated, thereby providing a semiconductor memory device having good holding characteristics. it can.
[0025]
Further, since the dissipation of the retained charge of the memory function body can be suppressed by the coating film, a highly reliable semiconductor memory device having more favorable retention characteristics can be provided.
[0026]
In addition, since a coating film made of an insulating film is formed above and on the side of the gate electrode, there is no need to provide a large margin for misalignment when designing the contact formation position as in the related art. The area occupied by the element can be reduced, and the manufacturing cost can be reduced.
[0027]
In one embodiment of the present invention, in the semiconductor memory device according to any one of the first to third inventions, the source / drain diffusion region is arranged at a distance from the gate electrode in a channel direction. It is characterized by being.
[0028]
According to the semiconductor memory device of the above embodiment, in addition to having the effects of the semiconductor memory devices of the first and second inventions, the source / drain diffusion region is not arranged below the gate electrode, that is, the coating film Since the offset region is left below, the inversion layer disappears or is formed depending on the presence or absence of the surplus electrons in the charge holding portion in the coating film. As a result, a large hysteresis (change in threshold value) is obtained, and good writing / writing is achieved. A semiconductor memory device having erasing characteristics is provided.
[0029]
Further, since writing / erasing can be performed by hot carriers generated in the offset region, a semiconductor memory device capable of 2-bit operation is provided.
[0030]
According to the semiconductor memory device of the above embodiment, in addition to having the effects of the semiconductor memory device of the third aspect, the source / drain diffusion region is not arranged below the gate electrode, that is, the offset region is formed below the coating film. , The inversion layer disappears or is formed depending on the presence or absence of surplus electrons in the charge holding portion in the memory function body. As a result, a large hysteresis (change in threshold value) is obtained, and good write / erase characteristics are obtained. Semiconductor memory device is provided.
[0031]
Further, since writing / erasing can be performed by hot carriers generated in the offset region, a semiconductor memory device capable of 2-bit operation is provided.
[0032]
In one embodiment, in the semiconductor memory device according to any one of the first to third inventions, the semiconductor substrate and the gate electrode are made of silicon, and the gate insulating film, the coating film, The interlayer insulating film is made of a silicon compound, and the silicon compound of the coating film is a silicon nitride film.
[0033]
According to the semiconductor memory device of the above embodiment, the semiconductor substrate, the gate electrode, the gate insulating film, the coating film, and the interlayer insulating film are made of silicon or a silicon compound which is often used as a material of a semiconductor device at present. Since a semiconductor process having a very high affinity with the semiconductor manufacturing process can be constructed, a semiconductor memory device with low manufacturing cost can be provided.
[0034]
Further, since the above-mentioned coating film is made of a silicon nitride film, in the conventional semiconductor manufacturing process, the interlayer insulating film and the element isolation region are made of a silicon oxide film. Can obtain a large etching selectivity, so that a process having a very high affinity with the conventional semiconductor manufacturing process can be constructed, and a contact failure and a short circuit between the source / drain diffusion region and the semiconductor substrate can be suppressed. Semiconductor memory device with low cost can be provided. Further, the nitride film is 1 × 10 ¹² cm ^-2 It is possible to provide a semiconductor memory device having a good degree of charge trapping and good write / erase characteristics.
[0035]
In one embodiment, in the semiconductor memory device according to the third aspect of the present invention, the memory function body includes a first insulator as the dissipation prevention insulator formed on both sides of the gate electrode. A nitride film as the charge holding portion formed on a side wall portion of the first insulator; and a side wall insulator formed on a side wall portion of the nitride film.
[0036]
According to the semiconductor memory device of the above embodiment, the electric charge can be favorably held by the nitride film, and the dissipation of the electric charge can be effectively prevented by sandwiching the nitride film between the first insulator and the sidewall insulator. Even if an insulating film leaks, which degrades the retention characteristics of the memory, all the charges held in the first insulating film do not leak and are held in the nitride film near the insulating film leak portion. The stored charge only leaks. Therefore, a semiconductor memory device having excellent retention characteristics and extremely high long-term reliability is provided. Further, the nitride film is 1 × 10 ¹² cm ^-2 It is possible to provide a semiconductor memory device having a good degree of charge trapping and good write / erase characteristics.
[0037]
In one embodiment, in the semiconductor memory device according to the third aspect of the present invention, the memory function body includes a first insulator as the dissipation prevention insulator formed on both sides of the gate electrode. And a sidewall insulator formed on the sidewall of the first insulator and including a plurality of fine particles as the charge holding unit.
[0038]
According to the semiconductor memory device of the above embodiment, the structure in which the plurality of fine particles hold electric charge, that is, the structure in which the region having the function of holding electric charge is subdivided into minute regions such as fine particles is used. Even when the insulating film leaks, which deteriorates the holding characteristics, all the charges held by the plurality of fine particles do not leak, and the charges held by the fine particles (silicon dots) near the insulating film leak portion leak. Stay only. Therefore, a semiconductor memory device having excellent retention characteristics and extremely high long-term reliability is provided. Further, as an example, a region made of a material having a function of retaining charges can be formed in a nanodot shape having a size that causes a Coulomb blockade effect. Therefore, the memory effect is significantly improved by the Coulomb blockade effect.
[0039]
In one embodiment, in the semiconductor memory device according to the third aspect of the present invention, the memory function body includes a first insulator as the dissipation prevention insulator formed on both sides of the gate electrode. A side wall insulation as the dissipation prevention insulator formed so as to sandwich the charge holding portion between the charge holding portion formed on the side wall portion of the first insulator and the first insulator; Wherein the charge holding section is narrower in width than the memory function body.
[0040]
According to the semiconductor memory device of the above-described embodiment, electrons injected by writing are limited to the vicinity of the vicinity of the channel, so that the electrons can be easily removed by erasing and erroneous erasing can be prevented.
[0041]
Further, since the amount of injected charge does not change and the volume of the charge holding unit that holds the charge is reduced, the amount of charge per unit volume can be increased, so that writing / erasing of electrons can be efficiently performed. A semiconductor memory device which can be performed at a high writing / erasing speed is provided.
[0042]
Further, since the side wall of the charge holding portion is covered with the side wall insulator, it is possible to prevent a short circuit between the charge holding portion and the contact during the step of contacting the source / drain diffusion region. Therefore, a margin for misalignment between the contact and the memory function body at the time of design may be small, and miniaturization is possible. Therefore, a semiconductor memory device with reduced cost is provided.
[0043]
In one embodiment, in the semiconductor memory device according to the third aspect of the present invention, the memory function body includes a first insulator as the dissipation prevention insulator formed on both sides of the gate electrode. A charge holding portion formed on a side wall portion of the first insulator; and a side wall insulator serving as the dissipation prevention insulator formed so as to cover the charge holding portion. Is characterized in that it is narrower in width than the memory function body and lower in height than the memory function body, and is in contact with the first insulator and covered with the side wall insulator.
[0044]
According to the semiconductor memory device of the above embodiment, the charge injection portion having a width smaller than that of the memory function body and reduced so as to have a height lower than that of the memory function body allows electrons to be injected by writing. Is limited to a narrower region near the channel, so that the electrons can be easily removed by erasing, and erroneous erasing can be prevented.
[0045]
Further, since the amount of injected charge does not change and the volume of the charge holding unit that holds the charge is reduced, the amount of charge per unit volume can be increased, so that writing / erasing of electrons can be efficiently performed. A semiconductor memory device which can be performed at a high writing / erasing speed is provided.
[0046]
Further, since the charge holding portion is completely covered with the sidewall insulator, it is possible to completely prevent a short circuit between the charge holding portion and the contact in the step of contacting the gate electrode. Therefore, the design contact margin can be further reduced, and the occupied area can be reduced. Thus, a semiconductor memory device with reduced manufacturing cost is provided.
[0047]
In one embodiment of the present invention, in the semiconductor memory device according to the third aspect, the memory function body includes a plurality of fine particles as the charge holding portions formed on both sides of the gate electrode. A film made of a conductor or a semiconductor disposed between the side wall insulator and the gate electrode and between the side wall insulator and the semiconductor substrate; a film formed of the conductor or the semiconductor; A first insulator serving as the dissipation prevention insulator disposed between the gate electrode and between the conductor or semiconductor film and the semiconductor substrate;
[0048]
According to the semiconductor memory device of the embodiment, by providing a film made of a conductor or a semiconductor between the semiconductor substrate and the plurality of fine particles, the fine particles as the charge holding portions formed on both sides of the gate electrode And variations in the threshold voltage and drive current of the field-effect transistor due to variations in the position and size of the transistor. Therefore, a highly reliable semiconductor memory device in which erroneous reading is suppressed can be provided.
[0049]
Further, as one embodiment of the semiconductor memory device, the first insulating film and the side wall insulator are made of a silicon oxide film or a silicon oxynitride film, the charge holding part is made of polysilicon, and the fine particles are made of silicon. It is characterized by.
[0050]
According to the semiconductor memory device of the above embodiment, since the charge holding portion is made of polysilicon, the charge injection amount can be controlled, thereby enabling multi-valued, and the manufacturing cost per bit can be reduced. . Further, since the fine particles are also made of silicon, the material is used as a standard material in an LSI (Large Scale Integrated Circuit) process, so that the manufacturing cost can be reduced.
[0051]
Further, in one embodiment of the semiconductor memory device, the charge holding portion is made of a silicon nitride film.
[0052]
According to the semiconductor memory device of the above embodiment, the charge holding portion is made of the silicon nitride film, and the side wall insulator is formed of the silicon oxide film or the silicon oxynitride film, so that the level for trapping the charge is one. × 10 ¹² cm ^-2 Level, large hysteresis characteristics can be obtained, the charge retention time is long, and the problem of charge leakage due to the occurrence of a leak path is suppressed, so that the retention characteristics are good. Since the material is used, manufacturing costs are reduced.
[0053]
According to a fourth aspect of the present invention, in the semiconductor memory device according to any one of the first to third aspects, the source / drain diffusion regions of the semiconductor memory elements adjacent to each other are electrically separated. It is characterized by having an element isolation region arranged.
[0054]
Conventionally, according to the semiconductor memory device having the above-described structure, the element is designed with a sufficient contact and misalignment allowance of the element isolation region so that the element isolation region is not simultaneously etched in the etching for forming the contact hole. However, according to the present invention, for example, a nitride film can be used as a coating film, and an oxide film is mainly used as an element isolation region, so that a sufficient misalignment margin between the element isolation region and the contact can be provided. Therefore, it is possible to provide a semiconductor memory device having a small occupied area and capable of reducing manufacturing costs.
[0055]
Furthermore, as one embodiment of the semiconductor memory device, in the semiconductor memory device according to any one of the first to third inventions, the semiconductor substrate and the gate electrode are made of silicon, and the gate insulating film, The coating film and the interlayer insulating film are made of a silicon compound, the coating film is made of a silicon nitride film, and the element isolation region is mainly made of an oxide film.
[0056]
Conventionally, an element has been manufactured with a design having sufficient misalignment allowance between the contact and the element isolation region so that the element isolation region is not simultaneously etched in the etching for forming the contact hole. According to the semiconductor memory device, it is possible to design the semiconductor memory device without having sufficient margin for misalignment between the element isolation region and the contact. Therefore, it is possible to provide a semiconductor memory device having a small occupied area and a reduced manufacturing cost.
[0057]
Further, a semiconductor device according to a fifth aspect of the present invention includes:
A semiconductor device in which a memory region having a semiconductor memory device according to any one of the first to third inventions and a logic circuit region having a semiconductor switching element are arranged on a semiconductor substrate,
The semiconductor storage device and the semiconductor switching element are field-effect transistors each having a gate electrode and a pair of source / drain diffusion regions formed on the surface of a semiconductor substrate corresponding to both sides of the gate electrode;
In the semiconductor switching element, in addition to the structure of the semiconductor memory device according to any one of the first to third aspects, at least a part of the source / drain diffusion region is disposed below the gate electrode on the surface of the semiconductor substrate. It is characterized in that it extends so that
[0058]
According to the semiconductor device having the above-described configuration, the semiconductor switching element whose source / drain diffusion region is not offset from the end of the gate electrode and the semiconductor memory device whose offset is offset can be mixedly mounted on the same substrate. And a semiconductor switching element having a high current driving capability.
[0059]
Further, when a memory functional body is formed for both the semiconductor memory device and the semiconductor switching element, there is no significant difference in the manufacturing process between the two. Therefore, a logic circuit or the like including the semiconductor switching element and a nonvolatile semiconductor including the semiconductor memory device are used. A semiconductor device which can be easily mounted together with a memory circuit can be provided.
[0060]
Further, the conventional flash memory has only the ability as a field-effect transistor having a thick gate insulating film because the charge holding portion is located below the gate electrode. Since the holding portion is on the side of the gate electrode, the holding portion can be formed independently of the gate insulating film. Therefore, a semiconductor memory device to which a state-of-the-art MOSFET manufacturing process can be easily applied, and a semiconductor device including the same can be provided.
[0061]
Further, a logic circuit area is constituted by the plurality of semiconductor switching elements, and a memory area is constituted by the plurality of semiconductor storage devices. Therefore, the logic circuit area has the above-mentioned effect and is easily mounted on the same substrate. And a semiconductor device having a memory region.
[0062]
Further, as one embodiment of the semiconductor device, the semiconductor device according to the fifth aspect of the present invention is characterized in that a nonvolatile memory section is configured by the semiconductor storage device.
[0063]
According to the semiconductor device of the above embodiment, the logic circuit portion is configured by the semiconductor switching elements, and the nonvolatile memory portion is configured by the semiconductor storage device. Therefore, the semiconductor device of the fifth aspect has the advantages of the semiconductor device of the fifth aspect. It is possible to realize a semiconductor device in which a logic circuit portion and a nonvolatile memory portion having the effects of the semiconductor memory devices of the first to third inventions are easily mounted on the same semiconductor substrate.
[0064]
Further, as one embodiment of the semiconductor device, the semiconductor device according to the fifth aspect of the present invention is characterized in that the semiconductor device includes the logic circuit region driven by a power supply voltage lower than a power supply voltage supplied to the memory region.
[0065]
According to the semiconductor device of the above-described embodiment, for example, a high power supply voltage can be supplied to the nonvolatile memory portion, so that the write / erase speed can be significantly improved. Further, since a low power supply voltage can be supplied to the logic circuit portion, deterioration of transistor characteristics due to destruction of a gate insulating film or the like can be suppressed, and power consumption can be further reduced. Therefore, it is possible to realize a semiconductor device having a highly reliable logic circuit portion easily mounted on the same substrate and a nonvolatile memory portion having a remarkably high write / erase speed.
[0066]
Further, as one embodiment of the semiconductor device, in the semiconductor device according to the fifth aspect of the present invention, the semiconductor memory device further comprises a static random access memory.
[0067]
According to the semiconductor device of the embodiment, a logic circuit unit and a static random access memory are configured by the semiconductor storage device, and a nonvolatile memory unit is configured by the semiconductor storage device. A semiconductor device having the effect of any of the third invention and having a logic circuit portion, a static random access memory, and a nonvolatile memory portion easily mounted on the same substrate can be realized. Further, by incorporating the static random access memory as the high-speed operation memory temporary storage memory, it is possible to further improve the function of the semiconductor device.
[0068]
According to a sixth aspect of the present invention, there is provided an IC card including the semiconductor memory device according to any one of the first to third aspects or the semiconductor device according to the fifth aspect.
[0069]
According to the IC card of the sixth aspect, it is possible to provide an IC card having the same effects as those of the first to third aspects or the fifth aspect. For example, an IC card has a semiconductor device in which a nonvolatile memory and its peripheral circuit portion, a logic circuit portion, an SRAM portion, and the like are easily mixed and the cost is reduced. Therefore, an IC card that can reduce costs can be provided.
[0070]
According to a seventh aspect of the invention, a portable electronic device includes the semiconductor memory device according to any one of the first to third aspects or the semiconductor device according to the fifth aspect.
[0071]
According to the portable electronic device of the seventh aspect, it is possible to provide a portable electronic device having effects similar to those of the first to third or fifth aspects. For example, a mobile phone has a semiconductor device in which a nonvolatile memory and its peripheral circuit portion, a logic circuit portion, an SRAM portion, and the like are easily mixed and the cost is reduced. Therefore, a portable electronic device that can reduce costs can be provided.
[0072]
Further, a method of manufacturing a semiconductor memory device according to an eighth aspect of the present invention includes
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After forming the gate electrode, a step of forming a first coating film made of an insulator having a function of retaining electric charge so as to cover the semiconductor substrate and the gate electrode;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Removing the first coating film exposed in the contact hole to expose a part of a side wall and an upper surface of the gate electrode;
After removing the first coating film, a second coating film made of an insulator having a function of retaining electric charges is formed on at least a side wall and an upper surface of the gate electrode newly exposed in the contact hole. And a process.
[0073]
According to the method of manufacturing a semiconductor memory device of the eighth aspect, the etching of the interlayer insulating film is performed under an etching condition having a high selectivity to the coating film, and the etching is stopped at the coating film. And a short circuit between the source / drain diffusion region and the semiconductor substrate due to etching of the semiconductor substrate, and a highly reliable semiconductor memory device can be provided. In addition, since only the covering film can have two functions of a memory function and a function of stopping the etching, the process can be simplified and a semiconductor memory device with low manufacturing cost can be provided.
[0074]
Further, a method of manufacturing a semiconductor memory device according to a ninth aspect is as follows.
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After forming the gate electrode, a step of forming a first coating film made of an insulator having a function of retaining electric charge so as to cover the semiconductor substrate and the gate electrode;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Anisotropic selective etching back is performed on the first coating film exposed in the contact hole to remove a part of the upper surface of the gate electrode and the semiconductor substrate while leaving a side wall shape on the side surface of the gate electrode. Exposing,
Forming a second coating film on at least the upper surface of the gate electrode newly exposed in the contact hole after exposing the semiconductor substrate.
[0075]
According to the method of manufacturing a semiconductor memory device of the ninth aspect, the etching of the interlayer insulating film is performed under etching conditions having a high selectivity to the coating film, and the etching is stopped at the coating film. And a short circuit between the source / drain diffusion region and the semiconductor substrate due to etching of the semiconductor substrate, and a highly reliable semiconductor memory device can be provided. In addition, since only the covering film can have two functions of a memory function and a function of stopping the etching, the process can be simplified and a semiconductor memory device with low manufacturing cost can be provided.
[0076]
Further, a method of manufacturing a semiconductor memory device according to a tenth aspect of the present invention includes:
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
Forming a third coating film above the gate electrode;
After forming the third coating film, a first coating film made of an insulator having a function of retaining electric charge is formed so as to cover the semiconductor substrate, the gate electrode, and the third coating film. Forming,
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Subjecting the first coating film exposed in the contact hole to anisotropic selective etching back to expose the semiconductor substrate while leaving a side wall shape on a side surface of the gate electrode. And
[0077]
According to the method of manufacturing a semiconductor memory device of the tenth aspect, the etching of the interlayer insulating film is performed under etching conditions having a high selectivity to the first coating film, and the etching is stopped at the first coating film. By doing so, a contact failure due to etching of the semiconductor substrate and a short circuit between the source / drain diffusion region and the semiconductor substrate can be suppressed, and a highly reliable semiconductor memory device can be provided. Further, since only the first coating film can have two functions of a memory function and a function of stopping the etching, the process can be simplified and a semiconductor memory device with low manufacturing cost can be provided. it can.
[0078]
In one embodiment of the present invention, in the method for manufacturing a semiconductor memory device according to any one of the eighth to tenth aspects, the method further comprises the step of: And a step of forming the source / drain diffusion regions in a self-aligned manner at intervals in the channel direction with respect to the gate electrode.
[0079]
According to the method of manufacturing the semiconductor device of the above embodiment, the source / drain diffusion region is not disposed below the gate electrode, that is, the offset region is left below the coating film. The inversion layer disappears or is formed depending on the presence or absence of the surplus electrons in the holding portion. As a result, a large hysteresis (change in threshold value) is obtained, and a semiconductor memory device having good writing / erasing characteristics is provided.
[0080]
Further, since writing / erasing can be performed by hot carriers generated in the offset region, a semiconductor memory device capable of 2-bit operation is provided.
[0081]
The method for manufacturing a semiconductor memory device according to the eleventh aspect of the present invention includes:
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After the gate electrode is formed, a charge holding portion made of a material having a function of holding charge on a side wall of the gate electrode, and a dissipation prevention insulator having a function of preventing dissipation of the charge held in the charge holding portion. Forming a memory function body comprising:
After forming the memory function body, forming a first coating film so as to cover the semiconductor substrate, the gate electrode, and the memory function body;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Removing the first coating film exposed in the contact hole to expose a part of a side wall and an upper surface of the memory function body;
After the step of removing the first coating film, a step of forming a second coating film on a side wall and an upper surface of the memory function body newly exposed in the contact hole is provided.
[0082]
According to the method of manufacturing a semiconductor device of the eleventh aspect, similarly to the eighth aspect, a contact failure and a short circuit between the source / drain diffusion region and the semiconductor substrate can be suppressed, and a highly reliable semiconductor device can be obtained. A storage device can be provided.
[0083]
Further, the charge held in the charge holding portion having the function of holding the charge is suppressed by the dissipation prevention insulator having the function of preventing the charge from being dissipated, so that a semiconductor memory device having good holding characteristics can be provided. . In addition, since the charge injected during the rewrite operation is suppressed from dissipating to the gate electrode and other nodes, the charge injection efficiency is increased, and higher-speed operation is possible. Further, since the first and second coating films cover the memory function body and the gate electrode, outward diffusion of impurities which causes depletion of impurities in the gate electrode is suppressed, and the yield is improved. Further, since the dissipation of the retained charges of the memory function body can be suppressed in the first and second coating films, a highly reliable semiconductor memory device having more favorable retention characteristics can be provided.
[0084]
Further, a method for manufacturing a semiconductor memory device according to the twelfth invention is characterized in that:
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After the gate electrode is formed, a charge holding portion made of a material having a function of holding charge on a side wall of the gate electrode, and a dissipation prevention insulator having a function of preventing dissipation of the charge held in the charge holding portion. Forming a memory function body comprising:
After forming the memory function body, forming a first coating film so as to cover the semiconductor substrate, the gate electrode, and the memory function body;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Anisotropic selective etching back is performed on the first coating film exposed in the contact hole to remove a part of the upper surface of the gate electrode and the semiconductor substrate while leaving a side wall shape on the side surface of the gate electrode. Exposing,
Forming a second coating film on at least the upper surface of the gate electrode newly exposed in the contact hole after exposing the semiconductor substrate.
[0085]
According to the method of manufacturing a semiconductor device of the twelfth aspect, similarly to the ninth aspect, a contact failure and a short circuit between the source / drain diffusion region and the semiconductor substrate can be suppressed, and a highly reliable semiconductor device can be obtained. A storage device can be provided.
[0086]
Further, the charge held in the charge holding portion having the function of holding the charge is suppressed by the dissipation prevention insulator having the function of preventing the charge from being dissipated, so that a semiconductor memory device having good holding characteristics can be provided. . In addition, since the charge injected during the rewrite operation is suppressed from dissipating to the gate electrode and other nodes, the charge injection efficiency is increased, and higher-speed operation is possible. Further, since the first and second coating films cover the memory function body and the gate electrode, outward diffusion of impurities which causes depletion of impurities in the gate electrode is suppressed, and the yield is improved. Further, since the dissipation of the retained charges of the memory function body can be suppressed in the first and second coating films, a highly reliable semiconductor memory device having more favorable retention characteristics can be provided.
[0087]
Further, a method for manufacturing a semiconductor memory device according to a thirteenth aspect of the present invention includes:
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After the gate electrode is formed, a charge holding portion made of a material having a function of holding charge on a side wall of the gate electrode, and a dissipation prevention insulator having a function of preventing dissipation of the charge held in the charge holding portion. Forming a memory function body comprising:
Forming a third coating film above the gate electrode after forming the memory function body;
Forming a first coating film so as to cover the semiconductor substrate, the gate electrode, the third coating film, and the memory function body;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Subjecting the first coating film exposed in the contact hole to anisotropic selective etching back to expose the semiconductor substrate while leaving a side wall shape on a side surface of the gate electrode. And
[0088]
According to the method of manufacturing a semiconductor device of the thirteenth aspect, similarly to the tenth aspect, a contact failure and a short circuit between the source / drain diffusion region and the semiconductor substrate can be suppressed, and a highly reliable semiconductor device can be obtained. A storage device can be provided.
[0089]
Further, the charge held in the charge holding portion having the function of holding the charge is suppressed by the dissipation prevention insulator having the function of preventing the charge from being dissipated, so that a semiconductor memory device having good holding characteristics can be provided. . In addition, since the charge injected during the rewrite operation is suppressed from dissipating to the gate electrode and other nodes, the charge injection efficiency is increased, and higher-speed operation is possible. Further, since the memory function body and the gate electrode are covered with the first and third coating films, outward diffusion of impurities which causes depletion of impurities in the gate electrode is suppressed, and the yield is improved. Further, since the dissipation of the retained charges of the memory function body can be suppressed in the first and third coating films, a highly reliable semiconductor memory device having more favorable retention characteristics can be provided.
[0090]
Further, as one embodiment of a method for manufacturing a semiconductor memory device,
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
An insulator having a function of retaining charge on the side wall of the gate electrode, a semiconductor or a conductor, and a step of forming a memory function body including a dissipation prevention insulator having a function of preventing dissipation of charge;
Implanting impurities to form source / drain diffusion regions in a self-aligned manner in the channel direction with respect to the gate electrode,
Forming a coating film on the semiconductor substrate and on the gate electrode and on the side of the gate electrode via the memory function body;
Forming an interlayer insulating film above the coating film;
Forming a contact hole in the interlayer insulating film using anisotropic selective etching,
A step of removing the coating film below the contact hole.
[0091]
According to the method for manufacturing a semiconductor device of the above embodiment, a contact failure and a short circuit between the source / drain diffusion region and the semiconductor substrate can be suppressed, and a highly reliable semiconductor memory device can be provided.
[0092]
Further, the charge held in an insulator, a semiconductor, or a conductor having a charge holding function is prevented from being dissipated by a dissipation prevention insulator having a function for preventing the charge from being dissipated. Equipment can be provided. In addition, since the charge injected during the rewrite operation is suppressed from dissipating to the gate electrode and other nodes, the charge injection efficiency is increased, and higher-speed operation is possible. Further, since the memory functional unit and the gate electrode are covered with the coating film, outward diffusion of impurities which causes depletion of impurities in the gate electrode is suppressed, and the yield is improved. Further, since the dissipation of the retained charges of the memory function body in the coating film can be suppressed, a highly reliable semiconductor memory device having more favorable retention characteristics can be provided. Furthermore, since the source / drain diffusion regions are not arranged below the gate electrode, that is, the offset region is left below the memory function body, the inversion layer is lost or formed depending on the presence or absence of excess electrons in the memory function body, As a result, a large hysteresis (change in threshold) is obtained, and a semiconductor memory device having good write / erase characteristics is provided. Further, since writing / erasing can be performed by hot carriers generated in the offset region, a semiconductor memory device capable of 2-bit operation is provided.
[0093]
According to one embodiment of the present invention, there is provided a method of manufacturing a semiconductor memory device according to the eighth to tenth aspects.
The coating film is a nitride film.
[0094]
According to the method for manufacturing a semiconductor memory device of the above embodiment, the first coating film made of a nitride film, which is an insulating film, having a function of retaining electric charges is formed above and on the side of the gate electrode. Therefore, it is not necessary to provide a large margin for misalignment when designing the contact formation position as in the related art, so that the area occupied by the device can be reduced and the manufacturing cost can be reduced.
[0095]
In addition, the etching for forming the contact hole of the interlayer insulating film in this step is performed under etching conditions having a high selectivity with respect to the coating film, and the etching is stopped at the coating film, thereby etching the semiconductor substrate. And the problems such as short-circuit between the source / drain diffusion region and the semiconductor substrate due to the contact failure can be suppressed. In addition, since only the covering film can have two functions of a memory function and a function of stopping the etching, the process can be simplified and a semiconductor memory device with low manufacturing cost can be provided.
[0096]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor storage device, a semiconductor device, an IC card, a portable electronic device, and a method of manufacturing a semiconductor storage device according to the present invention will be described in detail with reference to the illustrated embodiments. In the following description of the drawings, portions using the same material and substance may be denoted by the same reference numerals, and do not necessarily indicate the same shape.
[0097]
(1st Embodiment)
An outline of a semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIGS.
[0098]
FIG. 1A shows a sectional structure of a semiconductor memory device according to a first embodiment of the present invention. In this semiconductor memory device, as shown in FIG. 1A, a gate electrode 3 formed on a semiconductor substrate 1 via a gate insulating film 2 (a gate stack 8 is formed by the gate insulating film 2 and the gate electrode 3). A channel forming region 19 disposed at least in a region below the gate electrode 3 of the semiconductor substrate 1, and a channel forming region 19 disposed on both sides of the channel forming region 19 of the semiconductor substrate 1 and having a conductivity type opposite to that of the channel forming region 19. A pair of source / drain diffusion regions 13a and 13b, an interlayer insulating film 23 formed at least above the gate electrode 3, and a top and side of the gate electrode 3; First and second covering films 21 and 26 made of an insulator formed on the sides of the interlayer insulating film 23; and the first and second covering films 21 and 26 and the interlayer insulating film. And a contact 25 of the contact material embedded in third contact hole formed in the side of the.
[0099]
The contact 25 is electrically connected to the source / drain diffusion regions 13a and 13b. Further, the first and second coating films 21 and 26 have charge holding portions 18a and 18b made of an insulator having a function of holding charge, and also have an etching stop material when etching the interlayer insulating film 23. It becomes. It is desirable to use an insulating film as the first and second coating films 21 and 26 so that the wiring and the electrode can be electrically separated.
[0100]
The material of the first and second coating films 21 and 26 is coated in the anisotropic selective etching of the interlayer insulating film 23 so as to function as an etching stopper in the etching for opening a contact hole in the interlayer insulating film 23. It is desirable to use a material that satisfies the condition that the etching selectivity to the films 21 and 26 is large. As an example, since a silicon oxide film is often used as a material of the interlayer insulating film 23, a silicon nitride film is preferably used as a material of the first and second coating films 21 and 26.
[0101]
The material of the first and second coating films 21 and 26 is made of a material for the element isolation region so as not to etch the element isolation region when opening the contact with the first and second coating films 21 and 26. Alternatively, it is preferable to use a material other than the material for filling the element isolation region, which satisfies the condition that the etching selectivity to the element isolation region is large in the anisotropic selective etching of the first and second coating films 21 and 26. As an example, since a silicon oxide film is often used as a material of the element isolation region or a material for filling the element isolation region, a silicon nitride film is preferably used as a material of the first and second coating films.
[0102]
In this case, the first and second coating films 21 and 26 are silicon nitride films having trap levels for retaining charges. Further, both side wall portions of the gate stack 8 in the first and second coating films 21 and 26 are charge holding portions 18a and 18b, respectively, which actually hold charges. Further, as a structure which is a feature of the present invention, there is a structure of a first coating film 21 and an interlayer insulating film 23 formed thereon. By etching the first coating film 21 covering the semiconductor substrate 1 and the gate stack 8 using the interlayer insulating film 23 as a mask, the structure of the illustrated first coating film 21 is formed. The first coating film 21 and the interlayer insulating film 23 have a relationship between the film to be etched and the etching mask. Further, the above-described etching is etching for forming the contact 25, and is performed by temporarily stopping the etching at the first coating film 21 and further etching the first coating film 21. The contact failure is suppressed by suppressing the surface roughness of the source / drain diffusion regions 13a and 13b, and the source / drain diffusion regions 13a and 13b are not deeply etched. The short circuit is prevented, and furthermore, the short circuit between the source / drain diffusion regions 13a and 13b and the semiconductor substrate 1 caused by etching the device isolation region at the time of contact etching when the device isolation region is provided can be suppressed.
[0103]
Further, a second coating film 26 is formed on the first coating film 21, the interlayer insulating film 23, and a portion exposed to the contact hole of the gate stack 8. Further, a contact 25 is formed on a side wall of the second coating film 26, and is in electrical contact with the source / drain diffusion regions 13a and 13b. Furthermore, since the gate stack 8 is covered with the coating films 21 and 26, outward diffusion of impurities which causes depletion of impurities in the gate electrode 3 is suppressed, and the yield is improved.
[0104]
The source / drain diffusion regions 13a and 13b function as a source region or a drain region, respectively. The semiconductor memory device has an offset structure. That is, since the source / drain diffusion regions 13a and 13b on both sides do not reach the region below the gate electrode, offset regions 20 and 20 are formed.
[0105]
As described above, in the semiconductor memory device shown in FIG. 1A, the first covering film 21 and the second covering film 26 have a function of reducing the element occupied area for a plurality of contacts, and the contact failure is also reduced. It also has a function as a memory function unit that suppresses and holds the charges in the 2-bit memory element. These functions are performed by forming the first coating film 21 and the second coating film 26. Accordingly, the steps can be simplified, and a semiconductor memory device with low manufacturing cost can be provided.
[0106]
FIG. 1A shows that the contact 25 is formed only on one side of the gate electrode 3 near the gate electrode 3, and the second covering film 26 is formed even if the contact hole is formed above the gate electrode 3. Therefore, the contact 25 and the gate electrode 3 are not effectively short-circuited. Thus, it is not necessary to make a large misalignment in design between the contact 25 and the gate electrode 3, and the element can be miniaturized. That is, even if the gate electrode 3 and the contact hole overlap in actual processing, the gate electrode 3 can be covered by the coating film if the width is equal to or less than the thickness of the coating film. However, in this structure, the other contact hole does not cover the side wall of the gate electrode 3. According to this structure, the contact 25 is close to the gate electrode 3 only on one side, and the element occupied by the other contact 25 increases.
[0107]
On the other hand, FIG. 1B shows a cross-sectional structure of another semiconductor memory device according to the first embodiment of the present invention, which has the same effect as that of FIG. It is a structure that enables. Since the semiconductor memory device has the above-described structure on both sides, elements are further miniaturized as compared with the structure shown in FIG.
[0108]
In the following embodiments and illustrations, only one of the structures in FIG. 1A or FIG. 1B is shown and described, but either structure may be used without particular description. When a structure in which the contact holes on both sides extend over the side wall of the gate electrode as shown in FIG. 1B is effective for the above miniaturization, the other effects are almost the same. Needless to say.
[0109]
FIG. 1C shows a cross-sectional structure of another semiconductor memory device according to the first embodiment of the present invention, in which a third covering film 27 is formed on a gate electrode 3. 1A and 1B, the gate electrode 3 and the contact 25 are not short-circuited even when the contact hole overlaps the gate electrode 3 in processing. The effect of conversion is exhibited. Further, similarly to the relationship between FIG. 1A and FIG. 1B, both sides of the gate electrode 3 may be formed so as to overlap with the contact hole in processing, and the same effect as described above is exhibited.
[0110]
Further, in FIG. 1, the charge holding units 18a and 18b may have a structure in which nanometer-sized quantum dots (nanodots) are distributed in a scattered manner in the insulating film. Can be played. For example, in the semiconductor memory device shown in FIG. 1, the first coating film 21 and the second coating film 26 cover the side surface and the upper surface of the gate stack 8, but the charge holding portion that substantially holds the charge. Reference numerals 18a and 18b denote both side wall portions of the gate electrode 3. In other words, it is sufficient that a substance that retains the function of retaining electric charge or retains polarization is disposed in these regions. If nanodots are formed in those regions, the retention characteristics are further improved.
[0111]
FIG. 2 shows another semiconductor memory device according to the first embodiment of the present invention. In FIG. 2, 101 is a semiconductor substrate, 102 is a gate insulating film, 103 is a gate electrode, 108 is a gate stack, 113a and 113b are source / drain diffusion regions, 117 is a silicon nitride film as an example of a charge holding portion, and 112 is A first insulator, 116 is a sidewall insulator, 119 is a channel formation region, 120 is an offset region, 121 is a first coating film, 122 is a region under the gate electrode 103, 123 is an interlayer insulating film, 125 is a contact, 126 is a second coating film. The semiconductor memory device differs from the semiconductor memory device of FIG. 1 in that memory function bodies 111a and 111b are formed. Each of the memory function bodies 111a and 111b includes a silicon nitride film 117 having a trap level for retaining electric charges, a first insulator 112 made of a silicon oxide film sandwiching the silicon nitride film 117, and a sidewall insulator 116. Each of the charge holding portions 18a and 18b in FIGS. 1A to 1C corresponds to the silicon nitride film 117 in the memory function bodies 111a and 111b in FIG.
[0112]
Therefore, since the silicon nitride film 117 serving as the charge holding portion in FIG. 2 is sandwiched between the first insulator 112 and the side wall insulator 116, the held charge is suppressed from being separated, and the semiconductor memory having good holding characteristics is provided. Equipment can be provided. Further, with the structure in which the silicon nitride film 117 is sandwiched between the first insulator 112 and the sidewall insulator 116, the charge injected at the time of the rewrite operation is suppressed from being dispersed to the gate electrode or another node. As a result, the charge injection efficiency is increased, and a higher-speed operation becomes possible. Furthermore, since the memory function bodies 111a and 111b and the gate stack 108 are covered by the first and second coating films 121 and 126, outward diffusion of impurities that causes depletion of impurities in the gate electrode 103 is suppressed. , The yield is improved. Further, it has a function of reducing the element occupation area for a plurality of contacts, and also suppresses a contact failure. These functions are achieved by forming the first and second coating films 121 and 126, so that the steps can be simplified and a semiconductor memory device with low manufacturing cost can be provided.
[0113]
In FIG. 2, the silicon nitride film 117 may be replaced with a conductor (floating gate) or a ferroelectric, and the same effect is obtained in that case.
[0114]
Although the first insulator 112 and the sidewall insulator 116 use a silicon oxide film here, a similar effect can be obtained as long as the material can suppress the separation of charges. Examples of the material in that case include an insulating film such as a silicon oxynitride film; a high dielectric film such as an aluminum oxide film, a titanium oxide film, a tantalum oxide film, and a hafnium oxide film; a low dielectric film.
[0115]
Hereinafter, various aspects of the semiconductor memory device will be described.
[0116]
This semiconductor memory device mainly includes a gate insulating film, a gate electrode formed on the gate insulating film, a memory function body (or charge holding portion) formed on both sides of the gate electrode, and a memory function body (or charge). A source / drain diffusion region, at least a portion of which is disposed under the holding portion, and a gate electrode or a gate electrode and a memory function body (or a charge holding portion), and further, are formed so as to cover a part of the semiconductor substrate. And a covering film.
[0117]
This semiconductor storage device functions as a semiconductor storage device that stores quaternary or more information by storing binary or more information in one memory function body (or charge holding unit). Due to the variable resistance effect of the memory function body, it also functions as a memory cell having both functions of a selection transistor and a memory transistor. However, this semiconductor memory device does not necessarily need to store and function quaternary information or more, and may store and function binary information, for example.
[0118]
Further, the semiconductor memory device can function as a memory cell having both functions of a selection transistor and a memory transistor due to the variable resistance effect of the memory function body.
[0119]
Further, it is preferable that the semiconductor substrate and the gate electrode be formed of a material made of silicon. In this case, the semiconductor substrate and the gate electrode are made of silicon, which is often used as a material of a semiconductor device at present, so that a semiconductor process having a very high affinity with a conventional semiconductor manufacturing process can be constructed, so that the semiconductor manufacturing cost is low. A storage device can be provided.
[0120]
When configuring the semiconductor device of the present invention, the semiconductor memory device is preferably formed on a semiconductor substrate or on a well region of the same conductivity type as a channel formation region formed in the semiconductor substrate.
[0121]
The semiconductor substrate is not particularly limited as long as it is used for a semiconductor device. For example, a substrate made of an element semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe, or GaN is used. No. Further, as a substrate having a semiconductor layer on its surface, various substrates such as an SOI (Silicon on Insulator) substrate or a multilayer SOI substrate, or a substrate having a semiconductor layer on a glass or plastic substrate may be used. . Among them, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor substrate or the semiconductor layer may have a small amount of current flowing therein, but may be single crystal (for example, by epitaxial growth), polycrystal, or amorphous.
[0122]
An element isolation region is preferably formed on such a semiconductor substrate or a semiconductor layer. Further, elements such as a transistor, a capacitor, and a resistor, a circuit including the elements, a semiconductor device, and an interlayer insulating film are combined to form a single element. Alternatively, it may be formed in a multi-layer structure. The element isolation region can be formed by various element isolation films such as a LOCOS (local oxide) film, a trench oxide film, an STI (Shallow Trench Isolation) film, and the like. The semiconductor substrate may have a P-type or N-type conductivity type, and it is preferable that at least one first conductivity type (P-type or N-type) well region is formed in the semiconductor substrate. . The impurity concentration of the semiconductor substrate and the well region can be in a range known in the art. Note that when an SOI substrate is used as the semiconductor substrate, a well region may be formed in the surface semiconductor layer, or a body region may be provided below the channel region. As described above, the well region and the body region formed in the semiconductor substrate and the surface semiconductor layer have a conductivity type opposite to that of the impurity in the source / drain diffusion region, and are adjusted to an appropriate impurity concentration. Things. That is, the current leaking from one source / drain diffusion region to the other source / drain diffusion region can be reduced by forming the well region and the body region. This makes it possible to reduce the substrate floating effect, which is a problem when using an SOI substrate.
[0123]
The gate insulating film or the insulating film is not particularly limited as long as it is generally used for a semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film; an aluminum oxide film, a titanium oxide film; A single-layer film or a laminated film of a high-dielectric film such as a film, a tantalum oxide film, and a hafnium oxide film can be used. Among them, a silicon oxide film is preferable. The gate insulating film has a thickness of, for example, about 1 nm to 20 nm, preferably about 1 nm to 6 nm. The gate insulating film may be formed only immediately below the gate electrode, or may be formed larger (wider) than the gate electrode. Depending on the structure and the process, if it is wide, it can also serve as an insulating film below the memory function body, and the process can be simplified.
[0124]
Further, the gate electrode or the electrode is formed on the gate insulating film in a shape which is usually used for a semiconductor device or a shape having a concave portion at a lower end portion. Note that a single gate electrode means a gate electrode which is formed as an integral shape without being separated by a single-layer or multilayer conductive film. Further, the gate electrode may have a sidewall insulating film on a sidewall. The gate electrode is not particularly limited as long as it is generally used for a semiconductor device, and a conductive film, for example, a metal such as polysilicon: copper and aluminum: a high melting point metal such as tungsten, titanium, and tantalum: A single-layer film such as a silicide with a high-melting-point metal or a laminated film may be used. The gate electrode is preferably formed to have a thickness of, for example, about 50 nm to 400 nm. Note that a channel formation region is formed below the gate electrode. This channel formation region is preferably formed not only below the gate electrode but also below a region including the gate electrode end outside in the gate length direction (offset structure). As described above, when there is a channel formation region that is not covered with the gate electrode, it is preferable that the channel formation region be covered with a gate insulating film or a charge holding portion described later.
[0125]
Further, the memory function body is configured to include at least a film or a region having a function of holding charge, having a function of storing and holding charge, trapping charge, or holding a charge polarization state. . Silicon nitride; silicon; silicate glass containing impurities such as phosphorus and boron; silicon carbide; alumina; high dielectric substances such as hafnium oxide, zirconium oxide, and tantalum oxide; zinc oxide; Body; metal and the like. The memory function body includes, for example, an insulator film including a silicon nitride film; an insulator film including a conductive film or a semiconductor layer therein; an insulator film including one or more conductors or semiconductor dots; It can be formed by a single layer or a laminated structure such as an insulating film including a ferroelectric film in which the state is maintained. Above all, the silicon nitride film has a large hysteresis characteristic due to the presence of a large number of levels for trapping charges, and has a long charge retention time and does not cause a problem of charge leakage due to generation of a leak path. It is preferable because it has good characteristics and is a material that is used as a standard in LSI processes.
[0126]
In addition, by using an insulating film including an insulating film having a charge holding function, such as a silicon nitride film, as a memory function body, reliability of storage and retention can be improved. This is because, since the silicon nitride film is an insulator, even if a charge leaks to a part of the silicon nitride film, the charge of the entire silicon nitride film is not immediately lost. Further, when a plurality of semiconductor memory devices are arranged, even if the distance between the elements is reduced and the adjacent memory function bodies come into contact with each other, the memory function bodies are stored in the respective memory function bodies as in the case where the memory function bodies are made of conductors. No lost information is lost. Further, the contact plug can be arranged closer to the memory function body, and in some cases, can be arranged so as to overlap with the memory function body, which facilitates miniaturization of the element.
[0127]
Further, in order to increase the reliability of memory retention, the insulating film having a function of retaining charges does not necessarily have to be in the form of a film, and insulators having a function of retaining charges are discretely present in the insulating film. Is preferred. Specifically, it is preferable that the material is dispersed in a dot shape in a material that does not easily retain charge, for example, silicon oxide.
[0128]
In addition, by using an insulator film including a conductive film or a semiconductor layer therein as a memory function body, the amount of charge injected into the conductor or the semiconductor can be freely controlled;
[0129]
Furthermore, by using an insulator film including one or more conductors or semiconductor dots as a memory function body, writing and erasing by direct tunneling of electric charges can be easily performed, which has an effect of reducing power consumption.
[0130]
Further, a ferroelectric film such as PZT (lead zirconate titanate) or PLZT (lanthanum-doped lead zirconate titanate) whose polarization direction is changed by an electric field may be used as the memory function body. In this case, electric charges are substantially generated on the surface of the ferroelectric film due to the polarization, and are maintained in that state. Therefore, the charge is supplied from the outside of the film having the memory function, and the same hysteresis characteristic as that of the film for trapping the charge can be obtained, and the charge retention of the ferroelectric film requires the injection of the charge from outside the film. In addition, since the hysteresis characteristic can be obtained only by the polarization of the charge in the film, there is an effect that writing / erasing can be performed at high speed.
[0131]
In addition, it is preferable that the memory function body further include a region which makes it difficult for electric charge to escape or a film which has a function of making it difficult for electric charge to escape. As a material that functions to make it difficult for electric charge to escape, a silicon oxide film or the like can be given.
[0132]
The charge holding portions included in the memory function body are formed directly or on both sides of the gate electrode via the insulating film, and are directly formed on the semiconductor substrate (the well region, the body region or the body region) via the gate insulating film or the insulating film. (Source / drain region or diffusion region). The charge holding portions on both sides of the gate electrode are preferably formed so as to cover all or a part of the side wall of the gate electrode directly or via an insulating film. With such an arrangement, the contact plug can be arranged closer to the gate electrode, so that miniaturization of the semiconductor memory element is facilitated. As an application example, when the gate electrode has a concave portion at the lower end, the gate electrode may be formed to completely or partially fill the concave portion directly or via an insulating film. The gate electrode is preferably formed only on the side wall of the memory function body, or does not cover the upper part of the memory function body. With such an arrangement, the contact plug can be arranged closer to the gate electrode, so that miniaturization of the device is facilitated. In addition, a semiconductor memory device having such a simple arrangement is easy to manufacture and can improve the yield.
[0133]
In the case where a conductive film is used as the charge holding portion, the charge holding portion is arranged via an insulating film so as not to come into direct contact with the semiconductor substrate (the well region, the body region, the source / drain region, or the diffusion region) or the gate electrode. Is preferred. For example, a stacked structure of a conductive film and an insulating film, a structure in which a conductive film is dispersed in a dot shape or the like in an insulating film, a structure in which a part is arranged in a side wall insulating film formed on a side wall of a gate, and the like are given. .
[0134]
The source / drain diffusion regions are arranged on the side opposite to the gate electrode of the memory function body as diffusion regions having a conductivity type opposite to that of the semiconductor substrate or the well region. The junction between the source / drain diffusion region and the semiconductor substrate or the well region preferably has a steep impurity concentration. This is because hot electrons and hot holes are efficiently generated at a low voltage, and high-speed operation can be performed at a lower voltage. The junction depth of the source / drain diffusion region is not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. Note that when an SOI substrate is used as the semiconductor substrate, the source / drain diffusion region may have a junction depth smaller than the thickness of the surface semiconductor layer; It is preferable to have a bonding depth of the order.
[0135]
The source / drain diffusion region may be arranged so as to overlap with the gate electrode end, may be arranged so as to coincide with the gate electrode end, or may be arranged so as to be offset from the gate electrode end. May be. In particular, in the case of offset, when a voltage is applied to the gate electrode, the easiness of inversion of the offset region under the charge holding portion greatly changes depending on the amount of charge held in the memory function body, and the memory effect increases. In addition, it is preferable because the short channel effect is reduced. If the offset is too much, the drive current between the source and the drain becomes extremely small. Therefore, the offset amount is larger than the thickness of the charge holding portion in the gate length direction, that is, the source / drain closer to one gate electrode end in the gate length direction. The shorter the distance to the region, the better. What is particularly important is that at least a part of the charge holding portion in the memory function body overlaps a part of the source / drain diffusion region which is a diffusion region. This is because the essence of the semiconductor memory device of the present invention is to rewrite the memory by the electric field crossing the memory function body due to the voltage difference between the gate electrode and the source / drain diffusion region existing only on the side wall of the memory function body.
[0136]
Further, since the source / drain diffusion region is offset with respect to the end of the gate electrode, the injection of electrons and the injection of holes into the memory function body are efficiently performed, and the writing and erasing speeds are high. A semiconductor memory device can be formed.
[0137]
The source / drain diffusion region may partially extend to a position higher than the surface of the channel region, that is, the lower surface of the gate insulating film. In this case, it is appropriate that a conductive film integrated with the source / drain diffusion region is laminated on the source / drain diffusion region formed in the semiconductor substrate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-mentioned metals, and high-melting point metals. Among them, polysilicon is preferable. Polysilicon has a much higher impurity diffusion rate than a semiconductor substrate, so it is easy to reduce the junction depth of the source / drain diffusion region in the semiconductor substrate, and it is easy to suppress the short channel effect. is there. In this case, it is preferable that a part of the source / drain diffusion region is disposed so as to sandwich at least a part of the charge holding portion together with the gate electrode.
[0138]
The covering film is made of a silicon nitride film and functions as a stopper for contact etching when forming a contact hole in the interlayer insulating film. Therefore, a short circuit between the source / drain diffusion region and the semiconductor substrate due to deep etching of the semiconductor substrate is prevented, and furthermore, by suppressing the surface roughness of the semiconductor substrate, a contact failure between the source / drain diffusion region and the upper wiring is prevented. In addition, a short circuit between the contact to the source / drain diffusion region and the gate electrode is prevented, and there is no need to consider a misalignment margin for avoiding a short circuit. A possible and low-cost semiconductor memory device can be provided.
[0139]
This semiconductor memory device uses a single gate electrode formed on a gate insulating film, one source / drain diffusion region, another source / drain diffusion region and a semiconductor substrate as four terminals. By applying a predetermined potential to each of the terminals, writing, erasing and reading operations are performed. Specific operation principles and examples of operation voltages will be described later. When the semiconductor memory devices of the present invention are arranged in an array to form a memory cell array, each memory cell can be controlled by a single control gate, so that the number of word lines can be reduced.
[0140]
Further, the memory function body (or charge holding section) of the present invention is formed independently of the gate insulating film. Therefore, the memory function performed by the memory function body (or the charge holding unit) is separated from the transistor operation function performed by the gate insulating film. Therefore, the design policy of thinning the gate insulating film and the like for optimizing the transistor operation and the design policy of the material of the memory functional body for optimizing the memory function can be determined independently of each other. A good memory function can be easily achieved while maintaining transistor operation characteristics.
[0141]
The semiconductor memory device of the present invention can be formed by a normal semiconductor process, for example, by a method similar to the method of forming a single-layer or stacked-layer sidewall spacer on the side wall of a gate electrode. Specifically, after forming the gate electrode or electrode,
-Forming a single-layer film or a laminated film including a charge holding portion such as a charge holding portion, a charge holding portion / insulating film, an insulating film / charge holding portion, and an insulating film / charge holding portion / insulating film, under appropriate conditions. How to etch back and leave these films as sidewall spacers
An insulating film or a charge retaining portion is formed and etched back under appropriate conditions to leave a sidewall spacer, and further a charge retaining portion or an insulating film is formed and etched back to leave a sidewall spacer. Method
A method in which an insulating film material in which a particulate charge retaining material is dispersed is applied or deposited on a semiconductor substrate including a gate electrode, etched back under appropriate conditions, and the insulating film material is left in a sidewall spacer shape.
After forming the gate electrode, a method of forming the single-layer film or the laminated film and patterning using a mask
And the like.
[0142]
Before forming a gate electrode or an electrode, a charge holding portion, a charge holding portion / insulating film, an insulating film / charge holding portion, an insulating film / charge holding portion / insulating film, and the like are formed, and a channel region of these films is formed. An opening is formed in a region to be formed, a gate electrode material film is formed over the entire surface, and the gate electrode material film is patterned into a shape including the opening and larger than the opening.
[0143]
The best mode of a semiconductor memory device when a semiconductor memory device of the present invention is arranged to form a memory cell array is, for example,
(I) a gate electrode of a plurality of semiconductor storage devices is integrated to have a word line function;
(Ii) a memory function body is formed on both sides of the word line;
(Iii) It is an insulator (especially a silicon nitride film) that holds a charge in the memory function body.
(Iv) The memory function body is formed of an ONO (Oxide Nitride Oxide) film, and the silicon nitride film has a surface substantially parallel to the surface of the gate insulating film.
(V) the silicon nitride film in the memory function body is separated from the word line and the channel region by the silicon oxide film;
(Vi) the silicon nitride film and the diffusion layer in the memory function body overlap,
(Vii) the thickness of the insulating film separating the silicon nitride film having a surface substantially parallel to the surface of the gate insulating film from the channel region or the semiconductor layer is different from the thickness of the gate insulating film;
(Viii) writing and erasing operations of one semiconductor memory device are performed by a single word line;
(Ix) there is no electrode (word line) having a function of assisting write and erase operations on the memory function body;
(X) a region having a high impurity concentration of a conductivity type opposite to the conductivity type of the diffusion region in a portion immediately below the memory function body and in contact with the diffusion region;
It satisfies the requirement. The best mode is the case where all the above requirements are satisfied. However, it is needless to say that all the above requirements need not be satisfied.
[0144]
When a plurality of the above requirements are satisfied, a particularly preferable combination exists. For example, (iii) an insulator (especially a silicon nitride film) holds charges in the memory function body, and (ix) an electrode (word line) having a function of assisting writing and erasing operations on the memory function body. ) And (vi) the insulating film (silicon nitride film) in the memory function body and the diffusion layer overlap. If the insulator holds the charge in the memory function body and there is no electrode having a function of assisting the writing and erasing operations on the memory function body, the insulating film ( Only when the silicon nitride film) and the diffusion layer overlap, it has been found that the writing operation is performed favorably. That is, when the requirements (iii) and (ix) are satisfied, it is particularly preferable that the requirement (vi) is satisfied. On the other hand, when the conductor holds the electric charge in the memory function body, or when there is an electrode having a function of assisting the writing and erasing operations on the memory function body, the insulating film and the diffusion layer in the memory function body Was able to perform the write operation even when the data did not overlap.
[0145]
However, in the case where it is an insulator, not a conductor, that retains electric charge in the memory function body, or when there is no electrode having a function of assisting the writing and erasing operations on the memory function body, the following A very large effect can be obtained. That is, the contact plug can be arranged closer to the memory function body, or the stored information can be retained even if the distance between the elements is short and a plurality of memory function bodies interfere with each other. It will be easier. Further, since the element structure is simple, the number of steps can be reduced, the yield can be improved, and it is easy to mix transistors with transistors forming a logic circuit or an analog circuit. Further, it was confirmed that the writing and erasing operations were performed at a low voltage of 5 V or less. From the above, it is particularly preferable that the requirements (iii), (ix) and (vi) are satisfied.
[0146]
The semiconductor storage device of the present invention can be used for IC cards, portable electronic devices, and the like. Examples of the portable electronic device include a portable information terminal, a mobile phone, and a game device.
[0147]
Hereinafter, the present invention is illustrated and explained in detail. It goes without saying that the present invention is not limited to the following embodiments. That is, in the following embodiments, the case where an N-channel element is used as a memory is described, but a P-channel element may be used as a memory. In this case, the conductivity types of the impurities may be all reversed.
[0148]
Also, it should be noted that the following drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness and size of each layer and each part, and the like are different from actual ones. Therefore, the specific dimensions of the thickness and size should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.
[0149]
The semiconductor memory device of the present invention can store 2-bit (quaternary) information, and each operation principle of the semiconductor memory device shown in FIGS. 1A to 1C will be described below.
[0150]
Next, the principle of the write operation of the semiconductor memory device will be described.
[0151]
Here, writing refers to injecting electrons into the charge holding portion when the semiconductor memory device is an N-channel type. Hereinafter, the semiconductor memory device will be described as an N-channel type.
[0152]
In FIG. 1, in order to inject (write) electrons into the second charge holding portion 18b, the first source / drain diffusion region 13a (having N-type conductivity) is used as a source electrode and the second source / drain diffusion region 13a is used as a second electrode. The source / drain diffusion region 13b (having N-type conductivity) is used as a drain electrode. For example, 0V may be applied to the first source / drain diffusion region 13a and the semiconductor substrate 1, + 5V may be applied to the second source / drain diffusion region 13b, and + 2V may be applied to the gate electrode 3. According to such a voltage condition, the inversion layer extends from the first source / drain diffusion region 13a (source electrode), but does not reach the second source / drain diffusion region 13b (drain electrode). Occurs. The electrons are accelerated by a high electric field from the pinch-off point to the second source / drain diffusion region 13b (drain electrode), and become so-called hot electrons (high-energy conduction electrons). Writing is performed by injecting the hot electrons into the second charge holding portion 18b. Note that no writing is performed in the vicinity of the first charge holding section 18a because hot electrons do not occur.
[0153]
In this manner, writing can be performed by injecting electrons into the second charge holding portion 18b.
[0154]
On the other hand, in order to inject (write) electrons into the first charge holding portion 18a, the second source / drain diffusion region 13b is used as a source electrode, and the first source / drain diffusion region 13a is used as a drain electrode. . For example, 0V may be applied to the second source / drain diffusion region 13b and the semiconductor substrate 1, + 5V may be applied to the first source / drain diffusion region 13a, and + 2V may be applied to the gate electrode 3. As described above, when the electrons are injected into the second charge holding unit 18b, by exchanging the source / drain regions, the electrons can be injected into the first charge holding unit 18a and writing can be performed.
[0155]
Next, the principle of the erasing operation of the semiconductor memory device will be described.
[0156]
In the first method of erasing information stored in the first charge holding unit 18a, a positive voltage (for example, + 6V) is applied to the first source / drain diffusion region 13a, and the positive voltage is applied to the semiconductor substrate 1 by 0V. To apply a reverse bias to the PN junction between the first source / drain diffusion region 13a and the semiconductor substrate 1, and further apply a negative voltage (for example, -5 V) to the gate electrode 3. At this time, in the vicinity of the gate electrode 3 of the PN junction, the potential gradient becomes particularly steep due to the influence of the gate electrode to which the negative voltage is applied. Therefore, hot holes (high-energy holes) are generated on the semiconductor substrate 1 side of the PN junction due to the band-to-band tunnel. The hot holes are drawn in the direction of the gate electrode 3 having a negative potential, and as a result, holes are injected into the first charge holding portion 18a. Thus, the erasing of the first charge holding unit 18a is performed. At this time, 0 V may be applied to the second source / drain diffusion region 13b.
[0157]
When erasing the information stored in the second charge holding section 18b, the potentials of the first source / drain diffusion region 13a and the second source / drain diffusion region 13b may be replaced in the erasing.
[0158]
In the second method of erasing information stored in the first charge holding section 18a, a positive voltage (for example, +5 V) is applied to the first source / drain diffusion region 13a, and the second source / drain diffusion region It is sufficient to apply 0 V to 13b, apply a negative voltage (for example, −4 V) to the gate electrode 3, and apply a positive voltage (for example, +0.8 V) to the semiconductor substrate 1. At this time, a forward voltage is applied between the semiconductor substrate 1 and the second source / drain diffusion region 13b, and electrons are injected into the semiconductor substrate 1. The injected electrons diffuse to the PN junction between the semiconductor substrate 1 and the first source / drain diffusion region 13a, where they are accelerated by a strong electric field to become hot electrons. The hot electrons generate electron-hole pairs at the PN junction. That is, when a forward voltage is applied between the semiconductor substrate 1 and the second source / drain diffusion region 13b, the electrons injected into the semiconductor substrate 1 serve as a trigger, and a PN junction located on the opposite side is used. Hot holes occur. Hot holes generated at the PN junction are drawn in the direction of the gate electrode 3 having a negative potential, and as a result, holes are injected into the first charge holding portion 18a.
[0159]
According to the second method, even when only a voltage sufficient to generate a hot hole due to an interband tunnel is applied to the PN junction between the P-type well region and the first source / drain diffusion region 13a, The electrons injected from the second source / drain diffusion region 13b serve as a trigger for generating an electron-hole pair at the PN junction, and can generate a hot hole. Therefore, the voltage at the time of the erase operation can be reduced. In particular, when the offset region 20 (120 in FIG. 2) exists, the effect that the PN junction is sharpened by the gate electrode to which the negative potential is applied is small. Therefore, it is difficult to generate a hot hole due to the band-to-band tunnel. However, the second method can compensate for the disadvantage and realize the erasing operation at a low voltage.
[0160]
Note that when erasing information stored in the first charge holding unit 18a, in the first erasing method, +6 V had to be applied to the first source / drain diffusion region 13a, but the second In the erasing method, +5 V was sufficient. As described above, according to the second method, the voltage at the time of erasing can be reduced, so that power consumption is reduced and deterioration of the semiconductor memory device due to hot carriers can be suppressed.
[0161]
Next, the principle of the read operation of the semiconductor memory device will be described.
[0162]
When reading the information stored in the first charge holding unit 18a, the first source / drain diffusion region 13a is used as a source electrode, the second source / drain diffusion region 13b is used as a drain electrode, and the transistor is operated in a saturated region. . For example, 0V may be applied to the first source / drain diffusion region 13a and the semiconductor substrate 1, + 2V may be applied to the second source / drain diffusion region 13b, and + 1V may be applied to the gate electrode 3. At this time, when no electrons are accumulated in the first charge holding unit 18a, a drain current easily flows. On the other hand, when electrons are accumulated in the first charge holding unit 18a, an inversion layer is not easily formed in the vicinity of the first charge holding unit 18a, so that a drain current does not easily flow. Therefore, by detecting the drain current, the information stored in the first charge holding unit 18a can be read. At this time, the presence or absence of charge accumulation in the second charge holding unit 18b does not affect the drain current because the vicinity of the drain is pinched off.
[0163]
When reading information stored in the second charge holding portion 18b, the second source / drain diffusion region 13b is used as a source electrode, the first source / drain diffusion region 13a is used as a drain electrode, and the transistor is operated in a saturated region. . For example, 0V may be applied to the second source / drain diffusion region 13b and the semiconductor substrate 1, + 2V may be applied to the first source / drain diffusion region 13a, and + 1V may be applied to the gate electrode 3. As described above, when the information stored in the first charge storage unit 18a is read, the information stored in the second charge storage unit 18b can be read by exchanging the source / drain regions. .
[0164]
When a channel region (offset region 20) not covered by the gate electrode 3 is left, an inversion layer is formed in the channel region not covered by the gate electrode 3 depending on the presence or absence of surplus electrons in the charge holding portions 18a and 18b. It disappears or forms, resulting in a large hysteresis (change in threshold). However, if the width of the offset region 20 is too large, the drain current is greatly reduced, and the reading speed is significantly reduced. Therefore, it is preferable to determine the width of the offset region 20 so that sufficient hysteresis and reading speed can be obtained.
[0165]
Even when the source / drain diffusion regions 13a and 13b reach the end of the gate electrode 3, that is, even when the source / drain diffusion regions 13a and 13b and the gate electrode 3 overlap, the transistor is written by the write operation. Although the threshold value did not change substantially, the parasitic resistance at the source / drain ends changed greatly, and the drain current was greatly reduced (one digit or more). Therefore, reading can be performed by detecting the drain current, and a function as a memory can be obtained. However, when a larger memory hysteresis effect is required, it is preferable that the source / drain diffusion regions 13a and 13b and the gate electrode 3 do not overlap (the offset region 20 exists).
[0166]
With the above operation method, two bits can be selectively written and erased per transistor.
[0167]
Further, in the above operation method, two bits are written and erased per transistor by exchanging the source electrode and the drain electrode. However, the source electrode and the drain electrode may be fixed to operate as a one-bit memory. In this case, one of the source / drain regions can be set to a common fixed voltage, and the number of bit lines connected to the source / drain regions can be reduced by half.
[0168]
The above operation principles are the same in the semiconductor memory device shown in FIG.
[0169]
As is clear from the above description, according to the semiconductor memory device of the first embodiment, the charge holding portion is formed independently of the gate insulating film and is formed on both sides of the gate electrode. Operation is possible. Further, since each charge holding portion is separated by the gate electrode, interference at the time of rewriting is effectively suppressed. Further, since the memory function of the charge holding portion is separated from the transistor operation function of the gate insulating film, the gate insulating film can be made thinner to suppress the short channel effect. Therefore, miniaturization of the semiconductor memory device becomes easy.
[0170]
(Second embodiment)
A semiconductor memory device using the semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS.
[0171]
In the semiconductor memory device according to the second embodiment, as shown in FIG. 4F, a gate electrode 203 is formed on a semiconductor substrate 201 with a gate insulating film 202 interposed therebetween. A first coating film 221 and a second coating film 226 made of a silicon nitride film formed on the upper and side surfaces of the gate stack 208 including the gate electrode 203 and the semiconductor substrate 201; It comprises charge holding portions 218a and 218b defined near the region 220, and a pair of source / drain diffusion regions 213 formed below the charge holding portions 218a and 218b.
[0172]
In the second embodiment, the first coating film 221 and the second coating film 226 function as a memory unit as a semiconductor memory device, and a contact 225 to the source / drain diffusion region 213 and a gate electrode It has a function of electrically isolating 203. Further, it has a function of preventing a short circuit between the source / drain diffusion region 213 and the semiconductor substrate 201, and further has a function of preventing the element isolation region from being etched at the same time in etching for forming a contact hole. Have. In other words, in order to realize each function, it is conventionally necessary to form different films, and the manufacturing cost is increased through very complicated steps and the area occupied per element is increased. Manufactured by the method. However, by using the formation method in the second embodiment, it is possible to provide a semiconductor memory device with low manufacturing cost and small occupation area per element.
[0173]
Hereinafter, the manufacturing process of the semiconductor memory device will be described step by step along FIGS. 3A to 3C and FIGS. 4D to 4F.
[0174]
As shown in FIG. 3A, a gate insulating film 202 and a gate electrode 203 having a MOS structure, which have been subjected to a MOS (metal-oxide-semiconductor) formation process on a semiconductor substrate 201 having a p-type conductivity, that is, A gate stack 208 is formed.
[0175]
A typical MOS formation process at this time is as follows.
[0176]
First, an element isolation region (not shown) is formed on a semiconductor substrate 201 made of silicon having a p-type semiconductor region by a known method. The element isolation region can prevent leakage current from flowing between adjacent devices through the substrate. However, such device isolation regions need not be formed between devices that share a source / drain diffusion region between adjacent devices. The known method for forming an element isolation region is to use a known LOCOS oxide film or a method using a known trench isolation region to achieve the purpose of isolating elements using other known methods. Anything can be used. In the present embodiment, the case where the above-mentioned element isolation region is not formed is described, and is not shown.
[0177]
Next, although not specifically shown, an impurity diffusion region is formed near the exposed surface of the semiconductor substrate. This impurity diffusion region is for adjusting the threshold voltage, and increases the concentration of the channel formation region. An appropriate impurity diffusion region for setting an appropriate threshold voltage may be formed by a known method.
[0178]
Next, an insulating film is formed on the entire exposed surface of the semiconductor region. Since it is sufficient that this insulating film can suppress leakage, it is difficult to form an oxide film, a nitride film, a composite film of an oxide film and a nitride film, a high-dielectric insulating film such as a hafnium oxide film, a zirconium oxide film, or the like. A composite film may be used. Further, since it becomes a gate insulating film of the MOSFET, N ₂ It is desired to form a film having good performance as a gate insulating film by using a process including O oxidation, NO oxidation, nitridation after oxidation, and the like. A film with good performance as a gate insulating film means that the short channel effect of the MOSFET is suppressed, the leakage current, which is a current that flows through the gate insulating film unnecessarily, is suppressed while the depletion of impurities in the gate electrode is suppressed. This is an insulating film that can suppress any inconvenient factors in miniaturizing and improving the performance of MOSFETs, such as suppressing diffusion of gate electrode impurities into a formation region. Typical films are thermal oxide film, N ₂ It is an oxide film such as an O oxide film and a NO oxide film, and the film thickness is suitably in the range of 1 nm to 6 nm.
[0179]
Next, a gate electrode material is formed on the gate insulating film. As the gate electrode material, any material that can have the performance as a MOSFET, such as a semiconductor such as polysilicon or doped polysilicon, a metal such as Al, Ti, or W, or a compound of these metals and silicon, may be used. Any material can be used. Here, when a polysilicon film is formed as an example, the polysilicon film thickness is preferably about 50 nm to 400 nm.
[0180]
Next, a desired photoresist pattern is formed on the gate electrode material by a photolithography process, gate etching is performed using the photoresist pattern as a mask, and the gate electrode material and the gate insulating film are etched. The structure of FIG. 3A is formed. That is, the gate insulating film 202, the gate electrode 203, and the gate stack 208 including them are formed. Although not shown, the gate insulating film need not be etched at this time. When used as an injection protection film during the next step of impurity injection without etching, the step of forming the injection protection film can be simplified.
[0181]
Note that, as described above, the materials of the gate insulating film 202 and the gate electrode 203 may be materials used in a logic process in accordance with the scaling rule of that era, and are not limited to the above materials.
[0182]
Further, the gate stack 208 may be formed by the following method. A gate insulating film similar to the above is formed on the entire exposed surface of the semiconductor substrate 201 having the p-type semiconductor region. Next, a gate electrode material similar to the above is formed on the gate insulating film. Next, a mask insulating film such as an oxide film, a nitride film, and an oxynitride film is formed over the gate electrode material. Next, a photoresist pattern similar to the above is formed on the mask insulating film, and the mask insulating film is etched. Next, the photoresist pattern is removed, and the gate electrode material is etched using the mask insulating film as an etching mask. Next, the structure shown in FIG. 3A is formed by etching the exposed portions of the mask insulating film and the gate insulating film. When the gate stack is formed in this manner, the selectivity at the time of etching, that is, the selectivity between the gate electrode material and the gate insulating film material can be increased, and the etching of the thin film gate insulating film can be performed without etching the substrate. Becomes possible. Although not shown, the gate insulating film does not need to be etched at this time for the same reason as described above.
[0183]
Next, as shown in FIG. 3B, a first coating film 221 made of a silicon nitride film is formed on the exposed surfaces of the gate stack 8 and the semiconductor substrate 201. As a formation method, a known CVD (Chemical Vapor Deposition) method having good step coverage may be used. Here, the film thickness may be about 2 nm to 100 nm. This film thickness is an important parameter for forming the source / drain diffusion region 213 (shown in FIG. 3C) by offsetting with respect to the gate electrode 203. It is better to adjust within.
[0184]
Next, as shown in FIG. 3C, a source / drain diffusion region 213 is formed, an interlayer insulating film 223 is formed, and then a contact for forming a contact connecting the source / drain diffusion region 213 and a wiring is formed. A hole 224 is formed in the interlayer insulating film 223. Each step is described below.
[0185]
The source / drain diffusion region 213 is formed by implanting source / drain impurities using the gate electrode 203 and the first coating film 221 as a source / drain implantation mask and performing a known heat treatment. Here, the source / drain diffusion region 213 may be formed so as to be appropriately offset from the gate electrode 203 as described above.
[0186]
Next, an interlayer insulating film 223 is formed, and a contact hole 224 for forming a contact connecting the source / drain diffusion region 213 and the wiring is formed in the interlayer insulating film 223. It is preferable that the interlayer insulating film 223 be formed to a thickness that can be sufficiently planarized by a reflow process or the like. Typically, it is about 500 nm, but it is preferable to make it thin by a known technique so that the aspect ratio with respect to the contact diameter does not become too high.
[0187]
Here, the contact hole 224 is formed using a known photoresist and an anisotropic selective etching process. The etching of the interlayer insulating film is preferably performed under etching conditions having a high selectivity with respect to the first coating film 221 (silicon nitride film). By doing so, it is possible to suppress a contact failure caused by etching the semiconductor substrate 201.
[0188]
Here, when the conventional manufacturing method is used, it is necessary to form the contact hole in consideration of a sufficient misalignment margin so as not to be connected to the gate electrode. However, according to the manufacturing method of the present embodiment, the contact hole may be shifted and slightly applied to the gate electrode (in addition to the coating film). Therefore, it is not necessary to form a contact hole in consideration of a sufficient margin from the gate electrode with a margin for misalignment as compared with the related art, and the contact and the gate electrode (as well as the coating film) can be actually formed. Since the semiconductor memory device can be formed with an overlapping portion, an occupied area per element can be extremely reduced, and a semiconductor memory device with low manufacturing cost can be provided.
[0189]
Next, as shown in FIG. 4D, the first coating film 221 under the contact hole is removed by using isotropic selective etching. In this way, the etching of the interlayer insulating film is temporarily stopped by the first coating film 221 and then the first coating film 221 is etched to completely open a contact hole. By doing so, a short circuit between the source / drain diffusion region and the substrate due to the deep etching of the semiconductor substrate 201 can be prevented, the surface roughness of the semiconductor substrate can be easily suppressed, and the contact failure can be suppressed. As the isotropic selective etching, wet etching may be used, or dry isotropic etching using remote plasma may be used. Etching by wet etching is effective in that the semiconductor substrate is not dug deep and in that the roughness of the semiconductor substrate surface etching is suppressed.
[0190]
However, as shown, the first coating film 221 on both side surfaces of the gate stack is removed, not only when the first coating film on one side surface of the gate stack is completely removed and the gate stack is exposed. May remain, and the gate stack 208 may not be exposed. In the case shown, the alignment in the photolithography process for forming the contact is largely shifted from the base. However, the second embodiment is not limited to this, and shows an effective effect in that even if there is no misalignment, a margin for misalignment does not need to be provided in design.
[0191]
Next, as shown in FIG. 4E, the side wall of the second coating film 226 made of a silicon nitride film is formed on the side surface of the contact hole and the exposed surface of the gate stack 201. First, a silicon nitride film is deposited on the entire exposed surface by using a CVD method having good step coverage. Next, the silicon nitride film is etched by an etching back method using anisotropic selective etching so as to expose the semiconductor substrate 201 while keeping the gate electrode 203 covered. Therefore, a short circuit between the contact of the source / drain diffusion region and the gate electrode can be prevented. Here, when the contact hole is small, the deposited film thickness of the silicon nitride film may be reduced so that the semiconductor substrate is exposed. However, if the gate electrode is too thin, the gate electrode is exposed. As described above, the second coating film 226 is formed.
[0192]
Next, as shown in FIG. 4F, a contact 225 is formed by embedding a contact material in the contact hole. Further, the contact material is etched on the interlayer insulating film 223 using a photolithography and etching process to form a wiring pattern.
[0193]
With the above manufacturing method, not only can a 2-bit (quaternary) semiconductor memory device be formed, but also a short circuit between the source / drain diffusion region and the semiconductor substrate due to the deep etching of the semiconductor substrate can be prevented. By suppressing the roughness, it is possible to suppress a contact failure between the source / drain diffusion region and the upper wiring, and further to prevent a short circuit between the contact to the source / drain diffusion region and the gate electrode, thereby avoiding a short circuit. There is no need to consider the misalignment margin. Therefore, it is possible to significantly reduce the occupied area and provide a low-cost semiconductor memory device.
[0194]
Further, as described above, it is possible to provide a semiconductor memory device having the above effects at low cost without adding a special process.
[0195]
(Third embodiment)
A semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIG.
[0196]
The third embodiment uses substantially the same steps as those of the semiconductor memory device of the second embodiment. However, the differences are as follows. As shown in FIG. 4D, in the second embodiment, the first coating film 221 exposed in the contact hole is removed by using isotropic etching. Instead, the first coating film 321 is left in the side wall shape using anisotropic etching. By doing so, since the charge holding portions on the left and right of the gate electrode are formed by the same process, the film quality is the same, the variation in the memory effect between the left and right charge holding portions is reduced, and a highly reliable semiconductor memory device can be provided. The second coating film 326 does not need to be made of a film material such as a silicon nitride film that retains electric charges in the second embodiment, and may be any insulator having good step coverage, such as an oxide film or an acid film. A nitride film may be used.
[0197]
Hereinafter, the manufacturing process of the semiconductor memory device will be described step by step with reference to FIGS.
[0198]
First, a structure similar to that of the semiconductor memory device of the second embodiment shown in FIG. 3C is formed by the method of manufacturing the semiconductor memory device of the second embodiment.
[0199]
Next, as shown in FIG. 5A, the first coating film 321 made of the silicon nitride film below the contact hole 324 is etched back by anisotropic selective etching, and the exposed side surface of the gate stack 308 is formed. Leave in the side wall shape. In this way, the etching of the interlayer insulating film 323 is once stopped by the first coating film 321, and then the first coating film 321 is etched to completely open the contact hole 324. In this manner, a short circuit between the source / drain diffusion region 313 and the substrate caused by deeply etching the semiconductor substrate can be prevented, the surface roughness of the semiconductor substrate can be suppressed, and contact failure can be suppressed.
[0200]
Next, as shown in FIG. 5B, the side wall of the second coating film 326 is formed on the side surface of the contact hole, the exposed surface of the gate electrode 303 and the exposed surface of the first coating film 321 remaining on the side surface of the gate stack 308. To form
[0201]
In the formation method, first, the second coating film 326 is deposited on the entire exposed surface by using the CVD method having good step coverage. Next, the second coating film 326 is etched by an etching back method using anisotropic selective etching so as to expose the semiconductor substrate 301 while keeping the gate electrode 303 covered. As described above, since the contact hole can be opened while the gate electrode 303 is covered, a short circuit between the contact 325 (shown in FIG. 5C) of the source / drain diffusion region 313 and the gate electrode 303 can be prevented.
[0202]
Here, when the contact hole is small, the deposited silicon nitride film should be thin so that the semiconductor substrate is exposed. However, if the gate electrode is too thin, the gate electrode is exposed.
[0203]
Next, as shown in FIG. 5C, a contact material is embedded in the contact hole to form a contact 325. Further, the contact material is etched on the interlayer insulating film 323 using a photolithography and etching process to form a wiring pattern.
[0204]
With the above manufacturing method, not only can a 2-bit (quaternary) semiconductor memory device be formed, but also a short circuit between the source / drain diffusion region and the semiconductor substrate due to the deep etching of the semiconductor substrate can be prevented. By suppressing the roughness, it is possible to suppress a contact failure between the source / drain diffusion region and the upper wiring, and further to prevent a short circuit between the contact to the source / drain diffusion region and the gate electrode, thereby avoiding a short circuit. There is no need to consider the misalignment margin. Therefore, it is possible to significantly reduce the occupied area and provide a low-cost semiconductor memory device.
[0205]
Further, as described above, it is possible to provide a semiconductor memory device having the above effects at low cost without adding a special process.
[0206]
(Fourth embodiment)
A semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to FIGS.
[0207]
The fourth embodiment uses substantially the same steps as those of the semiconductor memory devices of the second and third embodiments. However, the differences are as follows. That is, the third coating film 427 is provided on the upper part of the gate stack, and the second coating film is not formed in the contact holes shown in FIGS. Thereby, as compared with the effect of the third embodiment, since the etching for forming the gate electrode can be performed using the hard mask (the third coating film mask), a gate stack having a good shape suitable for miniaturization can be obtained. Since it can be formed, and further, there is no need to form a second coating film, the process is greatly simplified and the manufacturing cost is reduced.
[0208]
Hereinafter, the manufacturing process of the semiconductor memory device of the fourth embodiment will be described step by step along FIGS. 6A to 6C and FIGS. 7D to 7E.
[0209]
As shown in FIG. 6A, a gate insulating film 402 having a MOS structure, a gate electrode 403, and a gate electrode 403 having undergone a MOS (metal-oxide-semiconductor) formation process on a semiconductor substrate 401 having a p-type conductivity. The third coating film 427, that is, the gate stack 408 is formed.
[0210]
A typical MOS formation process at this time is as follows.
[0211]
First, an impurity diffusion region is formed near an element isolation region and a surface of a semiconductor substrate by the same method of manufacturing a semiconductor memory device as in the second embodiment.
[0212]
Further, an insulating film and a gate electrode material are sequentially formed on the exposed surface of the semiconductor substrate by the same method of manufacturing a semiconductor memory device as in the second embodiment.
[0213]
Next, a third coating film is formed on the entire surface of the gate electrode material. Here, the material of the third coating film may be any material that can prevent a short circuit between the gate electrode and the contact to the source / drain diffusion region, such as a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. A single-layer film or a laminated film of a high dielectric film such as an aluminum oxide film, a titanium oxide film, a tantalum oxide film, and a hafnium oxide film. Among them, a silicon nitride film is preferable.
[0214]
Next, a desired photoresist pattern is formed on the third coating film by a photolithography process, gate etching is performed using the photoresist pattern as a mask, and a gate electrode material and a gate insulating film are etched. Thus, the structure shown in FIG. 6A is formed.
[0215]
That is, the gate insulating film 402, the gate electrode 403, the third covering film 427, and the gate stack 408 including them are formed. Although not shown, the gate insulating film need not be etched at this time. When used as an injection protection film during the next step of impurity injection without etching, the step of forming the injection protection film can be simplified.
[0216]
Note that, as described above, the materials of the gate insulating film 402 and the gate electrode 403 may be materials used in a logic process in accordance with the scaling rule of that era, and are not limited to the above materials.
[0219]
Further, since the third coating film 427 functions as an etching stopper at the time of etching the first coating film 421 in a later step, if the same material as the first coating film, that is, a nitride film is used, the third coating film 427 is etched. It is preferable to form a film having a thickness large enough not to expose the upper surface of the gate electrode. In the case where a material different from that of the first coating film is used, a material having a high etching selectivity may be used. For example, an oxide film may be used.
[0218]
Further, the gate stack 408 may be formed by the following method. As described above, an insulating film, a gate electrode material, and a third coating film are sequentially formed on the exposed surface of the semiconductor substrate. Next, a photoresist pattern for forming a gate stack similar to the above is formed on the third coating film, and the third coating film is etched to form the third coating film shown in FIG. A cover film 427 is formed. Next, the photoresist pattern is removed, and the gate electrode material is etched using the third coating film as an etching mask. Next, the structure of FIG. 3A is formed by etching the exposed portion of the gate insulating film. When the gate stack is formed in this manner, the selectivity at the time of etching, that is, the selectivity between the gate electrode material and the gate insulating film material can be increased, and the etching of the thin film gate insulating film can be performed without etching the substrate. This makes it possible to form a gate stack suitable for miniaturization, reduce the area occupied by elements, and reduce the manufacturing cost per element.
[0219]
Although not shown, the gate insulating film need not be etched at this time for the same reason as described above.
[0220]
Next, as shown in FIG. 6B, a first coating film 421 made of a silicon nitride film is formed on the exposed surfaces of the gate stack 408 and the semiconductor substrate 401 by the same method as in the second embodiment. I do.
[0221]
Next, as shown in FIG. 6C, a source / drain diffusion region 413 is formed, an interlayer insulating film 423 is formed, and then a source / drain is formed by the same method of manufacturing a semiconductor memory device as in the second embodiment. A contact hole 424 for forming a contact connecting the drain diffusion region 413 and the wiring is formed in the interlayer insulating film.
[0222]
Here, when the conventional manufacturing method is used, it is necessary to form the contact hole in consideration of a sufficient misalignment margin so as not to be connected to the gate electrode. However, according to the manufacturing method of the present embodiment, the contact hole may be shifted and slightly applied to the gate electrode. Therefore, as compared with the related art, it is not necessary to form a contact hole with a margin for misalignment in consideration of a sufficient margin from the gate electrode, and the contact and the gate electrode are formed with a portion that actually overlaps. Therefore, the area occupied by one element can be extremely reduced, and a semiconductor memory device with low manufacturing cost can be provided.
[0223]
Furthermore, according to the present embodiment, unlike the other embodiments, the misalignment of the contacts is considerably large, and even if the contact holes are formed so as to greatly extend over the gate electrode, the other embodiments do not. The short circuit between the gate electrode and the contact can be suppressed without increasing the thickness of the required second coating film, so that the occupied area can be sufficiently reduced as compared with the other embodiments. And a semiconductor memory device with low manufacturing cost can be provided.
[0224]
Next, as shown in FIG. 7D, the first coating film 421 below the contact hole 424 is etched by anisotropic selective etching by the same method for manufacturing a semiconductor memory device as in the third embodiment. Backing is performed to leave a side wall shape on the side surface of the gate stack 408.
[0225]
Here, since the third coating film 427 is used as an etching stopper as described above, the gate electrode 403 is not exposed.
[0226]
However, as shown, the first insulating film completely formed in the side wall shape on the side surface of the gate stack may be separated from the first insulating film on the gate stack, or may not be separated. . In the case shown, the alignment in the photolithography process for forming the contact is largely deviated from the base. However, the present invention is not limited to this, and even when there is no misalignment, an effective effect is exhibited in that it is not necessary to allow a margin for misalignment in design.
[0227]
In this manner, the etching of the interlayer insulating film 423 is once stopped by the first coating film 421, and then the first coating film 421 is etched to completely open the contact hole 424. By doing so, a short circuit between the source / drain diffusion region and the substrate caused by deeply etching the semiconductor substrate can be prevented, the surface roughness of the semiconductor substrate can be suppressed, and contact failure can be suppressed.
[0228]
Next, as shown in FIG. 7E, a contact material is embedded in the contact hole to form a contact 425. Further, the contact material is etched on the interlayer insulating film using a photolithography and etching process to form a wiring pattern.
[0229]
According to the above method of manufacturing a semiconductor memory device, not only can a 2-bit (quaternary) semiconductor memory device be formed, but also a short circuit between a source / drain diffusion region and a substrate caused by deeply etching a semiconductor substrate can be prevented. By suppressing the surface roughness of the semiconductor substrate, contact failure between the source / drain diffusion region and the upper wiring is suppressed, and furthermore, a short circuit between the contact to the source / drain diffusion region and the gate electrode is prevented, thereby causing a short circuit. It is not necessary to consider the misalignment margin to avoid. Therefore, it is possible to significantly reduce the occupied area and provide a low-cost semiconductor memory device.
[0230]
Further, as described above, it is possible to provide a semiconductor memory device having the above effects at low cost without adding a special process.
[0231]
(Fifth embodiment)
A semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to FIGS.
[0232]
The fifth embodiment is substantially the same as the steps and the structure described in the second embodiment, but differs in the following points.
[0233]
That is, an element isolation region 528 is provided between elements. According to the present embodiment, the element isolation region is simultaneously etched by the etching for opening the contact hole, which is one of the effects of each coating film, and as a result, the contact becomes the source / drain of the semiconductor substrate 501 or the well region. It is possible to clarify the effect of preventing a defect that the source / drain diffusion region below the diffusion region is connected to the region of the opposite conductivity type and short-circuited.
[0234]
In addition, the features of this embodiment can be applied to other embodiments. In such a case, the effect of the characteristic point (having the element isolation region) applied in addition to the effect inherent in the other embodiments can be exhibited.
[0235]
The steps of manufacturing the semiconductor memory device according to the fifth embodiment will be sequentially described below with reference to FIGS. 8A to 8C and FIGS. 9D to 9F.
[0236]
First, as shown in FIG. 8A, a semiconductor device having a p-type conductivity type and having a MOS (metal-oxide-semiconductor) formation process on a semiconductor substrate 501 having an element isolation region 528 has a MOS structure. A gate insulating film 502 and a gate electrode 503, that is, a gate stack 508 are formed. Except for the method of forming the element isolation region, the same method as that of the second embodiment may be used.
[0237]
The element isolation region 528 is formed by a known method. The element isolation region can prevent leakage current from flowing between adjacent devices. However, such device isolation regions need not be formed between devices that share a source / drain diffusion region between adjacent devices. The known method for forming an element isolation region is to use a known LOCOS oxide film or a method using a known trench isolation region to achieve the purpose of isolating elements using other known methods. Anything can be used. In the present embodiment, a case will be described in which most of the element isolation regions are formed of an oxide film. However, the effect of the present embodiment can be obtained as long as the material constituting most of the element isolation region is a material other than the oxide film, which is etched simultaneously with the contact etching of the interlayer insulating film.
[0238]
Next, as shown in FIG. 8B, a first coating film 521 made of a silicon nitride film is formed on the exposed surfaces of the gate stack 508, the semiconductor substrate 501, and the element isolation region 528. After that, source / drain diffusion regions 513 are formed. Each forming method may be the same method of manufacturing a semiconductor memory device as described in the second embodiment. After the formation of the source / drain diffusion region 513, a first coating film 521 made of a silicon nitride film may be formed. In this case, it is possible to provide a semiconductor memory device in which implantation damage does not occur in the nitride film, film quality is good, and good memory characteristics are exhibited.
[0239]
Next, as shown in FIG. 8C, an interlayer insulating film 523 made of an oxide film is formed, and then a contact hole 524 for forming a contact connecting the source / drain diffusion region 513 and the wiring is formed in the interlayer insulating film. 523. Each step may be the same method as described in the second embodiment.
[0240]
However, in order to clearly show the effect of the present embodiment, the position of the contact hole is a case where at least a part of the contact hole is located above the element isolation region 528. However, the effect is exhibited even if it is not actually located at the position of the contact hole as in the present embodiment. In other words, in the case of the memory device described in the prior art, the design must be made with a margin for misalignment between the device isolation region and the contact hole, for example, and the occupied area of the device has increased. In the case of the embodiment, since it is not necessary to provide a sufficient margin for misalignment, the area occupied by the elements is reduced, and the manufacturing cost per element can be reduced. More specifically, the above-described effect, which is a characteristic effect of the present embodiment, is generated by having each coating film, and is generated from the time of element design. It cannot be measured.
[0241]
Here, in the case of the conventional memory element, the etching for opening the contact hole is performed without taking a sufficient misalignment, and the position of the contact hole is over the element isolation region 528 as shown in the figure. Since the first covering film 521 made of a nitride film is not provided and both the interlayer insulating film material and the material occupying most of the element isolation region are oxide films, the element isolation region is etched by contact etching. The etching depth of the element isolation region depends on the amount of over-etching related to the etching variation. A contact is formed. Therefore, the source / drain diffusion region and the substrate are connected via the contact, and a failure due to a short circuit occurs.
[0242]
On the other hand, when the first coating film 521 made of a nitride film is formed, the etching for opening the contact hole can be stopped by the first coating film having a different material from that of the interlayer insulating film. In a later step, when the first coating film made of a nitride film is etched to completely open the contact hole, only the first coating film is etched, and the element isolation region is almost etched. Can not. Therefore, defects due to connection between the source / drain diffusion region and the semiconductor substrate via the contact can be suppressed, and a semiconductor memory device with good yield and low manufacturing cost can be provided.
[0243]
Recently, a technique of forming a shallow source / drain diffusion region has been actively used in order to suppress a short channel effect. Therefore, there is a high risk of a short circuit, and an etching technique using this coating film is very difficult. It is effective for
[0244]
Next, as shown in FIG. 9D, the first coating film 521 under the contact hole is removed by using isotropic selective etching or anisotropic selective etching. As described above, the etching of the interlayer insulating film is temporarily stopped by the first coating film 521, and then the first coating film 521 is etched to completely form a contact hole. By doing so, a short circuit between the source / drain diffusion region and the substrate due to the deep etching of the semiconductor substrate can be prevented, the surface roughness of the semiconductor substrate can be easily suppressed, and the contact failure can be suppressed. As the isotropic selective etching, wet etching may be used, or dry isotropic etching using remote plasma may be used. Further, as described above, short-circuit failure between the source / drain diffusion region and the substrate due to the etching of the element isolation region 528 can be suppressed.
[0245]
However, as shown, not only when the first coating film on one side surface of the gate stack is completely removed and the gate stack is exposed, the first coating film on both side surfaces of the gate stack is removed. In some cases, the fourth embodiment does not expose the gate stack. In the case shown, the alignment in the photolithography process for forming the contact is largely deviated from the base. However, the fifth embodiment is not limited to this, and shows an effective effect in that even if there is no misalignment, a margin for misalignment does not need to be provided in design.
[0246]
Next, as shown in FIG. 9E, the side wall of the second coating film 526 made of a silicon nitride film is formed on the side surface of the contact hole and the exposed surface of the gate stack. As a forming method, the method for manufacturing a semiconductor memory device described in the second embodiment may be used.
[0247]
Next, as shown in FIG. 9F, a contact material is embedded in the contact hole to form a contact 525. Further, the wiring pattern is formed by etching the contact material on the interlayer insulating film 523 using photolithography and an etching process.
[0248]
According to the above method of manufacturing a semiconductor memory device, not only can a 2-bit (quaternary) semiconductor memory device be formed, but also a short circuit between a source / drain diffusion region and a substrate caused by deeply etching a semiconductor substrate can be prevented. By suppressing the surface roughness of the semiconductor substrate, contact failure between the source / drain diffusion region and the upper wiring is suppressed, and further, a short circuit between the contact to the source / drain diffusion region and the gate electrode is prevented. A short circuit between the source / drain diffusion layer and the semiconductor substrate is suppressed. As a result, it is not necessary to consider a misalignment margin for avoiding a short circuit or the like, so that the occupied area can be greatly reduced and a low-cost semiconductor memory device can be provided.
[0249]
Further, as described above, it is possible to provide a semiconductor memory device which has the above-described effects at low cost without adding a special step, that is, without adding a special mask.
[0250]
(Sixth embodiment)
A semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to FIGS.
[0251]
The present embodiment is almost the same as the process described in the fifth embodiment, but differs in the following points.
[0252]
That is, as shown in FIG. 10C, before forming the first coating film 621 (shown in FIG. 10D), the memory function body 611 having a charge holding function is formed. As shown in FIG. 11G, an element having the same shape as that of the semiconductor memory device shown in FIG. 2 is formed except for an element isolation region.
[0253]
With this structure, a memory function body is formed, and as shown in FIG. 10C, the silicon nitride film 617 having a function of retaining charges is sandwiched between the first insulator 612 and the side wall insulator 616. It is possible to provide a semiconductor memory device in which the held charge is suppressed from being dispersed and the holding characteristics are good. In addition, with the structure in which the silicon nitride film 617 is sandwiched between the first insulator 612 and the sidewall insulator 616, the charge injected during the rewrite operation is prevented from being dispersed to the gate electrode or another node. As a result, the charge injection efficiency is increased, and a higher-speed operation becomes possible. Furthermore, since the first covering film 621 (shown in FIG. 10D) covers the memory function body 611 and the gate stack 608, impurity outdiffusion causing depletion of impurities in the gate electrode 603 is prevented. The yield is improved. Further, it has a function of reducing the element occupation area for a plurality of contacts, and also suppresses a contact failure. Since a plurality of functions relating to the first coating film 621 can be achieved only by forming the coating film, the steps can be simplified and a semiconductor memory device with low manufacturing cost can be provided.
[0254]
In this embodiment, the case where the element isolation region is formed is described. However, it is needless to say that the case where the element isolation region is not formed is also effective. In that case, effects other than the effects related to element isolation among the effects described in the present embodiment are exhibited.
[0255]
Hereinafter, the manufacturing process of the semiconductor memory device according to the sixth embodiment will be described step by step with reference to FIGS. 10 (a) to 10 (d) and FIGS. 11 (e) to 11 (g).
[0256]
First, as shown in FIG. 10A, a semiconductor substrate 601 having a p-type conductivity and having an element isolation region 628 has a MOS structure formed by a MOS (metal-oxide-semiconductor) formation process. A gate insulating film 602 and a gate electrode 603, that is, a gate stack 608 are formed. Except for the method of forming the element isolation regions, the same forming method as that of the second embodiment may be used.
[0257]
The element isolation region 628 is formed by a known method. The element isolation region can prevent leakage current from flowing between adjacent devices. However, some devices do not form such an element isolation region between devices having a common source / drain diffusion region between adjacent devices. The known method for forming an element isolation region is to use a known LOCOS oxide film or a method using a known trench isolation region to achieve the purpose of isolating elements using other known methods. Anything can be used. In the present embodiment, a case will be described in which most of the element isolation regions are formed of an oxide film. However, the same effect can be obtained by using a material other than an oxide film as a material constituting most of the element isolation regions, as long as the material is simultaneously etched during the contact etching of the interlayer insulating film.
[0258]
Next, as shown in FIG. 10B, a first insulating film 609 made of an oxide film is formed substantially uniformly on the exposed surfaces of the gate stack 608, the semiconductor substrate 601 and the element isolation region 628. Although an oxide film is used here as the first insulating film 609, a film having high withstand voltage, low leakage current, and high reliability is preferable because the first insulating film 609 is an insulating film through which electrons pass. For example, similarly to the material of the gate insulating film 602, a thermal oxide film, N ₂ An oxide film such as an O oxide film or a NO oxide film is used. The oxide film thickness is preferably about 1 nm to 20 nm. Furthermore, when the insulating film is formed thin enough to allow a tunnel current to flow, the voltage required for charge injection / erase can be reduced, thereby reducing power consumption. In this case, a typical thickness is preferably about 1 nm to 5 nm.
[0259]
Next, a nitride film 617 is deposited substantially uniformly. Here, a nitride film is used, but instead of a nitride film, a material such as an oxynitride film capable of holding a substance having electric charges such as electrons and holes, an oxide film having a charge trap, or a material such as polarization. Materials such as ferroelectrics that can induce charges on the surface of the memory function body due to phenomena, and materials that have a structure that has a substance that can hold charges such as floating polysilicon or silicon dots in an oxide film. Any material can be used as long as it can hold and induce electric charges, and the same effect can be obtained. The nitride film thickness may be, for example, about 2 nm to 100 nm.
[0260]
Further, a second insulating film 629 made of an oxide film is formed substantially uniformly. As the second insulating film, a film having good step coverage using CVD (Chemical Vapor Deposition) such as HTO (High Temperature Oxide) is preferably used. When an oxide film is used, the thickness may be about 5 nm to 100 nm. Further, the second insulating film may be formed by treating the surface of the nitride film using heat treatment. In this case, a thermal oxide film, N ₂ An oxide film such as an O oxide film or a NO oxide film is used. The oxide film thickness is preferably about 1 nm to 20 nm. Furthermore, when the insulating film is formed thin enough to allow a tunnel current to flow, the voltage required for charge injection / erase can be reduced, thereby reducing power consumption. In this case, a typical thickness is preferably about 1 nm to 5 nm.
[0261]
Here, by forming the first insulating film 609, the nitride film 617 having a function of retaining electric charges comes into contact with the semiconductor substrate and the gate electrode via the insulating film. Can be suppressed. Thus, a semiconductor memory device having good charge retention characteristics and high long-term reliability is formed.
[0262]
Next, as shown in FIG. 10C, a memory function body 611 including a first insulator 612, a nitride film 617, and a sidewall insulator 616, and a source / drain diffusion region 613 are formed. Here, the source / drain diffusion regions 613 may be formed before the formation of the memory function body 611, or may be formed after the formation of the memory function body 611, and have the same effect. However, when the source / drain diffusion region 613 is formed before the formation of the memory function body 611, the injection protection film is not required, and the process can be simplified. Here, the case where the source / drain diffusion region 613 is formed after the formation of the memory function body 611 will be described.
[0263]
First, the side wall insulator 616 is formed on the side wall of the gate stack 608 via the first insulating film 609 and the nitride film 617 by anisotropically etching the second insulating film 629. The etching is preferably performed under such a condition that the second insulating film 629 can be selectively etched and the etching selectivity with the nitride film 617 is large.
[0264]
However, a similar effect can be obtained when an electrically conductive material (conductor or the like) 614 such as a conductor or a semiconductor is used instead of the nitride film. However, in this case, if the left and right memory function bodies 611a and 611b become conductive after the formation of the memory function body 611, the 2-bit operation cannot be performed. Therefore, it is necessary to electrically insulate the left and right memory function bodies 611a and 611b. Therefore, as shown in the top view of FIG. 12A, a part (removed region) of the sidewall insulator 616 is removed by etching. The removal method uses a known photolithography process to pattern the photoresist so as to cover the sidewall insulator 616 other than the removal region.
[0265]
Thereafter, as shown in FIG. 16C, anisotropic etching or isotropic etching is performed to etch the side wall insulator 616 in the removed region. This etching is preferably performed under the condition that the etching selectivity with the nitride film 617 is large. However, it is desirable that the removal region exists on the element isolation region.
[0266]
Next, using the sidewall insulator 616 as an etching mask, the nitride film 617 is isotropically or anisotropically etched to form an L-shaped nitride film 617 on the sidewall of the gate stack 608 via the first insulating film 612. To form In this case, the etching is preferably performed under such a condition that the nitride film 617 can be selectively etched, and the etching selectivity with the first insulating film 609 made of an oxide film and the sidewall insulator 616 is large.
[0267]
However, when a material (conductor or the like) 614 is used instead of the nitride film 617, as shown in the top view of FIG. 12A, a part (removed region) of the sidewall insulator 616 is etched by a previous step. If the etching in this step is performed using isotropic etching, a part of the material (conductor or the like) 614 is removed together with the side wall insulator 616 by this step, and FIG. The shape is as shown.
[0268]
Therefore, as shown in FIG. 10C, the left and right memory function bodies 611 can be electrically insulated.
[0269]
Next, a first insulator 612 is formed on the side wall of the gate stack 608 by anisotropically etching the first insulating film 609. In this case, it is preferable that the etching be performed under the condition that the first insulating film 609 can be selectively etched and the etching selectivity of the nitride film 617, the gate electrode 603, and the semiconductor substrate 601 is large.
[0270]
As described above, the memory function body 611 including the first insulator 612, the L-shaped nitride film 617, and the sidewall insulator 616 is formed on the side wall of the gate stack 608.
[0271]
Next, source / drain diffusion regions 613 are formed. The forming method may be the same as that described in the second embodiment. However, unlike the second embodiment, since the source / drain diffusion region is not formed by injecting impurities into the semiconductor substrate 601 through the first coating film 621, the implantation energy is adjusted and the first coating is performed. It is preferable to perform the implantation so as to be shallow as much as the thickness of the film 621 does not exist so that the junction is formed in the same manner as in the second embodiment.
[0272]
At this time, as shown in FIG. 12C, a part (removed region) of the sidewall insulator 616 and the nitride film 617 has been removed by etching. In this step, anisotropic etching is used. Therefore, a part of the first insulator 612 which is not covered with the nitride film 617 is etched, but a part remains around the gate electrode 603 in a state as shown in FIG. Here, since a part of the first insulator 612 covers the outer periphery of the gate electrode 603, a short circuit between the contact to the source / drain diffusion region or the memory function body and the gate electrode or the gate electrode contact is suppressed. be able to. As a result, miniaturization becomes easy, and high integration of the memory becomes possible.
[0273]
However, both the first insulator 612 and the sidewall insulator 616 may be formed of the same material such as an oxide film, in which case a large etching selectivity cannot be obtained. Therefore, in this case, it is necessary to appropriately reduce the etching amount when forming the sidewall insulator in consideration of the etching amount of the sidewall insulator when etching the first insulating film.
[0274]
Further, the process from the structure in FIG. 10B to the structure in FIG. 10C may be performed in one step. That is, the first insulating film 609, the second insulating film 629, and the nitride film 617 can be selectively etched together, and the anisotropy using a large etching selectivity with the gate electrode 603 material and the semiconductor substrate 601 material can be obtained. By performing the etching, a part that normally requires three steps can be performed in one step, so that the number of steps can be reduced and the manufacturing cost can be reduced.
[0275]
However, in this case, when an electrically conductive material (conductor or the like) 614 such as a conductor or a semiconductor is used instead of the nitride film 617, as shown in FIG. (Shown in FIG. 10C) must be electrically insulated. Therefore, after the memory function body is formed around the entire gate stack 608 by the above-described method, as shown in FIG. 12C, a part (removed region) of the sidewall insulator 616 is removed by etching. The removal method uses a known photolithography process to pattern the photoresist so as to cover the sidewall insulator 616 other than the removal region. After that, isotropic etching is performed to remove a removal region which is an exposed portion of the sidewall insulator 616. It is preferable that the etching be performed under the condition that the sidewall insulator 616 can be selectively etched and the etching selectivity with the material (a conductor or the like) 614 is large.
[0276]
Further, a part (removed region) of the material (conductor or the like) 614 is removed by etching. In the removal method, anisotropic etching or isotropic etching is performed by using the photoresist formed earlier or the sidewall insulator 616 as an etching protection film and covering a material (conductor or the like) 614 other than the removal region. The removal region that is the exposed portion is removed. It is preferable that the etching be performed under the condition that a material (a conductor or the like) 614 can be selectively etched and the etching selectivity with the first insulator 612 is large.
[0277]
In this step, the portion of the first insulator remains so as to cover the outer periphery of the gate electrode, thereby suppressing a short circuit between the contact to the source / drain diffusion region or the memory function body and the gate electrode or the gate electrode contact. can do. As a result, miniaturization becomes easy, and high integration of the memory becomes possible.
[0278]
Further, as shown in FIG. 12D, the removed regions of the memory function bodies 611a and 611b formed so as to surround the gate electrode 603 may be etched at one time. That is, using a known photolithography process, the photoresist is patterned so as to cover the memory function body other than the removal area. After that, the first insulating film 609, the second insulating film 629, and the nitride film 617 can be selectively etched together, and anisotropic using a large etching selectivity with the gate electrode 603 material and the semiconductor substrate 601 material. By performing the etching, a part that normally requires three steps can be performed in one step, so that the number of steps can be reduced and the manufacturing cost can be reduced.
[0279]
Next, using the gate electrode 603 and the memory function body 611 as a mask, source / drain implantation is performed, and an existing heat treatment for activation is performed to form the source / drain diffusion region 613 in a self-aligned manner.
[0280]
Through the above steps, a memory function body was formed. The semiconductor memory device using this memory function has the following effects.
[0281]
When the charge is held in the memory function body, a part of the channel region is strongly affected by the charge, so that the drain current value changes. As a result, a semiconductor memory device for determining the presence or absence of charges is formed.
[0282]
In addition, by separately arranging the gate insulating film 2 and the memory function body 611, different scalings can be performed, and a short channel effect can be suppressed to provide a semiconductor memory device having a good memory effect.
[0283]
Further, since the nitride film 617 in the memory function body is in contact with the semiconductor substrate 601 and the gate electrode 603 via the insulating film, leakage of retained charges can be suppressed by the insulating film. Thus, a semiconductor memory device having good charge retention characteristics and high long-term reliability is formed.
[0284]
When a conductor or semiconductor is used as the memory function body, when a positive potential is applied to the gate electrode, polarization occurs in the memory function body, electrons are induced near the sidewall of the gate electrode, and electrons near the channel region decrease. I do. Thereby, injection of electrons from the semiconductor substrate or the source / drain diffusion region can be promoted, and a semiconductor memory device with high writing speed and high reliability can be formed.
[0285]
Next, as shown in FIG. 10D, a first coating film 621 made of a silicon nitride film is formed on the exposed surfaces of the gate stack 608, the memory function body 611, the semiconductor substrate 601 and the element isolation region 628. . The method for forming the first coating film 621 may be the same as the method for manufacturing the semiconductor memory device described in the second embodiment.
[0286]
Next, as shown in FIG. 11E, an interlayer insulating film 623 made of an oxide film is formed, and then a contact hole 624 for forming a contact connecting the source / drain diffusion region 613 and the wiring is formed in the interlayer insulating film. 623. Each step may be the same as the method of manufacturing the semiconductor memory device described in the second embodiment.
[0287]
Here, in order to clearly show the effect of this embodiment, the drawing shows a case where the position of the contact hole is at least partly above the element isolation region 628. However, the effect can be obtained even if the contact hole is not actually provided as in the present embodiment. In other words, in the case of the conventional memory element, it is necessary to design the element with a margin for misalignment between the element isolation region and the contact hole at the time of design, and the area occupied by the element is not large. In this case, since it is not necessary to provide a sufficient margin for misalignment, the area occupied by the elements is reduced, and the manufacturing cost per element can be reduced. More specifically, the above-described effect, which is a characteristic effect of the present embodiment, is generated by having each coating film, is generated from the time of element design, and is not a functional effect due to a completed shape. .
[0288]
Here, in the case of the conventional memory element, the etching for opening the contact hole is performed without taking a sufficient misalignment, and the position of the contact hole is over the element isolation region 628 as illustrated. Since the first covering film 621 made of a nitride film is not provided, and the material of the interlayer insulating film and the material occupying most of the element isolation region are both oxide films, the element isolation region is etched by the contact etching. The etching depth of the element isolation region depends on the amount of over-etching related to the etching variation. A contact is formed in the portion. Therefore, the source / drain diffusion region and the semiconductor substrate are connected via the contact, and a failure due to a short circuit occurs.
[0289]
On the other hand, when the first covering film 621 made of a nitride film is formed, the etching for forming the contact hole can be stopped by the first covering film 621 made of a different material from that of the interlayer insulating film 623. In a later step, when the first coating film 621 made of a nitride film is etched to completely open the contact hole, only the first coating film 621 is etched and the element isolation region 628 is etched. Can be almost not etched. Therefore, a defect due to connection between the source / drain diffusion region 613 and the semiconductor substrate 601 through the contact can be suppressed, and a semiconductor memory device with good yield and low manufacturing cost can be provided.
[0290]
In recent years, a technique of forming shallow source / drain diffusion regions has been actively used in order to suppress the short channel effect. Therefore, there is a high risk of a short circuit, and the first coating film 621 is used. The etching technique is very effective.
[0291]
Next, as shown in FIG. 11F, the first coating film 621 under the contact hole is removed by using anisotropic selective etching. The etching method may be the same as the method described in the third embodiment.
[0292]
As described above, the etching of the interlayer insulating film 623 is temporarily stopped by the first coating film 621, and then the first coating film 621 is etched to completely form a contact hole. By doing so, a short circuit between the source / drain diffusion region and the substrate due to the deep etching of the semiconductor substrate can be prevented, the surface roughness of the semiconductor substrate can be easily suppressed, and the contact failure can be suppressed. In addition, the element isolation region 628 can also suppress a short circuit between the source / drain diffusion region and the substrate due to etching.
[0293]
Next, as shown in FIG. 11G, the side wall of the second coating film 626 made of a silicon nitride film is formed on the side surface of the contact hole and the exposed surface of the gate stack. Then, a contact material is embedded in the contact hole to form a contact 625. Further, the contact material is etched on the interlayer insulating film 623 using photolithography and an etching process to form a wiring pattern.
[0294]
By the above manufacturing method, not only can a 2-bit (quaternary) semiconductor memory device be formed, but also a short circuit between the source / drain diffusion region and the substrate due to the deep etching of the semiconductor substrate can be prevented, and the surface of the semiconductor substrate can be roughened. To suppress a contact failure between the source / drain diffusion region and the upper wiring, further prevent a short circuit between the contact to the source / drain diffusion region and the gate electrode, and characteristically, the source / drain diffusion Short circuit between the layer and the semiconductor substrate is suppressed. As a result, it is not necessary to consider a misalignment margin for avoiding a short circuit or the like, so that the occupied area can be greatly reduced and a low-cost semiconductor memory device can be provided.
[0295]
Further, since the formation method for achieving the above-described functional effects can be performed without adding a complicated process, a semiconductor memory device having the above-described effects at low cost can be provided.
[0296]
Further, with the structure of the memory function body, it is possible to provide a semiconductor memory device having good holding characteristics and capable of operating at higher speed.
[0297]
(Seventh embodiment)
A semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to FIG. The semiconductor memory device according to the seventh embodiment shows the configuration of the memory function body according to the sixth embodiment. It has the following effects in addition to the effects of the sixth embodiment.
[0298]
Further, unlike the first to sixth embodiments, the first coating film does not necessarily need to be an insulating film, because the outer periphery of the memory function body is completely removed in FIGS. 13 (a) to 13 (e). Since the accumulated charge is covered with the insulator and the accumulated charge is suppressed, it is not necessary to use the first covering film as an insulator in order to prevent a short circuit between the memory function body and the contact. Any material can be used as long as the selection ratio of the material of the region can be obtained, and the same effect is exhibited.
[0299]
Here, the names of the memory functional unit and each unit thereof are defined as follows.
[0300]
As shown in FIG. 13, the memory function body includes a charge holding portion that can hold the charge and a dissipation prevention insulator that is a portion that prevents the charge from being dissipated. It is assumed that at least one of the silicon 715 and the dissipation prevention insulator includes at least one of the first insulator 712 and the sidewall insulator 716.
[0301]
That is, as shown in FIGS. 13A to 13D, the charge holding portion is a silicon dot 710, and the dissipation prevention insulator includes the first insulator 712 and the side wall insulator 716, and FIG. As shown in FIGS. 13E to 13G, the charge holding portion is made of polysilicon 715, and the dissipation prevention insulator is formed of the first insulator 712 and the sidewall insulator 716, and as shown in FIG. 13 (i) and 13 (j), the charge holding portions are silicon dots 710 and polysilicon 715, and the dissipation prevention insulator is composed of a first insulator 712 and a sidewall insulator 716. As described above, in some cases, the charge holding portion is the polysilicon 715, and the dissipation prevention insulator includes only the first insulator 712.
[0302]
In the memory function body shown in FIG. 13A, a side wall insulator 716 including one layer of silicon dots is formed on a side wall of a first insulator 712.
[0303]
In the manufacturing method, after the first insulator 712 is formed, silicon dots are formed, a deposited insulating film is deposited, an etching back step and a residue removing step are performed, and the illustrated structure is manufactured. Details of each step are shown below.
[0304]
First, a method for forming silicon dots will be described. Silicon dots 710 are grown for 2 minutes at a substrate temperature of 700 ° C. under a pressure of 1 Torr using disilane as a source gas by a CVD method. At this time, the size of the silicon dot is about 5 nm. However, the size of the silicon dot at this time is preferably about 1 nm to 50 nm. More preferably, it is desirably about 1 nm to 15 nm, which is a size that exhibits a quantum effect such as Coulomb blockade. Here, by appropriately changing and adjusting the conditions such as the source gas, the pressure, the substrate temperature, and the growth time in the CVD, it is possible to optimize and form the size, density, and the like of the silicon dots.
[0305]
Also, considering that the dot diameter is reduced due to the oxidation in the next step, by appropriately forming the dot size, a silicon dot having an optimal shape can be formed.
[0306]
Further, although not shown, it is desirable to oxidize the surface of the silicon dot 710 after the formation of the silicon dot 710. This oxidation step may use thermal oxidation. At this time, the smaller the size of the silicon dot, the slower the oxidation speed, so that the size variation of the silicon dot can be suppressed. Further, since the silicon dot surface oxide film is an insulating film through which electrons pass, any film having high withstand voltage, low leakage current, and high reliability may be used. For example, N ₂ An oxide film such as an O oxide film or a NO oxide film may be used. The film thickness of the silicon dot 710 and the semiconductor substrate (not shown) in the final shape, and the thickness of the insulating film located between the silicon dot 710 and the gate electrode is 1 nm in equivalent oxide film thickness including the first insulator 712. From about 20 nm. More preferably, when the size of the silicon dot is about 1 nm to 15 nm, the equivalent oxide film thickness is desirably about 1 nm to 10 nm. As described above, when the silicon dots are oxidized to be smaller, it is needless to say that the silicon dots need to be formed larger in consideration of the size reduction when forming the silicon dots. Further, in the case where the insulating film is formed thin enough to allow a tunnel current to flow and charges are retained by the Coulomb blockade effect using a double tunnel junction, the voltage required for charge injection / erase can be reduced. Thus, power consumption can be reduced. In this case, a typical oxide film thickness is preferably about 1 nm to 3 nm. Further, the silicon dots may be unevenly deposited without uniform height.
[0307]
Next, as a method for forming a deposited insulating film using a CVD method, a film with good step coverage using HTO (High Temperature Oxide) or LPCVD (Low Pressure Chemical Vapor Deposition) is used. Good to use. When an HTO film is used, the film thickness may be about 20 nm to 100 nm. The deposited insulating film is etched back into a sidewall spacer shape in a subsequent step, and functions as an implantation mask when implanting impurities for forming source / drain diffusion regions. In other words, this is an important factor for defining the shape of the source / drain diffusion region, particularly the offset width from the end of the gate electrode. And an optimum offset width can be obtained.
[0308]
Next, by performing anisotropic etching of the deposited insulating film and the silicon dots 710, a memory function body including the silicon dots 710 in a side wall spacer shape is formed on the side wall of the gate stack. At this time, by selecting different materials as the materials of the first insulator 712 and the deposited insulating film, the selectivity between these films can be increased, and this step can be performed efficiently and easily. Become. For example, a nitride film is preferably used as a material of the first insulator 712, and an oxide film is preferably used as a material of the deposited insulating film.
[0309]
However, in many cases, a silicon substrate is usually used as a semiconductor substrate. In this case, silicon is used as a material for the dots, so that the silicon dots cannot be etched and etching residues may be left out. After the isotropic etching, the remaining insulating film is preferably isotropically etched by wet etching using hydrofluoric acid or the like, so that silicon residues are lifted off. Further, when a residue remains, it is preferable to perform oxidation so that the surface or the whole of the residue is oxidized, and then remove the residue by wet etching using hydrofluoric acid or the like.
[0310]
As described above, by using a structure in which electric charges are retained by silicon dots, even if an insulating film leaks, which deteriorates the memory retention characteristics, all the retained electric charges do not leak, and the insulating film leak portion The charges held in the neighboring silicon dots only leak. Therefore, a semiconductor memory device having good holding characteristics is provided.
[0311]
Further, by oxidizing the surface of the silicon dot, a variation in the size of the silicon dot can be suppressed, and a semiconductor memory device with less variation in electrical characteristics is provided.
[0312]
Next, in the memory function body shown in FIG. 13B, a sidewall insulator 716 including two layers of silicon dots 710 is formed on the sidewall of the first insulator 712.
[0313]
As a manufacturing method, after the first insulator 712 is formed, the silicon dots 710 are formed by the method described in FIG. 13A and the surface of the silicon dots is oxidized. Thereafter, silicon dots are further formed by the same method, and thereafter, a deposited insulating film is deposited, and an etching back step and a residue removing step are performed to produce the illustrated structure. It is preferable to use the method shown in FIG.
[0314]
With this structure, since the silicon dots form multiple dots of two or more in the vertical direction, the memory holding performance is dramatically improved as compared with the single dots. Further, as compared with the single dot, the number of silicon dots in the memory function film increases, so that the number of retained charges increases. Therefore, a difference in threshold voltage between writing and erasing and a difference in driving current increase, so that a semiconductor memory device having a large voltage margin and improved reliability can be formed.
[0315]
Next, in the memory function body shown in FIG. 13C, a side wall insulator 716 including three layers of silicon dots 710 is formed on the side wall of the first insulator 712.
[0316]
In the manufacturing method, after the first insulator 712 is formed, the silicon dots 710 are formed by the method shown in FIG. 13A and the surface of the silicon dots is oxidized. Further, a silicon dot 710 is formed, and the surface of the silicon dot is oxidized. Thereafter, a silicon dot is further formed, and then a deposited insulating film is deposited, and an etching back step and a residue removing step are performed to produce the illustrated structure. It is preferable to use the method shown in FIG.
[0317]
According to this structure, since the silicon dots constitute multiple dots of three or more in the vertical direction, the memory retention performance is significantly improved as compared with single and double dots. Further, as compared with the single and double dots, the number of silicon dots in the memory function film increases, so that the number of retained charges increases. Therefore, a difference in threshold voltage between writing and erasing and a difference in driving current increase, so that a semiconductor memory device having a large voltage margin and improved reliability can be formed.
[0318]
FIG. 13D shows that the sidewall insulator 716 in which the silicon dots 710 are stacked on the sidewall portion of the first insulator 712 is formed to a thickness enough to fill the inside of the sidewall insulator 716. Things.
[0319]
13A to 13C, the steps of forming the silicon dots and oxidizing may be repeated a plurality of times as appropriate. As compared with the case of single, double and triple dots, the memory retention performance is dramatically improved. Furthermore, compared to single, double and triple dots, the number of silicon dots in the memory function film increases, so that the number of retained charges increases. Therefore, a difference in threshold voltage between writing and erasing and a difference in driving current increase, so that a nonvolatile memory with a large voltage margin and improved reliability can be formed.
[0320]
FIG. 13E illustrates a structure in which a sidewall insulator 716 including a small sidewall-shaped polysilicon 715 near the charge injection portion is formed on the sidewall of the first insulator 712. .
[0321]
After the first insulator 712 is formed, polysilicon is deposited by a method with good step coverage such as LPCVD and etched back, so that charges are injected into the corners of the memory function body as shown in the figure. It is formed limited to. After that, a deposited insulating film is deposited and an etching back step is performed to produce the illustrated structure.
[0322]
With this structure, electrons injected by writing are limited to the vicinity of the vicinity of the channel, so that the electrons can be easily removed by erasing, and erroneous erasing can be prevented. Furthermore, the amount of charge per unit volume can be increased by reducing the volume of the memory function body that retains the charge without changing the amount of injected charge, thereby efficiently writing / erasing electrons. And a semiconductor memory device with a high write / erase speed is provided. Further, since the sidewall insulator 716 covers the polysilicon 715, a short circuit between the polysilicon 715 and the contact can be prevented in the step of contacting the gate electrode or the source / drain diffusion region. Here, it is important that different materials are used for the interlayer insulating film and the sidewall insulator, such as an oxide film and a nitride film, respectively. Therefore, the design contact margin may be small, so that it is miniaturized. Therefore, a semiconductor memory device with reduced cost is provided.
[0323]
FIG. 13F shows a structure in which a sidewall insulator 716 including a narrow sidewall-shaped polysilicon 715 near the charge injection portion is formed on the sidewall of the first insulator 712. .
[0324]
The forming method may be the same as the method shown in FIG. 13E, and can be formed by adjusting the deposited film thickness and the etching amount of polysilicon. The effect is the same as that of FIG.
[0325]
FIG. 13G shows a memory function body in which polysilicon 715 is formed on the side wall of the first insulator 712 and a side wall insulator 716 is formed on the side wall.
[0326]
As a forming method, after forming the first insulator 712, polysilicon is deposited by a method having good step coverage such as LPCVD, and subsequently, a deposited insulating film is deposited. After that, the polysilicon and the deposited insulating film are etched to form the illustrated structure. With this structure, the same effect as that of FIG. 13E can be obtained.
[0327]
FIG. 13H shows a memory function body in which a polysilicon 715 is formed on a side wall of a first insulator 712 and a side wall insulator 716 including a plurality of silicon dots 710 is formed on the side wall. It is.
[0328]
The formation method is such that after forming the first insulator 712, polysilicon is deposited by a method with good step coverage such as LPCVD, the surface is oxidized, silicon dots are formed, and subsequently a deposited insulating film is deposited. This structure is preferably formed using the steps shown in FIGS. 13A and 13G. With this structure, by forming a semiconductor or conductor film between the semiconductor substrate and the plurality of fine particles, it is possible to suppress the influence of variations in the positions and sizes of the fine particles on the threshold voltage of the field effect transistor. can do. Therefore, a semiconductor memory device in which erroneous reading is suppressed can be provided. Also, in the silicon dot forming step, a memory functional unit having the respective effects added by using the structure shown in FIG. 13B to FIG. Can be formed.
[0329]
Also, the following steps can be used.
[0330]
After the formation of the first insulator 712, polysilicon is deposited by a method having good step coverage such as LPCVD, and the surface is oxidized. After that, a process is performed under the same conditions as those for depositing the polysilicon. In this step, silicon dots are formed due to the difference in roughness of the underlying oxide film between the initial polysilicon deposition and the current step. When such silicon dots are formed, if the silicon dots are too small, the Coulomb blockade effect is too large, making it difficult to inject electric charges. The thickness is about 1 nm to 20 nm. As a typical example, similarly to the above-mentioned polysilicon film, SiH at 620 ° C. ₄ A 5 nm-thick polysilicon film and silicon dots can be formed by a low pressure chemical vapor deposition (LPCVD) method in an atmosphere.
[0331]
FIG. 13I shows a memory function body in which polysilicon 715 is formed on the side wall of the first insulator 712. In the formation method, after the first insulator 712 is formed, polysilicon is deposited by a method with good step coverage such as LPCVD, and is anisotropically etched to form a memory function body having a sidewall spacer shape. This structure has a large polysilicon region and can hold a large amount of electric charge, so that multi-value can be easily achieved. Further, since the structure is simple, the manufacturing is easy and the manufacturing cost can be reduced.
[0332]
FIG. 13J shows a memory function body having a structure in which polysilicon is reduced on the side wall of the first insulator 712 in the vicinity of the charge injection part as compared with FIG. 13I. As a forming method, after forming the first insulator 712, polysilicon is deposited by a method with good step coverage such as LPCVD and anisotropic selective etching. Thereafter, it can be formed by further performing isotropic selective etching such as wet etching. With this structure, electrons injected by writing are limited to the vicinity of the vicinity of the channel, so that the electrons can be easily removed by erasing, and erroneous erasing can be prevented. Furthermore, since the volume of the injected charge does not change and the volume of the memory function body holding the charge decreases, the amount of charge per unit volume can be increased, so that writing / erasing of electrons can be performed efficiently. And a semiconductor memory device having a high writing / erasing speed is provided.
[0333]
Further, according to the structures of FIGS. 13E to 13J, the first insulator 712 can suppress the dissipation of the charge accumulated in the polysilicon. Therefore, a highly reliable semiconductor memory device having good holding characteristics can be provided.
[0334]
The memory function bodies described in FIGS. 13E to 13J need to remove the wraparound portion of the gate electrode as shown in FIG. 12 in order to prevent a short circuit between the left and right memory function bodies.
[0335]
Further, if the polysilicon of the memory function body shown in FIGS. 13E to 13J has a function of retaining charges, the same effect as described above can be obtained without using polysilicon. For example, a silicon nitride film, a conductor, or a ferroelectric such as PZT or PLZT may be used.
[0336]
However, since polysilicon is used, the amount of charge injection can be controlled, whereby multi-valued data can be obtained, and the manufacturing cost per bit can be reduced. Further, since the material is used as a standard in the LSI process, the manufacturing cost can be reduced.
[0337]
When a silicon nitride film is used in place of polysilicon, the level of trapping charge in the charge holding portion is 1 × 10 ¹² cm ^-2 , A large hysteresis characteristic can be obtained, the charge retention time is long, and the problem of charge leakage due to the occurrence of a leak path does not occur, so that the retention characteristic is good. Since it is a standard material, the manufacturing cost is reduced.
[0338]
(Eighth embodiment)
A semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to FIG. In the eighth embodiment, a semiconductor memory device having the same structure as the semiconductor memory device in which the various memory function bodies shown in the sixth embodiment are formed on the side walls is formed, and is formed by using the second to fourth semiconductor memory devices. This is an embodiment applied to the embodiment. That is, the sixth embodiment is different from the semiconductor memory device of the fifth embodiment only in that a process of forming a memory function body by the forming method described in the sixth embodiment is added. What is necessary is just to apply the manufacturing method of the semiconductor memory device shown in 5th Embodiment to the manufacturing method of a semiconductor memory device. Similarly, also in the second to fourth embodiments, the structure of the present embodiment can be formed only by adding the step of forming the memory function body, and the effects described in the second to fourth embodiments can be obtained. The added effect can be obtained.
[0339]
14A to 14C will be described in detail. 14A to 14C, 801 is a semiconductor substrate, 802 is a gate insulating film, 803 is a gate electrode, 808 is a gate stack, 811 is a memory function body, 813 is a source / drain diffusion region, and 821 is A first coating film, 825 is a contact, and 826 is a second coating film.
[0340]
The structure of FIG. 14A is almost the same as the process described in the second embodiment, but the difference is as follows.
[0341]
That is, before forming the first coating film 821 shown in FIG. 3B of the second embodiment, the memory function body 811 having the charge holding function is formed. The point is that a device having the same shape as the described semiconductor memory device is formed. Here, as the memory function body 811, the memory function body having the structure and the formation method described in the sixth and seventh embodiments may be used.
[0342]
With this structure, not only the effects described in the third embodiment but also the effects related to the memory function body described in the sixth or seventh embodiment can be obtained.
[0343]
The method of manufacturing the semiconductor memory device is as follows.
[0344]
First, the structure shown in FIG. 10C is formed by using the method described in the sixth and seventh embodiments. At this time, the memory function body 811 is not limited to the one shown in FIG. 10C, and may be the memory function body described in FIGS. 13A to 13J. Can have an effect.
[0345]
After that, the semiconductor memory device shown in FIG. 14A can be formed by using the same steps as those described in the second embodiment after FIG. By the way, in the case of the eighth embodiment, unlike the second embodiment, since the memory function body is formed, the design margin can be reduced. That is, in the memory function body shown in FIGS. 13A to 13F, the silicon dots 710 and the polysilicon 715 which are the portions holding the electric charges are covered with the side wall insulator 716, and the contact and the memory function body are formed. Contact does not cause a short circuit. Therefore, in the memory function body shown in FIGS. 13A to 13F, it is sufficient to provide a margin such that the contact does not short-circuit with the gate electrode. As a result, miniaturization is facilitated.
[0346]
Next, in the structure of FIG. 14B, similarly to the above, before forming the first coating film 821, a memory function body 811 having a charge holding function is formed, and the semiconductor described in the sixth embodiment is formed. A device having the same shape as the storage device is formed. However, it differs from FIG. 14A in that the steps after the formation of the first coating film use the steps described in the third embodiment.
[0347]
The method of manufacturing the semiconductor memory device is as follows.
[0348]
First, the structure shown in FIG. 10C of the sixth embodiment is formed by using the method described in the sixth and seventh embodiments. At this time, the memory function body 811 is not limited to the one shown in FIG. 10C, and may be the memory function body shown in FIGS. 13A to 13J, and thereby, is described in the seventh embodiment. The effect can be obtained.
[0349]
After that, the semiconductor memory device shown in FIG. 14B can be formed by using the same steps as those described in the third embodiment after FIG. 5A. By the way, in the case of the present embodiment, unlike the third embodiment, since a memory function body is formed, a design margin can be reduced. That is, in the memory function body shown in FIGS. 13A to 13F, the silicon dots 710 and the polysilicon 715 which are the portions holding the electric charges are covered with the side wall insulator 716, and the contact and the memory function body are formed. Contact does not cause a short circuit. Furthermore, if the portion of the memory function body that holds the charge is made of a material such as a nitride film that holds the charge in a trap in the material, the stored charge is maintained even if the contact and the nitride film are short-circuited. Is not released, no short circuit occurs even if the contact comes into contact with the memory functional unit.
[0350]
Therefore, in the memory function body shown in FIGS. 13A to 13F and the memory function body in which the charge holding unit is made of a nitride film or the like, a margin is provided as long as the contact does not short-circuit with the gate electrode. Well, as a result, miniaturization becomes easy.
[0351]
Next, FIG. 14C will be described in detail.
[0352]
14C is different from FIGS. 14A and 14B in that a third covering film 827 is previously formed on the gate electrode 803. As a result, in the structure of FIG. 14C, even if a contact is made on the gate electrode 803, there is no short circuit with the gate electrode 803, and the design margin can be minimized. It can be easily miniaturized. In that respect, the structure has exactly the same effect as the structure shown in the fourth embodiment.
[0353]
That is, as long as there is no problem of short-circuit between the contacts, as shown in FIG. 14C, the contact 825 can tolerate a deviation as long as the contact / drain diffusion region 813 can maintain electrical connection. However, the memory function body shown in FIGS. 13A to 13J in which the memory function body may be in contact with the contact, and the portion holding the charge of the memory function body is charged in a trap in a substance such as a nitride film. Only if it is made of a substance that retains
[0354]
Therefore, in the memory function body and the memory function body 811 shown in FIGS. 13A to 13F in which the charge holding portion is made of a nitride film or the like, the contact 825 can be electrically connected to the source / drain diffusion region 813. And miniaturization becomes easy as a result.
[0355]
(Ninth embodiment)
A semiconductor memory device according to a ninth embodiment of the present invention will be described with reference to FIG.
[0356]
The ninth embodiment is an embodiment of the configuration of the semiconductor memory device having a memory function body on the side of the gate electrode shown in FIG. 2 of the first embodiment or FIGS. 11 and 12 of the sixth embodiment. It is shown. That is, the embodiment of the semiconductor memory device including the gate stack which is the portion covered by the coating film of the first embodiment in FIGS. 2 and 3 and the memory function body and the semiconductor substrate on both sides thereof. It is shown.
[0357]
Since the configuration and the like of the memory function body are described in detail from the ninth embodiment to a fifteenth embodiment to be described later, the structure and effect of the coating film and the like are not described, and Although not shown, a structure such as a coating film, which is not specifically mentioned in these embodiments, complies with the above-described embodiment, and should be considered in consideration of this point.
[0358]
The semiconductor memory device according to the ninth embodiment has the following effect in addition to the effects of the semiconductor memory device shown in FIG. 2 of the first embodiment or FIGS. 11 and 12 of the sixth embodiment. is there.
[0359]
In the semiconductor memory device of the ninth embodiment, as shown in FIG. 15, the memory function bodies 961 and 962 are regions where electric charges are held (regions where electric charges are stored and which have a function of holding electric charges). And a region that makes it difficult for the charge to escape (the film may have a function of making the charge hard to escape). For example, as shown in FIG. 10, it has an ONO structure. That is, a silicon nitride film 942 as an example of a charge holding portion is sandwiched between a silicon oxide film 941 as an example of a first insulator and a silicon oxide film 943 as an example of a sidewall insulator, and a memory function body 961 , 962. Here, the silicon nitride film plays a role of a charge holding portion having a function of holding charges. In addition, the silicon oxide films 941 and 943 function as a dissipation prevention insulator having a function of making it difficult for the electric charge stored in the silicon nitride film to escape.
[0360]
In addition, regions (silicon nitride films 942) of the memory function bodies 961 and 962 that retain electric charges overlap with the source / drain diffusion regions 912 and 913, respectively. Here, the term “overlap” means that at least a part of the region (the silicon nitride film 942) that retains electric charges exists on at least a part of the diffusion regions 912 and 913. Note that 911 is a semiconductor substrate, 914 is a gate insulating film, 917 is a gate electrode, and 971 is an offset region (between the gate electrode and the diffusion region). Although not shown, the top surface portion of the semiconductor substrate 911 below the gate insulating film 914 becomes a channel region.
[0361]
The effect of the overlap between the silicon nitride film 942 and the diffusion regions 912 and 913 in the regions holding the electric charges in the memory function bodies 961 and 962 will be described.
[0362]
FIG. 16 is an enlarged view of the periphery of the memory function body 962 on the right side of FIG. W1 indicates an offset amount of the offset region 971 between the gate electrode 917 and the diffusion region 913. W2 indicates the width of the memory function body 962 at the cut surface of the gate electrode 917 in the gate length direction, and the end of the memory function body 962 on the side of the silicon nitride film 942 remote from the gate electrode 917 is the gate. The width of the memory function body 962 was defined as W2 because it coincided with the end of the memory function body 962 away from the electrode 917. W2-W1 is the amount of overlap between the memory function body 962 and the diffusion region 913. The amount of overlap between the memory function body 962 and the diffusion region 913 is represented by W2−W1. It is particularly important that the memory function body 962 formed of the silicon nitride film 942 among the memory function bodies 962 overlaps with the diffusion region 913, that is, satisfies the relationship of W2> W1.
[0363]
As shown in FIG. 17, the end of the silicon nitride film 942a of the memory function body 962a on the side away from the gate electrode 917 does not coincide with the end of the memory function body 962a on the side away from the gate electrode 917. In such a case, W2 may be defined as from the end of the gate electrode 917 to the end of the silicon nitride film 942a on the far side from the gate electrode. In FIG. 17, reference numeral 911a denotes a semiconductor substrate, 913a denotes a source / drain diffusion region, 914a denotes a gate insulating film, 943a denotes a silicon oxide film, and 971a denotes an offset region.
[0364]
FIG. 18 shows the drain current Id when the width W2 of the memory function body 962 is fixed to 100 nm and the offset amount W1 is changed in the structure of the semiconductor memory device of FIG. Here, the drain current was obtained by device simulation using the memory function body 962 in an erased state (having holes stored therein) and using the diffusion regions 912 and 913 as a source electrode and a drain electrode, respectively.
[0365]
As is clear from FIG. 18, when W1 is 100 nm or more (that is, the silicon nitride film 942 and the diffusion region 913 do not overlap), the drain current decreases rapidly. Since the drain current value is almost proportional to the read operation speed, the memory performance is rapidly deteriorated when W1 is 100 nm or more. On the other hand, in the range where the silicon nitride film 942 and the diffusion region 913 overlap, the drain current decreases slowly. Therefore, in consideration of variations in mass production, if at least a part of the silicon nitride film 942, which is a film having a function of retaining electric charges, does not overlap with the source / drain region, a memory function can be effectively obtained. Have difficulty.
[0366]
Based on the results of the device simulation described above, a memory cell array was manufactured with W2 fixed at 100 nm and W1 set at 60 nm and 100 nm as design values. When W1 is 60 nm, the silicon nitride film 942 and the diffusion regions 912 and 913 overlap by 40 nm as a design value, and when W1 is 100 nm, they do not overlap as a design value. As a result of measuring the read time of these memory cell arrays, the read access time was 100 times faster when W1 was set to 60 nm as the design value, compared with the worst case in which the variation was considered. In practice, the read access time is preferably 100 nanoseconds or less per bit, but it has been found that this condition cannot be achieved at all when W1 = W2. In addition, it has been found that W2-W1> 10 nm is more preferable in consideration of manufacturing variations.
[0367]
In the semiconductor memory device illustrated in FIG. 16, reading of information stored in the memory function body 961 (region 981) is performed by using the diffusion region 912 as a source electrode and the diffusion region 913 as a drain region in the channel region closer to the drain region. Preferably, a pinch-off point is formed. That is, when reading information stored in one of the two memory function bodies, it is preferable to form a pinch-off point in a region within the channel region and close to the other memory function body. Thus, regardless of the storage state of the memory function body 962, the storage information of the memory function body 961 can be detected with high sensitivity, which is a major factor that enables 2-bit operation.
[0368]
On the other hand, when information is stored only on one side of the two memory function bodies or when the two memory function bodies are used in the same storage state, it is not always necessary to form a pinch-off point at the time of reading.
[0369]
Although not shown in FIG. 15, it is preferable to form a well region (P-type well in the case of an N-channel device) on the surface of the semiconductor substrate 911. By forming the well region, it is easy to control the other electrical characteristics (breakdown voltage, junction capacitance, short channel effect) while optimizing the impurity concentration of the channel region for the memory operation (rewrite operation and read operation). .
[0370]
In addition, from the viewpoint of improving the retention characteristics of the memory, the memory function body preferably includes a charge retention film as a charge retention portion having a function of retaining charges and an insulating film. In the ninth embodiment, a silicon nitride film 942 having a level for trapping charges as a charge holding film, and silicon oxide films 941 and 943 serving as an insulating film for preventing the charge held in the charge holding film from dissipating. Used. Since the memory function body includes the charge holding film and the insulating film, the charge can be prevented from dissipating and the holding characteristics can be improved. Furthermore, the volume of the charge holding film can be appropriately reduced as compared with the case where the memory function body is composed of only the charge holding film. By appropriately reducing the volume of the charge holding film, the movement of charges in the charge holding film can be limited, and a change in characteristics due to the charge transfer during storage can be suppressed.
[0371]
Further, it is preferable that the memory function body includes a charge retaining film that is disposed substantially in parallel with the surface of the gate insulating film. In other words, it is preferable that the upper surface of the charge retaining film in the memory function body is disposed at an equal distance from the upper surface of the gate insulating film.
[0372]
Specifically, as shown in FIG. 19, the silicon nitride film 942 a as a charge holding portion of the memory function body 962 formed on the side of the gate electrode 917 has a surface substantially parallel to the surface of the gate insulating film 914. Have. In other words, the silicon nitride film 942a is preferably formed to have a uniform height from a height corresponding to the surface of the gate insulating film 914. Since the memory function body 962 includes the silicon nitride film 942a substantially parallel to the surface of the gate insulating film 914, the ease of forming the inversion layer in the offset region 971 due to the amount of charge held in the silicon nitride film 942a is reduced. Effective control can be achieved, and the memory effect can be increased. Further, by making the silicon nitride film 942a substantially parallel to the surface of the gate insulating film 914, even when the offset amount (W1) varies, the change in the memory effect can be kept relatively small, and the variation in the memory effect can be suppressed. can do. In addition, the movement of the charges in the upper direction of the silicon nitride film 942a is suppressed, and it is possible to suppress a change in characteristics due to the movement of the charges during storage.
[0373]
Further, the memory function body 962 includes an insulating film (for example, an offset region 971 of a silicon oxide film 944 (W2)) separating a silicon nitride film 942a substantially parallel to the surface of the gate insulating film 914 and a channel region (or a well region). Upper part). With this insulating film, dissipation of the charge held in the charge holding film is suppressed, and a semiconductor memory device with better holding characteristics can be obtained.
[0374]
The semiconductor substrate 911 is controlled by controlling the film thickness of the silicon nitride film 942a and controlling the film thickness of the insulating film under the silicon nitride film 942a (portion of the silicon oxide film 944 above the offset region 971) to be constant. The distance from the surface to the charge stored in the charge holding film can be kept substantially constant. In other words, the distance from the surface of the semiconductor substrate 911 to the charge stored in the charge holding film is determined from the minimum thickness of the insulating film under the silicon nitride film 942a to the maximum thickness of the insulating film under the silicon nitride film 942a. Control can be performed up to the sum of the maximum thickness value of the nitride film 942a. Thus, the density of the lines of electric force generated by the electric charges stored in the silicon nitride film 942a can be substantially controlled, and the variation in the memory effect of the semiconductor memory device can be greatly reduced.
[0375]
(Tenth embodiment)
FIG. 20 is an enlarged view of a peripheral portion of a memory function unit of a semiconductor memory device according to a tenth embodiment of the present invention, and the same components as those of FIG. 16 of the ninth embodiment are denoted by the same reference numerals. . In the semiconductor memory device according to the tenth embodiment of the present invention, as shown in FIG. 20, the silicon nitride film 942 of the memory function body 962 has a substantially uniform thickness and is disposed substantially parallel to the surface of the gate insulating film 914. (Arrow 981), and (arrow 982) arranged substantially parallel to the side surface of the gate electrode 917.
[0376]
When a positive voltage is applied to the gate electrode 917, lines of electric force in the memory function body 962 pass through the silicon nitride film 942 twice (as indicated by arrows 982 and 981) as indicated by an arrow 983. . When a negative voltage is applied to the gate electrode 917, the direction of the lines of electric force is on the opposite side. Here, the relative permittivity of the silicon nitride film 942 is about 6, and the relative permittivity of the silicon oxide films 941 and 943 is about 4. Therefore, the effective relative dielectric constant of the memory function body 962 in the direction of the line of electric force (arrow 983) becomes larger than when only the charge holding film indicated by the arrow 981 is present, and the potential difference at both ends of the line of electric force is reduced. Can be smaller. That is, most of the voltage applied to the gate electrode 917 is used to increase the electric field in the offset region 971.
[0377]
The charge is injected into the silicon nitride film 942 during the rewrite operation because the generated charge is drawn by the electric field in the offset region 971. Therefore, by including the charge holding film indicated by the arrow 982, the charge injected into the memory function body 962 during the rewrite operation increases, and the rewrite speed increases.
[0378]
If the silicon oxide film 943 is also a silicon nitride film, that is, if the charge holding film is not uniform with respect to the height corresponding to the surface of the gate insulating film 914, the charge in the upward direction of the silicon nitride film is increased. Movement becomes conspicuous, and the holding characteristics deteriorate.
[0379]
It is more preferable that the charge retention film is formed of a high dielectric material such as hafnium oxide having a very large relative dielectric constant instead of the silicon nitride film.
[0380]
Further, the memory function body 962 further includes an insulating film (a portion of the silicon oxide film 941 on the offset region 971) separating the charge holding film substantially parallel to the surface of the gate insulating film 914 and the channel region (or well region). Is preferred. With this insulating film, dissipation of the charges held in the charge holding film is suppressed, and the holding characteristics can be further improved.
[0381]
In addition, the memory function body 962 further includes an insulating film (a part of the silicon oxide film 941 in contact with the gate electrode 917) separating the gate electrode 917 and the charge holding film extending in a direction substantially parallel to the side surface of the gate electrode 917. It is preferred to include. With this insulating film, it is possible to prevent electric charges from being injected from the gate electrode 917 to the charge holding film and to prevent a change in electrical characteristics, thereby improving the reliability of the semiconductor memory device.
[0382]
Further, it is preferable to control the thickness of the insulating film under the silicon nitride film 942 (the portion of the silicon oxide film 941 above the offset region 971) to be constant, and furthermore, the insulating film (silicon oxide film) disposed on the side surface of the gate electrode 917. It is preferable that the thickness of the portion of the film 941 which is in contact with the gate electrode 917 is controlled to be constant. Thus, the density of lines of electric force generated by the charges stored in the silicon nitride film 942 can be substantially controlled, and charge leakage can be prevented.
[0383]
(Eleventh embodiment)
FIG. 21 is a schematic sectional view showing the outline of the structure of the semiconductor memory device according to the eleventh embodiment of the present invention, and the same components as those in FIG. 15 of the ninth embodiment are denoted by the same reference numerals. . A semiconductor memory device according to an eleventh embodiment of the present invention relates to optimization of a gate electrode, a memory functional unit, and a distance between source / drain regions.
[0384]
As shown in FIG. 21, A is the gate electrode length in the cut surface in the gate length direction, B is the distance between the source / drain regions (channel length), and C is from one end of one memory function body to the other memory function body. From the end of the film having the function of retaining the charge in one memory function body (the side remote from the gate electrode) on the cut surface in the gate length direction, that is, the charge in the other memory function body It shows the distance to the end of the film having the function of performing the function (the side away from the gate electrode).
[0385]
First, it is preferable that B <C. An offset region 971 exists between a portion of the channel region below the gate electrode 917 and the source / drain diffusion regions 912 and 913. Due to B <C, the easiness of inversion is effectively changed in the entire region of the offset region 971 due to charges accumulated in the memory function bodies 961 and 962 (silicon nitride film 942). Therefore, the memory effect increases, and particularly, the speed of the read operation is increased.
[0386]
When the gate electrode 917 is offset from the source / drain diffusion regions 912 and 913, that is, when A <B is satisfied, the offset region is easily inverted when a voltage is applied to the gate electrode 917. Varies greatly depending on the amount of charge held in the memory function bodies 961 and 962, so that the memory effect increases and the short channel effect can be reduced. However, as long as the memory effect appears, it is not always necessary to exist. Even when there is no offset region 971, if the impurity concentration of the source / drain regions 912 and 913 is sufficiently low, a memory effect can be exhibited in the memory functional bodies 961 and 962 (silicon nitride film 942).
[0387]
Therefore, it is most preferable that A <B <C.
[0388]
(Twelfth embodiment)
As shown in FIG. 22, the semiconductor memory device according to the twelfth embodiment has substantially the same configuration as the ninth embodiment except that the semiconductor substrate in the ninth embodiment is an SOI substrate. Have the same reference numbers.
[0389]
In this semiconductor memory device, a buried oxide film 988 is formed on a semiconductor substrate 986, and an SOI layer is further formed thereon. Diffusion regions 912 and 913 are formed in the SOI layer, and the other region is a body region 987.
[0390]
This semiconductor memory device also has the same functions and effects as the semiconductor memory device of the ninth embodiment. Further, the junction capacitance between the diffusion regions 912 and 913 and the body region 987 can be significantly reduced, so that the speed of the element can be increased and the power consumption can be reduced.
[0391]
(Thirteenth embodiment)
As shown in FIG. 23, the semiconductor memory device according to the thirteenth embodiment of the present invention differs from the ninth embodiment in that the P-type high-concentration region is adjacent to the channel side of the N-type source / drain regions 912 and 913. It has substantially the same configuration except that an area 991 has been added, and the same components are denoted by the same reference numerals.
[0392]
That is, the P-type impurity (for example, boron) concentration in the P-type high concentration region 991 is higher than the P-type impurity concentration in the region 992. The P-type impurity concentration in the P-type high concentration region 991 is, for example, 5 × 10 ¹⁷ cm ^-3 ~ 1 × 10 ¹⁹ cm ^-3 The degree is appropriate. The P-type impurity concentration of the region 992 is, for example, 5 × 10 ¹⁶ cm ^-3 ~ 1 × 10 ¹⁸ cm ^-3 It can be.
[0393]
By providing the P-type high-concentration region 991 in this manner, the junction between the diffusion regions 912 and 913 and the semiconductor substrate 911 becomes steep immediately below the memory function bodies 961 and 962. Therefore, hot carriers are easily generated at the time of writing and erasing operations, and the voltage of the writing and erasing operations can be reduced, or the speed of the writing and erasing operations can be increased. Further, since the impurity concentration of the region 992 is relatively low, the threshold value when the memory is in the erased state is low, and the drain current increases. Therefore, the reading speed is improved. Therefore, a semiconductor memory device having a low rewrite voltage or a high rewrite speed and a high read speed can be obtained.
[0394]
In FIG. 23, a P-type high-concentration region 991 is provided near the source / drain diffusion regions 912 and 913 and below the memory function bodies 961 and 962 (that is, not directly below the gate electrode 917). The threshold value of the transistor as a whole increases significantly. The degree of this rise is significantly greater than when the P-type high concentration region 991 is directly below the gate electrode 917. When write charges (electrons when the transistor is an N-channel type) are accumulated in the memory function bodies 961 and 962, the difference is further increased. On the other hand, when sufficient erase charges (holes when the transistor is an N-channel type) are accumulated in the memory function bodies 961 and 962, the threshold value of the transistor as a whole is set to the channel region (region 992) below the gate electrode 917. Lower than the threshold value determined by the impurity concentration. That is, the threshold value at the time of erasing does not depend on the impurity concentration of the P-type high-concentration region 991, while the threshold value at the time of writing is greatly affected. Therefore, by disposing the P-type high-concentration region 991 below the memory function bodies 961 and 962 and in the vicinity of the source / drain diffusion regions 912 and 913, only the threshold value at the time of writing fluctuates greatly, and the memory effect ( (Difference in threshold between writing and erasing) can be significantly increased.
[0395]
(14th embodiment)
As shown in FIG. 24, the semiconductor memory device according to the fourteenth embodiment of the present invention differs from the ninth embodiment in that the thickness of the insulating film separating the charge holding film (silicon nitride film 942) from the channel region or the well region is different from that of the ninth embodiment. Except that the thickness (T1) is smaller than the thickness (T2) of the gate insulating film, they have substantially the same configuration, and the same components are denoted by the same reference numerals.
[0396]
The thickness T2 of the gate insulating film 914 has a lower limit due to a demand for withstand voltage during a memory rewrite operation. However, the thickness T1 of the silicon oxide film 941 can be made smaller than T2 regardless of the demand for the withstand voltage.
[0397]
In the semiconductor memory device according to the fourteenth embodiment, the degree of freedom in designing T1 as described above is high for the following reason. In the semiconductor memory device of this embodiment, the insulating film that separates the charge holding film from the channel region or the well region is not sandwiched between the gate electrode 917 and the channel region or the well region. Therefore, the high electric field that acts between the gate electrode 917 and the channel region or the well region does not directly act on the insulating film that separates the charge retention film from the channel region or the well region, and the insulating film relatively weakly spreads laterally from the gate electrode 917. An electric field acts. Therefore, T1 can be made smaller than T2 regardless of the demand for the withstand voltage for the gate insulating film 914. On the other hand, for example, in an EEPROM typified by a flash memory, an insulating film separating a floating gate and a channel region or a well region is sandwiched between a gate electrode 917 (control gate) and a channel region or a well region. The high electric field from the electrode 917 acts directly. Therefore, in the EEPROM, the thickness of the insulating film separating the floating gate from the channel region or the well region is limited, and the optimization of the function of the semiconductor memory device is hindered.
[0398]
As is clear from the above, in the semiconductor memory device of the fourteenth embodiment, the insulating film separating the charge retaining film (silicon nitride film 942) from the channel region or the well region is formed by the gate electrode 917 and the channel region or the well region. Is an essential reason for increasing the degree of freedom of T1.
[0399]
By making T1 thinner, it becomes easier to inject charges into the memory function bodies 961 and 962, and it is possible to lower the voltage of the write operation and the erase operation or to increase the speed of the write operation and the erase operation. Since the amount of charges induced in the channel region or the well region when the charges are accumulated in the silicon nitride film 942 increases, the memory effect can be increased.
[0400]
By the way, as shown by an arrow 983 in FIG. 20, there are short lines of electric force in the memory function bodies 961 and 962 that do not pass through the silicon nitride film 942. Since the electric field strength is relatively large on such a short line of electric force, it plays a large role during the rewriting operation. By reducing the thickness of T1, the silicon nitride film 942 moves to the lower side in the figure, and the lines of electric force indicated by arrows 983 pass through the silicon nitride film 942. Therefore, the effective relative permittivity in the memory function bodies 961 and 962 along the lines of electric force (indicated by the arrow 983) increases, and the potential difference between both ends of the lines of electric force can be further reduced. Therefore, much of the voltage applied to the gate electrode 917 is used to increase the electric field in the offset region, and the writing operation and the erasing operation are performed at high speed.
[0401]
As is clear from the above, by setting T1 <T2, the voltage of the writing operation and the erasing operation can be reduced, or the writing operation and the erasing operation can be speeded up without lowering the withstand voltage performance of the memory, and the memory effect can be further improved. It is possible to increase.
[0402]
Note that the thickness T1 of the silicon oxide film 941 is 0.8 nm or more, at which uniformity and film quality due to the manufacturing process can be maintained at a certain level, and retention characteristics are not extremely deteriorated. Is more preferred.
[0403]
(Fifteenth embodiment)
As shown in FIG. 25, in the semiconductor memory device according to the fifteenth embodiment of the present invention, in the ninth embodiment, the thickness of the insulating film separating the charge holding portion (silicon nitride film 942) from the channel region or well region is different from that of the ninth embodiment. It has substantially the same configuration except that the thickness (T1) is larger than the thickness (T2) of the gate insulating film 914.
[0404]
The thickness T2 of the gate insulating film 914 has an upper limit due to a demand for preventing a short channel effect of the element. However, the thickness T1 of the insulating film can be made larger than T2 irrespective of the need to prevent the short channel effect.
[0405]
As described above, in the semiconductor memory device of the fifteenth embodiment, the reason for the high degree of freedom in design for T1 is that the insulating film that separates the charge holding film from the channel region or the well region is formed by the gate electrode. 917 and a channel region or a well region. Therefore, T1 can be made thicker than T2 regardless of the requirement for the gate insulating film 914 to prevent the short channel effect.
[0406]
By increasing the thickness of T1, it is possible to prevent the electric charges held in the memory function bodies 961 and 962 from dissipating, and to improve the holding characteristics of the memory.
[0407]
Therefore, by setting T1> T2, it is possible to improve the holding characteristics without deteriorating the short channel effect of the memory.
[0408]
Note that the thickness T1 of the silicon oxide film 941 as the first insulator is preferably 20 nm or less in consideration of a reduction in the rewriting speed.
[0409]
(Sixteenth embodiment)
A semiconductor device according to a sixteenth embodiment of the present invention includes a memory unit including the semiconductor storage device of the present invention, a peripheral circuit unit of a nonvolatile memory including a general MOSFET (MOS field effect transistor) having a normal structure, It comprises a logic circuit section such as an MPU (micro processing unit), an SRAM (static RAM) section and the like (these are collectively referred to as a logic circuit section and the like).
[0410]
More specifically, as shown in FIG. 26A, in order for the semiconductor memory device of the present invention to function as a memory unit such as a RAM (random access memory), a memory area in which the semiconductor memory devices are arranged in an array is provided. It is necessary to arrange a peripheral circuit 1002 which is a logic circuit area around the memory cell array 1001 which is a logical circuit area. As the peripheral circuit 1002, a semiconductor device is configured by a logic circuit including a normal MOSFET such as a decoder 1007, a write / erase circuit 1009, a read circuit 1008, an analog circuit 1006, a control circuit 1005, various I / O circuits 1004, and the like. .
[0411]
Further, in order for a memory unit such as a RAM to function as a storage device of an information processing system such as a personal computer or a mobile phone, in addition to the memory unit having the above configuration, as shown in FIG. It is necessary to configure a logic circuit including a normal MOSFET such as a processing unit 1011, a cache SRAM (static RAM) 1012, a logic circuit 1013, and an analog circuit 1014.
[0412]
The logic circuit section or the like of the memory according to the present embodiment refers to a circuit or a unit that can be configured using the above-described logic circuit including a general MOSFET.
[0413]
As can be seen from the procedures described in the first to fifteenth embodiments, the procedure for forming the semiconductor memory device has a very high affinity with a known general MOSFET forming process. . Further, as is apparent from FIG. 1, the configuration of the memory element is close to a known general MOSFET. In order to change the general MOSFET to the memory element, for example, in a general MOSFET, a coating film is formed after forming a gate electrode, or a charge is formed after forming a memory function body as a sidewall spacer. It is only necessary to form a coating film having a holding portion. However, since the offset region is formed, the LDD region is not formed after the gate stack is formed.
[0414]
Here, even if a sidewall spacer of a general MOSFET constituting a logic circuit portion or the like has a function as a memory function body or a coating film is formed, the coating film or the sidewall spacer and the coating film may be used. The transistor performance is not impaired as long as the transistor is operated in a voltage range in which the rewrite operation does not occur with an appropriate width.
[0415]
Therefore, a common coating film or a sidewall spacer and a coating film can be used for a general MOSFET and a semiconductor memory device.
[0416]
In addition, in order to mix a general MOSFET constituting the logic circuit portion and the like with the semiconductor memory device, it is possible to form an LDD structure only in the logic circuit portion and the like. In order to form an LDD structure, impurities may be implanted for forming an LDD region after forming the gate electrode and before depositing the material constituting the memory function body. Therefore, when the impurity is implanted for forming the LDD, only the memory region is masked with a photoresist, so that the semiconductor memory device and the normal structure MOSFET constituting the logic circuit portion and the like can be easily mounted together. Is possible. Further, if the SRAM is constituted by the semiconductor memory device and the MOSFET having the normal structure constituting the logic circuit portion, the semiconductor memory device, the logic circuit, and the SRAM can be easily mounted together.
[0417]
In the semiconductor memory device, when it is necessary to apply a higher voltage than is allowed in the logic circuit portion and the SRAM portion, a mask for forming a high breakdown voltage well and a mask for forming a high breakdown voltage gate insulating film are used as standard. It only needs to be added to the MOSFET forming mask. Conventionally, a process of mounting an EEPROM (programmable ROM capable of electrically writing and erasing) and a logic circuit unit on one chip is significantly different from a standard MOSFET process, and the number of required masks and the number of process steps have been significantly increased. Therefore, the number of masks and the number of process steps can be drastically reduced as compared with the conventional case where the EEPROM and the circuit such as the logic circuit unit are mixed. Therefore, the cost of a chip in which a general MOSFET such as a logic circuit unit and the semiconductor memory device of the present invention are mixed is reduced. Further, since a high power supply voltage can be supplied to the semiconductor memory device, the writing / erasing speed can be remarkably improved. Furthermore, since a low power supply voltage can be supplied to the logic circuit portion, the SRAM portion, and the like, deterioration of transistor characteristics due to destruction of a gate insulating film or the like can be suppressed, and power consumption can be further reduced. Therefore, it is possible to realize a semiconductor device having a highly reliable logic circuit portion easily mounted on the same substrate and a semiconductor memory device having a remarkably high writing / erasing speed.
[0418]
A semiconductor memory device used in the semiconductor device according to the sixteenth embodiment of the present invention will be described with reference to FIGS.
[0419]
In the present embodiment, it is shown that a general MOSFET and a semiconductor memory device in a logic circuit and the like, and respective devices can be easily formed on the same substrate without requiring complicated processes at the same time. More specifically, a photolithography step is added to the step of forming the semiconductor memory device described in the second embodiment, and a region where an LDD diffusion region is formed and a region where no LDD diffusion region is formed are automatically separated on the same substrate. Shows that a general MOSFET and a semiconductor memory device can be manufactured.
[0420]
The manufacturing process will be described below step by step with reference to the drawings.
[0421]
FIGS. 27 and 28 show left and right devices. The left side is a general MOSFET in the logic circuit area 1104, and the right side is a semiconductor memory device in the memory area 1105.
[0422]
Up to the LDD region forming step, the same steps as those in the second embodiment may be used. That is, as shown in FIG. 27A, the logic circuit region 1104 and the memory region 1105 of the semiconductor substrate 101 form the structure of FIG. 3A in the second embodiment. In FIG. 27A, reference numeral 1102 denotes a gate insulating film, 1103 denotes a gate electrode, and 1108 denotes a gate stack.
[0423]
Next, as shown in FIG. 27B, an LDD region 1106 is formed only in the logic circuit region 1104. At this time, the photoresist 1107 is formed in the memory region 1105, and the LDD region 1106 is not formed. Here, the LDD region 1106 is not formed in the memory region 1105, while the LDD region can be formed in the logic circuit region 1104 which forms a transistor having a general normal structure. The photoresist may be one that prevents implantation and that can be selectively removed, and may be an insulating film such as a nitride film. Only this step is a special step different from the second embodiment, and thereafter, the same steps as those in the second embodiment may be used.
[0424]
Next, as shown in FIG. 27C, a first covering film 1121 is formed using the same steps as those in FIG. 3B of the second embodiment.
[0425]
Further, as shown in FIG. 27D, a source / drain diffusion region 1113 is formed using the same steps as in FIG. 3C of the second embodiment, an interlayer insulating film 1123 is formed, and A contact hole 1124 for forming a contact connecting the / drain diffusion region and the wiring is formed in the interlayer insulating film 1123.
[0426]
Further, as shown in FIG. 28E, the first coating film 1121 under the contact hole is formed by anisotropic selective etching using the same process as that of FIG. 4D of the second embodiment. To remove.
[0427]
Further, as shown in FIG. 28F, the sidewalls of the portions of the interlayer insulating film 1123 and the gate stack 1108 exposed to the contact holes are formed by using the same steps as those of FIG. 4E of the second embodiment. A second coating film 1126 is formed.
[0428]
Further, as shown in FIG. 28G, a contact material is buried in the contact hole to form a contact 1125 by using a process similar to that of FIG. 4F of the second embodiment. Further, the contact material is etched on the interlayer insulating film 1123 using a photolithography and etching process to form a wiring pattern.
[0429]
As described above, a photolithography step is added to the step of forming the semiconductor memory device according to the second embodiment, and a region where an LDD diffusion region is formed and a region where no LDD diffusion region is formed are automatically separated on the same substrate. A general MOSFET and the semiconductor memory device of the present invention can be easily manufactured without requiring a complicated process.
[0430]
(Seventeenth embodiment)
An IC card according to a seventeenth embodiment of the present invention will be described with reference to FIG.
[0431]
FIG. 29 is a diagram showing a configuration of an IC card.
[0432]
As shown in FIG. 29A, an MPU (Micro Processing Unit) unit 1201 and a connect unit 1208 are built in the IC card 1200A. The MPU unit 1201 includes a data memory unit 1204, a calculation unit 1202, a control unit 1203, a ROM (Read Only Memory) 1205, and a RAM (Random Access Memory) 1206, which are formed on one chip. The semiconductor device according to the sixteenth embodiment of the present invention is incorporated in the MPU unit 1201. The components 1202, 1203, 1204, 1205, and 1206 are connected by wiring (including a data bus and a power supply line) 1207. The connection unit 1208 and the external reader / writer 1209 are connected when the IC card 1200A is mounted on the reader / writer 1209, and power is supplied to the IC card 1200A and data is exchanged.
[0433]
The feature of this embodiment is that the MPU unit 1201 and the data memory unit 1204 are formed on one semiconductor chip, and constitute the MPU unit 1201 in which the data memory unit 1204 is mounted.
[0434]
As the data memory unit 1204, a semiconductor memory device described in this patent that can reduce the manufacturing cost is used.
[0435]
Since the semiconductor memory device can be easily miniaturized and can operate in two bits, it is easy to reduce the area of a memory cell array in which the semiconductor memory device is arranged. Therefore, the cost of the memory cell array can be reduced. If this memory cell array is used for the data memory unit 1204 of the IC card, the cost of the IC card can be reduced.
[0436]
Further, since the data memory unit 1204 is built in the MPU unit 1201 and formed on one chip, the cost of the IC card 1200A can be greatly reduced.
[0437]
Further, since the semiconductor memory device of the present invention is used for the data memory unit 1204 and the semiconductor device of the present invention is used for other circuit units, that is, the MPU unit 1201 is formed of the semiconductor device of the present invention. For example, as compared with the case where a flash memory is used, the elements forming the logic circuit unit (arithmetic unit and control unit) of the MPU unit 1201 are very similar in formation process, and are very easy to mix and match. The consolidation process is significantly simplified. Therefore, the cost reduction effect by forming the MPU unit 1201 and the data memory unit 1204 on one chip is particularly large.
[0438]
Note that the ROM 1205 may be configured by the above-described semiconductor storage device. By doing so, it is possible to externally rewrite the ROM 1205 in which the program for driving the MPU unit 1201 is stored, and the function of the IC card 1200A can be greatly enhanced. Since the above semiconductor storage device can be easily miniaturized and can perform 2-bit operation, replacing the mask ROM with the semiconductor storage device hardly causes an increase in chip area. Further, since the process of forming the semiconductor memory device is almost the same as a normal CMOS forming process, it is easy to mount the semiconductor memory device together with a logic circuit portion.
[0439]
Next, as shown in FIG. 29B, an MPU unit 1201, an RF interface unit 1210, and an antenna unit 1211 are built in the IC card 1200B. The MPU unit 1201 includes a data memory unit 1204, a calculation unit 1202, a control unit 1203, a ROM 1205, and a RAM 1206, which are formed on one chip. The units 1202, 1203, 1204, 1205, and 1206 are connected by wiring (including a data bus and a power supply line) 1207.
[0440]
The IC card 1200B in FIG. 29B differs from the IC card 1200A in FIG. 29A in that it is a non-contact type. Therefore, the control unit 1203 is connected to the RF interface unit 1210 instead of the connect unit 1208. The RF interface unit 1210 is further connected to the antenna unit 1211. The antenna unit 1211 has a function of communicating with an external device and collecting power. The RF interface unit 1210 has a function of rectifying a high-frequency signal transmitted from the antenna unit 1211 and supplying power, and a function of modulating and demodulating a signal. The RF interface unit 1210 and the antenna unit 1211 may be mounted together with the MPU unit 1201 on one chip.
[0441]
Since the IC card 1200B of this embodiment shown in FIG. 29B is a non-contact type, it is possible to prevent electrostatic breakdown through the connecting portion. Further, since it is not always necessary to make close contact with the external device, the degree of freedom of the use form is increased. Further, since the semiconductor memory device constituting the data memory unit 1204 operates at a lower power supply voltage (for example, about 9 V) than the conventional flash memory (about 12 V power supply voltage), the circuit of the RF interface unit is downsized. , The cost can be reduced.
[0442]
(Eighteenth Embodiment)
A mobile electronic device according to an eighteenth embodiment of the present invention will be described with reference to FIG.
[0443]
The semiconductor storage device or the semiconductor storage device or the semiconductor device of the first to sixteenth embodiments can be used for a battery-driven portable electronic device. The portable electronic device includes, in particular, a portable information terminal, a mobile phone, a game device, and the like.
[0444]
FIG. 30 illustrates a mobile phone as an example of a mobile electronic device. The MPU unit 1301 incorporates the semiconductor device of the present invention.
[0445]
By using the semiconductor device of the present invention in a portable electronic device, the manufacturing cost of the control circuit is reduced, so that the cost of the portable electronic device itself can be reduced. Alternatively, the capacity of the nonvolatile memory included in the control circuit can be increased to enhance the functions of the portable electronic device.
[0446]
As shown in FIG. 30, an MPU unit 1301, a man-machine interface unit 1308, an RF circuit unit 1310, and an antenna unit 1311 are built in a mobile phone. The MPU unit 1301 includes a data memory unit 1304, a calculation unit 1302, a control unit 1303, a ROM 1305, and a RAM 1306, which are formed on one chip. The units 1302, 1303, 1304, 1305, and 1306 are connected by wiring (including a data bus and a power supply line) 1307.
[0447]
A feature of this embodiment is that the MPU unit 1301 and the data memory unit 1304 are formed on one semiconductor chip, and constitute the MPU unit 1301 in which the data memory unit 1304 is mounted.
[0448]
For the data memory unit 1304, a semiconductor memory device of the present invention which can reduce manufacturing cost is used.
[0449]
Since the semiconductor memory device can easily reduce the occupied area and can perform 2-bit operation, it is easy to reduce the area of the memory cell array in which it is arranged. Therefore, the cost of the memory cell array can be reduced. If this memory cell array is used for the data memory section of a mobile phone, the cost of the mobile phone can be reduced.
[0450]
Further, since the data memory unit 1304 is built in the MPU unit 1301 and formed on one chip, the cost of the mobile phone can be greatly reduced.
[0451]
Further, since the semiconductor memory device of the present invention is used for the data memory portion 1304 and the semiconductor device of the present invention is used for other circuit portions, that is, the MPU portion 1301 is formed of the semiconductor device of the present invention. For example, as compared with the case where a flash memory is used, the elements forming the logic circuit unit (arithmetic unit and control unit) of the MPU unit 1301 are very similar in formation process, and are very easy to be mounted together. The consolidation process is significantly simplified. Therefore, the cost reduction effect by forming the MPU unit 1301 and the data memory unit 1304 on one chip is particularly large.
[0452]
Note that the ROM 1305 may be constituted by the above-mentioned semiconductor storage device. By doing so, it is possible to externally rewrite the ROM 1305 in which the program for driving the MPU unit 1301 is stored, so that the function of the mobile phone can be dramatically improved. Since the semiconductor memory device can easily reduce the occupied area and can perform 2-bit operation, replacing the mask ROM with the memory device hardly causes an increase in chip area. Further, since the process of forming the semiconductor memory device is almost the same as a normal CMOS forming process, it is easy to mount the semiconductor memory device together with a logic circuit portion.
[0453]
(Nineteenth Embodiment)
A semiconductor memory device using the semiconductor memory device according to the nineteenth embodiment of the present invention is preferably applied to a memory cell array as an example of a semiconductor memory device configured by arranging the semiconductor memory devices. .
[0454]
The two types of memory cell arrays of the nineteenth embodiment will be described with reference to FIGS. FIG. 31A is a circuit diagram of the two types of memory cell arrays, and FIG. 31B is a schematic plan view of the memory cell array, and the circuit diagram and the plan view are the same. FIG. 32A is a schematic cross-sectional view of the first memory cell array taken along section line CC of FIG. 31B, and FIG. 32B is a second memory cell array having a different configuration. FIG. 32 is a schematic sectional view taken along line CC of FIG. 31 (b). However, in FIG. 31B, the upper wiring structure (bit lines and contacts) is represented as a connection diagram for simplicity. Although FIGS. 31 and 32 show a memory cell array of 3 rows × 3 columns, the number of rows and the number of columns are arbitrary.
[0455]
As shown in FIGS. 32A and 32B, a P-type well region 1402 is formed on a semiconductor substrate 1401. On the surface of the P-type well region 1402, an element isolation region 1408 is formed. A region on the surface of the semiconductor substrate 1401 where the element isolation region 1408 is not formed is an active region. Active regions are arranged on the semiconductor substrate 1401. In FIG. 31A, the word lines WL1, WL2, WL3 extend in the horizontal direction on the paper and are formed side by side in the vertical direction on the paper. Word lines WL1, WL2, WL3 pass through each active region via a gate insulating film, and source / drain regions are formed on both sides of each word line (regions which are active regions and are not covered by word lines). A diffusion region (shown in FIGS. 32A and 32B) is formed. The word line (gate electrode) and two source / drain diffusion regions (source region or drain region) formed on both sides of the word line constitute one field effect transistor. Here, the field effect transistor refers to a semiconductor memory device having a memory function as shown in FIGS. 1 and 2 of the first embodiment, and a memory functional unit similar to that shown in FIG. 13 of the seventh embodiment. Is formed. As the method of manufacturing the semiconductor memory device, it is preferable to use the preferred one of the first to fifteenth embodiments.
[0456]
Next, a schematic plan view of the memory cell array shown in FIG. Three adjacent bit lines are selected, and are arranged as a bit line BL1, a bit line BL2, and a bit line BL3 in the order of arrangement. At this time, an active region existing between the bit line BL1 and the bit line BL2 is defined as an active region A1. Similarly, an active region existing between the bit line BL2 and the bit line BL3 is defined as A2. At this time, the bit line BL2 is connected to one of the active region A1 and the source / drain diffusion region belonging to the active region A2. The bit line BL3 is connected to the other of the source / drain diffusion regions belonging to the active region A2. The bit line BL1 is connected to the other of the source / drain diffusion regions belonging to the active region A1. Further, when two adjacent word lines (for example, WL1 and WL2) are selected, a source / drain diffusion region belonging to the active region A1 and sandwiched between the two word lines, The source / drain diffusion regions belonging to A2 and sandwiched between the two word lines are both connected to the bit line BL2, or connected to the bit lines BL1 and BL3, respectively. That is, when an appropriate voltage serving as a source or a drain is applied to the active region connected to the bit lines BL2 and BL3 in the active region A2 to select a word line (for example, WL1), the word line WL1 is sandwiched from above and below. The active region A2 becomes a source or a drain, and the semiconductor memory device is selected.
[0457]
32, reference numeral 1431 denotes a contact hole (a hole for connecting an active layer or a word line to a first-layer metal wiring); and 1433, a via hole (a hole for connecting the first-layer metal wiring to a second-layer metal wiring). Hole). In the nineteenth embodiment, the first bit line is formed by the first-layer metal wiring 1432 and the second bit line is formed by the second-layer metal wiring 1434. However, the wiring method is not limited to this. Absent.
[0458]
The effect according to the present embodiment is the same as the effect produced when the contact hole is formed on the element isolation region according to the second embodiment. That is, as shown in FIG. 32A, even if the contact hole 1431 is formed on the element isolation region 1408, the element isolation region 1408 is not etched, and good contact characteristics can be obtained. Therefore, as in the second embodiment, the occupied area can be greatly reduced, and a low-cost semiconductor memory device can be provided.
[0459]
Further, in the case where the contact materials embedded in the adjacent contact holes 1431 are connected to each other by the first-layer metal wiring 1432, which is a characteristic aspect of the present embodiment, a more excellent effect can be obtained.
[0460]
That is, as shown in FIGS. 32A and 32B, when adjacent source / drain diffusion regions 1407 are connected via the element isolation region 1408, the first memory cell array shown in FIG. As shown in FIG. 32 (b), a unique contact hole is formed for each source / drain diffusion region 1407, and the adjacent source / drain diffusion regions 1407 are connected by the first-layer metal wiring 1432. When the adjacent source / drain diffusion regions 1407 are connected to each other by the contact holes 1431 as in the second memory cell array shown in FIG. 1), the design margin in consideration of misalignment can be reduced, and the memory can be dramatically improved. The area of the cell array can be reduced. In other words, in the case of FIG. 32B, adjacent contact holes are connected to form one large contact hole, so that there is no need to perform alignment with the contact hole of the element isolation region below the connected portion. Therefore, the misalignment allowance between the contact hole and the element isolation region 1408 is reduced by half. Thereby, the area of the memory cell array can be significantly reduced.
[0461]
Here, as in the second memory cell array shown in FIG. 32B, a large contact hole 1431 that straddles the element isolation region 1408 can be formed only in the element isolation region 1408 and the interlayer insulating film 1441. This is because there is a step of forming a coating film 1421 using a material having a large etching ratio on the semiconductor substrate 1401 over the element isolation region 1408. With the coating film 1421, the etching is temporarily stopped at the coating film during the contact etching. This can prevent the element isolation region 1408 from being excessively etched. Further, when the coating film 1421 exposed in the contact hole is etched, etching can be performed under an etching condition having a high selectivity with respect to the element isolation region 1408, so that the element isolation region 1408 can be prevented from being excessively etched, and a favorable contact can be prevented. Properties can be obtained.
[0462]
Next, the operation of the memory cell array will be described.
[0463]
In the circuit diagram of the memory cell array shown in FIG. 31A, for simplicity, storage elements are represented by symbols representing ordinary field-effect transistors.
[0464]
First, a reading method will be described. Here, it is assumed that the information stored in the memory storage unit (charge holding unit) M1 on the bit line BL2 side of the memory cell M22 is read. First, the bit lines BL1 and BL2 are precharged to a logic level L, and the bit lines BL3 and BL4 are precharged to a logic level H. After the precharge is completed, the word line WL2 is set to the logic level H. At the moment when the word line WL2 goes to the logic level H, the memory cell M22 is turned on. At this time, a high voltage (logic level H-logic level L) is applied between the source and the drain of the memory cell M22 and a current flows, but the current amount changes depending on the state of the memory storage unit M1. Therefore, the state of the memory storage unit M1 of the memory cell M22 can be known by detecting the amount of current flowing through the bit line BL2 or BL3 or monitoring the potential change of the bit line BL2 or BL3.
[0465]
In the above operation, if the bit line BL1 has not been precharged to the logic level L, the memory cell M21 is turned on at the moment when the word line WL2 goes to the logic level H, and the memory cell M21 is turned on from the bit line BL1 to the bit line BL2. Electric current flows. Such a current hinders detection of a current flowing through the selected memory cell M22. Therefore, it is preferable that bit line BL1 be precharged to the same logic level L as bit line BL2. Similarly, it is preferable that the bit line BL4 be precharged to the same logic level H as the bit line BL3.
[0466]
When the storage information of the memory storage unit (M2) on the bit line BL3 side of the memory cell M22 is called, the bit lines, BL1 and BL2 are set to the logic level H, BL3 and BL4 are set to the logic level L, and the precharge is performed. Do. After the precharge is completed, the word line WL2 may be set to the logic level H.
[0467]
Table 1 shows an example of specific voltages in the write, read, and erase operations of the memory cell array according to the nineteenth embodiment. In Table 1, Lbw, Hbw, Lww, and Hww are the low-level potential of the bit line, the high-level potential of the bit line, the low-level potential of the word line, and the high-level potential of the word line during writing, respectively. Lbr, Hbr, Lwr, and Hwr are the low-level potential of the bit line, the high-level potential of the bit line, the low-level potential of the word line, and the high-level potential of the word line during reading, respectively. Lbe1, Lbe2, Hbe, Lwe, and Hwe are the low level potential 1 of the bit line, the low level potential 2 of the bit line, the high level potential of the bit line, the low level potential of the word line, and the high level of the word line during erasing, respectively. Potential. In each case, an example of a specific voltage is shown in parentheses.
[0468]
Note that the erasing method shown in Table 1 uses the above-described second erasing method. Therefore, at the time of erasing, Lbe2 (+0.8 V in Table 1) is applied to the P-type well region. When erasing the memory storage unit M1 of the memory cell M22, electrons injected by a forward voltage applied to the P-type well region and the bit line BL3 serve as a trigger to perform erasing. In addition, Lbe2 is applied to the bit line BL1 in order to prevent erroneous erasure of the memory cell M21.
[0469]
[Table 1]

[0470]
As is clear from Table 1, the memory cell array of the present embodiment is capable of random access (reading and rewriting operation for each bit). For this reason, the access efficiency can be improved as compared with a device that needs to be erased all at once. In addition, there is no need to perform a sequence such as temporary storage of the memory state, batch erasing, and writing, so that the control circuit is simplified.
[0471]
According to the above-described read operation, when two-bit storage of a certain memory cell is continuously read (for example, the memory storage units M1 and M2 of the memory cell M22 are continuously read), a nearby bit line is read. Must be inverted (in the above example, the potentials of the bit lines BL1 to BL4 are all inverted), which is inefficient. Therefore, as will be described later, by devising an address decoder circuit and the like, and taking measures such as separating addresses for accessing the left and right memory storage units (charge holding units), it is possible to avoid a state in which data is continuously read alternately. Is preferred.
[0472]
In the memory cell Mij (i = 1, 2, 3, j = 1, 2, 3), the gate electrode is connected to the word line WLi (i = 1, 2, 3) and one of the source / drain diffusion regions is set to the first. The other of the source / drain diffusion regions is connected to the bit line BL1j (j = 1, 2, 3) and the second bit line BL2j (j = 1, 2, 3), respectively.
[0473]
The operation of the memory cell array may be performed by applying a voltage required for the operation method of the semiconductor memory device to a desired memory cell via a specific word line and first and second bit lines. For example, when writing to one of the memory storage units (charge holding units) of the memory cell M11, for example, + 2V is applied to the word line WL1, + 6V is applied to the first bit line BL11, and 0V is applied to the second bit line BL21. May be given respectively. To write data to the other of the memory storage unit (charge holding unit) of the memory cell M11, for example, + 2V is applied to the word line WL1, 0V is applied to the first bit line BL11, and + 6V is applied to the second bit line BL21. May be given respectively. At this time, for example, 0 V may be applied to other unselected word lines and unselected bit lines.
[0474]
As is clear from the above description, the memory cell array according to the nineteenth embodiment is configured by arranging the semiconductor memory devices. As described above, the semiconductor memory device can store two bits with one element and can reduce the thickness of the gate insulating film, so that miniaturization is easy. Therefore, the memory cell array according to the present embodiment in which the semiconductor memory devices are arranged and arranged is also easily miniaturized, and the manufacturing cost is reduced.
[0475]
Further, as described above, the process of forming the semiconductor memory device is very similar to a normal CMOS process, and can be manufactured much more easily than a conventional nonvolatile memory having a floating gate such as an EEPROM. is there. Therefore, it is easy to manufacture the memory cell array of the present embodiment, and it is also easy to mount the memory cell array together with the logic circuit.
[0476]
【The invention's effect】
As is clear from the above, according to the semiconductor memory device of the present invention, the interlayer insulating film is etched under the etching condition having a large selectivity with respect to the coating film, and the etching is stopped at the coating film. A semiconductor memory device having high reliability and low manufacturing cost can be provided. Further, since the contact and the gate electrode are isolated from each other and short-circuited by the coating film, a design margin can be reduced and a semiconductor memory device which can be easily miniaturized can be provided.
[0477]
Further, according to the semiconductor device of the present invention, a nonvolatile semiconductor memory device having a good memory effect and a semiconductor switching element having a high current driving capability can be mixedly mounted.
[0478]
Further, according to the IC card of the present invention, a highly reliable and low-cost IC card can be provided.
[0479]
According to the portable electronic device of the present invention, a highly reliable and low-cost portable electronic device can be provided.
[0480]
According to the method of manufacturing a semiconductor memory device of the present invention, the interlayer insulating film is etched under the etching condition having a large selectivity with respect to the coating film, and the etching is stopped at the coating film. A semiconductor memory device with high cost and low manufacturing cost can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing an outline of the structure of a semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a schematic sectional view showing an outline of another structure of the semiconductor memory device of the first embodiment.
FIG. 3 is a schematic cross-sectional view showing a manufacturing process of a semiconductor memory device using a semiconductor memory device according to a second embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a manufacturing step of a semiconductor memory device using the semiconductor memory device following FIG. 3;
FIG. 5 is a schematic cross-sectional view showing a manufacturing process of a semiconductor memory device using the semiconductor memory device according to the third embodiment of the present invention.
FIG. 6 is a schematic sectional view showing a manufacturing process of a semiconductor memory device using a semiconductor memory device according to a fourth embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a manufacturing step of the semiconductor memory device following FIG. 6;
FIG. 8 is a schematic sectional view showing a manufacturing process of a semiconductor memory device using a semiconductor memory device according to a fifth embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor memory device following FIG. 8;
FIG. 10 is a schematic sectional view showing a manufacturing process of a semiconductor memory device using a semiconductor memory device according to a sixth embodiment of the present invention.
FIG. 11 is a schematic cross-sectional view showing a manufacturing step of the semiconductor memory device following FIG. 10;
FIG. 12 is a schematic overhead view showing a separated memory function body in a manufacturing process of the semiconductor memory device.
FIG. 13 is a schematic cross-sectional view showing an outline of a structure of a memory function body of a semiconductor memory device according to a seventh embodiment of the present invention.
FIG. 14 is a schematic cross-sectional view showing a manufacturing step of the semiconductor memory device according to the eighth embodiment of the present invention.
FIG. 15 is a schematic sectional view showing the outline of the structure of a semiconductor memory device according to a ninth embodiment of the present invention;
FIG. 16 is an enlarged view of a peripheral portion of a memory function body on the right side of FIG. 15;
FIG. 17 shows a case where the end of the memory function body of the semiconductor memory device on the side remote from the gate electrode of the silicon nitride film does not coincide with the end of the memory function body on the side away from the gate electrode; It is an enlarged view of a memory functional body peripheral part.
FIG. 18 is a diagram showing a drain current when the offset amount is changed while the width of the memory function body of the semiconductor memory device is fixed.
FIG. 19 is an enlarged view of a peripheral portion of the memory function body when the upper surface of the charge holding film of the semiconductor memory device is arranged at an equal distance from the upper surface of the gate insulating film.
FIG. 20 is an enlarged view of a peripheral portion of a memory function body of a semiconductor memory device according to a tenth embodiment of the present invention.
FIG. 21 is a schematic sectional view showing an outline of a structure of a semiconductor memory device according to an eleventh embodiment of the present invention;
FIG. 22 is a schematic sectional view of a semiconductor memory device according to a twelfth embodiment of the present invention.
FIG. 23 is a schematic sectional view of a semiconductor memory device according to a thirteenth embodiment of the present invention.
FIG. 24 is a schematic sectional view of a semiconductor memory device according to a fourteenth embodiment of the present invention.
FIG. 25 is a schematic sectional view of a semiconductor memory device according to a fifteenth embodiment of the present invention.
FIG. 26 is a configuration diagram of a semiconductor device according to a sixteenth embodiment of the present invention.
FIG. 27 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device.
FIG. 28 is a schematic sectional view showing a manufacturing step of the semiconductor device following FIG. 27;
FIG. 29 is a schematic block diagram showing an IC card according to a seventeenth embodiment of the present invention.
FIG. 30 is a schematic block diagram showing a portable electronic device according to an eighteenth embodiment of the present invention.
FIG. 31 (a) is a circuit diagram of a memory cell array of a semiconductor memory device according to a nineteenth embodiment of the present invention, and FIG. 31 (b) is a schematic plan view of the memory cell array.
32 (a) is a schematic cross-sectional view of the first memory cell array taken along section line CC of FIG. 31 (b), and FIG. 32 (b) is a section line of FIG. 31 (b). FIG. 4 is a schematic cross-sectional view of the first memory cell array along CC.
FIG. 33 is a structural sectional view of a flash memory device as a conventional semiconductor memory device.
[Explanation of symbols]
1,101,201,301,401,501,601,801,911,986,1101,1401 ... semiconductor substrate
2, 102, 202, 302, 402, 502, 602, 802, 914, 1102, 1402 ... gate insulating film
3, 103, 203, 303, 403, 503, 603, 803, 917, 1103, 1403 ... gate electrode
8, 108, 208, 308, 408, 508, 608, 808, 1108 ... gate stack
13a, 13b, 113a, 113b, 213, 313, 413, 513, 613, 813, 912, 913, 1113, 1407 ... source / drain diffusion regions
116, 616, 716, 943 ... sidewall insulator
117,942 ... Silicon nitride film
18a, 18b, 218a, 218b ... charge holding unit
19: Channel formation region
20, 120, 220, 971 ... offset area
21, 121, 221, 321, 421, 521, 621, 821, 1121... First coating film
23, 123, 223, 323, 423, 523, 623, 1123, 1441 ... interlayer insulating film
25,125,225,325,425,525,625,1125 ... contact
26, 126, 226, 326, 526, 626, 826, 1126 ... second coating film
27, 427... Third coating film
28, 528, 628, 1408: Element isolation region
111a, 111b, 811, 961, 962, 981 ... memory function body
112, 612, 712... First insulator
122: region under the gate electrode
224, 524, 1124 ... contact holes
609: first insulating film
617: silicon nitride film
614 ... material (conductor, etc.)
615, 715: polysilicon
629: Second insulating film
710: Silicon dot
941 ... Silicon oxide film
987: Body area
988: buried oxide film
991 ... P type high concentration area
992 ... channel area
1000 ... semiconductor substrate
1001 ... memory cell array
1002 ... Peripheral circuit
1003 ... Decoder
1004 ... I / O circuit
1005 ... Control circuit
1006 ... Analog circuit
1007 ... Decoder
1008 readout circuit
1011 ... MPU
1012: Cache SRAM
1013 Logic circuit
1014: Analog circuit
1104: Logic circuit area
1105 memory area
1106: LDD area
1107 Photoresist
1200A, 1200B ... IC card
1201… MPU part
1202 ... Calculation unit
1203 ... Control unit
1204: Data memory unit
1205 ROM
1206 ... RAM
1207 ... Wiring
1208: Connect section
1209 ... Reader / writer
1210 ... RF interface
1211: Antenna part
1301 ... MPU section
1302 arithmetic unit
1303 ... Control unit
1304 Data memory unit
1305 ... ROM
1306 RAM
1307 ... Wiring
1308: Man-machine interface
1310 ... RF circuit section
1311 ... antenna part
1421 ... Coating film
1431 ... contact hole
1432: 1st layer metal wiring
1433: Via hole
1434: Second layer metal wiring

Claims (22)

A gate electrode formed on a semiconductor substrate via a gate insulating film,
A channel formation region arranged at least in a region below the gate electrode of the semiconductor substrate,
A pair of source / drain diffusion regions disposed on both sides of the channel formation region of the semiconductor substrate and having a conductivity type opposite to that of the channel formation region;
An interlayer insulating film formed at least above the gate electrode;
A coating film formed of an insulator having a function of retaining charges formed on the sides of the interlayer insulating film, formed to cover the upper side and the side of the gate electrode;
A contact formed on the side of the gate electrode via the coating film and electrically connected to the source / drain diffusion region;
The semiconductor memory device according to claim 1, wherein the coating film is made of a material having a selectivity to the interlayer insulating film so as to function as an etching stop material when etching the interlayer insulating film. A gate electrode formed on a semiconductor substrate via a gate insulating film,
A channel formation region arranged at least in a region below the gate electrode of the semiconductor substrate,
A pair of source / drain diffusion regions disposed on both sides of the channel formation region of the semiconductor substrate and having a conductivity type opposite to that of the channel formation region;
A third coating film made of an insulator formed on the gate electrode,
A first coating film made of an insulator having a function of retaining electric charges formed at least on a side of the gate electrode and a side of the third coating film;
An interlayer insulating film formed at least above the third coating film;
A contact formed on the side of the gate electrode via the first coating film and electrically connected to the source / drain diffusion region;
The semiconductor memory device according to claim 1, wherein the first coating film is made of a material having a selectivity to the interlayer insulating film so as to function as an etching stop material when etching the interlayer insulating film. A gate electrode formed on a semiconductor substrate via a gate insulating film,
A channel formation region arranged at least in a region below the gate electrode of the semiconductor substrate,
A pair of source / drain diffusion regions disposed on both sides of the channel formation region of the semiconductor substrate and having a conductivity type opposite to that of the channel formation region;
A memory function body formed on both sides of the gate electrode and formed of a charge holding portion made of a material having a function of holding charge and a dissipation prevention insulator having a function of preventing dissipation of the charge held in the charge holding portion; ,
An interlayer insulating film formed at least above the gate electrode;
A coating film formed of an insulator formed on the side of the interlayer insulating film, and formed to cover the gate electrode and the memory function body;
A contact formed on the side of the gate electrode via the coating film and electrically connected to the source / drain diffusion region;
The semiconductor memory device according to claim 1, wherein the coating film is made of a material having a selectivity to the interlayer insulating film so as to function as an etching stop material when etching the interlayer insulating film. The semiconductor memory device according to claim 1, wherein
The semiconductor memory device according to claim 1, wherein the source / drain diffusion region is arranged at a distance from the gate electrode in a channel direction. The semiconductor memory device according to claim 1, wherein
The semiconductor substrate and the gate electrode are made of silicon,
The gate insulating film and the coating film and the interlayer insulating film are made of a silicon compound,
A semiconductor memory device, wherein the silicon compound of the coating film is a silicon nitride film. The semiconductor memory device according to claim 3,
The memory function body,
A first insulator as the dissipation prevention insulator formed on both sides of the gate electrode;
A nitride film as the charge holding portion formed on a side wall portion of the first insulator;
A semiconductor memory device comprising: a sidewall insulator serving as the dissipation prevention insulator formed on a sidewall of the nitride film. The semiconductor memory device according to claim 3,
The memory function body,
A first insulator as the dissipation prevention insulator formed on both sides of the gate electrode;
A semiconductor memory device, comprising: a side wall insulator formed on a side wall portion of the first insulator, the side wall insulator including a plurality of fine particles as the charge holding portion. The semiconductor memory device according to claim 3,
The memory function body,
A first insulator as the dissipation prevention insulator formed on both sides of the gate electrode;
The charge holding portion formed on a side wall of the first insulator;
A sidewall insulator as the dissipation prevention insulator formed so as to sandwich the charge holding portion between the first insulator and the first insulator;
The semiconductor storage device according to claim 1, wherein the charge holding unit is narrower than the memory functional unit. The semiconductor memory device according to claim 3,
The memory function body,
A first insulator as the dissipation prevention insulator formed on both sides of the gate electrode;
The charge holding portion formed on a side wall of the first insulator;
Having a sidewall insulator as the dissipation prevention insulator formed so as to cover the charge holding portion,
The charge holding portion is narrower in width than the memory function body and lower in height than the memory function body, and is in contact with the first insulator and covered with the sidewall insulator. Semiconductor storage device. The semiconductor memory device according to claim 3,
The memory function body,
The anti-dissipation insulator formed on both sides of the gate electrode, a sidewall insulator including a plurality of fine particles therein as the charge holding unit,
A film made of a conductor or a semiconductor disposed between the sidewall insulator and the gate electrode and between the sidewall insulator and the semiconductor substrate;
A first insulator serving as the dissipation prevention insulator disposed between the conductor or semiconductor film and the gate electrode and between the conductor or semiconductor film and the semiconductor substrate; A semiconductor memory device characterized by the following. The semiconductor memory device according to claim 1, wherein
A semiconductor memory device having an element isolation region arranged so as to electrically separate a source / drain diffusion region of a semiconductor memory element adjacent to each other. A semiconductor device having a memory region having the semiconductor memory device according to claim 1 and a logic circuit region having a semiconductor switching element arranged on a semiconductor substrate,
The semiconductor storage device and the semiconductor switching element are field-effect transistors each having a gate electrode and a pair of source / drain diffusion regions formed on the surface of a semiconductor substrate corresponding to both sides of the gate electrode;
4. The semiconductor switching element according to claim 1, wherein at least a part of the source / drain diffusion region is disposed below the gate electrode on the surface of the semiconductor substrate. A semiconductor device, wherein the semiconductor device extends. An IC card comprising the semiconductor storage device according to claim 1 or the semiconductor device according to claim 12. 13. A portable electronic device comprising the semiconductor memory device according to claim 1 or the semiconductor device according to claim 12. Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After forming the gate electrode, a step of forming a first coating film made of an insulator having a function of retaining electric charge so as to cover the semiconductor substrate and the gate electrode;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Removing the first coating film exposed in the contact hole to expose a part of a side wall and an upper surface of the gate electrode;
After removing the first coating film, a second coating film made of an insulator having a function of retaining electric charges is formed on at least a side wall and an upper surface of the gate electrode newly exposed in the contact hole. And a method of manufacturing a semiconductor memory device. Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After forming the gate electrode, a step of forming a first coating film made of an insulator having a function of retaining electric charge so as to cover the semiconductor substrate and the gate electrode;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Anisotropic selective etching back is performed on the first coating film exposed in the contact hole to remove a part of the upper surface of the gate electrode and the semiconductor substrate while leaving a side wall shape on the side surface of the gate electrode. Exposing,
Forming a second coating film on at least the upper surface of the gate electrode newly exposed in the contact hole after exposing the semiconductor substrate. Forming a gate electrode on the semiconductor substrate via a gate insulating film;
Forming a third coating film above the gate electrode;
After forming the third coating film, a first coating film made of an insulator having a function of retaining electric charge is formed so as to cover the semiconductor substrate, the gate electrode, and the third coating film. Forming,
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Subjecting the first coating film exposed in the contact hole to anisotropic selective etching back to expose the semiconductor substrate while leaving a side wall shape on a side surface of the gate electrode. Manufacturing method of a semiconductor memory device. The method of manufacturing a semiconductor memory device according to claim 15,
Forming a source / drain diffusion region in a self-aligned manner at a distance from the gate electrode in the channel direction by implanting impurities after forming the first coating film. Of manufacturing a semiconductor memory device. Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After the gate electrode is formed, a charge holding portion made of a material having a function of holding charge on a side wall of the gate electrode, and a dissipation prevention insulator having a function of preventing dissipation of the charge held in the charge holding portion. Forming a memory function body comprising:
After forming the memory function body, forming a first coating film so as to cover the semiconductor substrate, the gate electrode, and the memory function body;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Removing the first coating film exposed in the contact hole to expose a part of a side wall and an upper surface of the memory function body;
After the step of removing the first coating film, a step of forming a second coating film on a side wall and an upper surface of the memory function body newly exposed in the contact hole. A method for manufacturing a storage device. Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After the gate electrode is formed, a charge holding portion made of a material having a function of holding charge on a side wall of the gate electrode, and a dissipation prevention insulator having a function of preventing dissipation of the charge held in the charge holding portion. Forming a memory function body comprising:
After forming the memory function body, forming a first coating film so as to cover the semiconductor substrate, the gate electrode, and the memory function body;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Anisotropic selective etching back is performed on the first coating film exposed in the contact hole to remove a part of the upper surface of the gate electrode and the semiconductor substrate while leaving a side wall shape on the side surface of the gate electrode. Exposing,
Forming a second coating film on at least the upper surface of the gate electrode newly exposed in the contact hole after exposing the semiconductor substrate. Forming a gate electrode on the semiconductor substrate via a gate insulating film;
After the gate electrode is formed, a charge holding portion made of a material having a function of holding charge on a side wall of the gate electrode, and a dissipation prevention insulator having a function of preventing dissipation of the charge held in the charge holding portion. Forming a memory function body comprising:
Forming a third coating film above the gate electrode after forming the memory function body;
Forming a first coating film so as to cover the semiconductor substrate, the gate electrode, the third coating film, and the memory function body;
Forming an interlayer insulating film above the first coating film;
Forming a contact hole by performing anisotropic selective etching on the interlayer insulating film using the first coating film as an etching stopper material;
Subjecting the first coating film exposed in the contact hole to anisotropic selective etching back to expose the semiconductor substrate while leaving a side wall shape on a side surface of the gate electrode. Manufacturing method of a semiconductor memory device. The method of manufacturing a semiconductor memory device according to claim 15,
A method for manufacturing a semiconductor memory device, wherein the coating film is a nitride film.

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