JP2004335641A - Method of manufacturing substrate having built-in semiconductor element - Google Patents

Method of manufacturing substrate having built-in semiconductor element Download PDF

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JP2004335641A
JP2004335641A JP2003127990A JP2003127990A JP2004335641A JP 2004335641 A JP2004335641 A JP 2004335641A JP 2003127990 A JP2003127990 A JP 2003127990A JP 2003127990 A JP2003127990 A JP 2003127990A JP 2004335641 A JP2004335641 A JP 2004335641A
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semiconductor element
sheet
semiconductor chip
substrate
manufacturing
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Hiroshi Kondo
浩史 近藤
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Canon Inc
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Canon Inc
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a simple and high accurate method of manufacturing a substrate having a built-in semiconductor element which is miniaturized by embedding the semiconductor element in a circuit substrate. <P>SOLUTION: In this method of manufacturing a substrate having a built-in semiconductor element, the semiconductor element is bonded on a first sheet, a second sheet having an opening is placed thereon, a conductive third sheet is further placed thereon, and then the first to third sheets are collectively subjected to thermal compression. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、回路基板に電気回路部品を実装した半導体素子内蔵基板の製造方法に関するものである。
【０００２】
【従来の技術】
近年電子機器製品の小型・軽量化のため、電子機器製品内に組み込まれる半導体素子内蔵基板の小型化が望まれている。
【０００３】
従来の半導体素子内蔵基板の小型化の手段として、プリプレグからなり孔部を有する枠材を底板にプレス積層して凹部を有する基板を形成し、その後に半導体チップを凹部に貼り付けた後圧着し、さらにその上に絶縁層や配線層を形成し、さらにその上に電気回路部品を実装する方法が提案されている（例えば特許文献１参照。）
また、半導体チップを回路基板上に逐次積層していく方法が提案されている。（例えば特許文献２参照。）
さらには、半導体チップの電極部にバンプを形成して絶縁樹脂を塗布して埋め込み、研磨する方法が提案されている。（例えば特許文献３参照。）
【特許文献１】
特開２００２−１６１７３号公報（第４頁）
【特許文献２】
特開平５−１３９６７号公報
【特許文献３】
特開２００２−２９０００６号公報
【０００４】
【発明が解決しようとする課題】
しかしながら、特開２００２−１６１７３号公報記載の発明には次のような課題があった。
【０００５】
基板を積層する際のプレス工程においてプレス圧力が不均一となり密着不足を発生させたり、凹部の形状が不均一になる。特に、熱プレスを用いた場合、プリプレグ中の樹脂が熱プレス工程により軟化して凹部内に流れ込み、凹部の底に大きな凹凸をもったり、最悪の場合凹部が埋まってしまい、後に半導体チップを載置するために必要な凹部形状が保てない。
【０００６】
また、半導体チップを埋め込むためには、回路基板凹部の底に半導体チップを保持できるようにするための保持面を形成しなければならず、この保持面のための絶縁層が必要になるが、このようにすると半導体チップを挟んだ導体層間の絶縁層の厚みは、半導体チップ厚に保持面上の絶縁層の厚みが加わったものとなり非常に厚くなってしまう。そのため、複数の層からなる回路基板の複数の層間に半導体チップを埋め込んだ場合、回路基板の層厚がきわめて厚くなり小型化できなくなる。
【０００７】
さらに、このように凹部を形成した後に半導体チップを組み込み、その後に埋め込む方式では、多層化していく際に各々の層毎に凹部を形成していかなければならず、極めて生産効率が悪い。
【０００８】
また、このような凹部を基板に設けその中に半導体チップを搭載し、その後にこの半導体チップを覆うために液状絶縁性樹脂を用いる方法では、絶縁樹脂の硬化収縮時の樹脂量が面内で異なることから、硬化後の絶縁性樹脂表面の均一性・平坦性が得られ難く、そのため、露光・現像・エッチング工程にてレジスト像が乱れ、微細な配線パターンの形成をおこなうことができない。特に半導体チップ周辺は、チップ厚み分の樹脂が硬化収縮するため、表面が凹になりやすい。
【０００９】
凹部を形成しないで埋め込む方式の場合には、基板の表面にあらかじめ形成された配線パターンの電極部と半導体チップの電極部とを接続する接合工程が必ず必要になる。
【００１０】
この接続を行う方法として、フリップチップ接続をおこなう場合には、半導体チップの電極パッド部にはんだバンプあるいはボールを形成させる必要がある。
そして、この半導体チップのはんだバンプと基板の配線パターンの電極部とを位置合わせの後に半導体チップをパターン電極上に搭載し、加熱することで接合させる。そして、半導体チップ表面と基板表面との間のバンプによってできているギャップ間にアンダーフィル材と呼ばれる接続補強樹脂を注入し固着させるといた複雑な接合工程が必要となる。
【００１１】
さらに、このようなフリップチップ接続を今後の多ピン化が進む半導体チップで行おうとするならば、半導体チップに形成されるバンプやハンダボールの微細化かつ高精度化が要求されるだけでなく、基板の配線ピッチも、より微細化を要求される。そのため、バンプ形成コストと基板コストが大幅に上昇する。さらに、搭載時の位置合わせ精度もより厳しいものが要求され、装置コストの上昇を招いてしまう。
【００１２】
逐次積層していく方式では、常に半導体チップの電極部は、同一面方向を向かざるを得ない。そのため、半導体チップと半導体チップとの間を接続するには、最短でも半導体Ｃｈｉｐ厚以上は必要になり配線長を短くすることが難しい。そのため、より高速な信号の伝送を行う際に信号波形の遅れや波形形状の乱れになり、高速な信号伝送が難しい。
【００１３】
また、半導体チップ上に積層されかつ、各半導体チップの電極部より配線を接続するためには、必ず半導体チップ上に積層される半導体チップのサイズは、その下の半導体チップより小さくなくてはならず、積層する各半導体チップがそのサイズによって限定されるといった設計制約がある。
【００１４】
半導体チップの電極部にバンプを形成して絶縁樹脂を塗布して埋め込み、研磨する方式では、バンプ上を覆っている絶縁樹脂を除去するためと、絶縁樹脂表面を平坦化させるために必ず研磨工程が必要になる。一方レーザーによってスタッドバンプを露出させるものに関しては、反射率の高い金からなり、かつネックカットした形状安定性の悪いスタッドバンプにレーザー光があたると、レーザー光が反射・散乱され加工穴形状が著しく悪くなる。そのため、通常１００μｍ以下という極めて狭ピッチな半導体チップの電極部ピッチに対して、安定した接続用の穴加工を行うことができない。
【００１５】
また、穴加工精度を緩和させるための半導体チップ電極面積より大きいバンプを半導体チップ上に設ける方式では、半導体チップの電極数の増加に伴う電極間ピッチの狭ピッチ化に対応できない。また、穴加工時の位置精度のためだけに、バンプ形成工程が必要となりコストアップとなる。
【００１６】
【課題を解決するための手段】
本発明に係る第１の半導体素子内蔵基板の製造方法は、回路基板中に半導体素子が埋設された半導体素子内蔵基板の製造方法において、
第一のシートに前記半導体素子を接着する工程と、
硬化反応途中の絶縁性樹脂からなり開口部を有する第二のシートを、前記開口部中に前記半導体素子が収容されるように前記第一のシート上に載置する工程と、
導電体からなる第三のシートを前記第二のシート上に載置する工程と、
前記第一、第二及び第三のシートを一括して熱圧着する工程と、
前記第二及び第三のシートの、前記半導体素子の電極部直上に位置する部分を除去する工程と、
前記電極部と前記第三のシートとを電気的に接続する工程と、
前記第三のシートをパターン状に加工し配線を形成する工程と、を有することを特徴とするものである。
【００１７】
本発明に係る第２の半導体素子内蔵基板の製造方法は、上記第１の製造方法において、第三のシートは第二のシートに面する側に硬化反応途中の絶縁性樹脂を有することを特徴とするものである。
【００１８】
本発明に係る第３の半導体素子内蔵基板の製造方法は、上記第１の製造方法において、第一のシートに半導体素子を接着する工程の際、前記半導体素子の電極部を有する面側を前記第一のシートに接着することを特徴とするものである。
【００１９】
本発明に係る第４の半導体素子内蔵基板の製造方法は、上記第１の製造方法において、第一のシートに半導体素子を接着する工程の際、接着部材として無機粒子を含有する絶縁性樹脂を用いることを特徴とするものである。
【００２０】
本発明に係る第５の半導体素子内蔵基板の製造方法は、上記第１の製造方法において、第二のシートは熱圧着する工程における加熱温度では溶融あるいは流動しない材料を含んでいることを特徴とするものである。
【００２１】
従来の半導体素子内蔵基板の製造方法に比べ、以下のような様々な効果を得ることが可能となる。
【００２２】
本発明では、完成あるいは、半完成の回路基板に凹部を設けるといった工程を必要とせず、複数の積層されたシートと半導体素子を一括して熱圧着して半導体素子を回路基板内に埋め込むことにより、大幅な工程の短縮とコスト削減が図られる。さらに半導体素子を搭載保持するための絶縁層部を設ける必要がないので、半導体素子の埋め込み後の厚みを薄くすることが可能である。
【００２３】
また、従来生じていた、半導体ウェハー上への再配線を行う際に不良な半導体素子までも再配線を形成していた問題、半導体素子上にしか電極を拡張できず、多ピン化に対応できない問題は、容易に解決できる。
【００２４】
さらに、複数の半導体素子を積層する場合のバーイン検査に関しても、半導体素子を内蔵し配線が形成されたものであれば、テスト治具の有する電極端子ピッチに十分対応することができコストアップせず容易に検査を行うことが可能となる。そこで、検査後の良品のものを組み合わせることが可能であり、かつ内蔵された半導体素子のサイズに関係なく基板上に接続用電極を設けることが可能であるので、組み合わせに関しての半導体素子のサイズ制約なく半導体素子を組み合わせることが可能となる。
【００２５】
さらに、半導体素子が内蔵された両面回路基板の一面には、システム基板接続用の電極を設け、他面には汎用ＩＣ用の電極を設けておくことにより、パッケージ上に汎用ＩＣを搭載することが可能となるので、製品毎の様々な仕様変更に対しても容易に対応が可能といった設計の自由度が大幅に大きくなる。
【００２６】
また、熱圧着工程により、半導体素子を取り囲む第二のシートが均一な材料特性を有する絶縁層として形成されるため、半導体素子内蔵基板全体の反りやうねりの発生を抑えることになり、安定した微細配線パターンを形成することが可能である。
【００２７】
さらに、半導体素子裏面直下にパターンを形成することも容易に行えるので、このパターンを放熱用のヒートスプレッダーにすることで放熱性を高めることができる。
【００２８】
また、上記のような半導体素子を内蔵した両面基板をそれぞれ準備し、それらをさらに積層していくことで、様々な回路構成に対応することが、容易に可能となる。
【００２９】
【発明の実施の形態】
（実施例１）
以下、本発明の実施例１にかかる半導体素子内蔵基板の製造方法について、図１を参照して説明する。図１は本発明の実施例１にかかる半導体素子内蔵基板の製造方法を示す断面図である。
【００３０】
図１（ａ）に示すように、半導体素子としての半導体チップ１の裏面に絶縁性エポキシ樹脂４を設け、半導体チップ１を絶縁性エポキシ樹脂４を介して銅箔からなる第一のシート３の粗面化された面側に搭載する。
【００３１】
第一のシートは導電性である事を有しないが、導電体である場合は公知のリソグラフィ技術を用いて第一のシートに配線パターンを容易に形成することが可能となる。
【００３２】
その後、絶縁性エポキシ樹脂４を熱硬化させ、半導体チップ１を第一のシート３に接着させる。
【００３３】
絶縁性エポキシ樹脂４の厚みは、接着に必要な強度を得ることが可能でなるならば、薄ければ薄いほど好ましいが、一般的には１０〜３０μｍの範囲が良い。
【００３４】
これよりも薄いと塗布時に均一な膜厚を確保することができず、気泡や未塗布の領域が発生してしまい、後の工程において剥離を発生させてしまう。
【００３５】
また、これよりも厚いと半導体チップを固定する際に半導体チップが加圧力のばらつきにより傾斜して取り付くことになり、後の熱プレス工程において半導体チップの端部に高い応力が加わり半導体チップが破損してしまう。
【００３６】
また、第一のシート３の厚みは８〜３５μｍの範囲が良い。
【００３７】
これよりも薄いとハンドリングの際にシートが破断してしまったり、よれ、うねりを発生させてしまい安定して生産することができない。
【００３８】
また、これよりも厚いと、この第１のシートに後に形成する配線を形成する際にエッチングにより微細な配線を形成することができなくなる。
【００３９】
次に図１（ｂ）に示すように半導体チップ１の厚み（通常５０〜１５０μｍ程度）とほぼ同じ厚みをもち、半導体チップ１に対応する形状の開口部５ａを打ち抜きプレスによって形成した第二のシート５をその開口部５ａが半導体チップ１を収容する位置に配置する。
【００４０】
第二のシート５は硬化反応途中の絶縁性樹脂であるエポキシ樹脂からなり、ガラスクロスが含まれたプリプレグ材を使用した。
【００４１】
第二のシート５の上に、第三のシート７を載置する。
【００４２】
第三のシート７として銅箔３’上に硬化反応途中の絶縁性樹脂としてのエポキシ樹脂６をコーティングしたＲＣＣ（レジンコーテッドカッパー）材を用いた。
【００４３】
エポキシ樹脂６の厚みは１０〜６０μｍの範囲が良い。
【００４４】
これよりも薄いと半導体チップ上面の微細な凹凸を埋め込みその上の導体層である銅箔３‘との層間絶縁性が保たれなくなったり、未充填部が発生し、後にその未充填部から剥離を発生させてしまう。
【００４５】
また、これよりも厚いと後の工程で半導体チップ電極との接続を行う際に電極部上に形成する穴のアスペクト比（穴径 対 深さ）が１以上となってしまい、非常に加工性が下がってしまう。
【００４６】
なお、第三のシート７には硬化反応途中の絶縁性樹脂は必ずしも無くて良い。
【００４７】
硬化反応性の樹脂を有する場合は、樹脂量を増やすことにより、銅箔との密着強度をより高く得ることができるとともに、未充填の発生頻度を抑えることができる。
【００４８】
このように積み重ねて配置した上記のシートに真空雰囲気にて熱圧着をおこなう。このときの加熱温度は１５０〜２００℃の温度が好ましい。
【００４９】
熱圧着により、第二のシート５中のエポキシ樹脂と第三のシート７のエポキシ樹脂６が溶融し、半導体チップ１を図１（ｃ）にあるように両面が銅箔に覆われたエポキシ樹脂中に埋め込んでしまう。
【００５０】
このとき、第二のシート５としてガラスクロス入りのプリプレグ材を使用するのは、熱圧着時の圧力により半導体チップ１が存在する場所と存在しない場所での圧力差によりプレス後の表面の平坦性が損なわれるのを防ぐためである。
【００５１】
従って、ガラスクロスの厚みは半導体チップの厚みと等しいか若干厚い方が好ましい。
【００５２】
次に、図１（ｄ）にあるように半導体チップ１の電極部２の位置に該当する部分の銅箔３’を通常のエッチングで除去し、その後、この穴部に露出する絶縁樹脂をＣＯ２あるいは、ＹＡＧ、エキシマといったレーザーにより除去し、半導体チップ１の電極部２が露出するようＶｉａ穴８を形成する。なお、半導体チップ１の電極部２は、Ａｌ上にＴｉ／Ｎｉの拡散バリア層をあらかじめウェハー工程にて作りこんでおく。
【００５３】
つぎに、Ｖｉａ穴８のクリーニングを過マンガン酸等により行い、図１（ｅ）に示すようにメッキ工程にて全面に銅層３ａを析出させる。これにより電極部２と銅箔３’とが接続される。
【００５４】
次に、銅層３ａとにレジスト材を塗り、露光・現像工程によりパターンをエッチングで形成し、図１（ｆ）のような半導体チップ１が内蔵された両面配線回路基板を得る。このような両面配線回路基板は、多層配線回路基板を製造する際の基本構成であることから、次に述べるような多層化が容易に行える。
【００５５】
図２に示すように、このような両面配線回路基板を間にプリプレグ材を介し、再度熱圧着をおこない、ドリルによる穴あけとメッキによるスルーホール９を形成することで、容易に多層化は可能となる。
【００５６】
また、積層させるものは、両面配線回路基板である必要はなく、プリプレグ材と銅箔とを本発明の両面配線回路基板の両面に配置し、熱圧着を行えば４層配線基板が形成される。
【００５７】
このように形成された半導体チップ１内蔵の回路基板は従来の回路基板と同じ工程により製造されているので、従来と同様に電子回路部品を表面に実装が可能であり、半導体チップ１が埋め込まれた半導体素子内蔵基板が容易に製造される。
【００５８】
（実施例２）
図３は本発明の実施例２にかかる回路基板の製造方法を示す断面図である。
【００５９】
本実施例においては、図３（ａ）に示すように、配線２１が形成された基板１０上に半導体チップ１を実施例と同様に搭載し、接着させる。そして、第１の実施例と同様にプリプレグ材とＲＣＣ材を用い、半導体チップを熱圧着により回路基板中に埋め込む。
【００６０】
次に、図３（ｄ）に示すように従来のビルドアップ基板の製造方法と同様に、銅箔３’上のビア穴を形成する位置にウィンドを形成し、レーザー光により絶縁層部にビア穴８、１１を形成する。その際、層間部２２を形成する際と半導体チップ１の電極部２を形成する際のレーザー光のスポット径を変えることにより、それぞれに適した穴径サイズを形成する。
【００６１】
次に、メッキ工程により、図３（ｅ）にあるように層間、半導体チップ１の電極部２とを接続し、その後、露出している銅にエッチングによりパターンを形成させる。
【００６２】
この工程を複数回繰り返せば、容易に多層化が図られることは、明らかである。
【００６３】
本実施例によれば、ビルドアップ基板の製造プロセスを用いることにより、層間接続にスルーホールでなくビアを使用するので、より高密度な回路基板を製造することが可能である。そのため、より高密度な実装による製品の小型化が可能となる。
【００６４】
（実施例３）
図４は、本発明の実施例３にかかる回路基板の製造方法を示す断面図である。
【００６５】
本実施例においては、半導体チップ１の電極部２を有する面を先に銅箔３と絶縁性エポキシ樹脂１２を用いて接着する。このエポキシ樹脂１２には、シリカ粒子が分散されており、熱伝導性の向上と、水分吸収率の低減と、熱膨張係数がエポキシ樹脂単独の５０ｐｐｍレベルから１０〜３０ｐｐｍへと低減することで半導体チップ表面にかかる熱応力の緩和を図ることが可能となっている。さらに、一括の熱プレスでの接着ではなく、半導体チップ１を個別に接着させるため、半導体チップ表面と銅箔３との間隔の制御が容易に行える。そのため、レーザーによる穴加工時のアスペクト比のばらつきがなく、より微細な穴径での加工ができ、より狭ピッチ多ピンの半導体チップに対応することが可能となる。
【００６６】
その他の製造方法は、実施例１と同様である。
【００６７】
（実施例４）
図５は、本発明の第４の実施例を示す模式的断面図である。
【００６８】
本実施例においては、保持用の絶縁性基材からなる基板１３上に半導体チップ１を搭載し、プリプレグ材５とＲＣＣ材７を介して一括熱プレスで半導体チップを埋設した後に、ＲＣＣ材の銅箔３’を全面で剥離する。その後レーザーにて、半導体チップ１の電極部２上にＶｉａ穴を設け、クリーニングした後全面にメッキにより銅を設ける。
【００６９】
その後、エッチングによりパターンを形成する。本実施例では、ＲＣＣ材の銅箔厚みがなく、メッキのみの厚みとなることから、より微細な配線パターンの形成が可能となる。
【００７０】
そして、パターン形成後、はんだレジスト層を設け、露出する銅パターンのランド部にはんだボール１４を搭載することで、半導体チップ内蔵の極めて薄いパッケージを提供することが可能となる。
【００７１】
さらに、スーパーＣＳＰ等のチップサイズ上だけしか接続用Ｐａｄを設けることができないといった制約は、ないので、接続Ｐａｄ数を満たした小型パッケージを容易に提供することが可能である。
【００７２】
また、本実施例では、保持用に絶縁性基材からなる基板１３を使用したが、熱伝導性の高い金属プレートを保持用に使用することも可能であり、この構成時には極めて放熱性の高いパッケージとなる。
【００７３】
本実施例では、通常のＣＳＰやＢＧＡパッケージのインターポーザー（中間基板）を別に製造するのではなく、インターポーザー製造と半導体チップの接続・封止工程を一括しておこなってしまう。そのため、非常に多くの工程数を削減でき、タクト時間の短縮、製造コストの削減をすることが可能となる。
【００７４】
（実施例５）
図６は、本発明の第５の実施例を示す模式的断面図である。
【００７５】
本実施例においては、上記第４の実施例による半導体チップが埋設され、パターンが形成された基板パッケージ１６の状態でバーンイン試験を行い、良品のチップが内蔵される基板パッケージ１６を判別する。そして、半導体チップが埋設された別の基板パッケージ１６’の一方の面に形成された配線ランド部にはんだペースト１７を印刷により設け、その後にこのランド部の位置に対向する位置にランド部が設けれているバーンイン試験で良品と判定された基板パッケージ１６を位置合わせの後搭載し、リフロー工程によりはんだペースト１７を溶融させ、基板パッケージの各ランド部間を接続する。
【００７６】
次に、この接続された基板パッケージの一方の面にあるランド部にはんだボール１４を搭載し、再びリフローによりはんだボール１４とランドとを接続し、パッケージ上にパッケージが実装された複合パッケージが正蔵される。
【００７７】
なお、本実施例では、半導体チップ内蔵基板パッケージ同士の組み合わせであったが、複数個のものを同様に組み合わせてもかまわない。
【００７８】
さらに、より汎用性の高い半導体チップと組み合わせる場合には、基板パッケージの接続用ランド部のデザインを汎用品のパッケージのランドデザインに合わせることで対応は、可能となる。
【００７９】
本実施例では、試験後の良品チップ内蔵のパッケージ同士を組み合わせることが可能となるため、不良混入による歩留まり低下を排除でき、かつ基板内部に半導体チップが埋め込まれていることから、パッケージを組み合わせても実装後の厚みは、極めて薄い複合パッケージを提供することが可能となる。
【００８０】
また、より薄い複合パッケージを求めるのであれば，図７に示すような不良率の高い半導体チップを基板内に埋め込み試験をおこない、その上で、良品と判断されたものにのみ、通常の半導体パッケージを製造するのと同様に半導体チップを搭載し、ワイヤーボンダーで接続しトランスファーモールドで封止をおこない、はんだボール１４を接続後、ダイシングソーにて個々のパッケージに切断することも可能である。
【００８１】
この方式では、通常のスタック構造より配線自由度、搭載チップサイズ自由度が大幅に高まるだけでなく、不良率の高い半導体チップに対しては中間検査を行えることか、より高い歩留まりを得ることができる。
【００８２】
【発明の効果】
以上述べてきたように、本発明では、半導体素子を基板製造工程中に一括した熱圧着工程にて基板内部に埋め込み、配線形成と合わせて接続することにより、半導体素子を基板内に精度良く埋め込み配置する事ができるとともに、大幅な製造工程の短縮が可能となる。
【００８３】
さらに、基板内部に埋め込まれ、パターンが形成されればバーンイン試験等の後工程試験は容易におこなうことが可能となることから、良品選別が可能であり、より複合化された場合であっても高い歩留まりを維持でき、低コスト化が可能となる。
【００８４】
また、配線設計自由度が高いことから、様々な半導体チップあるいは、電気回路部品との組み合わせに柔軟に対応することが可能であり、より高機能かつ小型の製品をローコストで提供することが可能となる。
【図面の簡単な説明】
【図１】第１の実施例を示す模式的断面製造図
【図２】第１の実施例の多層化を示す模式的断面製造図
【図３】第２の実施例を示す模式的断面製造図
【図４】第３の実施例を示す模式的断面製造図
【図５】第４の実施例を示す模式的断面製造図
【図６】第５の実施例を示す模式的断面製造図
【図７】第５の実施例を示す模式的断面製造図
【図８】従来例を示す模式的断面製造図
【符号の説明】
１ 半導体チップ
２ 半導体チップの電極部
３ 銅箔
４ 絶縁性接着剤
５ プリプレグ材
６ エポキシ樹脂（Ｂステージ状態）
７ ＲＣＣ
８ ビア穴
９ スルーホール
１０ 配線基板
１１ ビア穴（層間接続用）
１２ フィラー含有エポキシ樹脂
１３ 保持用基板
１４ はんだボール
１５ 基板パッケージ
１６ ランド部
１７ はんだペースト
１８ 金ワイヤー
１９ 封止モールド
２０ 凹部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a substrate with a built-in semiconductor element in which an electric circuit component is mounted on a circuit board.
[0002]
[Prior art]
In recent years, in order to reduce the size and weight of electronic device products, it is desired to reduce the size of a substrate with a built-in semiconductor element incorporated in the electronic device product.
[0003]
As a means for downsizing a conventional substrate with a built-in semiconductor element, a frame material having a hole made of prepreg is press-laminated on a bottom plate to form a substrate having a recess, and then a semiconductor chip is attached to the recess and then crimped. In addition, a method has been proposed in which an insulating layer or a wiring layer is further formed thereon, and an electric circuit component is further mounted thereon (see, for example, Patent Document 1).
A method of sequentially stacking semiconductor chips on a circuit board has been proposed. (For example, refer to Patent Document 2.)
Furthermore, a method has been proposed in which bumps are formed on electrode portions of a semiconductor chip, an insulating resin is applied, embedded, and polished. (For example, refer to Patent Document 3.)
[Patent Document 1]
JP 2002-16173 A (page 4)
[Patent Document 2]
JP-A-5-13967 [Patent Document 3]
Japanese Patent Laid-Open No. 2002-290006
[Problems to be solved by the invention]
However, the invention described in JP-A-2002-16173 has the following problems.
[0005]
In the pressing process when laminating the substrates, the pressing pressure becomes non-uniform, resulting in insufficient adhesion, and the shape of the recesses becomes non-uniform. In particular, when a hot press is used, the resin in the prepreg is softened by the hot pressing process and flows into the recesses, and the bottom of the recesses has large unevenness, or in the worst case, the recesses are buried, and the semiconductor chip is mounted later. The shape of the recess necessary for placement cannot be maintained.
[0006]
In order to embed a semiconductor chip, a holding surface for holding the semiconductor chip must be formed at the bottom of the concave portion of the circuit board, and an insulating layer for the holding surface is required. In this case, the thickness of the insulating layer between the conductor layers sandwiching the semiconductor chip is very thick because the thickness of the semiconductor chip is added to the thickness of the insulating layer on the holding surface. Therefore, when a semiconductor chip is embedded between a plurality of layers of a circuit board composed of a plurality of layers, the layer thickness of the circuit board becomes extremely thick and cannot be reduced in size.
[0007]
Further, in the method of incorporating the semiconductor chip after forming the recesses and embedding after that, the recesses must be formed for each layer when the number of layers is increased, and the production efficiency is extremely low.
[0008]
Further, in a method in which such a recess is provided in a substrate and a semiconductor chip is mounted therein, and then a liquid insulating resin is used to cover the semiconductor chip, the amount of resin when the insulating resin cures and shrinks is in-plane. Since they are different, it is difficult to obtain uniformity and flatness of the surface of the insulating resin after curing. For this reason, the resist image is disturbed in the exposure, development, and etching steps, and a fine wiring pattern cannot be formed. In particular, around the semiconductor chip, since the resin corresponding to the chip thickness cures and shrinks, the surface tends to be concave.
[0009]
In the case of a method of embedding without forming a concave portion, a bonding process for connecting the electrode portion of the wiring pattern formed in advance on the surface of the substrate and the electrode portion of the semiconductor chip is indispensable.
[0010]
As a method of performing this connection, when performing flip chip connection, it is necessary to form solder bumps or balls on the electrode pad portions of the semiconductor chip.
And after aligning the solder bump of this semiconductor chip and the electrode part of the wiring pattern of a board | substrate, a semiconductor chip is mounted on a pattern electrode and it joins by heating. Further, a complicated bonding process is required in which a connection reinforcing resin called an underfill material is injected and fixed between gaps formed by bumps between the semiconductor chip surface and the substrate surface.
[0011]
Furthermore, if such a flip chip connection is to be made with a semiconductor chip that will increase in the number of pins in the future, not only will the bumps and solder balls formed on the semiconductor chip be required to be finer and more precise, Substrate wiring pitch is also required to be finer. As a result, bump formation costs and substrate costs increase significantly. In addition, the positioning accuracy at the time of mounting is required to be stricter, leading to an increase in apparatus cost.
[0012]
In the method of laminating sequentially, the electrode portions of the semiconductor chip must always face in the same plane direction. Therefore, in order to connect between the semiconductor chips, it is necessary to make the thickness of the semiconductor chip at least as short as possible, and it is difficult to shorten the wiring length. For this reason, when a signal is transmitted at a higher speed, the signal waveform is delayed or the waveform shape is disturbed, and it is difficult to transmit the signal at a high speed.
[0013]
In addition, in order to connect the wiring from the electrode part of each semiconductor chip stacked on the semiconductor chip, the size of the semiconductor chip stacked on the semiconductor chip must be smaller than the semiconductor chip below it. However, there is a design constraint that each semiconductor chip to be stacked is limited by its size.
[0014]
In the method of forming bumps on the electrode part of the semiconductor chip, applying insulating resin, embedding and polishing, the polishing process is always performed to remove the insulating resin covering the bumps and to flatten the surface of the insulating resin Is required. On the other hand, when the stud bump is exposed by a laser, if the laser beam hits a stud bump made of gold with high reflectivity and a neck-cut shape with poor stability, the laser beam is reflected and scattered and the shape of the processed hole is remarkable. Deteriorate. For this reason, it is impossible to perform stable connection hole processing for the electrode portion pitch of a semiconductor chip having a very narrow pitch of 100 μm or less.
[0015]
Further, the method of providing bumps larger than the semiconductor chip electrode area on the semiconductor chip for relaxing the hole machining accuracy cannot cope with the narrowing of the inter-electrode pitch accompanying the increase in the number of electrodes of the semiconductor chip. In addition, a bump forming process is required only for the positional accuracy at the time of drilling, resulting in an increase in cost.
[0016]
[Means for Solving the Problems]
A first method for manufacturing a substrate with a built-in semiconductor element according to the present invention is a method for manufacturing a substrate with a built-in semiconductor element in which a semiconductor element is embedded in a circuit board.
Bonding the semiconductor element to the first sheet;
Placing a second sheet made of an insulating resin in the middle of the curing reaction and having an opening on the first sheet so that the semiconductor element is accommodated in the opening;
Placing a third sheet made of a conductor on the second sheet;
A step of thermocompression bonding the first, second and third sheets together;
Removing the portion of the second and third sheets located immediately above the electrode portion of the semiconductor element;
Electrically connecting the electrode part and the third sheet;
And processing the third sheet into a pattern to form a wiring.
[0017]
The second method for manufacturing a substrate with a built-in semiconductor element according to the present invention is characterized in that, in the first manufacturing method, the third sheet has an insulating resin in the middle of the curing reaction on the side facing the second sheet. It is what.
[0018]
According to the third method for manufacturing a substrate with a built-in semiconductor element according to the present invention, in the first manufacturing method, in the step of bonding the semiconductor element to the first sheet, the surface side having the electrode portion of the semiconductor element is the surface side. It is characterized by adhering to the first sheet.
[0019]
According to the fourth method for manufacturing a substrate with a built-in semiconductor element according to the present invention, in the first manufacturing method, an insulating resin containing inorganic particles is used as an adhesive member in the step of bonding the semiconductor element to the first sheet. It is characterized by using.
[0020]
According to a fifth aspect of the present invention, in the first manufacturing method, the second sheet includes a material that does not melt or flow at a heating temperature in the thermocompression bonding step. To do.
[0021]
Compared to the conventional method for manufacturing a semiconductor element embedded substrate, the following various effects can be obtained.
[0022]
The present invention does not require a step of providing a recess in a completed or semi-finished circuit board, and embeds the semiconductor element in the circuit board by thermocompression bonding a plurality of stacked sheets and semiconductor elements at once. The process can be greatly shortened and the cost can be reduced. Furthermore, since it is not necessary to provide an insulating layer portion for mounting and holding the semiconductor element, it is possible to reduce the thickness after the semiconductor element is embedded.
[0023]
In addition, the conventional problem of rewiring even a defective semiconductor element when performing rewiring on a semiconductor wafer, the electrode can be expanded only on the semiconductor element, and cannot cope with the increase in the number of pins. The problem can be solved easily.
[0024]
Furthermore, regarding the burn-in inspection in the case of stacking a plurality of semiconductor elements, if the semiconductor elements are built in and wiring is formed, the electrode terminal pitch of the test jig can be sufficiently accommodated and the cost is not increased. An inspection can be easily performed. Therefore, it is possible to combine non-defective products after inspection, and it is possible to provide a connection electrode on the substrate regardless of the size of the built-in semiconductor element. Thus, it is possible to combine semiconductor elements.
[0025]
Furthermore, a general-purpose IC should be mounted on the package by providing an electrode for connecting the system board on one side of the double-sided circuit board containing the semiconductor element and an electrode for general-purpose IC on the other side. Therefore, the degree of freedom of design that can easily cope with various specification changes for each product is greatly increased.
[0026]
In addition, since the second sheet surrounding the semiconductor element is formed as an insulating layer having uniform material characteristics by the thermocompression bonding process, the generation of warpage and undulation of the entire semiconductor element-embedded substrate is suppressed. It is possible to form a wiring pattern.
[0027]
Furthermore, since a pattern can be easily formed directly under the back surface of the semiconductor element, heat dissipation can be enhanced by using this pattern as a heat spreader for heat dissipation.
[0028]
Moreover, by preparing double-sided substrates each incorporating the semiconductor element as described above and further laminating them, it is possible to easily cope with various circuit configurations.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Example 1
Hereinafter, a manufacturing method of a semiconductor element embedded substrate according to Example 1 of the present invention will be described with reference to FIG. 1 is a cross-sectional view showing a method of manufacturing a substrate with a built-in semiconductor element according to Embodiment 1 of the present invention.
[0030]
As shown in FIG. 1A, an insulating epoxy resin 4 is provided on the back surface of a semiconductor chip 1 as a semiconductor element, and the semiconductor chip 1 is made of a first sheet 3 made of copper foil via the insulating epoxy resin 4. Mount on the roughened surface.
[0031]
The first sheet does not have conductivity, but when it is a conductor, a wiring pattern can be easily formed on the first sheet using a known lithography technique.
[0032]
Thereafter, the insulating epoxy resin 4 is thermally cured, and the semiconductor chip 1 is bonded to the first sheet 3.
[0033]
The thickness of the insulating epoxy resin 4 is preferably as thin as possible as long as the strength necessary for adhesion can be obtained, but generally the range of 10 to 30 μm is preferable.
[0034]
If it is thinner than this, a uniform film thickness cannot be ensured at the time of coating, bubbles and uncoated areas are generated, and peeling occurs in a later step.
[0035]
If it is thicker than this, the semiconductor chip will be tilted and attached due to variations in the applied pressure when fixing the semiconductor chip, and the semiconductor chip will be damaged due to high stress applied to the edge of the semiconductor chip in the subsequent hot pressing process. Resulting in.
[0036]
The thickness of the first sheet 3 is preferably in the range of 8 to 35 μm.
[0037]
If it is thinner than this, the sheet may break during handling, or it may be twisted or swollen, and stable production cannot be achieved.
[0038]
On the other hand, if it is thicker than this, fine wiring cannot be formed by etching when forming wiring to be formed later on the first sheet.
[0039]
Next, as shown in FIG. 1 (b), a second portion in which an opening 5a having a thickness substantially equal to the thickness of the semiconductor chip 1 (usually about 50 to 150 μm) and corresponding to the semiconductor chip 1 is formed by punching press. The sheet 5 is disposed at a position where the opening 5 a accommodates the semiconductor chip 1.
[0040]
The second sheet 5 was made of an epoxy resin that is an insulating resin in the middle of the curing reaction, and a prepreg material containing glass cloth was used.
[0041]
A third sheet 7 is placed on the second sheet 5.
[0042]
As the third sheet 7, an RCC (resin coated copper) material in which an epoxy resin 6 as an insulating resin during the curing reaction was coated on the copper foil 3 ′ was used.
[0043]
The thickness of the epoxy resin 6 is preferably in the range of 10 to 60 μm.
[0044]
If it is thinner than this, fine irregularities on the upper surface of the semiconductor chip are embedded, and the interlayer insulation with the copper foil 3 ′, which is the conductor layer thereon, cannot be maintained, or an unfilled part is generated, which is later peeled off from the unfilled part Will be generated.
[0045]
On the other hand, if it is thicker than this, the aspect ratio (hole diameter to depth) of the hole formed on the electrode part when connecting to the semiconductor chip electrode in a later process becomes 1 or more, which is very workable. Will go down.
[0046]
The third sheet 7 does not necessarily have an insulating resin in the middle of the curing reaction.
[0047]
In the case of having a curing reactive resin, by increasing the amount of resin, it is possible to obtain higher adhesion strength with the copper foil and to suppress the occurrence frequency of unfilling.
[0048]
The above-described sheets arranged in a stacked manner are subjected to thermocompression bonding in a vacuum atmosphere. The heating temperature at this time is preferably 150 to 200 ° C.
[0049]
The epoxy resin in the second sheet 5 and the epoxy resin 6 in the third sheet 7 are melted by thermocompression bonding, and the semiconductor chip 1 is coated with copper foil on both sides as shown in FIG. I embed it inside.
[0050]
At this time, the glass sheet-containing prepreg material is used as the second sheet 5 because of the difference in pressure between the place where the semiconductor chip 1 exists and the place where the semiconductor chip 1 does not exist due to the pressure during thermocompression bonding. This is to prevent damage.
[0051]
Therefore, the thickness of the glass cloth is preferably equal to or slightly thicker than the thickness of the semiconductor chip.
[0052]
Next, as shown in FIG. 1 (d), the copper foil 3 'corresponding to the position of the electrode portion 2 of the semiconductor chip 1 is removed by ordinary etching, and then the insulating resin exposed in this hole portion is CO 2. Alternatively, the via hole 8 is formed so that the electrode portion 2 of the semiconductor chip 1 is exposed by removing with a laser such as YAG or excimer. In the electrode part 2 of the semiconductor chip 1, a Ti / Ni diffusion barrier layer is previously formed on Al by a wafer process.
[0053]
Next, the via hole 8 is cleaned with permanganic acid or the like, and a copper layer 3a is deposited on the entire surface in a plating step as shown in FIG. 1 (e). Thereby, the electrode part 2 and copper foil 3 'are connected.
[0054]
Next, a resist material is applied to the copper layer 3a, and a pattern is formed by etching by an exposure / development process, thereby obtaining a double-sided wiring circuit board in which the semiconductor chip 1 is embedded as shown in FIG. Since such a double-sided wiring circuit board is a basic configuration when a multilayer wiring circuit board is manufactured, the following multi-layering can be easily performed.
[0055]
As shown in FIG. 2, such a double-sided wiring circuit board is subjected to thermocompression bonding again with a prepreg material in between, and drilling and plating through-holes 9 can be easily formed in multiple layers. Become.
[0056]
Moreover, what is laminated does not need to be a double-sided wiring circuit board, and a four-layer wiring board is formed by placing prepreg material and copper foil on both sides of the double-sided wiring circuit board of the present invention and performing thermocompression bonding. .
[0057]
Since the circuit board with the built-in semiconductor chip 1 formed in this way is manufactured by the same process as the conventional circuit board, the electronic circuit component can be mounted on the surface as in the conventional case, and the semiconductor chip 1 is embedded. In addition, a semiconductor element built-in substrate can be easily manufactured.
[0058]
(Example 2)
FIG. 3 is a sectional view showing a circuit board manufacturing method according to the second embodiment of the present invention.
[0059]
In the present embodiment, as shown in FIG. 3A, the semiconductor chip 1 is mounted and bonded to the substrate 10 on which the wiring 21 is formed in the same manner as in the embodiment. Then, similarly to the first embodiment, the prepreg material and the RCC material are used, and the semiconductor chip is embedded in the circuit board by thermocompression bonding.
[0060]
Next, as shown in FIG. 3 (d), a window is formed at a position where a via hole is to be formed on the copper foil 3 ', and a via is formed in the insulating layer portion by laser light, as in the conventional build-up board manufacturing method. Holes 8 and 11 are formed. At that time, by changing the spot diameter of the laser beam when forming the interlayer part 22 and when forming the electrode part 2 of the semiconductor chip 1, the hole diameter size suitable for each is formed.
[0061]
Next, as shown in FIG. 3E, the interlayer and the electrode portion 2 of the semiconductor chip 1 are connected by a plating process, and then a pattern is formed on the exposed copper by etching.
[0062]
Obviously, if this process is repeated a plurality of times, the number of layers can be easily increased.
[0063]
According to the present embodiment, by using a build-up substrate manufacturing process, vias are used for interlayer connection instead of through-holes, so that a higher-density circuit board can be manufactured. Therefore, it is possible to reduce the size of the product by mounting with higher density.
[0064]
(Example 3)
FIG. 4 is a cross-sectional view showing a method for manufacturing a circuit board according to Example 3 of the present invention.
[0065]
In this embodiment, the surface having the electrode portion 2 of the semiconductor chip 1 is first bonded using the copper foil 3 and the insulating epoxy resin 12. Silica particles are dispersed in the epoxy resin 12, and the semiconductor is improved by improving thermal conductivity, reducing the moisture absorption rate, and reducing the thermal expansion coefficient from the 50ppm level of the epoxy resin alone to 10-30ppm. It is possible to alleviate the thermal stress applied to the chip surface. Furthermore, since the semiconductor chip 1 is bonded individually, not by batch hot pressing, the distance between the semiconductor chip surface and the copper foil 3 can be easily controlled. For this reason, there is no variation in the aspect ratio at the time of drilling with a laser, processing with a finer hole diameter can be performed, and it becomes possible to cope with a semiconductor chip with a narrower pitch and more pins.
[0066]
Other manufacturing methods are the same as those in the first embodiment.
[0067]
Example 4
FIG. 5 is a schematic sectional view showing a fourth embodiment of the present invention.
[0068]
In the present embodiment, the semiconductor chip 1 is mounted on the substrate 13 made of an insulating base material for holding, and the semiconductor chip is embedded by batch hot pressing through the prepreg material 5 and the RCC material 7. The copper foil 3 ′ is peeled off on the entire surface. Thereafter, a via hole is provided on the electrode portion 2 of the semiconductor chip 1 with a laser, and after cleaning, copper is provided on the entire surface by plating.
[0069]
Thereafter, a pattern is formed by etching. In the present embodiment, there is no thickness of the copper foil of the RCC material, and only the thickness of the plating is obtained, so that a finer wiring pattern can be formed.
[0070]
Then, by providing a solder resist layer after pattern formation and mounting the solder balls 14 on the exposed land portions of the copper pattern, it is possible to provide a very thin package with a built-in semiconductor chip.
[0071]
Furthermore, since there is no restriction that the connection pad can be provided only on the chip size of a super CSP or the like, it is possible to easily provide a small package satisfying the number of connection pads.
[0072]
In the present embodiment, the substrate 13 made of an insulating base material is used for holding, but a metal plate having high thermal conductivity can also be used for holding. In this configuration, the heat dissipation is extremely high. It becomes a package.
[0073]
In the present embodiment, the interposer manufacturing and the semiconductor chip connection / sealing process are performed in a lump, instead of manufacturing a normal CSP or BGA package interposer (intermediate substrate) separately. Therefore, a very large number of processes can be reduced, and the tact time can be shortened and the manufacturing cost can be reduced.
[0074]
(Example 5)
FIG. 6 is a schematic sectional view showing a fifth embodiment of the present invention.
[0075]
In the present embodiment, the burn-in test is performed in the state of the substrate package 16 in which the semiconductor chip according to the fourth embodiment is embedded and the pattern is formed, and the substrate package 16 in which the non-defective chip is incorporated is discriminated. Then, a solder paste 17 is provided by printing on a wiring land portion formed on one surface of another substrate package 16 ′ in which the semiconductor chip is embedded, and then a land portion is provided at a position opposite to the land portion. The board package 16 determined to be non-defective in the burn-in test is mounted after alignment, and the solder paste 17 is melted by a reflow process to connect the land portions of the board package.
[0076]
Next, the solder ball 14 is mounted on the land portion on one side of the connected board package, the solder ball 14 and the land are connected again by reflow, and the composite package in which the package is mounted on the package is fully stored. Is done.
[0077]
In the present embodiment, the combination of semiconductor chip built-in substrate packages is used, but a plurality of packages may be combined in the same manner.
[0078]
Further, when combined with a semiconductor chip having higher versatility, it is possible to cope with this by matching the design of the connection land portion of the substrate package with the land design of the general-purpose product package.
[0079]
In this example, since it is possible to combine packages with good chips after the test, it is possible to eliminate a decrease in yield due to mixing of defects, and semiconductor chips are embedded inside the substrate. In addition, it becomes possible to provide a composite package having a very thin thickness after mounting.
[0080]
If a thinner composite package is desired, a semiconductor chip with a high defect rate as shown in FIG. 7 is embedded in the substrate, and only those that are determined to be non-defective products are subjected to normal semiconductor packages. It is also possible to mount a semiconductor chip in the same manner as in manufacturing, connect with a wire bonder, seal with a transfer mold, connect the solder balls 14, and then cut into individual packages with a dicing saw.
[0081]
In this method, not only the degree of freedom of wiring and the size of the mounted chip is greatly increased compared to the normal stack structure, but it is also possible to perform intermediate inspection on a semiconductor chip with a high defect rate or to obtain a higher yield. it can.
[0082]
【The invention's effect】
As described above, in the present invention, the semiconductor element is embedded in the substrate with high accuracy by embedding the semiconductor element in the substrate in a batch thermocompression bonding process during the substrate manufacturing process and connecting with the wiring formation. It can be arranged and the manufacturing process can be greatly shortened.
[0083]
Furthermore, since it is possible to easily perform post-process tests such as a burn-in test if the pattern is formed inside the substrate, it is possible to select non-defective products, even if they are more complex. High yields can be maintained and costs can be reduced.
[0084]
In addition, since the degree of freedom in wiring design is high, it is possible to flexibly respond to combinations with various semiconductor chips or electrical circuit components, and it is possible to provide more sophisticated and compact products at low cost. Become.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional manufacturing view showing a first embodiment. FIG. 2 is a schematic cross-sectional manufacturing view showing multi-layering of the first embodiment. FIG. 3 is a schematic cross-sectional manufacturing view showing a second embodiment. FIG. 4 is a schematic cross-sectional manufacturing view showing a third embodiment. FIG. 5 is a schematic cross-sectional manufacturing view showing a fourth embodiment. FIG. 6 is a schematic cross-sectional manufacturing view showing a fifth embodiment. FIG. 7 is a schematic cross-sectional manufacturing view showing a fifth embodiment. FIG. 8 is a schematic cross-sectional manufacturing view showing a conventional example.
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Semiconductor chip electrode part 3 Copper foil 4 Insulating adhesive 5 Prepreg material 6 Epoxy resin (B stage state)
7 RCC
8 Via hole 9 Through hole 10 Wiring board 11 Via hole (for interlayer connection)
12 Filler-containing epoxy resin 13 Holding substrate 14 Solder ball 15 Substrate package 16 Land portion 17 Solder paste 18 Gold wire 19 Sealing mold 20 Recess

Claims (5)

回路基板中に半導体素子が埋設された半導体素子内蔵基板の製造方法において、
第一のシートに前記半導体素子を接着する工程と、
硬化反応途中の絶縁性樹脂からなり開口部を有する第二のシートを、前記開口部中に前記半導体素子が収容されるように前記第一のシート上に載置する工程と、
導電体からなる第三のシートを前記第二のシート上に載置する工程と、
前記第一、第二及び第三のシートを一括して熱圧着する工程と、
前記第二及び第三のシートの、前記半導体素子の電極部直上に位置する部分を除去する工程と、
前記電極部と前記第三のシートとを電気的に接続する工程と、
前記第三のシートをパターン状に加工し配線を形成する工程と、を有することを特徴とする半導体素子内蔵基板の製造方法。In a method for manufacturing a semiconductor element embedded substrate in which a semiconductor element is embedded in a circuit board,
Bonding the semiconductor element to the first sheet;
Placing a second sheet made of an insulating resin in the middle of the curing reaction and having an opening on the first sheet so that the semiconductor element is accommodated in the opening;
Placing a third sheet of conductor on the second sheet;
A step of thermocompression bonding the first, second and third sheets together;
Removing the portion of the second and third sheets located immediately above the electrode portion of the semiconductor element;
Electrically connecting the electrode portion and the third sheet;
And a step of processing the third sheet into a pattern to form a wiring. 第三のシートは第二のシートに面する側に硬化反応途中の絶縁性樹脂を有することを特徴とする請求項１記載の半導体素子内蔵基板の製造方法。The method for producing a substrate with a built-in semiconductor element according to claim 1, wherein the third sheet has an insulating resin in the middle of the curing reaction on the side facing the second sheet. 第一のシートに半導体素子を接着する工程の際、前記半導体素子の電極部を有する面側を前記第一のシートに接着することを特徴とする請求項１記載の半導体素子内蔵基板の製造方法。2. The method of manufacturing a substrate with a built-in semiconductor element according to claim 1, wherein in the step of adhering the semiconductor element to the first sheet, the surface side having the electrode portion of the semiconductor element is adhered to the first sheet. . 第一のシートに半導体素子を接着する工程の際、接着部材として無機粒子を含有する絶縁性樹脂を用いることを特徴とする請求項１記載の半導体素子内蔵基板の製造方法。The method for manufacturing a substrate with a built-in semiconductor element according to claim 1, wherein an insulating resin containing inorganic particles is used as an adhesive member in the step of bonding the semiconductor element to the first sheet. 第二のシートは熱圧着する工程における加熱温度では溶融あるいは流動しない材料を含んでいることを特徴とする請求項１記載の半導体素子内蔵基板の製造方法。2. The method of manufacturing a substrate with a built-in semiconductor element according to claim 1, wherein the second sheet contains a material that does not melt or flow at a heating temperature in the thermocompression bonding step.
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