JP2004317311A - Scan test circuit device and flip-flop group initialization method inside integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scan test circuit device and a flip-flop group initialization method inside an integrated circuit capable of reducing wiring by simplifying a constitution for initialization reset and by heightening operation speed. <P>SOLUTION: In this scan test circuit device, an initialization reset means performs in a scan mode, initialization reset in the integrated circuit constituted of a combination circuit 11 and scan test circuits S1 to Sn+m, and D-FF-1 to D-FF-n+m, based on an initialization reset signal CL synchronized with a scan clock pulse CK for performing operation of a scan test. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to the initialization of a flip-flop group inside an integrated circuit. However, since the circuit of the present invention uses a scan test circuit on the premise that the circuit is included in the integrated circuit, it is a technique related to the scan test of the integrated circuit.
[0002]
[Prior art]
In a system including a large-scale integrated circuit (hereinafter, referred to as “LSI”) or an LSI, it is generally necessary to perform an initialization reset inside the LSI in the following cases. When an initialization reset inside the LSI is necessary, first, at the start of simulation for LSI design, second, at the start of LSI shipping test, third, at the start of LSI operation, and fourth, at the time of host system For recovery operation after detecting an abnormal state of the LSI.
[0003]
In the initialization reset in the LSI in the case described above, an asynchronous reset function is conventionally added to a D flip-flop (hereinafter, referred to as “D-FF”) that requires initialization, and an asynchronous reset function of each D-FF is provided. The initialization has been performed asynchronously by connecting the reset terminal CL so that an external reset signal can be supplied.
[0004]
A general scan circuit is described in p. FIG. 11 shows an example of a conventional LSI circuit having a scan test and initialization reset function.
[0005]
11, the scan input SI is input to the B terminal of the selector S1, and the data inputs IN1, IN2, IN3... INn, which are the outputs of the preceding combinational circuit, are connected to the A terminals of the selectors S1, S2, S3. , And the select signal S is input to the S terminals of the selectors S1, S2, S3,..., Sn, so that the output from the Y terminal can be selected.
[0006]
The outputs from the Y terminals of the selectors S1, S2, S3,... Sn are input to the D input terminals of D-FF-1, D-FF-2, D-FF-3,. The outputs from the Q output terminals of D-FF-1, D-FF-2, D-FF-3,..., D-FF-n are input to the combinational circuit 111 and the selectors S2, S3,. , Sn + 1 at the B terminal.
[0007]
The output of the combinational circuit 111 is input to the A terminals of the selectors Sn + 1, Sn + 2, Sn + 3... Sn + m, the select signal S is input to the S terminals of the selectors S1, S2, S3. Make it selectable.
[0008]
The outputs from the Y terminals of the selectors Sn + 1, Sn + 2, Sn + 3... Sn + m are input to D input terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3. The outputs from the Q output terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,..., D-FF-n + m are output as data outputs OUT1, OUT2, OUT3,. The output from the Q output terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,..., D-FF-n + m-1 is B of selectors Sn + 2, Sn + 3,. Input to the terminal. The output from the Q output terminal of D-FF-n + m is output as a scan output.
[0009]
The clock signal CK is D-FF-1, D-FF-2, D-FF-3 ... D-FF-n, D-FF-n + 1, D-FF-n + 2, D-FF-n + 3 ... D-FF-n + m is input to the clock terminal CK, and the initialization reset signal CL is D-FF-1, D-FF-2, D-FF-3,... D-FF-n, D-FF-n + 1. , D-FF-n + 2, D-FF-n + 3,..., D-FF-n + m.
[0010]
A general scan flip-flop (hereinafter referred to as “S-FF”) is shown in FIG. 13 of Patent Document 1. Here, FIG. 12 shows a symbol diagram of an S-FF with asynchronous reset, and FIG. 13 shows an example of the internal circuit. A 131 composed of AND circuits A1, A2, an inverter INV1, and a NOR circuit N1 shown in FIG. 13 corresponds to the selector 121 shown in FIG. 12, and NAND circuits NA1, NA2, inverters INV2, INV3, INV4, INV5 shown in FIG. , PMOSs p1, p2, p3, p4 and nMOSs n1, n2, n3, n4 correspond to the D-FF 122 shown in FIG.
As can be seen from FIG. 12, the S-FF has a configuration in which the selector 121 is added to the D-FF 122. FIG. 16 shows an example of an internal circuit of the D-FF with asynchronous reset.
[0011]
On the other hand, FIG. 14 shows a symbol diagram of an S-FF without an asynchronous reset function, and FIG. 15 shows an internal circuit including MOS and a logic circuit. A 151 composed of AND circuits A1, A2, an inverter INV1, and a NOR circuit N1 shown in FIG. 15 corresponds to the selector 141 shown in FIG. 14, and the inverters INV2, INV3, INV4, INV5, INV6, INV7, pMOSp1 shown in FIG. , P2, p3, p4 and nMOS n1, n2, n3, n4 correspond to the D-FF 142 shown in FIG.
[0012]
The operation of the conventional LSI circuit having the scan test and initialization reset function configured as described above will be described below.
D-FF-1, D-FF-2, D-FF-3,..., D-FF-n are data inputs IN1, IN2, IN3,. .., D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,..., D-FF-n + m read the output of the combinational circuit 111, and output data OUT1, OUT2, OUT3,. However, when the scan test mode is entered, the scan input SI functions as a shift register, and scan input SI, which is test data, is read into D-FF-1, D-FF-2, D-FF-3,. . D-FF-n + 1, D-FF-n + 2, D-FF-n + 3... D-FF-n + m fetch the output of the combination circuit 111 and read the fetched value. Using the shift operation, data outputs OUT1, OUT2, OUT3,..., OUTn are output to a subsequent combinational circuit outside the LSI circuit.
[0013]
Thus, each stage of the combinational circuit 111 in the LSI circuit can be separately tested.
[0014]
.., D-FF-3,..., D-FF-n, D-FF-n + 1, which constitute the S-FF with the asynchronous reset function. By inputting the D-FF-n + 2, D-FF-n + 3,... D-FF-n + m to the initialization reset terminal CL, the initialization reset in the LSI circuit can be performed asynchronously with the clock signal CK.
[0015]
[Patent Document 1]
JP 2002-267723 A
[Non-patent document 1]
Itaru Sakurai, "Basic Technology for LSI Design", Techno Press Co., published the first edition on July 23, 1999, p. 164-169
[0016]
[Problems to be solved by the invention]
However, if the S-FF with the asynchronous reset function is used in the above-described conventional LSI circuit example having the scan test and the initialization reset function to perform the initialization reset inside the LSI, it can be understood by comparing FIG. 13 and FIG. As described above, the two inverters INV4 and INV6 become the two NAND circuits NA1 and NA2 having two inputs, and the number of transistors, the cell area, and the power consumption increase.
[0017]
In addition, since a reset logic gate is provided in the memory holding loop in the S-FF, the setup time for holding the value slightly before the rising edge of the clock signal of the S-FF is compared with the case without the reset function. However, there is a disadvantage that the hold time for holding the value after the rise increases and the operation speed decreases.
[0018]
Further, as shown in FIG. 11, there is a disadvantage that the number of wirings and buffers for supplying an initialization reset signal to all the S-FFs requiring resetting increases.
[0019]
Therefore, the present invention has been made in view of such a point, and has been made on the assumption that a scan test circuit is built in an integrated circuit, and reduces the number of gates for initialization reset, thereby reducing the operation speed. It is an object of the present invention to provide a scan test circuit device and a method of initializing a flip-flop group inside an integrated circuit, which can reduce the number of wirings.
[0020]
[Means for Solving the Problems]
In the scan test circuit device of the present invention, the initialization reset means performs an initialization reset in the integrated circuit in a scan mode based on an initialization reset signal synchronized with a scan clock pulse for performing a scan test operation. In the method for initializing a group of flip-flops in an integrated circuit according to the present invention, the initialization reset step includes the step of resetting the flip-flops in the integrated circuit based on an initialization reset signal synchronized with a scan clock pulse for performing a scan test operation. The initialization of the group is reset in the scan mode.
[0021]
Therefore, according to the present invention, the following operations are performed.
Conventionally, an asynchronous reset is often executed by connecting a reset signal supplied from the outside to a reset terminal of a D-FF that requires initialization in an LSI.
On the other hand, in the present invention, the initialization reset function is realized in the scan mode on the assumption that the scan test circuit is built in for the shipment test of the LSI.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment applied to the present invention will be described below with reference to the drawings as appropriate.
[0023]
[First Embodiment]
The first embodiment applied to the present invention realizes initialization reset using a scan test mechanism for shipping test.
[0024]
FIG. 1 is a diagram showing an example of an LSI circuit having a scan test and an initialization reset function according to a first embodiment applied to the present invention.
In FIG. 1, the scan input SI is input to one input terminal of an AND circuit A1 at the first stage of the S-FF, the initialization reset signal CL is input to the other input terminal of the AND circuit A1, and the input terminal of the NAND circuit N1 is The scan mode signal SN is input to one input terminal, and is input to the other input terminal of the NAND circuit N1. The output of the NAND circuit N1 becomes the select signal S.
[0025]
The output of the AND circuit A1 is input to the B terminal of the selector S1, and the data inputs IN1, IN2, IN3... INn, which are the outputs of the preceding combinational circuit, are input to the A terminals of the selectors S1, S2, S3. Then, the select signal S is input to the S terminals of the selectors S1, S2, S3,... Sn, and enables the output from the Y terminal to be selected.
[0026]
The outputs from the Y terminals of the selectors S1, S2, S3,... Sn are input to the D input terminals of D-FF-1, D-FF-2, D-FF-3,. The outputs from the Q output terminals of D-FF-1, D-FF-2, D-FF-3,..., D-FF-n are input to the combinational circuit 11, and the selectors S2, S3,. , Sn + 1 at the B terminal.
[0027]
The output of the combinational circuit 11 is input to the A terminals of the selectors Sn + 1, Sn + 2, Sn + 3,..., Sn + m. The select signal S is input to the S terminals of the selectors Sn + 1, Sn + 2, Sn + 3,. Make it selectable.
[0028]
The outputs from the Y terminals of the selectors Sn + 1, Sn + 2, Sn + 3... Sn + m are input to D input terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3. The outputs from the Q output terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,. The output from the Q output terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,..., D-FF-n + m-1 is B of selectors Sn + 2, Sn + 3,. Input to the terminal. The output from the Q output terminal of D-FF-n + m is output as a scan output.
[0029]
The clock signal CK is D-FF-1, D-FF-2, D-FF-3 ... D-FF-n, D-FF-n + 1, D-FF-n + 2, D-FF-n + 3 ... D-FF-n + m is input to the clock terminal CK, and the initialization reset signal CL is D-FF-1, D-FF-2, D-FF-3,... D-FF-n, D-FF-n + 1. , D-FF-n + 2, D-FF-n + 3,..., D-FF-n + m.
[0030]
The LSI circuit example having a scan test and initialization reset function according to the first embodiment applied to the present invention shown in FIG. 1 is different from the conventional circuit shown in FIG. An AND circuit A1 is added to the first stage of the FF, and an initialization reset signal CL is input to the AND circuit A1.
[0031]
Each S-FF does not have an asynchronous reset function and generates an initialization reset signal CL so that an initialization reset in an LSI circuit can be performed in synchronization with a clock signal CK.
[0032]
FIG. 8 shows a symbol diagram of the S-FF with scan synchronization reset, and FIG. 9 shows an example of an internal circuit using MOS and a logic circuit. An AND circuit A1 (91) shown in FIG. 9 corresponds to the AND circuit A1 (81) shown in FIG. 8, and a 92 composed of the AND circuit A2, the inverter INV1, and the NOR circuit N1 shown in FIG. 9 is a selector shown in FIG. The D-FF 83 shown in FIG. 8 corresponds to 82 and includes inverters INV2, INV3, INV4, INV5, INV6, INV7, pMOSs p1, p2, p3, p4, nMOSs n1, n2, n3, and n4 shown in FIG. Corresponding to
As can be seen from FIG. 8, the S-FF has a configuration in which a selector 82 is added to the D-FF 83.
[0033]
On the other hand, FIG. 10 shows an internal circuit including a MOS and a logic circuit of the S-FF without the scan synchronization reset function. Inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, pMOSs p1, p2, p3, p4, nMOSs n1, n2, n3, and n4 shown in FIG. 10 correspond to D-FFs.
[0034]
The operation of the thus configured LSI circuit example with scan test and initialization reset function according to the first embodiment applied to the present invention will be described below.
2 is a timing chart showing an initialization reset period. FIG. 2A shows data inputs IN1 to INn + m, FIG. 2B shows a scan mode signal SN, FIG. 2C shows an initialization reset signal CL, FIG. 2E shows the clock signal CK, and FIG. 2F shows the initialization reset values and the initialization reset periods of D-FF-1, D-FF-2, D-FF-3,..., D-FF-n + m.
[0035]
At the time of the initialization reset, at time T0, the initialization reset signal CL shown in FIG. 2C is enabled (ON) (CL = Low level in the examples of FIGS. 1 and 2). The scan mode signal SN shown in FIG. 2B is also enabled (ON) (SN = Low level). At this time, the output of the AND circuit A1 (= Low level) provided at the first stage of the scan input also brings the B input of the selector S1 constituting the first stage S-FF of the scan circuit to the Low level.
[0036]
At the same time, since the initialization reset signal CL (= Low level) is input to the NAND circuit N1 together with the scan mode signal SN (= Low level), each S-FF is formed from the output of the NAND circuit N1. The select signals S (= High level) shown in FIG. 2D are supplied to the S terminals of the selectors S1, S2, S3... Sn, Sn + 1, Sn + 2, Sn + 3... Sn + m, and the initialization reset signal CL (= Low level). ) From the Y terminals of the selectors S1, S2, S3 ... Sn, Sn + 1, Sn + 2, Sn + 3 ... Sn + m to D-FF-1, D-FF-2, D-FF-3 ... D-FF- n, D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,... D-FF-n + m.
[0037]
In this state, the pulses of the clock signal CK shown in FIG. 2E corresponding to the number of stages of S-FFs required for the initialization reset are D-FF-1, D-FF-2, D-FF-3,. By inputting to FF-n, D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,... D-FF-n + m, the first-stage initialization reset period from time T0 to time T1 2F, the output value Q1 of the D-FF-1 shown in FIG. 2F is set to the value of the initialization reset signal CL (= Low level). During the initialization reset period of the second stage from the time T0 to the time T2, D shown in FIG. The output value Q2 of the FF-2 is set to the value of the initialization reset signal CL (= Low level), and the output of the D-FF-3 shown in FIG. 2F is output during the third stage initialization reset period from the time T0 to the time T3. Change the value Q3 to the value of the initialization reset signal CL (= Low level) , To a value of ... from T0 time to time Tn + m No. n + at m stages initialization reset period shown in FIG. 2F D-FF-n + m output values Qn + m initialization reset signal CL (= Low level).
[0038]
Here, the initialization reset period 21 of all stages is from the time T0 when the initialization reset signal CL shown in FIG. 2C is set to the low level to the time T11 when the initialization reset signal CL is set to the high level shown in FIG. 2C. Note that the normal operation 22 is performed after the time T11.
[0039]
As a result, the initialization reset signal CL (= Low level), which is a fixed value of the D-FF-1 constituting the S-FF at the first stage of the scan input, is sequentially changed to the D-FF-2, D constituting each S-FF. -FF-3 ... D-FF-n, D-FF-n + 1, D-FF-n + 2, D-FF-n + 3 ... D-FF-n + m to initialize the LSI circuit be able to.
[0040]
Examples of normal operation and scan test operation other than the above-mentioned initialization reset will be described later.
[0041]
[Second embodiment]
FIG. 3 is a diagram showing an example of an LSI circuit having a scan test and an initialization reset function according to the second embodiment applied to the present invention.
[0042]
In FIG. 3, the scan input SI is input to one input terminal of an AND circuit A1 at the first stage of the first block of the S-FF, and the initialization reset signal CL is the other input terminal of the AND circuit A1 at the first stage of the first block. Is input to the other input terminal of the n-stage AND circuit A2 in the second block of the S-FF, for example, and is also input to the other input terminal of the n + m-stage AND circuit A3 in the third block of the S-FF, for example, in the third block And the scan mode signal SN is input to one input terminal of the NAND circuit N1, and the scan mode signal SN is input to the other input terminal of the NAND circuit N1. The output of the NAND circuit N1 becomes the select signal S.
[0043]
The output of the AND circuit A1 is input to the B terminal of the selector S1, and the data inputs IN1, IN2, IN3... INn, which are the outputs of the preceding combinational circuit, are input to the A terminals of the selectors S1, S2, S3. Then, the select signal S is input to the S terminals of the selectors S1, S2, S3,... Sn, and enables the output from the Y terminal to be selected.
[0044]
The outputs from the Y terminals of the selectors S1, S2, S3,... Sn are input to the D input terminals of D-FF-1, D-FF-2, D-FF-3,. The outputs from the Q output terminals of D-FF-1, D-FF-2, D-FF-3,..., D-FF-n are input to the combinational circuit 11, and the selectors S2, S3,. Is input to the B terminal. Here, the output from the Q output terminal of the D-FF-n-1 is input to one input terminal of, for example, an n-stage AND circuit A2 in the second block of the S-FF, and the output of the AND circuit A2 is the selector Sn Is input to the B terminal.
[0045]
The output of the combinational circuit 11 is input to the A terminals of the selectors Sn + 1, Sn + 2, Sn + 3... Sn + m, the select signal S is input to the S terminals of the selectors S1, S2, S3. Make it selectable.
[0046]
The outputs from the Y terminals of the selectors Sn + 1, Sn + 2, Sn + 3... Sn + m are input to D input terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3. The outputs from the Q output terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,. The output from the Q output terminals of D-FF-n + 1, D-FF-n + 2, D-FF-n + 3,..., D-FF-n + m-2 are selectors Sn + 2, Sn + 3,. Is input to the B terminal. Here, the output from the Q output terminal of the D-FF-n + m-1 is input to one input terminal of, for example, an n + m-stage AND circuit A3 in the third block of the S-FF, and the output of the AND circuit A3 is a selector Sn + m Is input to the B terminal. The output from the Q output terminal of D-FF-n + m is output as a scan output.
[0047]
The clock signal CK is D-FF-1, D-FF-2, D-FF-3 ... D-FF-n, D-FF-n + 1, D-FF-n + 2, D-FF-n + 3 ... D-FF-n + m is input to the clock terminal CK, and the initialization reset signal CL is D-FF-1, D-FF-2, D-FF-3,... D-FF-n, D-FF-n + 1. , D-FF-n + 2, D-FF-n + 3,..., D-FF-n + m.
[0048]
The LSI circuit example having the scan test and initialization reset function according to the second embodiment shown in FIG. 3 which is applied to the present invention is different from the LSI circuit according to the first embodiment shown in FIG. The number of shift stages for initialization is reduced by dividing the FF into a plurality of blocks, for example, three blocks, and shifting the initialization reset signal CL from each block to the number of stages requiring initialization.
[0049]
In the LSI circuit according to the first embodiment of the present invention, the number of clock cycles corresponding to the number of stages constituting the S-FF is required for the initialization reset. Therefore, in the LSI circuit according to the second embodiment, the first stage scan input SI of the scan chain and the number of stages constituting the S-FF are divided into a plurality of stages of blocks, and the former stage constituting the S-FF also in the middle of the scan chain. And a plurality of AND circuits A1, A2, A3... For inputting the outputs from the Q output terminals of D-FF + n-1 and D-FF-n + m-1 to one input terminal, and the other input terminal Is to reduce the number of scan clock pulses required for initialization by connecting the initialization reset signal CL so that it can be input.
[0050]
The operation of the thus configured LSI circuit example having the scan test and initialization reset function according to the second embodiment applied to the present invention will be described below. Here, as an example, an example is shown in which the number of stages forming the S-FF is divided into three-stage blocks.
[0051]
4 is a timing chart showing an initialization reset period at the time of block division. FIG. 4A shows data inputs IN1 to INn + m, FIG. 4B shows a scan mode signal SN, FIG. 4C shows an initialization reset signal CL, and FIG. The select signal S, FIG. 4E is the clock signal CK, and FIG. 4F is the initialization reset value and the initialization reset period of D-FF-1, D-FF-2, D-FF-3,. is there.
[0052]
At the time of the initialization reset, at time T0, the initialization reset signal CL shown in FIG. 4C is enabled (ON) (CL = Low level in the examples of FIGS. 3 and 4). The scan mode signal SN shown in FIG. 4B is also enabled (ON) (SN = Low level). At this time, the number of stages constituting the S-FF is divided into three blocks, and the selector S1 constituting the first stage S-FF of the scan circuit is determined by the output (= Low level) of the AND circuit A1 provided at the first stage of the scan input. B input also becomes Low level. In addition, the B input of the selector Sn constituting the n-stage S-FF of the scan circuit is also at the low level by the output (= low level) of the AND circuit A2 provided at the n-th stage. Further, the B input of the selector Sn + m constituting the n-m-stage S-FF of the scan circuit is also at the low level by the output (= low level) of the AND circuit A3 provided at the n + m-stage.
[0053]
At the same time, since the initialization reset signal CL (= Low level) is input to the NAND circuit N1 together with the scan mode signal SN (= Low level), each S-FF is formed from the output of the NAND circuit N1. The select signals S (= High level) shown in FIG. 2D are supplied to the S terminals of the selectors S1, S2, S3... Sn, Sn + 1, Sn + 2, Sn + 3... Sn + m, and the initialization reset signal CL (= Low level). ) Is sequentially shifted from the Y terminals of the selectors S1, S2, S3... Sn-1 to D-FF-1, D-FF-2, D-FF-3. Mode. Further, the initialization reset signal CL (= Low level) is supplied from the Y terminals of the selectors Sn, Sn + 1, Sn + 2, Sn + 3,... S + mn−1 to D-FF-n, D-FF-n + 1, D-FF-n + 2, D -FF-n + 3... The scan mode is sequentially shifted to D-FF-n + m-1. In addition, a scan mode in which the initialization reset signal CL (= Low level) is shifted from the Y terminal of the selector S + mn to D-FF-n + m.
[0054]
In this state, the pulses of the clock signal CK in FIG. 4E corresponding to the number of stages of S-FFs required for the initialization reset are transmitted to the D-FF-1, D-FF-2, D-FF-3,. D-FF-n-1, D-FF-n of the second block, D-FF-n + 1, D-FF-n + 2, D-FF-n + 3... D-FF-n + m-1, of the third block The output value Q1 of the D-FF-1 shown in FIG. 4F is input to the D-FF-n + m during the first-stage initialization reset period from the time T0 to the time T1 to initialize the reset signal CL (= Low level). ), The output value Q2 of the D-FF-2 shown in FIG. 4F is set to the value of the initialization reset signal CL (= Low level) in the second stage initialization reset period from the time T0 to the time T2, FIG. 4F shows the third-stage initialization reset period from the time point to the time point T3. The output value Q3 of the D-FF-3 is set to the value of the initialization reset signal CL (= Low level), and during the initialization reset period of the n (4) th stage from the time T0 to the time T1, the D-FF shown in FIG. The output value Qn (4) of the flip-flop FF-1 is set to the value of the initialization reset signal CL (= Low level), and during the initialization reset period of the (n + 1) -th stage from the time T0 to the time T2, the signal D- shown in FIG. The output value Qn + 1 (5) of the FF-1 is set to the value of the initialization reset signal CL (= Low level), and during the initialization reset period of the (n + 2) -th stage from the time point T0 to the time point T3, D− shown in FIG. The output value Qn + 2 (6) of the FF-1 is set to the value of the initialization reset signal CL (= Low level).... During the initialization reset period of the (n + m) -th stage from the time T0 to the time T2, D− shown in FIG. First output value Qn + m of FF-1 To a value of reduction reset signal CL (= Low level).
[0055]
Here, the initialization reset period 41 of all stages is from the time T0 when the initialization reset signal CL shown in FIG. 4C is set to the low level to the time T11 when the initialization reset signal CL is set to the high level shown in FIG. 4C.
[0056]
As a result, the initialization reset signal CL (= Low level), which is a fixed value of the D-FF-1 of the first block constituting the S-FF at the first stage of the scan input, is sequentially applied to the D-FF constituting each S-FF. -2, D-FF-3 ... D-FF-n (4), D-FF-n (4) +1, D-FF-n (4) +2, D-FF-n + 3 in the second block The initialization in the LSI circuit can be performed in the initialization reset period 41 corresponding to the small number of clocks of the initialization reset signal CL shown in FIG. 4C by transmitting to the D-FF-n + m of the third block. The normal operation 42 is performed after the time T11.
[0057]
Thus, in the LSI circuit example of the second embodiment of the present invention, the AND circuit A2 and the AND circuit are provided in the middle of the scan chain of the S-FF as compared with the LSI circuit example of the first embodiment of FIG. By inserting the gate of A3, the number of clocks required for initialization can be reduced. As can be seen from the timing chart shown in FIG. 4, the initialization reset period 41 is approximately the maximum value of the number of D-FF stages between the gates of the inserted AND circuits A1, A2, and A3 × the clock cycle.
[0058]
[Third Embodiment]
FIG. 5 is a diagram illustrating an example of an internal clock and internal initialization signal generation circuit included in the third embodiment.
[0059]
The internal reset signal CL and the clock signal CK, which are the output signals of the internal clock and internal initialization signal generation circuit example shown in FIG. 5, are used for the LSI circuit example or the first embodiment shown in FIG. 3 is used as an input of the LSI circuit example of the second embodiment shown in FIG.
[0060]
The internal clock and internal initialization signal generation circuit shown in FIG. 5 receives an original clock signal CK_IN and an external reset signal POWER_ON_RESET supplied from the outside, and generates an internal clock signal CK and an initialization reset signal CL based on the input. is there.
[0061]
In FIG. 5, the original clock signal CK_IN is input to the frequency dividing circuit 51 and also to the B input terminal of the selector 53. The divided clock DIV-CLK output from the divider 51 is input to the A input terminal of the selector 53 and is also input to the counter 52 via the inverter INV1. The external reset signal POWER_ON_RESET is input to the frequency divider 51 and the reset terminal CL of the counter 52. The output of the counter 52 is input to the preset terminal of the counter 52 via the inverter INV2. The output of the counter 52 is input to the D input terminal and the reset terminal of the D flip-flop 54, and is output as the initialization reset signal CL. The divided clock DIV-CLK output from the divider 51 is input to the clock terminal CK of the D flip-flop 54. The Q output of the D flip-flop 54 is input to the select terminal S of the selector 53, and the output terminal Y of the selector 53 outputs the internal clock signal CK.
[0062]
The operation of the internal clock and internal initialization signal generation circuit of FIG. 5 configured as described above will be described below.
FIG. 6 is a timing chart of the internal clock and internal initialization signal generation circuit. FIG. 6A shows the original clock signal CK_IN, FIG. 6B shows the external reset signal POWER_ON_RESET, FIG. 6C shows the divided clock DIV-CLK, and FIG. FIG. 6E shows the clock signal CK and the initialization reset signal CL.
[0063]
The counter 52 is reset when the external reset signal POWER_ON_RESET shown in FIG. 6B is Low level, and the counter 52 starts operating when the external reset signal POWER_ON_RESET shown in FIG. The initialization reset signal CL of the output of the counter 52 shown in FIG.
[0064]
During this time, the counter 52 counts from the time point T1 to the time point Tn, and the internal clock signal CK shown in FIG. 6D required for initialization is output from the counter 52. When the S-FF is divided into a plurality of blocks, the number of presets according to the number of divisions is counted.
[0065]
At the time T11 when the initialization reset ends, the counter 52 stops operating, and the internal clock signal CK shown in FIG. 6D is the divided clock DIV-CLK shown in FIG. 6C of the low-speed clock divided for scanning at the time T12. From T to T13, the clock is switched to the high-speed clock for normal operation.
[0066]
[Operation during scan test]
The scan test is one of integrated circuit test methods, and is realized by replacing a flip-flop in a synchronous circuit designed on a D-FF basis with an S-FF.
[0067]
At the time of the scan test, in the examples of FIGS. 1, 3 and 11, the initialization reset signal CL is at the high level, the scan mode signal S_N is at the low level, and the select signal S is at the high level. At this time, since each S-FF operates as a shift register, it is necessary to scan input a scan input SI signal to each S-FF or to take out the value of each D-FF serially from the last stage of the scan shift to outside the LSI. Can be.
[0068]
7 is a timing chart at the time of a scan test. FIG. 7A is a scan input SI, FIG. 7B is a scan mode signal S_N, FIG. 7C is an initialization reset signal CL, FIG. 7D is a select signal S, and FIG. 7E is a clock signal CK. , FIG. 7F shows output values Q1, Q2, Q3... Qn + m of D-FF-1, D-FF-2, D-FF-3.
[0069]
Thus, the scan input SI signal can be input / output to / from the combination circuit 11 in the order of the scan chain via the S-FF, so that the test pattern needs to be considered only for the combination circuit 11 between the S-FFs. It will be easier.
[0070]
[Operation during normal operation]
During normal operation, in the examples of FIGS. 1, 3 and 11, the initialization reset signal CL is at the high level, the scan mode signal S_N is at the high level, and the select signal S is at the low level. At this time, each S-FF inputs and outputs signals to and from the combinational circuit 11 in parallel with the clock signal CK.
[0071]
【The invention's effect】
According to the present invention, the scan test circuit mounted for the shipping test is also used for the initialization reset, so that the amount of wiring and buffers required for the initialization reset can be reduced.
[0072]
Further, as compared with the conventional example in which a reset signal is connected to the asynchronous reset terminal of each D-FF and initialization is performed asynchronously, a reset function can be realized without a reset logic gate in the D-FF. Thus, an increase in power consumption can be suppressed.
[0073]
Furthermore, the setup time and the hold time of the D-FF are reduced, and the circuit operation becomes faster.
[0074]
Further, wiring and buffers for distributing the initialization reset signal can be reduced as in the related art.
[0075]
Further, since a clock pulse and an internal reset signal required for the initialization reset are generated from the external reset signal, even if the pulse width of the external reset signal is insufficient, it is possible to replace the circuit with the conventional circuit.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of an LSI circuit having a scan test and an initialization reset function according to a first embodiment applied to the present invention;
FIG. 2 is a timing chart showing an initialization reset period.
FIG. 3 is a diagram illustrating an example of an LSI circuit having a scan test and initialization reset function according to a second embodiment applied to the present invention;
FIG. 4 is a timing chart showing an initialization reset period at the time of block division.
FIG. 5 is a diagram showing an example of an internal clock and internal initialization signal generation circuit included in a third embodiment applied to the present invention.
FIG. 6 is a timing chart of an internal clock and an internal initialization signal generation circuit.
FIG. 7 is a timing chart during a scan test.
FIG. 8 is a diagram showing a scan flip-flop (S-FF) with a scan synchronization reset.
FIG. 9 is a diagram showing an example of an internal circuit of a scan flip-flop (S-FF) with a scan synchronization reset.
FIG. 10 is a diagram illustrating an example of an internal circuit of a D-FF.
FIG. 11 is a diagram showing an example of a conventional LSI circuit having scan test and initialization reset functions.
FIG. 12 is a diagram showing a scan flip-flop (S-FF) with an asynchronous reset.
FIG. 13 is a diagram illustrating an example of an internal circuit of a scan flip-flop with asynchronous reset (S-FF).
FIG. 14 is a diagram illustrating a scan flip-flop (S-FF) without an asynchronous reset function.
FIG. 15 is a diagram showing an example of an internal circuit of a scan flip-flop (S-FF) without an asynchronous reset function.
FIG. 16 is a diagram illustrating an example of an internal circuit of a D-FF with asynchronous reset.
[Explanation of symbols]
11 combination circuit, A1, A2, A3 AND circuit, N1 NOR circuit, S1 to Sn + m selector, D-FF-1 to D-FF-n + m D flip-flop, 51 minutes Peripheral circuit, 52 counter, 53 selector, 54 D flip-flop, S1 to Sn + m and D-FF-1 to D-FF-n + m scan test circuit

Claims (8)

A scan input is sequentially input to each stage of the combinational circuit in the integrated circuit by a scan mode shift operation using a scan test circuit built in the integrated circuit, and each stage of the combinational circuit is operated. In a scan test circuit device that performs a scan test by sequentially outputting and observing scan outputs from each stage of a combinational circuit by a shift operation in a scan mode,
A scan test circuit device comprising: an initialization reset means for performing an initialization reset in the integrated circuit in the scan mode based on an initialization reset signal synchronized with a scan clock pulse for performing the scan test operation. . The scan test circuit device according to claim 1,
The initialization reset means changes the scan input to a logic fixed value required for initialization reset by the scan mode based on the initialization reset signal supplied from the outside, and executes the initialization reset. A scan test circuit device, wherein an initialization reset is performed using a number of the reset scan clock pulses corresponding to the number of stages of a combinational circuit. The scan test circuit device according to claim 1,
The initialization reset means may be divided into a plurality of blocks corresponding to the number of stages of the combinational circuit requiring the initialization reset, and perform the initialization reset in the scan mode for each of the plurality of blocks. Scan test circuit device. The scan test circuit device according to claim 1,
The initialization reset means includes a synchronous reset signal generation unit that generates the scan clock pulse for the initialization reset according to the number of stages of the combinational circuit and the initialization reset signal from an external reset signal. Scan test circuit device. A scan input is sequentially input to each stage of the combinational circuit in the integrated circuit by a scan mode shift operation using a scan test circuit built in the integrated circuit, and each stage of the combinational circuit is operated. Initialize flip-flop groups in the integrated circuit using a scan test circuit that performs a scan test by sequentially outputting and observing scan outputs from each stage of the combinational circuit by a scan mode shift operation. In the flip-flop group initialization method of
An initialization reset step of performing an initialization reset of the flip-flop group in the integrated circuit in the scan mode based on an initialization reset signal synchronized with a scan clock pulse for performing the scan test operation. A method for initializing a flip-flop group inside an integrated circuit. 6. The method for initializing a flip-flop group inside an integrated circuit according to claim 5,
In the initialization reset step, the scan input is replaced with a logic fixed value required for initialization reset by the scan mode based on the initialization reset signal supplied from outside, and the initialization reset is required. A method for initializing a flip-flop group inside an integrated circuit, wherein initialization is performed using a number of the reset scan clock pulses corresponding to the number of stages of a combinational circuit. 6. The method for initializing a flip-flop group inside an integrated circuit according to claim 5,
The initialization reset step is characterized in that the initialization is divided into a plurality of blocks corresponding to the number of stages of the combinational circuit requiring the initialization reset, and the initialization reset is performed in the scan mode for each of the plurality of blocks. Initialization method for flip-flop group inside integrated circuit. 6. The method for initializing a flip-flop group inside an integrated circuit according to claim 5,
A flip-flop group inside an integrated circuit, wherein the initialization reset step generates the scan clock pulse for the initialization reset according to the number of stages of the combinational circuit and the initialization reset signal from an external reset signal. Initialization method.

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