JP2004310958A - Wobble demodulating device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a wobble demodulating device which reproduces stably and at high speed address information from a wobble signal modulated by PSK-modulation/FSK-modulation. <P>SOLUTION: A stable and accurate address can be reproduced by determining lock states of frequencies and phases of a carrier signal and a wobble signal and performing PSK-modulation/FSK-modulation in accordance with lock states. Also, a time required for address reproduction can be shortened by controlling operation of a wobble PLL in accordance with a lock state and making take-in stable and high speed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention demodulates digital information by detecting and demodulating a wobble signal from an optical recording medium on which digital information such as address information is recorded by forming a wobble modulated by FSK or PSK on a track. And a wobble demodulator.
[0002]
[Prior art]
Conventionally, a track groove is previously formed on a recordable optical recording medium, and information is recorded along the track groove, that is, in an area (land) on the track groove or between the track grooves. The track groove is formed to meander like a sine wave, and information is recorded in synchronization with a clock generated based on the wobble period. In order to record information at a predetermined position on the recording surface of the optical recording medium, an address is provided along the track groove. As a method of writing the address, a PSK (Phase Shift Keying) modulation method (for example, see Patent Document 1) and an FSK (Frequency Shift Keying) modulation method (for example, see Patent Document 2, Patent Document 3, and Patent Document 4). Are known.
[0003]
FIG. 13 shows a waveform of a wobble signal reproduced from a wobble track modulated by the above-described modulation method. FIG. 13A shows a wobble signal waveform subjected to PSK modulation, and the phase is inverted in the PSK modulation portion. FIG. 13B shows a wobble signal waveform obtained by MSK (Minimum Shift Keying) modulation, which is a type of FSK modulation. In contrast to the wobble waveform Cos (ωt) of the non-modulated portion, the wobble waveform of Cos (1.5ωt), -Cos (ωt), and -Cos (1.5ωt) is obtained every three carrier periods in the MSK modulated portion. become.
[0004]
A format in which the address information is recorded by a position at which a modulation mark based on the PSK modulation or the MSK modulation is arranged has been proposed. FIGS. 14 and 15 show an address format using the MSK modulation. The address information is recorded in a unit called an address word, and the address word is composed of 83 units. The unit represents a synchronization pattern (SYNC) or data bits in a 56 carrier cycle, and the address word is divided into an SYNC part of 8 units indicating a synchronization position and a data part of 75 units indicating an address value. FIG. 14 shows the configuration of the SYNC part. The SYNC part is composed of eight units arranged in the order of a monotone unit, a SYNC0 unit, a monotone unit, a SYNC1 unit, a monotone unit, a SYNC2 unit, a monotone unit, and a SYNC3 unit. An MSK modulation mark is arranged at the head of each unit, and an MSK modulation mark is arranged at a different position in each of the SYNC0 unit, the SYNC1 unit, the SYNC2 unit, and the SYNC3 unit. FIG. 15 shows the configuration of the data part. The data part includes a monotone unit, data 1 unit, and data 0 unit, and the data 1 unit and the data 0 unit are different in the position where the MSK modulation mark is arranged. A 5-bit unit of one monotone unit and four data 1 units or data 0 unit represents a 4-bit (1 Nibble) address value, and the data part 15 Nibble is composed of address data 9 Nibble and parity 6 Nibble, thereby correcting the error. can do.
[0005]
FIG. 16 is a block diagram showing a configuration of a conventional wobble demodulator that reproduces address information from a wobble track based on the arrangement position of a modulation mark of PSK modulation or MSK modulation as described above. In FIG. 16, reference numeral 1601 denotes an optical recording medium in which a wobble track is modulated, and 1602, an optical head which irradiates the optical recording medium 1601 with a light beam, detects the amount of light reflected from the optical recording medium 1601, and outputs an electric signal. is there. Reference numeral 1603 denotes wobble signal detection means for extracting a modulated wobble signal from the electric signal. Reference numeral 1604 denotes wobble PLL means for extracting a carrier signal from the wobble signal. Reference numeral 1605 denotes decoding means for reproducing address information from a wobble signal and a carrier signal (for example, see Patent Documents 2 and 3).
[0006]
The decoding unit 1605 multiplies 1606 the wobble signal and the carrier signal, and the modulation unit detection unit 1607 integrates the result or passes the result through a low-pass filter, and detects a modulation mark from the code of the output value. Further, the modulation mark may be detected based on how many times the rising and falling edges of the wobble signal are present in each cycle of the carrier signal. FIG. 17 is a timing chart when, for example, an MSK modulation mark is detected by multiplication with respect to the MSK modulation mark. As shown in FIG. 17A, in the MSK modulation mark portion, the multiplication value becomes a negative value, and the position of the MSK modulation mark can be detected.
[0007]
The SYNC detection unit 1608 determines SYNC0 unit / SYNC1 unit / SYNC2 unit / SYNC3 unit from the modulation mark position to detect a synchronization position. The value of the wobble counter 1609 is preset according to the synchronization position, and counts one address word in carrier cycle units. The data decoding unit 1610 performs demodulation by determining data 1 unit and data 0 unit in the data part from the modulation mark detection position for the wobble counter 1609, and further performs error correction and outputs address information.
[0008]
[Patent Document 1]
JP-A-10-69646
[Patent Document 2]
JP-A-2002-329441
[Patent Document 3]
JP 2002-352521 A
[Patent Document 4]
JP 2001-143404 A
[0009]
[Problems to be solved by the invention]
However, in the conventional method as described above, immediately after the track position for irradiating the optical recording medium with the light beam such as a seek or jump to an adjacent track changes, the frequency and phase of the wobble signal change from before that. Therefore, the frequency and phase of the carrier signal generated by the wobble PLL means do not match the wobble signal, and for example, as shown in FIG. As a result of the detection, the SYNC0 unit / SYNC1 unit / SYNC2 unit / SYNC3 unit is erroneously determined and synchronized with the shifted position, so that the address cannot be reproduced. In order to reproduce an accurate address from such a state, a carrier signal having the same frequency and phase as the wobble signal can be obtained. Therefore, there is a problem that it takes a long time to reproduce the address information, and the access performance to the optical recording medium is deteriorated.
[0010]
In view of the above situation, the present invention proposes a wobble demodulator capable of reproducing address information stably and in a short time when the frequency or phase of a wobble signal changes due to a seek or jump to an adjacent track. The purpose is to:
[0011]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a wobble demodulator according to claim 1 is characterized in that a track for recording data is wobbled, and the wobbling includes a frequency- or phase-modulated first modulated signal portion and a frequency- or phase-modulated signal. A demodulator for reproducing digital information from an optical recording medium formed according to a wobble signal modulated to represent digital information by a combination of unmodulated second carrier signal portions, Wobble signal detection means for extracting a wobble signal corresponding to the wobbling of the track from the optical recording medium, wobble PLL means for generating the carrier signal from the wobble signal, frequency and phase of the wobble signal and the carrier signal PLL lock determining means for performing lock detection and determining the locked state of the PLL And decoding means for detecting and decoding a synchronous position of the digital information from the wobble signal and the carrier signal, wherein the decoding means determines a synchronous position for the digital information if the PLL lock determining means makes a PLL lock determination. Is detected and locked, and if the PLL is unlocked, the locked synchronous position is unlocked.
[0012]
A wobble demodulator according to a second aspect is the wobble demodulator according to the first aspect, wherein a multiplying means for generating a wobble clock obtained by multiplying the frequency of the carrier signal, and a cycle of the wobble signal by the wobble clock. Is further provided, and the PLL lock determination means detects frequency lock if the sum or average of the wobble cycle measurement values in a predetermined section is within a predetermined first range, and performs a predetermined second If the frequency is out of the range, frequency unlock detection is performed.
[0013]
A wobble demodulation device according to a third aspect is the wobble demodulation device according to the first aspect, wherein the wobble binarization means for outputting a wobble binarization signal obtained by binarizing the wobble signal; Carrier binarizing means for outputting a carrier binarized signal obtained by binarizing the signal, and integrating means for integrating the result of the exclusive OR of the wobble binary signal and the carrier binary signal in a predetermined section. Wherein the PLL lock determining means detects a phase lock when the integrated value output by the integrating means is smaller than a predetermined first threshold, and detects a phase unlock when the integrated value output from the integrating means is larger than a predetermined second threshold. I do.
[0014]
The wobble demodulator according to claim 4 is the wobble demodulator according to claim 1, further comprising wobble cycle averaging means for generating an average wobble signal by averaging the cycle of the wobble signal, The PLL lock judging means inputs the averaged wobble signal instead of the wobble signal to the wobble PLL means when the frequency lock is not detected, and sends the averaged wobble signal to the wobble PLL means when the frequency lock is detected. Switching to input the wobble signal.
[0015]
A wobble demodulator according to a fifth aspect is the wobble demodulator according to the first aspect, wherein in the optical recording medium, the digital information is a predetermined information block unit having a synchronization signal including a plurality of sync patterns. The decoding means is configured to lock a synchronous position based on a position where the sync pattern is detected, when detecting a predetermined number or more of the sync patterns from the synchronous signal in one information block. It is characterized by the following.
[0016]
A wobble demodulation device according to a sixth aspect is the wobble demodulation device according to the first aspect, wherein in the optical recording medium, the digital information is a predetermined information block unit having a synchronization signal including a plurality of sync patterns. The decoding means operates so as to unlock the synchronization position when a predetermined number or more of the information blocks in which the synchronization signal cannot be detected from the synchronization signal continues for a predetermined number of times.
[0017]
A wobble demodulation device according to a seventh aspect is the wobble demodulation device according to the first aspect, wherein in the optical recording medium, the digital information is in units of a predetermined information block having a synchronization signal including a predetermined sync pattern. If the information block in which the position of the sync pattern detected from the synchronization signal is deviated from the previously detected synchronization position continues for a predetermined number of times, the decoding means corrects the amount by which the synchronization position is deviated. It is characterized by doing.
[0018]
The wobble demodulation device according to claim 8 is the wobble demodulation device according to claim 1, wherein in the optical recording medium, the digital information includes a synchronization signal including a predetermined sync pattern, a data and a data error. The decoding unit is configured in units of a predetermined information block having a correction code, and the decoding unit includes an error correction unit that performs error correction of the data using the error correction code. If the reproduced data cannot be corrected, the synchronous position is unlocked.
[0019]
The wobble demodulation device according to claim 9 is the wobble demodulation device according to claim 1, wherein in the optical recording medium, the digital information includes a synchronization signal including a predetermined sync pattern, a data and a data error. The decoding unit includes an error correction unit configured to perform error correction of the data using the error correction code, and the reproduced data cannot be corrected. When the information block continues for a predetermined number of times, the operation is performed so as to unlock the synchronous position.
[0020]
In a wobble demodulation method according to a tenth aspect, a track for recording data is wobbled, and the wobbling includes a first modulated signal portion that is frequency or phase modulated, and a wobble that is not frequency or phase modulated. A demodulation method for reproducing the digital information from an optical recording medium formed in accordance with a wobble signal modulated so as to represent digital information by a combination of the two carrier signal parts, A wobble signal detection step of extracting a wobble signal according to wobbling of a track, a wobble PLL step of generating the carrier signal from the wobble signal, and lock detection of a frequency and a phase of the wobble signal and the carrier signal. A PLL lock determination step of determining a lock state of the PLL; A decoding step of detecting and decoding a synchronization position of the digital information from the wobble signal and the carrier signal, wherein the decoding step detects a synchronization position with respect to the digital information if the PLL lock determination step determines PLL lock. Then, if the PLL is unlocked, it operates to unlock the locked synchronous position.
[0021]
A wobble demodulation method according to an eleventh aspect is the wobble demodulation method according to the tenth aspect, wherein: a multiplying step of generating a wobble clock obtained by multiplying the frequency of the carrier signal; The PLL lock determination step further includes detecting a frequency lock if the sum or average of the wobble cycle measurement values in a predetermined section is within a predetermined first range. If the frequency is out of the range, frequency unlock detection is performed.
[0022]
A wobble demodulation method according to claim 12 is the wobble demodulation method according to claim 10, wherein a wobble binarization step of outputting a wobble binarization signal obtained by binarizing the wobble signal; A carrier binarizing step of outputting a carrier binarized signal obtained by binarizing the above, and an integrating step of integrating the result of the exclusive OR of the wobble binary signal and the carrier binary signal in a predetermined section. Wherein the PLL lock determining step detects the phase lock when the integrated value output by the integrating step is smaller than a predetermined first threshold, and detects the phase unlock when the integrated value output from the integrating step is larger than a predetermined second threshold. I do.
[0023]
The wobble demodulation method according to claim 13 is the wobble demodulation method according to claim 10, further comprising a wobble cycle averaging step of generating an averaged wobble signal by averaging the cycle of the wobble signal. The PLL lock determination step includes inputting the averaged wobble signal in place of the wobble signal to the wobble PLL step when frequency lock is not detected, and performing the wobble PLL step when frequency lock is detected. Switching to input the wobble signal.
[0024]
The wobble demodulation method according to claim 14 is the wobble demodulation method according to claim 10, wherein in the optical recording medium, the digital information is in units of a predetermined information block having a synchronization signal including a plurality of sync patterns. The decoding step is operable to lock a synchronization position based on a position where the sync pattern is detected, when detecting a predetermined number or more of the sync patterns from the synchronization signal in one information block. It is characterized by the following.
[0025]
A wobble demodulation method according to a fifteenth aspect is the wobble demodulation method according to the tenth aspect, wherein in the optical recording medium, the digital information is a predetermined information block unit having a synchronization signal including a plurality of sync patterns. In the decoding step, when a predetermined number or more of information blocks in which the synchronization signal cannot be detected from the synchronization signal continues for a predetermined number of times, the decoding step operates to unlock the synchronization position.
[0026]
A wobble demodulation method according to claim 16 is the wobble demodulation method according to claim 10, wherein in the optical recording medium, the digital information is in units of a predetermined information block having a synchronization signal including a predetermined sync pattern. If the information block in which the position of the sync pattern detected from the synchronization signal is shifted from the previously detected synchronization position continues for a predetermined number of times, the decoding step corrects by the amount of the shift of the synchronization position. It is characterized by doing.
[0027]
A wobble demodulation method according to a seventeenth aspect is the wobble demodulation method according to the tenth aspect, wherein in the optical recording medium, the digital information includes a synchronization signal including a predetermined sync pattern, and data and data error. The decoding step includes an error correction step of performing error correction of the data using the error correction code. If the reproduced data cannot be corrected, the synchronous position is unlocked.
[0028]
The wobble demodulation method according to claim 18 is the wobble demodulation method according to claim 10, wherein in the optical recording medium, the digital information includes a synchronization signal including a predetermined sync pattern, and data and data error. The decoding step includes an error correction step of performing error correction of the data using the error correction code, and the reproduced data cannot be corrected. When the information block continues for a predetermined number of times, the operation is performed so as to unlock the synchronous position.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a wobble demodulator according to the present invention will be described.
[0030]
FIG. 1 is a block diagram showing a configuration of a wobble demodulator according to the present invention. In FIG. 1, reference numeral 101 denotes an optical recording medium in which a wobble track is MSK-modulated according to the address format shown in FIGS. An optical head 102 irradiates the optical recording medium 101 with a light beam, detects the amount of light reflected from the optical recording medium 101, and outputs an electric signal. 103 is a wobble signal detecting means for extracting the MSK modulated wobble signal from the electric signal. 104 is a wobble PLL means for generating a carrier signal synchronized in phase with the wobble signal. Reference numeral 105 denotes a PLL lock determination unit that determines a synchronization state between the frequency and the phase of the wobble signal and the carrier signal. A decoding unit 106 performs MSK demodulation from the wobble signal and the carrier signal and reproduces address information.
[0031]
A light beam emitted from the optical head 102 is condensed on the optical recording medium 101 and a track engraved on the optical recording medium 101 is scanned, so that a tracking error signal is generated from reflected light from both sides of the track. . The wobble signal detection means 103 extracts a wobble signal from the tracking error signal using a band pass filter. The wobble PLL means 104 multiplies the extracted wobble signal by a wobble clock, and generates a wobble clock and a carrier signal obtained by dividing the frequency. Further, the PLL lock determination unit 105 controls the pull-in operation of the wobble PLL unit 104 while determining the synchronization state of the frequency and the phase of the wobble signal and the carrier signal. The decoding means 106 detects the MSK modulation mark from the wobble signal and the carrier signal, and reproduces address information according to the position.
[0032]
Next, detailed operations of the wobble PLL unit 104 and the PLL lock determination unit 105 will be described.
[0033]
FIG. 2 is a block diagram showing a configuration of the wobble PLL unit and the PLL lock determination unit.
[0034]
The wobble PLL means includes a phase comparator 201 for comparing the phase of the wobble signal and the carrier signal, a charge pump 202, a loop filter 203 for smoothing the output of the charge pump 202, and a frequency corresponding to the voltage smoothed by the loop filter 203. A PLL section comprising a voltage controlled oscillator (VCO) 204 for generating a wobble clock, a frequency divider 205 for generating a carrier signal by dividing the wobble clock, and a cycle averaging means for averaging the cycle of the wobble signal It consists of 211.
[0035]
The PLL lock determination means includes a cycle measurement means 206 for measuring the cycle of the wobble signal, a frequency lock detection means 207 for detecting the frequency lock state from the cycle measurement value, and an exclusive control of the binary signal of each of the wobble signal and the carrier signal. EXOR integrating means 208 for integrating the logical sum (EXOR) result, phase lock detecting means 209 for detecting the phase lock state from the EXOR result integrated value, and PLL for detecting the PLL lock state from the frequency lock detection result and the phase lock detection result. It comprises lock detecting means 210.
[0036]
When detecting the rising edge of the wobble signal, the phase comparator 201 samples the frequency division counter value of the frequency divider 205 that generates the carrier signal, and transmits a phase error pulse corresponding to the value to the charge pump 202. . The charge pump 202 discharges or sinks current in response to the received phase error pulse, and controls the current charged to the subsequent loop filter 203 by this operation, thereby changing the voltage of the loop filter 203 and further changing the voltage of the subsequent loop filter. The oscillation frequency of the VCO 204 is controlled. The clock of the VCO 204 is frequency-divided at a frequency division period 205, and operates as a loop so that the phase error between the carrier signal and the wobble signal generated by frequency division approaches zero.
[0037]
FIG. 3 is a timing chart showing the operation of PLL lock detection by the PLL lock detection means 210. The PLL lock detecting means 210 determines the PLL lock state from the frequency lock detecting signal / frequency unlock detecting signal by the frequency lock detecting means 207 and the phase lock detecting signal / phase unlock detecting signal by the phase lock detecting means 209, Outputs the lock determination result. Also, it outputs a control signal for controlling the wobble PLL means according to the lock determination result.
[0038]
FIG. 3A is a timing chart showing the operation from the start of the pull-in of the PLL unit to the determination of the PLL lock. At the start of the pull-in, the PLL lock determination result starts from the frequency pull-in step, and if a frequency lock detection signal is output, the process transits to the phase pull-in step 1. If the frequency lock detection signal has been output in the phase lock-in step 1 and the phase lock detection signal has been output, the process proceeds to the phase lock-in step 2, in which both the frequency lock detection signal and the phase lock detection signal are output again. For example, the state transits to the PLL lock step.
[0039]
An input switching signal for selecting an input to the phase comparator 201 of the wobble PLL means and a charge pump 202 in order to stabilize and speed up the pull-in operation of the wobble PLL means according to the lock determination result of the above four steps. , And controls the pull-in operation. The gain of the charge pump 202 is set to a high gain during the period from the frequency pull-in step to the phase pull-in step 1 in order to shorten the pull-in time, and is low in order to increase the stability of the wobble clock in the phase pull-in step 2 to the PLL lock step. Gain. In the input to the phase comparator 201, in the frequency pull-in step, the charge pump 202 has a high gain, and the frequency of the wobble clock tends to fluctuate with respect to the 1.5 times frequency in the MSK modulation mark portion, and becomes unstable. As a result, it becomes impossible to converge on the carrier frequency, and therefore, an averaged wobble signal whose period has been averaged by the period averaging means 211 is input. After the phase pull-in step 1, a normal wobble signal is input.
[0040]
FIG. 4A is a timing chart showing the operation of the period averaging means 211. The cycle of the wobble signal is measured with a clock of an arbitrary fixed frequency, and the cycle average value is calculated from the measured value in the 56 wobble section. The period for calculating the period average value is a 56 wobble period or longer so that the MSK modulation mark is included at least once so that a change in the period due to the MSK modulation can be smoothed. The cycle averaging means 211 outputs an averaged wobble signal based on the calculated cycle average value. FIG. 4B shows the frequency of the wobble signal and the rate of change of the average value thereof. For the wobble frequency, if the data part is used, there are two MSK modulation marks every 56 wobbles, and a 1.5 times frequency exists. On the other hand, assuming that the section for calculating the average value is 56 wobbles, the average value side locally fluctuates by about 1.5% due to one MSK modulation mark, but the range of fluctuation varies as a whole. It is in the range of about 3%, and is very stable as compared with the wobble frequency itself. However, as can be seen from FIG. 4B, the average value is about 4% higher than the carrier frequency at the center frequency. In the next phase pull-in step 1, the phase pull-in range of the PLL section is insufficient, causing a cycle slip, and the time required for phase pull-in becomes long. Therefore, if an averaged wobble signal is generated based on a value that is 4% larger than the calculated period average value in order to eliminate the offset amount, in the frequency pull-in step, the average wobble signal is close to the carrier frequency without being affected by the MSK modulation. The frequency can be pulled in, and the phase can be pulled in a short time stably without generating a cycle slip in the next phase pull-in step 1.
[0041]
Next, determination of unlocking of the PLL will be described. FIG. 3B is a timing chart showing an operation when the frequency is unlocked from the PLL lock, and FIG. 3C is a timing chart showing an operation when the phase is unlocked from the PLL lock. When the frequency unlock detection signal is output, the PLL lock determination transitions to the frequency lock-in step, and thereafter, the locking operation up to the PLL lock step described above is performed. Further, when the phase unlock detection signal is output, the PLL lock determination shifts to the phase lock-in step 1, and thereafter, every time the phase lock detection signal is output, the phase shifts to the phase lock-in step 2 and the PLL lock step, and the lock-in is performed. Perform the operation. This makes it possible to immediately detect that the PLL is not locked even if the frequency or phase of the wobble signal suddenly changes when jumping to an adjacent track unintentionally. Further, when it is known that the PLL is unlocked in advance, such as in a seek operation, a frequency lock-in step is performed at the timing of performing the lock-in operation, the lock-in operation is performed from the beginning, and a stable carrier signal can be generated in a short time. Become.
[0042]
Next, detailed operations of frequency lock detection and phase lock detection will be described.
[0043]
FIG. 5A is a timing chart showing the operation of frequency lock detection by the cycle measuring means 206 and the frequency lock detecting means 207. The cycle measuring means 206 outputs a value obtained by measuring one cycle of the wobble signal with the wobble clock to the frequency lock detecting means 207. The frequency lock detecting means 207 calculates the sum of the cycle measurement values in the 56 wobble section, and if the value is larger than the threshold FOKmin and smaller than the threshold FOKmax, determines that the frequencies of the wobble signal and the carrier signal are locked, Outputs frequency lock detection signal. If the frequency is smaller than the threshold value FNGmin or larger than the threshold value FNGmax, it is determined that the frequency is unlocked, and a frequency unlock detection signal is output. Here, in the frequency locked state, if the wobble signal of all 56 wobble sections is the carrier frequency, the total of the cycle measurement values is 56 times the carrier cycle W (the wobble clock is W times the carrier cycle). However, as shown in FIGS. 14 and 15, there are always 1 to 3 MSK modulation marks in the 56 wobble section, and each MSK modulation mark has one more wavenumber of the wobble signal than the carrier signal. The section has the same length as the carrier 53 to 55 periods. Therefore, each threshold used for the frequency lock detection and the frequency unlock detection described above is
FOKmin = W × 53−a
FOKmax = W × 55 + a
FNGmin = W × 52
FNGmax = W × 56
And Here, a is an integer of 0 or more and less than W. When the PLL lock determination is a frequency lock-in step and the selected signal is an averaged wobble signal, since the influence of MSK modulation is reduced as described above, each threshold value is
FOKmin = W × 56−a
FOKmax = W × 56 + a
FNGmin = W × 55
FNGmax = W × 57
And
[0044]
FIG. 5B is a timing chart showing an operation of phase lock detection by the EXOR integrating means 208 and the phase lock detecting means 209. The EXOR integrating means 208 samples the exclusive OR of the binary signal of the wobble signal and the carrier signal with the wobble clock, and integrates the sampling result. The integrated value is output as an EXOR integrated value every 112 carrier cycles, and integration starts again from 0. If the EXOR integrated value is smaller than the threshold value POK, the phase lock detection means 209 determines that the phases of the wobble signal and the carrier signal are locked, and outputs a phase lock detection signal. If it is larger than the threshold value PNG, it is determined that the phase is unlocked, and a phase unlock detection signal is output. As shown in FIGS. 14 and 15, since there are 3 to 4 MSK modulation marks in the 112 carrier period section, the above-described threshold value is set for the value E integrated for one MSK modulation mark. Is
POK = E × 4 + b
PNG = POK + c
And Here, b is an integer of 0 or more and less than E, and c is an integer of 0 or more.
[0045]
According to the frequency lock detection and the phase lock detection as described above, the locked state of the PLL can be accurately detected even for the MSK-modulated wobble signal, and the pull-in operation can be controlled.
[0046]
Next, a detailed operation of the decoding means 106 will be described.
[0047]
FIG. 6 is a block diagram showing a configuration of the decoding means 106. In FIG. 6, reference numeral 601 denotes a modulation unit detecting unit that detects an MSK modulation mark. 602 is a section measuring means for measuring the interval between the MSK modulation mark detection positions, 603 is SYNC detecting means for detecting SYNC0 unit / SYNC1 unit / SYNC2 unit / SYNC3 unit from the measured section length, and 604 is SYNC detection This is a synchronization determination unit that determines a synchronization state from a result. A wobble counter 605 operates based on the SYNC detection position. Reference numeral 606 denotes data decoding means for determining data 1 unit and data 0 unit, and reference numeral 607 denotes error correction means for performing error correction on data decoded for each address word and outputting address information.
[0048]
The modulation section detection means 601 multiplies the wobble signal by the carrier signal, detects a point where a value obtained by integrating the multiplication result for each carrier cycle becomes a negative value as an MSK modulation mark, and outputs a modulation section detection signal. Alternatively, the multiplication result is input to a low-pass filter, a portion where the output value of the low-pass filter becomes a negative value is detected as an MSK modulation mark, and a modulation section detection signal is output.
[0049]
The section measurement unit 602 measures the interval between the modulation unit detection signals output by the modulation unit detection unit 601 in carrier cycle units, and outputs measured values for the past three sections.
[0050]
The SYNC detection unit 603 determines the position detected with each SYNC unit from the value of the MSK modulation mark detection position interval in the past three sections by the section measurement unit 602. As shown in FIG. 14, when the interval of the past three sections is {56, 16, 10}, the 29th carrier cycle of the SYNC0 unit, and when {16, 10, 30}, the 3rd of the monotone unit next to the SYNC0 unit. Carrier cycle, {10,30,56}, 3rd carrier cycle of SYNC1 unit, {56,18,10}, 31st carrier cycle of SYNC1 unit, {18,10,28} The third carrier cycle of the monotone unit next to the SYNC1 unit, the third carrier cycle of the SYNC2 unit when {10, 28, 56}, the 33rd carrier cycle of the SYNC2 unit when {56, 20, 10}, 20, 10, 26}, the third carrier cycle of the monotone unit next to the SYNC2 unit, {10, 26, 56} Is the third carrier cycle of the SYNC3 unit, {56,22,10} is the 35th carrier cycle of the SYNC3 unit, and {22,10,24} is the first monotone of the data part coming next to the SYNC3 unit In the case of {10, 24, 56}, the third carrier cycle of the unit, it can be determined to be the third carrier cycle of the data 0 unit or the data 1 unit next to the head monotone unit of the data part. Upon detecting the SYNC pattern, the SYNC detection means 603 outputs a SYNC pattern detection signal, a SYNCID value indicating 0 to 3 of the SYNC unit, and detection position information.
[0051]
The synchronization determination unit 604 determines a synchronization state from the lock determination result by the PLL lock determination unit 105 and the SYNC detection result by the SYNC detection unit 603, and performs preset control of the wobble counter 605. FIG. 7 is a state transition diagram of the synchronization state determination state machine in the synchronization determination unit 604. There are five states: an "initial state", a "synchronous NG state", a "pre-lock state", a "synchronous lock state", and a "position correction state". In the case of the pull-in step 1, the operation is in the “initial state” (transition condition (a)), and the synchronous position detecting operation is not performed. (Transition condition (b)).
[0052]
In the “synchronous NG state”, the wobble counter 605 is preset based on the first SYNC detection result, and the state transits to the “pre-lock state” (transition condition (c)).
[0053]
In the “pre-lock state”, if a predetermined number or more of the four SYNCs are detected in the transitioned address word and the decoding result of the address word is error-correctable by the error correction unit 607 (ECCOK), the state transits to the “synchronous lock state”. (Transition condition (d)). However, if the number of SYNC detections is less than the predetermined number or if error correction is not possible (ECCNG), the state transits to the “synchronous NG state” (transition condition (e)).
[0054]
FIG. 8 shows a timing chart of the operation of determining the number of SYNC detections. The modulation section detection means 601 outputs a modulation section detection signal at each MSK modulation mark section. The SYNC detection means 603 determines a SYNC pattern from output intervals of the past three sections of the modulation section detection signal, and outputs a SY pattern detection signal. The synchronization determination unit 604 generates an SY detection window indicating a position where SYNC should be detected based on the state of the state machine and the wobble counter 605. The SY detection window is fully open (always High) in the “synchronous NG state”, and when the SYNC is detected for the first time, the wobble counter 605 is preset based on the SYNC-ID value and the SYNC position, and the “pre-lock state” is set. After that, it is output only at the position where SYNC should be detected in accordance with the wobble counter value. The detection result of the SYNC is counted for each address word. If the detected number is equal to or more than a predetermined number, the SYNC detection number is OK. If the detected number is less than the predetermined number, the SYNC detection number is NG.
[0055]
FIG. 9 is a timing chart showing a transition operation from the “initial state” to the “synchronous lock state”. When the lock determination result of the wobble PLL is the frequency pull-in step or the phase pull-in step 1, the frequency or phase of the wobble signal and the carrier signal are not synchronized, and the sync position is erroneously detected. No output, and no synchronous position detection operation is performed in the "initial state". When the phase lock-in step 2 or the PLL lock step is reached, the synchronization detection ENB signal is output, and the synchronization position detection is started from the “synchronization NG state”. At the first SYNC detection, the wobble counter is preset, and the state transits to the “pre-lock state”. If the SYNC detection number is OK and ECCOK in the address word, the state transits to the “synchronous lock state”. After that, if the lock determination result of the wobble PLL is other than the phase lock-in step 2 and the PLL lock step, the synchronous ENB signal is not output, and the synchronous position detecting operation is stopped.
[0056]
FIG. 10 is a timing chart showing the operation when the decoding result of the address word that has transited to the “prelock state” is ECCNG. The state transits from the “synchronous NG state” to the “pre-lock state” upon the first SYNC detection. However, if the decoded result of the transitioned address word is ECCNG, it is determined that the synchronization position is not accurate, the state returns to the “synchronization NG state” again, and the synchronization position is detected from the beginning. To the "locked state".
[0057]
Next, returning to FIG. 7, the operation of detecting the synchronization unlock from the “synchronization lock state” will be described.
[0058]
In the “synchronous lock state”, if the decoding result is continuously ECCNG or the number of SYNC detections is continuously less than a predetermined number, it is determined that the synchronous position is unlocked, and the state transits to the “synchronous NG state” (transition condition). (F)). FIG. 11 is a timing chart showing a transition operation from the “synchronous lock state” to the “synchronous NG state”. In the “synchronous lock state”, if the number of SYNC detections is continuously less than the predetermined number, a SY consecutive NG signal is output, and the state transits to the “synchronous NG state”. When the decoding result is ECCNG continuously, an ECC continuous NG signal is output, and the state transits to the “synchronous NG state”. After the transition to the “synchronous NG state”, the operation is the same as described above.
[0059]
In the “synchronous lock state”, if a predetermined number of SY pattern detection signals are detected at a position one carrier cycle before or one carrier cycle after the SY detection window position, it is determined that the synchronization position is shifted one carrier cycle back and forth. Then, at the same time as correcting the value of the wobble counter by +1 or -1, the state transits to the "position correction state" (transition condition (g)). After the transition to the “position correction state”, if the decoding result of the address word is ECCOK, the state transits to the “synchronous lock state” (transition condition (h)), and if the decoding result is ECCNG, the state transits to the “synchronous NG state” (transition). Condition (i)). FIG. 12 is a timing chart showing the transition operation regarding the “position correction state”. When in the "synchronous lock state", a predetermined number or more of SYNCs are detected at positions shifted by +1 carrier cycle in the SYNC part of a certain address word, so that the wobble counter is corrected by +1 after passing the SYNC part, and the "position correction state"". After that, since the decoding result of the address word is ECCOK, the state changes to the “synchronous lock state” again. At this time, if it is ECCNG, it is determined that the positional deviation was not within the range that can be corrected, and the state transits to the “synchronous NG state”, and the synchronous position is detected again.
[0060]
Returning to FIG. 6, the configuration of the decoding means will be described. The wobble counter 605 counts one address word by itself on the basis of the carrier signal while being preset by the synchronization determination unit 604 as described above. The counter includes a carrier counter that counts 56 carrier cycles (= 1 unit) and a unit counter that counts 83 units (= 1 address word). Each counter value is set to SYNC at the output timing of the SY detection signal. -Preset according to the ID value and the SYNC detection position information. When the SYNC position deviation is detected, the value of the carrier counter is corrected by +1 or -1.
[0061]
When the state of the synchronization judging unit 604 is “pre-lock state”, “synchronous lock state”, or “position correction state”, the data decoding unit 606 uses the modulation unit detection signal and the value of the wobble counter 605 to output 1 unit of data and 0 data. The unit is determined, and a data determination result is output to the error correction unit 607. When the unit counter value of the wobble counter 605 is (9 + i × 5), (10 + i × 5), (11 + i × 5), or (12 + i × 5), the output position of the modulation unit detection signal with respect to the carrier counter value is The data is determined accordingly. The data determination result is converted to a 4-bit (Nible) parallel value each time the unit counter value becomes (8 + i × 5) or 0, and is output to the error correction unit 607. Further, after outputting the data determination result when the unit counter value is 0, a correction start signal for performing error correction is also output to the error correction means 607.
[0062]
The error correction means 607 accumulates the data determination result 15Nible for one address word from the data decoding means 606, and when a correction start signal is output, as shown in FIG. 15, the first half 9Nible is data and the second half 6Nible. An error correction process is performed as parity, and as a result, an address information and an ECCOK signal indicating whether error correction is possible or impossible are output.
[0063]
As described above, by controlling the operation of pulling in the wobble PLL with respect to the MSK-modulated wobble signal and the operation of decoding the address information recorded by the MSK modulation based on the determination result of the lock state of the wobble PLL, Even if the frequency or phase of the wobble signal changes due to a seek or jump to an adjacent track, address information can be reproduced stably and in a short time.
[0064]
Note that, in the above-described embodiment, an example is shown for a wobble track that has been subjected to MSK modulation. However, the present invention is not limited to this, and a similar effect can be achieved with PSK modulation or other FSK modulation. Further, the format in which digital information such as an address is recorded is a format as shown in FIGS. 14 and 15, but is not limited thereto.
[0065]
In the PLL lock determination means of the above-described embodiment, the total value of the measured periods is used as a method of detecting frequency lock, but the present invention is not limited to this, and an average value may be used.
[0066]
In the decoding means of the above-described embodiment, as a method of detecting the modulation section, the result of multiplication of the wobble signal and the carrier signal is detected from the result of integration or passing through a low-pass filter. The same effect can be obtained by using a wobble signal and a carrier signal.
[0067]
Further, the detection of the SYNC position shift in the synchronization judgment means of the decoding means is corrected if the SYNC detection position in one address word is shifted by one carrier cycle before and after, but is fixed continuously over a plurality of address words. If the amount is shifted, the wobble counter value may be corrected.
[0068]
Further, the method of decoding data by the decoding means is that decoding is performed from the output position of the modulation section detection signal with respect to the wobble counter value, but is not limited to this.
[0069]
【The invention's effect】
As described above, according to the wobble demodulation device of the present invention, the lock state of the wobble PLL is determined, and the control of detecting the synchronous position of digital information recorded by FSK modulation or PSK modulation is performed according to the determination result. By doing so, it becomes possible to reproduce address information stably.
[0070]
Further, by performing frequency lock detection based on a value obtained by measuring a wobble signal with a wobble clock and phase lock detection based on an exclusive OR of a wobble signal and a carrier signal in a section in which a modulation mark is included on average. , FSK-modulated or PSK-modulated wobble signal, it is possible to accurately determine the locked state of the wobble PLL.
[0071]
In addition, at the time of pulling in the frequency of the wobble PLL, an averaged wobble signal obtained by averaging the period of the wobble signal is input to the wobble PLL so that the wobble PLL can be pulled in stably and at high speed without being affected by a frequency change due to FSK modulation or PSK modulation. Becomes possible.
[0072]
Further, by determining the synchronization position based on the number of SYNCs indicating the synchronization position of the digital information and the decoding result based on the error correction result, the synchronization position of the digital information can be accurately and stably detected.
[0073]
Further, by detecting that the SYNC detection position is deviated by a predetermined amount and correcting the synchronization position, digital information can be stably reproduced.
[0074]
In addition, even if an unexpected track jump occurs, accurate address information is immediately reproduced, so that erroneous recording on an adjacent track can be minimized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a wobble demodulator according to an embodiment of the present invention.
FIG. 2 is a block diagram of a wobble PLL unit and a PLL lock determination unit of the wobble demodulation device according to the embodiment of the present invention.
FIG. 3 is a timing chart showing a lock determination operation of a PLL lock determination unit of the wobble demodulation device according to the embodiment of the present invention.
FIG. 4 is a timing chart showing a period averaging operation of the wobble demodulator according to the embodiment of the present invention.
FIG. 5 is a timing chart showing operation of frequency lock detection and phase lock detection of PLL lock determination means of the wobble demodulator according to the embodiment of the present invention.
FIG. 6 is a block diagram of a decoding unit of the wobble demodulator according to the embodiment of the present invention.
FIG. 7 is a state transition diagram of a synchronous position determination state of the decoding means of the wobble demodulator according to the embodiment of the present invention.
FIG. 8 is a timing chart showing an operation of SYNC detection of the decoding means of the wobble demodulator according to the embodiment of the present invention.
FIG. 9 is a timing chart showing a synchronous position lock detection operation of the decoding means of the wobble demodulator according to the embodiment of the present invention.
FIG. 10 is a timing chart showing the operation of unlock detection before locking of the synchronous position of the decoding means of the wobble demodulator according to the embodiment of the present invention.
FIG. 11 is a timing chart showing an operation of unlock detection from a synchronous position locked state of the decoding means of the wobble demodulator according to the embodiment of the present invention.
FIG. 12 is a timing chart showing a synchronous position correction operation of the decoding means of the wobble demodulator according to the embodiment of the present invention.
FIG. 13 is a diagram showing wobble signal waveforms subjected to PSK modulation and MSK modulation.
FIG. 14 is a diagram illustrating an example of a configuration of an address format SYNC;
FIG. 15 is a diagram showing an example of a data configuration of an address format.
FIG. 16 is a block diagram showing a configuration of a conventional wobble demodulator;
FIG. 17 is a timing chart showing an MSK modulation mark detection operation performed by a conventional wobble demodulator.
[Explanation of symbols]
101,1601 Optical recording medium
102,1602 Optical head
103,1603 wobble signal detecting means
104, 1604 Wobble PLL means
105 PLL lock determination means
106, 1605 decoding means
201 Phase comparator
202 charge pump
203 Loop filter
204 VCO
205 divider
206 Period measurement means
207 Frequency lock detection means
208 EXOR integrating means
209 Phase lock detecting means
210 PLL lock detecting means
211 Period averaging means
601, 1607 Modulation section detecting means
602 section measurement means
603, 1608 SYNC detection means
604 synchronization determination means
605,1609 Wobble counter
606, 1610 Data decoding means
607 Error correction means
1606 Multiplier

Claims (18)

A track on which data is recorded is wobbled, and the wobbling is performed by combining digital information by a combination of a frequency- or phase-modulated first modulated signal portion and a frequency- or phase-unmodulated second carrier signal portion. A demodulator for reproducing the digital information from an optical recording medium formed according to a wobble signal modulated as
Wobble signal detection means for extracting a wobble signal according to wobbling of the track from the optical recording medium;
Wobble PLL means for generating the carrier signal from the wobble signal;
PLL lock determination means for performing lock detection of the frequency and phase of the wobble signal and the carrier signal to determine a PLL lock state;
Decoding means for detecting and decoding the synchronous position of the digital information from the wobble signal and the carrier signal,
The decoding means operates to detect and lock the synchronous position with respect to the digital information when the PLL lock determining means makes a PLL lock determination, and unlocks the locked synchronous position when making a PLL unlock determination. A wobble demodulator, wherein A multiplying means for generating a wobble clock obtained by multiplying the frequency of the carrier signal; and a cycle measuring means for measuring a cycle of the wobble signal based on the wobble clock, wherein the PLL lock determining means comprises a wobble cycle measurement value in a predetermined section. 2. The wobble demodulator according to claim 1, wherein the frequency lock is detected if the sum or the average value is within a predetermined first range, and the frequency unlock is detected if the sum or the average value is outside the predetermined second range. Wobble binarization means for outputting a wobble binarized signal obtained by binarizing the wobble signal, carrier binarization means for outputting a carrier binarized signal obtained by binarizing the carrier signal, and wobble binarization An integrating means for integrating the result of the exclusive OR of the signal and the carrier binarized signal in a predetermined section, wherein the PLL lock determining means determines that the integrated value output by the integrating means is a predetermined first threshold value. 2. The wobble demodulator according to claim 1, wherein a phase lock is detected when the difference is smaller than a predetermined value, and a phase unlock is detected when the difference is larger than a second predetermined threshold. Wobble cycle averaging means for generating an averaged wobble signal by averaging the cycle of the wobble signal is provided, and the PLL lock determination means provides the wobble signal to the wobble PLL means when frequency lock is not detected. 2. The wobble demodulator according to claim 1, wherein the wobble demodulator is switched to input the wobble signal to the wobble PLL means when the averaged wobble signal is input and frequency lock is detected. In the optical recording medium, the digital information is configured in units of a predetermined information block having a synchronization signal including a plurality of sync patterns, and the decoding unit performs a predetermined number or more of the synchronization signals from the synchronization signal in one information block. 2. The wobble demodulator according to claim 1, wherein when detecting a sync pattern, the wobble demodulator operates so as to lock a synchronous position based on the position where the sync pattern is detected. In the optical recording medium, the digital information is configured in a predetermined information block unit having a synchronization signal including a plurality of sync patterns, and the decoding unit cannot detect a predetermined number or more of the sync patterns from the synchronization signal. 2. The wobble demodulator according to claim 1, wherein when the information block continues for a predetermined number of times, the synchronous position is unlocked. In the optical recording medium, the digital information is constituted by a predetermined information block unit having a synchronization signal including a predetermined sync pattern, and the decoding unit detects a position of the sync pattern detected from the synchronization signal before. 2. The wobble demodulator according to claim 1, wherein, if the information block shifted from the synchronized position continues a predetermined number of times, the information is corrected by the amount shifted from the synchronized position. In the optical recording medium, the digital information is composed of a synchronization signal including a predetermined sync pattern and a predetermined information block unit having data and an error correction code of the data, and the decoding unit includes the error correction code. Error correction means for performing error correction of the data by using the information block, and operates so as to unlock the synchronization position if the data reproduced in the information block where the synchronization position is first detected cannot be corrected. The wobble demodulator according to claim 1, wherein In the optical recording medium, the digital information is composed of a synchronization signal including a predetermined sync pattern and a predetermined information block unit having data and an error correction code of the data, and the decoding unit includes the error correction code. Error correction means for performing error correction of the data by using the information block, and operates so as to unlock the synchronous position when the information block in which the reproduced data is uncorrectable continues for a predetermined number of times. Item 2. A wobble demodulator according to item 1. A track for recording data is wobbled, and the wobbling is performed by combining digital information by a combination of a frequency- or phase-modulated first modulated signal portion and a frequency- or phase-unmodulated second carrier signal portion. A demodulation method for reproducing the digital information from an optical recording medium formed according to a wobble signal modulated to represent
A wobble signal detecting step of extracting a wobble signal according to wobbling of the track from the optical recording medium;
A wobble PLL step for generating the carrier signal from the wobble signal;
A PLL lock determining step of performing lock detection of the frequency and phase of the wobble signal and the carrier signal to determine a locked state of the PLL;
Decoding the synchronous position detection and decoding of the digital information from the wobble signal and the carrier signal,
The decoding step operates to detect and lock the synchronous position with respect to the digital information if the PLL lock determining step determines the PLL lock, and unlocks the locked synchronous position if the PLL unlock determination is made. A wobble demodulation method characterized by operating as follows. A multiplying step of generating a wobble clock obtained by multiplying the frequency of the carrier signal; and a cycle measuring step of measuring a cycle of the wobble signal using the wobble clock, wherein the PLL lock determination step includes a wobble cycle measurement value in a predetermined section. 11. The wobble demodulation method according to claim 10, wherein frequency lock detection is performed if the sum or average of the values is within a predetermined first range, and frequency unlock detection is performed if the sum or average value is outside the predetermined second range. A wobble binarization step of outputting a wobble binarized signal obtained by binarizing the wobble signal, a carrier binarization step of outputting a carrier binarized signal obtained by binarizing the carrier signal, and wobble binarization An integrating step of integrating the result of the exclusive OR of the signal and the carrier binarized signal in a predetermined section; wherein the PLL lock determining step includes determining that the integrated value output by the integrating step is a predetermined first threshold. 11. The wobble demodulation method according to claim 10, wherein the phase lock is detected when the value is smaller than the predetermined value, and the phase unlock is detected when the value is larger than a predetermined second threshold value. A wobble cycle averaging step for generating an averaged wobble signal by averaging the cycle of the wobble signal, wherein the PLL lock determination step is performed with respect to the wobble PLL step when the frequency lock is not detected. 11. The wobble demodulation method according to claim 10, wherein said averaging wobble signal is input instead, and switching is performed so as to input said wobble signal with respect to said wobble PLL step when frequency lock is detected. In the optical recording medium, the digital information is configured in units of a predetermined information block having a synchronization signal including a plurality of sync patterns, and the decoding step includes the step of decoding a predetermined number or more of the synchronization signal in one information block. 11. The wobble demodulation method according to claim 10, wherein when a sync pattern is detected, an operation is performed to lock a synchronization position based on the position where the sync pattern is detected. In the optical recording medium, the digital information is configured in a predetermined information block unit having a synchronization signal including a plurality of sync patterns, and the decoding step cannot detect a predetermined number or more of the sync patterns from the synchronization signal. 11. The wobble demodulation method according to claim 10, wherein when the information block continues for a predetermined number of times, the synchronous position is unlocked. In the optical recording medium, the digital information is configured in a predetermined information block unit having a synchronization signal including a predetermined sync pattern, and the decoding step includes detecting a position of the sync pattern detected from the synchronization signal before. 11. The wobble demodulation method according to claim 10, wherein, when the information block shifted from the synchronized position continues for a predetermined number of times, the information is corrected by the amount shifted from the synchronized position. In the optical recording medium, the digital information is composed of a synchronization signal including a predetermined sync pattern, and a predetermined information block unit having data and an error correction code of the data. And an error correction step of performing error correction of the data by using the information block. If the data reproduced from the information block in which the synchronization position is first detected cannot be corrected, the synchronization position is unlocked. The wobble demodulation method according to claim 10, wherein In the optical recording medium, the digital information is composed of a synchronization signal including a predetermined sync pattern, and a predetermined information block unit having data and an error correction code of the data. An error correction step of performing error correction of the data by using an information block, and operating so as to unlock a synchronization position when information blocks in which reproduced data cannot be corrected are repeated a predetermined number of times. Item 11. The wobble demodulation method according to Item 10.

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