JP2004309498A - Trouble analyzer for printed circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily make clear a mutual relation among a printed circuit board, a test jig and a tester pin number to facilitate trouble analysis for the printed circuit board. <P>SOLUTION: Pattern information generated by a printed circuit board diagnostic program, test program information and test jig production information are converted into data having the mutual relation to be correlated by the program, because they are single data respectively, to be displayed on a display 3 using a trouble analyzer. A tester 5 detects a trouble portion when testing the printed circuit board 6. The trouble portion is expressed as numeral value on the display 3, it is input into the trouble analyzer to be compared with an external storage device 2, trouble analysis position information is acquired thereby, and it is graphically displayed on the display 3 to facilitate the trouble analysis. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a failure analysis device used for easily performing a failure analysis when performing a failure analysis on a printed circuit board.

  For example, Patent Literatures 1 to 3 disclose a display device of elements on a printed circuit board and a display means and an editing means relating to the interrelation of these elements.

  Also, Patent Document 3 discloses a display device that displays an element by determining the size of the symbol of the element.

JP-A-4-138574 JP-A-63-140594 JP-A-4-138574

  Patent Document 3 describes a method for displaying elements on a printed circuit board, but discusses a tester pin position, a method for displaying a test jig, and a means for displaying and editing a test program for components on the printed circuit board. Not. Further, the document does not specifically describe a method of associating a printed circuit board with a test jig or a tester pin used in a test.

For this reason, in order to easily analyze the failure of the printed circuit board, it is necessary to clarify the relationship between the printed circuit board, the tester pin position, and the test jig.

  Further, Patent Document 1 discloses a technique of displaying a pattern of a plurality of layers constituting one circuit board by overlapping each other. However, this publication also does not show the relationship between the board, the test jig, the test pins, and the like when testing the circuit board.

As described above, the conventional technology does not consider the relationship between the printed circuit board, the test jig, and the tester pin position when performing the failure analysis of the printed circuit board, and the man-hours involved in the failure analysis increase due to the intervention of the manual operation. It was a burden at the time of analysis.

SUMMARY OF THE INVENTION It is an object of the present invention to associate a printed circuit board, information on a mounted component of a circuit board used for a test, wiring pattern information on the board, and information on a jig with each other and display the information on a display.

  In order to achieve the above object, the information is developed into mounting information, pattern information, and a test jig information table of a corresponding printed circuit board, and is associated with each other.

  It also edits and displays information related to the corresponding printed circuit board for display on the display. At this time, when viewing the relationship between the surrounding test jig and the tester pin position, by giving a plurality of commands, the display is superimposed on the screen and the relationship can be easily seen.

  In addition, in order to make it easier to understand the relation when the information is superimposed, the information is color-coded for each information. It is necessary to develop information in tables in a meaningful form and connect all related information with pointers, etc., because it is an essential condition for software development and data management. In order to search.

  In order to easily understand the state of the test, it is most desirable to display it as a picture on a display.

  Further, when a plurality of pieces of information are displayed on a single display to see the relationship between them, it is necessary to perform coloring or the like so that each piece of information can be understood independently.

  In the printed circuit board failure analysis device of the present invention, the external storage device connected to the central processing unit stores mounting information of components to be mounted on the board, wiring pattern information, and tester jig information. Since they are individually provided and used in association with each other, the mounted component, component pin, and wiring pattern position can be searched from the number of the tester pin implanted in the jig, and failure analysis can be easily performed.

  The central processing unit has means for displaying only the relevant portion of the detected failure analysis information on the display, thereby facilitating the failure analysis.

  Further, it has a function of displaying a test program corresponding to a component in which a failure has occurred.

  Further, since the test jig, the tester pin position, and the pattern circuit diagram of the printed circuit board can be respectively displayed and displayed in different colors as required, there is an effect that the workability is improved.

  Hereinafter, an embodiment of the present invention will be described with reference to FIG.

  FIG. 1 is a diagram of a failure analysis apparatus constituting the present invention. This apparatus includes a CPU 1, an external storage device 2, a display 3, a printer 4, a tester 5 for a printed circuit board, a printed circuit board 6 to be tested, and a test circuit. It comprises a tool 7, a keyboard 8, and an internal storage device 9 of the CPU 1.

  The CPU 1 stores software used in the present invention in its internal storage device 9, and the software operates on the CPU 1. The operation method of the software is instructed on the display 3.

  The external storage device 2 stores mounting information and pattern information of the printed circuit board 6, a test program of the component 61, pin setting position information of the test jig 7, and wiring information as a wiring pattern.

  The error information when a failure occurs in the printed circuit board 6 is extracted by the tester 5, output to the display 3 as character information, and simultaneously output to the printer 4.

  The keyboard 8 indicates a mounting position name of a component to be searched, a tester pin number, and the like.

  FIG. 2 is a schematic diagram in which information on the test target printed circuit board 6 and tester pins is divided into mounting position information, pattern information, and tester pin information, and a configuration diagram of a test system that tests the printed circuit board 6. .

  When the data necessary for testing the printed circuit board 6 is finely divided, it can be divided into mounting position information, pattern information, and jig information, and each piece of information can be represented by the diagram shown in FIG. Here, the mounting position information includes the printed circuit board 6 and the component 61 to be mounted, the pattern information includes the wiring pattern 64 printed on the board, and the jig information includes the pin setting positions 73 and 74 of the jig. Having.

  FIG. 3 shows how the tester 5, the jig 7 and the substrate 6 are connected during the test.

  When testing the component 61 on the printed circuit board 6, the test device 51 of the tester 5 supplies the test pattern to the tester pin 52 via the supply line 53, and this signal is transmitted to the interface pin 71 on the jig 7. , From the interface pin 71 to the probe pin 73 via the wiring 72.

Since the probe pin 73 is in contact with the component pin 62 of the test target component 61, this signal is supplied to the component pin 62 to operate the component 61. The operation result of the component 61 is output to the component pin 63. This signal is received by the probe pin 74 and propagated to the interface pin 71 via the wiring 75. Since the interface pin 71 is in contact with the test pin 52, this signal can be transmitted to the test device 51 via the supply line 53. The test device 51 can confirm the validity of the component 61 by examining the relationship between the input signal and the output signal. If the result is not correct, the result is displayed on the display 3. Further, the pin setting position of the test jig 7 may be set not only on the component pin 62 but also on the through hole 65.

  FIG. 4 is a plan view of the jig viewed from below.

  The flat jig 7 has a printed board area 7a for mounting a board to be tested and a tester pin area 7b.

Tester pins (probe pins) 73 and 74 necessary for the circuit board to be tested are implanted in the printed circuit board area 7a based on the pin setting information by the NC device.

  Interface pins 71 are arranged in a matrix in the tester pin area 7b, and are connected to the tester pins 73 and 74 in the printed circuit board area 7a by wiring lines 72 and 75.

  The mounting position file 21 prepared in the external storage device 2 of the computer shown in FIG. 5 includes a mounting position name of the component 61 on the printed circuit board 6, its pin number, pin coordinates (XY coordinates), and tester pins used by the tester 5. Stores the number. The tester pin file 22 includes a tester pin number used in the tester 5, tester pin coordinates implanted in the tester pin area 7b, pin setting coordinates of a pin in the printed circuit board area 7a that contacts the printed circuit board 6, and a mounting position file. 21 is stored. The pattern file 23 stores, for each record, information on each line segment of a printed pattern between components of the printed circuit board 6. One print pattern is composed of a plurality of line segments, and by storing pattern information indicating the coordinates of the start point and end point of the line segment and the same number as a recognition number when one print pattern is formed by a plurality of line segments. Stores the same potential net number indicating that multiple records have the same print pattern, the pin set coordinates of the probe pins that contact the print pattern, the tester pin number used in tester 5, and the layer name on which the net is mounted are doing. The test program file 24 stores mounting information position name information of the component 61 on the printed circuit board 6 and a test program thereof.

The table 10 in the internal storage device 9 of the computer shown in FIG. 6 stores an operation instruction instructing a test display method. The table 11 stores the mounting position when the instruction of the display method is the mounting position. The table 12 stores the tester pin number when the display method instruction is a tester pin number. The table 13 stores the maximum XY coordinate and the minimum XY coordinate of the instruction when the instruction of the display method is the pin setting coordinate. The table 14 is a coordinate and a magnification serving as a reference point when the displayed drawing is enlarged or reduced. FIGS. 7 and 8 are screen images displayed on the display 3 of the failure analysis apparatus of the present invention. When an operation instruction is given with an arrow 31, an operation selection field 32 for specifying a mounting position, an operation selection field 33 for specifying a tester pin number, an operation selection field 34 for specifying a coordinate, and a command corresponding to the specified operation are specified. A command instruction area 35 and a message area 36 for displaying a test program and a netlist of the test target component are displayed. When the failure analysis is performed by the mounting position instruction, the mounting position operation selection field 32 is selected by the arrow 31 and the mounting position name is specified in the command specifying area 35. When performing the tester pin number designation, the tester pin number designation 33 is selected by the arrow 31 and the tester pin number is designated in the command designation area 35. In the case of performing the coordinate designation, the coordinate designation operation selection field 34 is selected by the arrow 31, and thereafter, the arrow 31 is designated on the printed circuit board 6.

  After the display of the failure analysis position is completed, the display 3 displays an operation selection column 37 for performing a failure analysis of another position, an operation selection column 38 for enlarging / reducing the displayed screen, and a magnification when performing enlargement / reduction. And an operation instruction column 39 for performing an end operation of the program. When performing a failure analysis at another position, the operation instruction column 37 is selected by the arrow 31. When performing enlargement or reduction, the operation instruction column 38 is selected with the arrow 31 and the magnification is instructed in the magnification instruction column 381. When terminating the failure analysis, the operation instruction column 39 is selected by the arrow 31.

  FIG. 9 is a flowchart of the embodiment of the present invention.

  When it is desired to acquire the component pin information of a certain component 61 on the printed circuit board 6, the pin information of the test jig 7 in contact with the component pin, and the tester pin information, the mounting position is designated. When it is desired to acquire the coordinates of one tester pin on the tester pin position, the pattern information with which the tester pin contacts, and the component pin information connected to the pattern, the tester pin number is specified. When it is desired to acquire the component pin information and the pattern information included in a certain area on the printed circuit board 6 and the pin information of the test jig 7 contacting the pattern and the tester pin information, the coordinates on the printed circuit board 6 are designated by the range. I do.

  First, the failure analysis device is operated, and the operation instruction input screen shown in FIG.

  Next, in a default magnification setting 200, a default value is set in the table 14 as a display magnification of the printed circuit board 6 displayed on the display 3. Hereinafter, when the image is displayed on the display 3, the display is performed in consideration of the magnification.

  Next, an operation selection field for selecting an operation method of the program is indicated by an arrow 31, and the operation instruction input unit 300 stores the operation instruction indicated by the arrow 31 in the operation instruction table 10.

  Next, when the operation instruction is the mounting position instruction in the operation instruction selecting unit 310, the process branches to the mounting position instruction processing 400. If the operation instruction is a tester pin number instruction, the process branches to tester pin number instruction processing 500. When the operation instruction is a coordinate instruction, the process branches to a coordinate instruction process 600.

  When the process branches to the mounting position instruction processing 400, the mounting position instruction 410 stores the mounting position name specified by the keyboard 8 in the mounting position table 11. The mounting position display 420 searches the record of the mounting position file 21 using the mounting position as a key, acquires the pin coordinates of the corresponding mounting position name, and displays it on the display 3. Further, in the tester pin coordinate display 430, the tester pin number of the mounting position file 21 is stored in the tester pin number table 12, and the record of the tester pin file 22 is searched using the tester pin number as a key. When the same tester pin number is found from the tester pin file 22, the tester pin coordinates and pin stand coordinates in the record are displayed on the display 3. Further, in the pattern information display 440, the record of the pattern file 23 is searched using the tester pin number stored in the tester pin number 12 as a key, and when the same tester pin number is found from the pattern file 23, one piece of pattern information is acquired from the record and the display 3 To be displayed. In the pattern file 23, when one pattern is represented by a plurality of records, the records of the same print pattern have the same potential net numbers, so the pattern information of all the records having the same potential net numbers match, Is displayed.

  In the test program information display 450, the record of the test program file 24 is searched using the mounting position name stored in the mounting position table 11 as a key, and the corresponding test program is displayed on the display 3. Thus, all information related to the mounting position name designated by the mounting position input 410 can be output to the display 3. The information to be displayed on the display 3 is a plurality of parts information, pattern information, and tester pin information, and it is not easy to understand if the display is performed in an overlapping manner. It can be easily understood.

  When the process branches to the tester pin number designating process 500, the process 510 stores the tester pin number designated by the keyboard 8 in the tester pin number table 12. The tester pin coordinate display 520 searches the tester pin file 22 using the tester pin number stored in the tester pin number table 12 as a key, and displays the tester pin coordinates of the tester pin number and the pin setting coordinates of the test jig 7 on the display 3. Further, in the pattern information display 530, the pattern file 23 is searched using the tester pin number stored in the tester pin number table 12 as a key, and when a record having the same tester pin number as the key is found, the pattern information of the record and the same The physical wiring information of the print pattern formed by synthesizing the pattern information of another record having the same potential net number as the potential net number is displayed on the display 3. Further, in the mounting position display 540, the record of the mounting position file 21 is searched by using the tester pin number stored in the tester pin number table 12 as a key, and when the same tester pin number is found, the component pin coordinates of the mounting position and the mounting position name are displayed. 3 is displayed. Thus, all information relating to the tester pin number designated by the tester pin number input 510 can be displayed on the display 3.

  When the process branches to the coordinate designation process 600, the coordinates input 610 acquires the coordinates of two points on the display 3 designated by the mouse, and distinguishes these coordinates into a maximum X coordinate, a maximum Y coordinate, a minimum X coordinate, and a minimum Y coordinate. It is stored in the pin setting coordinate table 13. Thereby, the range of the rectangular area is specified. The pattern information display 620 searches the pattern file 23 including the pin setting position of the test jig 7 in this range, and displays the pattern information of the pattern in this range and the pin setting coordinates of the test jig 7 on the display 3. I do. Further, the tester pin number of the pattern file 23 is stored in the tester pin number table 12 in the tester pin coordinate display 630, and a record of the tester pin file 22 is searched using the tester pin number as a key. The tester pin coordinates and the pin setting coordinates of the test jig 7 are displayed on the display 3.

  Further, in the mounting position display 640, the component pin coordinates of the record of the mounting position file 21 indicated by the mounting position record pointer of the tester pin file 22 are displayed on the display 3. As a result, all information relating to the pattern within the coordinates designated in the range by the coordinate input can be output to the display 3.

  In the next processing selection instruction wait 700, the screen display processing is not performed until there is an operation instruction to be performed next. When the next operation instruction is generated, the process proceeds to the next processing selection instruction input unit 750.

  In the next process selection instruction input unit 750, the operation selection column 37 is instructed when the next process wants to refer to another position, and the operation selection column 38 is instructed in order to enlarge or reduce the size, and the program ends. When making a selection, the operation selection field 39 is indicated by an arrow 31. The operation instruction indicated by the arrow is stored in the operation instruction table 10.

  In the next process selection 800, the operation instruction stored in the operation instruction table 10 branches to one of the reference to another position 900, enlargement / reduction 1000, and end of program 1100.

  When another position is branched to the reference 900, the display 3 is cleared and another information is acquired by executing the program again from the operation instruction input screen display 100.

  In the case of branching to enlargement / reduction 1000, the reference point of the drawing to be enlarged / reduced is designated by the mouse with the position / magnification instruction 1200, and the magnification is designated from the keyboard 8.

In the magnification change 1300, a magnification that can be calculated by multiplying the designated magnification by the magnification stored in the table 14 is stored in the table 14 again. As a result, when redisplay is performed, the image is displayed at the new magnification. In this state, the process proceeds to the operation instruction selection unit 310, and the processes 400, 500, and 600 are selected again from the operation instructions already stored in the operation instruction table 10, and the process branches. When displaying a picture on the display 3 during this processing, the image is converted into coordinates in consideration of a reference point and a magnification and output.

  When branching to the program end 1100, the display 3 is cleared and the program ends.

FIG. 1 is a system configuration diagram for realizing the present invention. FIG. 3 is a schematic diagram in a case where pin setting information of a printed circuit board and a test jig is divided into mounting position information, pattern information, and pin setting information of a test jig. FIG. 1 is a configuration diagram of a test system for testing a printed circuit board. The bottom view of the jig of a tester. FIG. 4 is a file-related diagram used in the present invention. FIG. 3 is a table diagram used in the present invention. FIG. 4 is a screen image diagram displayed according to the present invention. FIG. 4 is a screen image diagram displayed according to the present invention. FIG. 4 is a processing flowchart of the present invention.

Explanation of reference numerals

1 CPU
2 External storage device 3 Display 4 Printer 5 Tester 6 Printed circuit board 61 Mounting parts 7 Test jig 8 Keyboard 9 Internal storage device 10 Operation instruction table 11 Mounting position table 12 Tester pin number table 13 Pin stand coordinate table 14 For enlargement / reduction processing Table 21 Mounting position file 22 Tester pin file 23 Pattern file 24 Test program file

Claims (1)

A failure analysis device for the printed circuit board connected to a tester that sends a test pattern signal to a terminal of a component mounted on the printed circuit board and detects a failure of the printed circuit board,
From the tester, receiving means for receiving information on the failure detected by the tester,
Display means for displaying a failure location of the printed circuit board detected by the tester,
Input means for inputting an instruction for displaying a failure location of the printed circuit board on the display means,
Storage means for storing information of components mounted on the printed circuit board, information of a wiring pattern of the printed circuit board, and jig information of the tester,
The output unit, the input unit, and a control unit for controlling each of the storage unit,
The control means, upon receiving from the input means an instruction to display the fault location of the printed circuit board on the display means, receives the instruction, each information stored in the storage means, and the reception means. The failure location of the printed circuit board is displayed on the display means based on the information on the failure, and the failure location of the printed circuit board displayed on the display means is enlarged or enlarged from the input means. Control means for controlling, when receiving an instruction to reduce the size of the printed circuit board, to display the failed portion of the printed circuit board in a size based on the instruction.

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