JP2004289326A - Optical signal transmitter for performing speed conversion processing of frame signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmission side apparatus and a reception side apparatus for a frame signal in an optical signal transmission system capable of performing data speed conversion processing flexibly coping with diversified FEC frame configurations. <P>SOLUTION: The transmission side apparatus for a frame signal in the optical signal transmission system includes: a speed conversion memory capable of simultaneously carrying out write and read; a write control section for outputting a write address; a read control section for outputting a read address; a frame generating section for adding a header and an error correction code to main signal data read from the speed conversion memory to generate the frame signal; a staff discrimination circuit for comparing the write address with the read address, obtains a residual capacity of the speed conversion memory, and discriminating the necessity of a staff operation with respect to the frame signal generated by the frame generating section; and a self-running oscillator. Then the frame generating section inserts presence/no presence information of the staff operation to the header of the frame signal according to a discrimination output of the staff discrimination circuit, and the read control section outputs the read address corresponding to a clock outputted from the self-running oscillator. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transmitting-side device and a receiving-side device that perform frame signal speed conversion processing in an optical signal transmission system. In particular, the present invention relates to a speed conversion method for a frame signal when a high-speed frame signal is formed by adding a check bit enabling error correction on the receiving side to the low-speed frame signal.
[0002]
[Prior art]
In recent years, in an optical signal transmission system, while an error correction function (FEC: Forward Error Correction) has been improved, a frame (hereinafter, referred to as an FEC frame) having a diversified error correction function has been flexibly supported and input. There is a demand for a clock transfer method (stuff control method) that enables data speed conversion processing without being dependently synchronized with a clock on the side.
[0003]
As a method of the speed conversion processing, there is a method of synchronizing an output clock frequency with an input clock frequency when constructing an FEC frame (hereinafter referred to as dependent synchronization) (for example, see Patent Document 1).
[0004]
FIG. 1 shows a conventional optical signal transmission system employing a clock transfer method, and is a diagram showing a conceptual configuration similar to the configuration described in Patent Document 1. The operation of the clock transfer method will be described below with reference to FIG.
[0005]
In FIG. 1, a received optical signal is converted into an electrical signal by an optical / electrical converter (not shown), and an SDH signal (SDH Frame: SDH frame) and a line clock signal (SDH Line CLK) are obtained.
[0006]
The SDH signal is input to the SDH termination circuit 1 in synchronization with the line clock signal, where processing such as SDH frame synchronization detection and overhead (OH) termination is performed. The output of the SDH termination circuit 1 is written to the speed conversion memory 2 by a line clock signal.
[0007]
On the other hand, a clock oscillator 3 is provided in the optical signal transmission system, and an SDH signal is read from the speed conversion memory 2 by a read clock signal output from the clock oscillator 3. At this time, if the read clock signal is faster than the line clock signal, low-speed / high-speed conversion is performed.
[0008]
Further, in order to synchronize the read clock signal with the line clock signal, the line clock signal is divided into 1 / n by the 1 / n frequency divider 4 and the read clock signal is divided by the 1 / m frequency divider 4 into 1 / m. And the phase difference is obtained by the phase comparator 6.
[0009]
Next, the phase difference output of the phase comparator 6 is input to the clock oscillator 3. The clock oscillator 3 performs a frequency shift corresponding to the magnitude of the input phase difference with respect to the output frequency. As a result, the speed-converted SDH signal is read from the speed conversion memory 2 by the read clock signal that is dependently synchronized with the line clock signal.
[0010]
The SDH signal read from the speed conversion memory 2 is further input to an FEC frame generation unit 7, where it is formed into an FEC frame to which an overhead OH and an error correction check bit ECC are added, and output. The FEC frame is further converted into an optical signal by an electric / optical converter (not shown), and sent out to the next optical signal transmission system.
[0011]
[Patent Document 1]
JP-A-5-37482
[0012]
[Problems to be solved by the invention]
In such subordinate synchronization, the following failures are pointed out due to abnormal optical input signals.
[0013]
First, due to the deterioration of the level of the optical input signal, clock extraction cannot be performed satisfactorily in the optical / electrical converter, causing a problem that the extracted clock frequency is largely shifted. In order to prevent this problem, a countermeasure is taken by detecting disconnection of an optical input signal or detecting loss of frame synchronization of SDH (Synchronous Digital Hierarchy) / SONET (Synchronous Optical Network) and switching to a self-running clock in the device. .
[0014]
However, during the period until the detection of an alarm for the loss of frame synchronization, an operation dependent on a clock having a frequency shift extracted from the line is performed. As a result, in the clock transfer circuit in the device, clock synchronization is lost, the transmission speed of the device output becomes unstable, and a clock extraction error occurs on the receiving side, leading to main signal error occurrence and frame loss. Fear was present.
[0015]
In addition, since the memory for speed conversion becomes uncontrollable due to the loss of clock synchronization, it is necessary to initialize the memory and the control circuit when restoring the optical signal. This means that the time from the recovery of the optical signal to the normal operation of the device requires the same time as the initial startup of the device every time. It was causing stretching.
[0016]
Accordingly, an object of the present invention is to be able to flexibly cope with FEC frame configurations that will be diversified in the future, and to enable data rate conversion processing without being dependently synchronized (affected) by an input side clock signal. It is an object of the present invention to provide an apparatus for transmitting and receiving a frame signal in an optical signal transmission system.
[0017]
[Means for Solving the Problems]
A first aspect of a frame signal transmitting apparatus according to the present invention that achieves the above object is a frame signal transmitting apparatus in an optical signal transmission system, wherein a speed conversion memory capable of simultaneously writing and reading is provided; A write control unit that outputs a write address for writing main signal data to the conversion memory; a read control unit that outputs a read address for reading the main signal data from the speed conversion memory; and the speed conversion memory The main signal data read from the header, a frame generation unit that adds an error correction code to generate a frame signal, and compares the write address and the read address output from the write control unit and the read control unit, The remaining amount of the speed conversion memory is obtained, and the frame signal generated by the frame A stuff determination circuit that determines whether or not stuff operation is necessary, and further includes a free-running oscillator, and the frame generation unit displays stuff operation presence / absence information in a header of the frame signal according to a determination output of the stuff determination circuit. The read control unit inserts the read address in response to a clock output from the free-running oscillator.
[0018]
Further, in a second aspect of the frame signal transmitting apparatus according to the present invention for achieving the above object, in the first aspect, the stuff determination circuit comprises a maximum capacity and a maximum remaining amount transition value of the speed conversion memory. And a minus direction threshold is provided between the zero capacity of the speed conversion memory and the minimum remaining amount transition position, and the remaining amount of the speed conversion memory exceeds the plus direction threshold. A transmitting apparatus for transmitting a frame signal, wherein the stuff is controlled so as to increase the stuff when it is lower than the negative threshold value.
[0019]
According to a third aspect of the frame signal transmitting apparatus according to the present invention for achieving the above object, in the second aspect, the stuff determination circuit further comprises a maximum capacity of the speed conversion memory, the + direction threshold, The alarm threshold is provided between the zero capacity of the speed conversion memory and the negative direction threshold, and the remaining amount of the speed conversion memory exceeds the positive alarm threshold. And outputting an alarm when the time is equal to or less than the -direction alarm threshold.
[0020]
According to a fourth aspect of the frame signal transmitting apparatus according to the present invention for achieving the above object, in the third aspect, when the stuff determination circuit outputs an alarm, the frame generation unit outputs the frame signal. Is not inserted in the header of the stuff operation.
[0021]
Further, a fifth aspect of the frame signal transmitting apparatus according to the present invention for achieving the above object is the first aspect, wherein in the initial state, the write address in the write control unit is changed to the maximum capacity of the speed conversion memory in the initial state. , And the read address in the read control unit is an address corresponding to the position of the capacity 0 of the speed conversion memory.
[0022]
A sixth aspect of the frame signal transmitting apparatus according to the present invention that achieves the above object, according to the first aspect, further includes a random pattern generator and a write address monitoring unit. Until the write address monitoring unit detects that all the addresses of the speed conversion memory have completed writing of the main signal data, the random pattern generated by the random pattern generator is changed to the main signal data and output. It is characterized by the following.
[0023]
A seventh aspect of the apparatus for transmitting a frame signal according to the present invention that achieves the above object is the sixth aspect, further comprising a monitoring unit for restoring an alarm state of the input line, wherein the monitoring unit detects an alarm state. When the recovery is detected, the random pattern generated by the random pattern generator is not changed until the write address monitoring unit detects that all the addresses of the speed conversion memory have completed writing the main signal data. It is characterized in that it is output in place of the main signal data.
[0024]
A first aspect of a frame signal receiving apparatus according to the present invention that achieves the above object is a frame signal receiving apparatus in an optical signal transmission system, wherein a speed conversion memory capable of simultaneously writing and reading is provided; A write control unit that outputs a write clock for writing a frame signal to the conversion memory; a read control unit that outputs a read clock for reading a frame signal from the speed conversion memory; and the write control unit and the read control unit A phase comparator for calculating a phase difference between a write clock and a read clock output from the oscillator, and an oscillator whose oscillation frequency is controlled to be changed according to the output of the phase comparator. A clock having a frequency corresponding to the output is output.
[0025]
Further, a second aspect of the frame signal receiving device according to the present invention that achieves the above object, in the aspect of the first receiving device, further includes a random pattern generator and a write address monitoring unit, In the initial state, a random pattern generated by the random pattern generator is used as the main signal data until the write address monitoring unit detects that all addresses of the speed conversion memory have completed writing of the main signal data. It is characterized by changing and outputting.
[0026]
Further, a third aspect of the frame signal receiving apparatus according to the present invention that achieves the above object, in the aspect of the second receiving apparatus, further includes an alarm state recovery monitoring unit for the input line, When detecting that the alarm state has been restored by the monitoring unit, the random pattern generator continues until the write address monitoring unit detects that all the addresses of the speed conversion memory have completed writing the main signal data. It is characterized in that the generated random pattern is converted into the main signal data and output.
[0027]
The features of the present invention will become more apparent from the embodiments of the present invention in accordance with the drawings.
[0028]
Embodiments of the present invention
An embodiment of the present invention will be described below with reference to the drawings. The embodiments described below are shown for understanding the present invention, and the application of the present invention is not limited thereto.
[0029]
FIG. 2 is a block diagram of a configuration example of an optical signal transmission system to which the transmission frame speed conversion processing method according to the present invention is applied. FIG. 2A shows the configuration of the FEC frame transmitting station side, and FIG. 2B shows the configuration of the FEC frame receiving station side. FIG. The FEC frame transmitting station and the FEC frame receiving station are connected by an optical transmission line (not shown).
[0030]
In the transmitting station shown in FIG. 2A in which the input side is connected to an SDH network (not shown), the data rate of the SDH signal is reduced to a rate that can be processed by the serial / parallel conversion circuit 21 and is input to the SDH termination unit 22. The SDH termination unit 22 detects an SDH frame synchronization signal of the SDH signal and performs an overhead termination.
[0031]
The output of the SDH termination unit 22 is input to a FIFO memory 23 that performs speed conversion from the SDH frame to the FEC frame, and is stored in the FIFO memory 23 under the write control of the write control unit 24.
[0032]
Here, in the embodiment of FIG. 2, the FIFO memory 23 (35) is used as a memory for performing the speed conversion on the transmitting station side (FIG. 2A) and the receiving station side (FIG. 2B). Is not limited to this as long as it is a memory that can be used simultaneously. The same applies to the following embodiments.
[0033]
The SDH frame stored in the FIFO memory 23 is read by the read control unit 25 and input to the FEC frame generation unit 26. The remaining amount of the FIFO memory 23 is detected by the FIFO remaining amount calculation unit 27 based on the phase difference between the write address from the write control unit 24 to the FIFO memory 23 and the read address from the read control unit 25.
[0034]
The stuff determining unit 28 determines whether a stuff operation is necessary based on the remaining amount of the FIFO memory 23 detected by the FIFO remaining amount calculating unit 27. The main signal data of the SDH frame read from the FIFO memory 23 and input to the FEC frame generation unit 26 is multiplexed here.
[0035]
Also, the result of the stuff operation is inserted into the FEC overhead, and an FEC frame is generated. According to the generated clock from the FEC frame output side clock source (OSC) 29, the signal is converted into a serial signal by the parallel / serial conversion circuit 30 and output.
[0036]
As described above, on the FEC frame transmitting side, the remaining amount of the speed conversion FIFO memory 23 is monitored by the FIFO remaining amount calculation unit 27, and the stuff determination unit 28 adjusts the output rate via the read control unit 25. .
[0037]
This makes it possible to avoid the problem that the output side clock follows the input clock.
[0038]
Here, the FEC frame generated by the FEC frame generation unit 26 will be described. FIG. 3 shows a configuration example of the FEC frame. FIG. 3A shows a frame configuration in which the configuration of the FEC frame generated by the FEC frame generation unit 26 is converted into a serial signal by the parallel / serial conversion circuit 30. . An error correction check bit II and an FEC overhead (OH) III are added to the SDH data (9.95 Gbps) I, and the serial data of 12.02 Gbps is output from the parallel / serial conversion circuit 30.
[0039]
The output of the parallel / serial conversion circuit 30 is converted into an optical signal and transmitted to a receiving station through an optical transmission path.
[0040]
In the receiving station shown in FIG. 2B, the received optical signal is converted into an electric signal, and then converted into a parallel signal by a serial / parallel converter 31 to facilitate the subsequent processing. As an example, the serial data of 12.02 Gbps shown in FIG. 3A is parallel-converted as shown in FIG. 3B, and the speed is reduced to 93.92 MHz.
[0041]
Thus, the FEC frame whose speed has been reduced by the serial / parallel converter 31 is input to the FEC frame termination unit 32. Here, synchronization detection of the FEC frame, termination of the FEC overhead, separation of the main signal, and the like are performed.
[0042]
The stuff detector 33 detects the presence or absence of a stuff operation on the FEC frame transmitting side from the FEC overhead of the received FEC frame. In accordance with the result of the presence / absence detection of the presence / absence of the stuff operation by the stuff detection unit 33, the increase / decrease of the number of times the write control unit 34 writes the received FEC frame into the FIFO memory 35 is controlled.
[0043]
The phase comparator 36 compares the phase (frequency) between the input clock of the FIFO memory 35 and the transmission side clock.
[0044]
The output-side clock oscillator voltage-controlled oscillator 37 is constituted by a voltage-controlled oscillator, and serves as an output-side clock source on the FEC frame receiving station side. The read clock of the read control unit 38 is controlled by increasing or decreasing the clock frequency corresponding to the phase difference output of the phase comparator 36.
[0045]
Next, the FEC frame output from the FIFO memory 35 is subjected to SDH frame synchronization detection by the SDH frame generation unit 39, the overhead OH is inserted, and the SDH frame is generated. The SDH frame generated by the SDH frame generation unit 39 is converted into a serial signal by the parallel / serial converter 40 and sent out to the connected SDH network.
[0046]
[FEC frame transmission side operation]
Next, FIG. 4 shows a specific embodiment of the configuration of the transmitting station for generating and transmitting the FEC frame in FIG. 2A, and the operation will be described in stages.
[0047]
FIG. 4 shows only the main part configuration of FIG. 2A, and a dual-port (DP) -RAM is used as the FIFO memory 23 in FIG. 2A. Further, in FIG. 4, the FIFO remaining amount calculation unit 27 and the stuff determination unit 28 in FIG. 2A are integrally shown as a stuff determination circuit 270.
[0048]
On the other hand, the FEC frame generation unit 26 in FIG. 2A includes an FEC frame generation circuit 261 and an FEC overhead insertion circuit 262 in FIG.
[0049]
In FIG. 4, iCLK78M is a 77.76 MHz clock obtained by dividing the frequency of the SDH line clock. oCLK94M is a 93.92 MHz clock obtained by dividing the frequency of the FEC frame transmission clock.
[0050]
(1) Read / write control of FIFO memory 23
The main signal data after the termination processing in the SDH termination unit 22 is multiplexed into the FEC frame by using the FIFO memory 23. Here, the capacity of the FIFO memory 23 has a main signal data amount of FEC × 1 frame (= 1848 words / 128 bits).
[0051]
The 128 bits of the main signal data are written to the speed conversion FIFO memory 23 with the iCLK78M clock, and the read control unit 25 reads data from the FIFO memory 23 based on the oCLK94M clock in accordance with the data insertion timing signal from the FEC frame generation circuit 261.
[0052]
Here, FIG. 5 is a diagram showing a main signal multiplex position (stuff area). When a stuff area increase (+) request is input from the stuff determination circuit 270, as shown in FIG. 5B showing the main signal data multiplexing position (stuff area), the FIFO memory 23 at the timing of the stuff (+) area a. Is added. Conversely, when the stuff area decrease (-) request is input, as shown in FIG. 5C, the read operation of the FIFO memory 23 is stopped at the timing of the stuff (-) area b. FIG. 5A shows a case without staff.
[0053]
(2) Staff judgment
Both are address counters, and a write (write) address and a read (read) address of the FIFO memory 23 are output from a write control unit 24 and a read control unit 25 each composed of a 1848 (d) counter. The stuff determination circuit 270 monitors the remaining memory of the FIFO memory 23 based on the write address and the read address output from the write control unit 24 and the read control unit 25.
[0054]
If the FIFO memory 23 is likely to overflow, a stuff (+) request is output. If the FIFO memory 23 is likely to underflow, a stuff (-) request is output to the read control unit 25 and the FEC overhead (OH) insertion circuit 262 to determine whether a stuff operation is performed. I do.
[0055]
In the initial state, since the FIFO memory 23 underflows, a stuff (-) request frequently occurs. However, by repeating the stuff operation, the read / write address (remaining amount) for the FIFO memory 23 shifts to an optimum position. The output data rate is naturally stabilized.
[0056]
In the write / read control of the FEC frame transmission-side speed conversion FIFO memory 23, the initial values of the address counters of the write control unit 24 and the read control unit 25 are set to '924' (d) and '0' (d), respectively. By doing so, it is possible to avoid a stuff operation that frequently occurs in the initial state, and the data output rate can be instantaneously stabilized.
[0057]
(3) FEC frame generation
The timing signal of the main signal data area shown in FIG. The main signal data read from the address of the FIFO memory 23 supplied to the read control unit 25 in synchronization with this timing signal is multiplexed as it is and sent to the FEC overhead insertion circuit 262.
[0058]
(4) Insert FEC overhead
The information on the presence or absence of the stuff operation from the stuff determination circuit 270 is inserted into the overhead area (FEC OH) of the FEC frame shown in FIG. 5 and is notified to the opposite receiving station side. Further, insertion of other FEC frame synchronization detection overhead and the like is also performed, but details thereof will not be described because they are not directly related to the present invention.
[0059]
[FEC frame receiving side operation]
Next, a specific embodiment of the configuration of the receiving station that receives the FEC frame in FIG. 2B is shown in FIG. 6, and the operation will be described in stages.
[0060]
6, the FEC frame termination unit 32 in FIG. 2B includes an FEC frame synchronization detection unit 320, an FEC overhead extraction unit 321, and a frame conversion memory 323, as compared with the configuration in FIG. 2B.
[0061]
In FIG. 6, iCLK94M is a 93.92 MHz clock obtained by dividing the FEC frame reception (line) clock. oCLK78M is a 77.76 MHz clock obtained by dividing the frequency of the SDH frame transmission side clock (VCXO).
[0062]
(1) FEC frame synchronization detection and data error correction
The synchronization detection overhead in the received FEC frame is detected by the FEC frame synchronization detection unit 320, and the synchronization of the FEC frame is established. After synchronization is established by the FEC frame synchronization detection unit 320, error correction of main signal data is further performed using various check bits. The means and method of error correction are not directly related to the present invention and will not be described in detail.
[0063]
FIG. 7 shows the data format after error correction. The FEC overhead timing signal and the main signal data timing signal obtained from the frame after the error correction are output to the FEC overhead extraction unit 321 and the write control unit 324 of the frame conversion memory 323, respectively.
[0064]
(2) FEC overhead extraction
The stuff information is extracted based on the FEC overhead timing signal provided from the frame synchronization detection unit 320, and the presence or absence of a stuff operation on the FEC frame transmitting side is detected.
[0065]
The detection result of the presence / absence of the stuff operation is output to the write control unit 324 and the smoothing processing unit 325 of the frame conversion memory 323.
[0066]
(3) Smoothing of main signal data
The smoothing processing unit 325 smoothes the main signal data shown in the data format shown in FIG. 7, that is, the SDH signal into data having an average of 78 Mbps. This smoothing process is for causing the clock on the transmission side to follow the stuff operation.
[0067]
For smoothing the main signal data, a frame conversion memory 323 (having a capacity of 512 words / 128 bits as an embodiment) is used. FIG. 8 is a diagram illustrating smoothing.
[0068]
As shown in FIG. 8, the write control unit 324 converts the main signal data (2) based on the main signal data timing signal (1) from the FEC frame synchronization detection unit 320 and the stuff information from the FEC overhead extraction unit 321. The data is written to the frame conversion memory 323 in units of 128 bits. At this time, the main signal data timing signal {circle around (1)} fluctuates by ± 1 clock CLK in accordance with the stuff (+) / (−) operation.
[0069]
When the stuff (+) is detected, the stuff (+) data a shown in FIG. 7 is also written in the frame conversion memory 323, and when the stuff (-) is detected, the stuff (-) data b is not written.
[0070]
On the other hand, reading from the frame conversion memory 323 is output by the read control unit 326. This is performed by the read enable signal (3) shown in FIG. At this time, the read enable signal {circle around (3)} has an average cycle of 78 Mbps (hereinafter referred to as Ave78M signal), and therefore, the main signal data is read out as read data {4} distributed evenly.
[0071]
By the writing and reading control to the frame conversion memory 323, the remaining amount of the frame conversion memory 323 changes as shown in FIG. In FIG. 9, writing and reading are performed during a period T1, and only reading is performed during a period T2.
[0072]
(4) Read / write processing of speed conversion FIFO memory
The speed of the smoothed main signal data is converted to a 77.76 Mbps SDH frame using the FIFO memory 35. Here, as the capacity of the FIFO memory 35, a main signal data amount (= 1848 words / 128 bits) for one frame of FEC is used as an embodiment.
[0073]
The 128-bit main signal data read from the frame conversion memory 323 by the Ave78M signal is written as it is to the FIFO memory 35 by the write control unit 34 based on the iCLK94M clock. On the other hand, the read control unit 38 reads and controls the FIFO memory 35 based on the oCLK78M clock.
[0074]
Both the write address counter 341 and the read address counter 381 are composed of 1848 (d) counters. When the write / read addresses of the write address counter 341 and the read address counter 381 are both “0” (d), a pulse for phase comparison between the input clock and the output clock is generated and output to the phase comparator 36.
[0075]
(5) Phase comparison control
The phase comparator 36 inputs the phase comparison pulses from the write control unit 34 and the read control unit 35 by dividing them by １ ／, and compares the phases of the input clock and the output clock. FIG. 10 is a diagram showing a time chart of the phase comparison in the phase comparator 36.
[0076]
The phase comparison pulse is generated from the write / read address of the FIFO memory 35. For this reason, the cycle differs depending on the presence or absence of the stuff operation.
[0077]
Here, in the VCXO 37 which is the clock source on the receiving side, the frequency is adjusted so that the phase comparison result becomes 50% of the duty (Duty).
[0078]
In the initial state, the duty value of the phase comparison result is lost because the counter values of the write address counter 341 and the read address counter 381 are substantially equal, but the frequency adjustment is performed by the VCXO 37 as needed. Duty is naturally optimized.
[0079]
Thereafter, the clock frequency on the output side becomes stable. Similarly, at the time of the stuff operation, the duty of the phase comparison result fluctuates, so that the frequency control of the VCXO 37 operates, whereby the output clock follows the stuff operation.
[0080]
FIG. 11 is a diagram showing an example configuration of the stuff determination processing unit 270 in the configuration of the transmitting station shown in FIG. As a feature, a staff determination threshold is provided.
[0081]
That is, the remaining amount remaining circuit 271 for calculating the remaining amount of the FIFO memory 23 from the FIFO write address and the FIFO read address, the stuff (+) setting threshold 272, the stuff (-) setting threshold 273, and the remaining amount remaining circuit 271 are used. Comparing circuits 274 and 275 are provided for comparing the calculated remaining amount with the stuff (+) setting threshold 272 and the stuff (-) setting threshold 273, respectively. With this configuration, a stuff (+) request is output when the value exceeds the + setting threshold, and a stuff (−) request is output when the value falls below the −setting threshold.
[0082]
FIG. 12 is a diagram showing the relationship between the change in the remaining amount of FIFO and the staff threshold, which is obtained by the operation of the staff determination processing unit 270 in FIG.
[0083]
The stuff + setting threshold is set between the maximum transition value (1) of the FIFO memory 23 and 1848 words (physical quantity of the FIFO memory 23), and the stuff (-) setting threshold is the minimum transition value of the FIFO memory 23 from 0 word (2). Set between. This makes it possible to cope with local fluctuations in the amount of input data.
[0084]
FIG. 13 is a diagram showing the configuration of another embodiment of the staff determination processing unit 270. As a feature, a stuff (+) alarm threshold 276 and a stuff (-) alarm threshold 277 are further provided, and the stuff (+) alarm threshold 276 and the stuff (-) alarm threshold 277 are compared with the FIFO remaining amount by comparison circuits 278 and 279. Like that.
[0085]
As a result of the comparison, a stuff (+) alarm is output when the FIFO remaining amount exceeds the stuff (+) alarm threshold 276, and a stuff (-) alarm is output when the FIFO remaining amount falls below. Thereby, it is possible to detect local data fluctuation on the input side.
[0086]
In this case, information (notification) indicating that the stuff operation has been performed, which is normally written in the overhead, is not included in the overhead. As a result, it is possible to prevent a reaction on the receiving side and prevent the hand shooter from performing.
[0087]
FIG. 14 is a diagram showing the relationship between the change in the remaining amount of FIFO and the staff threshold obtained by the operation of the stuff determination processing unit 270 in FIG.
[0088]
The staff (+) alarm threshold 276 is set to a question between the staff (+) threshold (1) and 1848 words, and the staff (-) alarm threshold 277 is set between O word and the staff (-) threshold (2). Thus, it is possible to detect that the actual input data fluctuation amount is a larger fluctuation amount than the fluctuation predicted in advance.
[0089]
Here, the effect of preventing the reaction on the receiving side so as not to perform the hand shooter using the configuration of the embodiment of FIG. 13 will be described with reference to FIG.
In the configuration of FIG. 13, a stuff operation frequently occurs when a stuff alarm is detected. When stuff occurs due to such an abnormal state on the input side, by stopping the stuff information (FEC overhead) notified to the opposite side, it is possible to prevent the FEC frame receiving side from following the stuff operation on the transmitting side.
[0090]
In FIG. 15, the stuff operation is repeated due to an abnormality on the input side (A), so that the output data rate on the FEC frame transmission side becomes abnormal. At this time, a stuff alarm is detected (B). However, the notification of the staff information is inhibited (C). As a result, the stuff information is not detected on the FEC frame receiving side (D), and the data destuffing operation is not performed. Therefore, VCXO, which is an output clock source on the FEC frame receiving side, is in a stable state without being affected by the FEC frame transmitting side (E).
[0091]
When such processing is performed, data loss occurs without performing data destuffing operation on the FEC frame receiving side. However, since the FEC frame transmitting side has already lost data due to an input error on the FEC frame transmitting side, the problem is that there is no problem. No.
[0092]
Here, in the read / write control of the FIFO for speed conversion on the FEC frame transmission side, when an input line alarm (clock cutoff, etc.) occurs, the optimal positional relationship between the write address counter and the read address counter is broken.
[0093]
Normally, even in this state, optimization is naturally performed by repeating the staff operation after the line alarm is restored.
[0094]
However, a great amount of time is required for the optimization, and during that time, the data output rate is also unstable. Therefore, when the line alarm is restored, the write address counter and the read address counter for the FIFO memory 23 are initialized, and their initial values are set to '924' (d) and 'O' (d), respectively, as shown in FIG. By doing so, it becomes possible to stabilize the data output rate instantaneously.
[0095]
Here, there is a system that is required to be dependent synchronization other than independent synchronization as an SDH network. FIG. 16 is a block diagram of an embodiment on the FEC frame transmitting side in which independent synchronization and dependent synchronization coexist in response to the requirements of such a system. 16, the FIFO memory 23, the write control unit 24, the read control unit 25, the stuff determination unit 270, the FEC frame generation unit 261 and the FEC overhead insertion unit 262 are the same as those described in FIG. I do.
[0096]
In FIG. 16, the selector (SEL1) 300 switches the write clock of the speed conversion FIFO memory 23. Normally, iCLK78M obtained from the received SDH frame is selected, and when a line alarm occurs, the clock frequency is switched to 77.78 MHz from the free-running reference clock oscillator (0SC) 301 in the own station.
[0097]
The decoder (DEC'158 '(d)) 302 detects the write address (=' 158 '(d)) of the FIFO memory 23 from the write control unit 24. The decoder (DEC'0 '(d)) 303 detects the read address (=' O '(d)) of the FIFO memory 23 from the read control unit 25.
[0098]
The first phase comparator 304 transmits an input clock and a transmission clock based on the write address (= '158' (d)) and the read address (= 'O' (d)) from the decoders 302 and 303 of the FIFO memory 23. Performs phase comparison with the side clock.
[0099]
The first frequency divider (1 / x) 305 divides the frequency of the clock 77.78 MHz from the free-running reference clock oscillator 301 into 1 / x. Further, the second frequency dividing circuit (1 / y) 306 further converts the clock obtained by dividing the clock from the output side clock source (VCXO) 307 by the third frequency dividing circuit (1 / n) 308 by 1 / n. Divide by 1 / y.
[0100]
The second phase comparator 309 compares the phases of the output clocks of the first frequency divider 305 and the second frequency divider 306. The second selector (SEL2) 310 selects the comparison result of the first phase comparator 304 and the second phase comparator 309 and outputs the result to the output clock source (VCXO) 307. The output clock source (VCXO) 307 performs frequency control based on the phase comparison result input from the second selector (SEL2) 310.
[0101]
Further, in FIG. 16, iCLK78M is a 77.76 MHz clock obtained by dividing the SDH line clock, and oCLK94M is a 93.92 MHz clock obtained by dividing the output of the transmission side clock source (VCX0) 307 by 1 / n.
[0102]
A voltage-controlled oscillator is used as the output side clock source (VCXO) 307, and the speed conversion unit is provided with a speed conversion circuit using a FIFO memory and a phase comparison control circuit in the same manner as the FEC frame receiving side configuration in FIG. In addition, it is possible to easily realize the dependent synchronization system in parallel with the independent synchronization.
[0103]
Hereinafter, the operation of the embodiment of FIG. 16 will be described in detail.
[0104]
(1) Speed conversion processing by staff operation
Also in this embodiment, the speed of data is converted by the stuff operation. However, here, a voltage controlled oscillator (VCXO) is used as the output side clock source 307, and the second phase comparator 309 uses the 1 / x frequency-divided clock and the oCLK94M clock of the free-running clock oscillator (OSC) 301 in the device. The phase is compared with the 1 / y frequency-divided clock, and is output to the output side clock source 307 through the second selector 310. In the output side clock source 307, frequency control is performed based on the comparison result of the second phase comparator 309.
[0105]
(2) Dependent synchronous operation
Similarly to the stuffing method, the main signal data is written to the speed conversion FIFO memory 23 by the iCLK78M clock, and the reading from the FIFO memory 23 is controlled by the oCLK94M clock.
[0106]
However, with respect to the write clock in the write control to the FIFO memory 23, the first selector 300 switches to the free-running oscillator (OSC) 301 when a line alarm is detected.
[0107]
Regardless of whether the first selector 300 switches the clock or not, when the read / write address of the FIFO memory 23 is '0' (d) and '158' (d), respectively, the input clock and the output clock are not changed. A phase comparison pulse is generated and output to the first phase comparator 304.
[0108]
The first phase comparator 304 performs the same comparison control as described in the above-described operation of the FEC frame receiving side [(5) Phase comparison control], and outputs the result through the second selector 310. Output to the side clock source 307. Therefore, the output side clock source 307 controls the frequency based on the comparison result of the first phase comparator 304.
[0109]
Here, as described above, in this embodiment, the read / write address of the FIFO memory 23 is set to '0' (d) and '158' (d), respectively, so that the conditions for generating the phase comparison pulse are as follows. The reason for the difference from the operation of the FEC frame receiving side [(4) read / write processing of the FIFO memory for speed conversion] described above with reference to the embodiment of FIG. 4 is as follows.
[0110]
That is, the optimal phase relationship of the read / write processing of the speed conversion FIFO memory 23 is as shown in the timing of the phase comparison control pulse shown in FIG. 17, and when the writing of one frame is completed, There is a relationship that is the timing to complete the half data reading.
[0111]
Here, the write-side and read-side phase comparison pulses may be generated at positions where both phases have the most margin. The generation timing is the position where the write address is '158' (d) and the read address is 'O' (d). The position where the phase has the most margin is the position where there is a phase of 11.8827 μs, which is half of 23.7654 μs of FEC × 1 frame, between both transfer comparison pulses.
[0112]
In FIG. 17, similarly to the receiving side in the embodiment shown in FIG. 6, when the phase comparison pulse is generated at the position where the read / write address is '0' (d), the phase comparison pulse is generated. A shift of oCLK94M × 384 clocks occurs. Therefore, the position where the offset is corrected, that is, the offset is converted to an iCLK78M clock, and the position where the write-side phase comparison pulse is delayed by half (= 159 (d)) is the most. The position has a phase margin.
[0113]
Here, in the initial state of the FEC frame transmission side and the reception side, when performing the reading operation of the speed conversion FIFO memories 23 (transmission side) and 35 (reception side), normal main signal data writing (writing) is performed. In some cases, the same sign is generated in the transmission data by reading out the address area in which ()) has not been completed. When the same code data is transmitted, an alarm such as LOS (Loss Of Signal) occurs on the receiving side.
[0114]
FIG. 18 is a diagram for explaining the outline of the operation of the embodiment for solving such a problem. In FIG. 18, a write address monitoring unit 311 monitors that normal main signal data has been written to all addresses of the speed conversion FIFO memory 23 (35). The random pattern generation unit 312 generates random data that does not become the same code data. The selector (SEL) unit 313 is a functional block that selects and sends either data from the random pattern generation unit 312 or data read from the FIFO memory 23 (35).
[0115]
During a period in which normal main signal data writing is not completed for all addresses of the speed conversion FIFO memory 23 (35), data from the random pattern generation unit 312 is selected and transmitted by the selector (SEL) unit 313.
[0116]
When the write operation is completed, the data selected and transmitted by the selector (SEL) unit 313 is switched to the data read from the FIFO memory 23 (35). By performing such control, transmission of the same code data in the initial state can be prevented.
[0117]
Further, when a line alarm on the input side occurs on the FEC frame transmission side and the reception side, data of the same code may be written to the speed conversion FIFO memory 23 (35). Therefore, at the time of alarm recovery, if the reading operation is performed before the normal main signal data has been written to all the addresses of the FIFO memory 23 (35), the same sign data written at the time of the alarm is transmitted as it is. Will be done.
[0118]
FIG. 19 is a diagram for explaining the outline of the operation of the embodiment for solving such a disadvantage. In addition to the configuration of the embodiment in FIG. 18, a line alarm detection / cancellation unit 314 is further provided. The line alarm detection / cancellation unit 314 is a functional block that detects and cancels an alarm on the input side line.
[0119]
In FIG. 19, after the line alarm detected by the line alarm detection / cancellation unit 314 is restored, the write address monitoring unit 311 writes normal main signal data to all addresses of the speed conversion FIFO memory 23 (35). Monitor that.
[0120]
The random pattern generation unit 312 generates random data that does not become the same code data, and the selector unit 313 selects and sends either the data from the random pattern generation unit 312 or the data read from the FIFO memory 23 (35). .
[0121]
After the recovery of the line alarm detected by the line alarm detection / cancellation unit 314, the random pattern generation unit 312 is a period during which normal main signal data writing to all addresses of the speed conversion FIFO memory 23 (35) is not completed. And sends it out. When the write operation is completed, the data is switched to the data read from the FIFO memory 23 (35).
[0122]
By performing such control, it becomes possible to prevent the transmission of the same code data after the recovery of the line alarm.
[0123]
(Appendix 1)
In the transmission device of the frame signal in the optical signal transmission system,
A speed conversion memory capable of simultaneously writing and reading,
A write control unit that outputs a write address for writing main signal data to the speed conversion memory,
A read control unit that outputs a read address for reading the main signal data from the speed conversion memory,
A header and a frame generation unit that generates a frame signal by adding an error correction code to the main signal data read from the speed conversion memory,
A write address and a read address output from the write control unit and the read control unit are compared, a remaining amount of the speed conversion memory is obtained, and it is determined whether a stuff operation is necessary for a frame signal generated by the frame generation unit. A staff determination circuit
Furthermore, it has a free-running oscillator,
The frame generator, according to the determination output of the stuff determination circuit, inserts the presence or absence information of the stuff operation in the header of the frame signal, the read control unit, the read control unit in response to the clock output from the free-running oscillator Output read address
A transmitting apparatus for transmitting a frame signal.
[0124]
(Supplementary Note 2) In Supplementary Note 1,
The stuff determination circuit sets a + direction threshold value between the maximum capacity of the speed conversion memory and the maximum remaining amount transition value, and sets a negative direction between the 0 capacity of the speed conversion memory and the minimum remaining amount transition position. A threshold value is provided, and control is performed such that the stuff is increased when the remaining amount of the speed conversion memory exceeds the + direction threshold, and further reduced when the remaining amount of the speed conversion memory is equal to or less than the − direction threshold. The transmitting device of the frame signal to be described.
[0125]
(Supplementary Note 3) In Supplementary note 2,
Further, the stuff determination circuit provides a + alarm threshold between the maximum capacity of the speed conversion memory and the + direction threshold, and provides a-alarm between the 0 capacity of the speed conversion memory and the-direction threshold. A frame signal transmitting apparatus, wherein a threshold is provided, and an alarm is output when the remaining amount of the speed conversion memory exceeds the + direction alarm threshold and when the remaining amount is equal to or less than the-direction alarm threshold.
[0126]
(Supplementary Note 4) In supplementary note 3,
A frame signal transmitting apparatus, wherein when the stuff determination circuit outputs an alarm, the frame generation unit does not insert information indicating whether a stuff operation is present in a header of the frame signal.
[0127]
(Supplementary Note 5) In Supplementary Note 1,
In the initial state, the write address in the write control unit is set to an address corresponding to a half of the maximum capacity of the speed conversion memory, and the read address in the read control unit is set to the position of the capacity 0 of the speed conversion memory. A transmitting apparatus for transmitting a frame signal.
[0128]
(Supplementary Note 6) In Supplementary Note 1,
Furthermore, it has a random pattern generator and a write address monitoring unit,
In the initial state, a random pattern generated by the random pattern generator is used as the main signal data until the write address monitoring unit detects that all addresses of the speed conversion memory have completed writing of the main signal data. An apparatus for transmitting a frame signal, wherein the output is changed.
[0129]
(Supplementary Note 7) In Supplementary note 6,
Furthermore, it has a monitoring unit for alarm state recovery of the input side line,
When detecting that the alarm state has been restored by the monitoring unit, the random pattern generator continues until the write address monitoring unit detects that all the addresses of the speed conversion memory have completed writing the main signal data. A transmitting apparatus for transmitting a frame signal, wherein a generated random pattern is converted into the main signal data and output.
[0130]
(Appendix 8)
In the receiving apparatus of the frame signal in the optical signal transmission system,
A speed conversion memory capable of simultaneously writing and reading,
A write control unit that outputs a write clock for writing a frame signal to the speed conversion memory,
A read control unit that outputs a read clock for reading a frame signal from the speed conversion memory,
A phase comparator for calculating a phase difference between a write clock and a read clock output from the write control unit and the read control unit;
An oscillator whose oscillation frequency is controlled to be changed according to the output of the phase comparator,
The read-side control unit outputs a clock having a frequency corresponding to an oscillation output of the oscillator.
[0131]
(Supplementary Note 9) In Supplementary Note 1,
Furthermore, it has a random pattern generator and a write address monitoring unit,
In the initial state, a random pattern generated by the random pattern generator is used as the main signal data until the write address monitoring unit detects that all addresses of the speed conversion memory have completed writing of the main signal data. An apparatus for receiving a frame signal, wherein the output is changed.
[0132]
(Supplementary Note 10) In Supplementary Note 9,
Furthermore, it has a monitoring unit for alarm state recovery of the input side line,
When detecting that the alarm state has been restored by the monitoring unit, the random pattern generator continues until the write address monitoring unit detects that all the addresses of the speed conversion memory have completed writing the main signal data. A frame signal receiving-side device that converts a generated random pattern into the main signal data and outputs the main signal data.
[0133]
【The invention's effect】
As described above with reference to the drawings, according to the present invention, it is possible to flexibly cope with FEC frame configurations that will be diversified in the future, and to perform data synchronization without being dependently affected (affected) by the input clock. Speed conversion processing becomes possible.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of an optical signal transmission system that employs a conventional clock transfer method.
FIG. 2 is a block diagram illustrating a configuration example of an optical transmission system to which a transmission frame speed conversion processing method according to the present invention is applied.
FIG. 3 is a configuration example of an FEC frame.
4 is a diagram showing a main part of an embodiment of the configuration of the transmitting station shown in FIG. 2;
FIG. 5 is a diagram showing a main signal data multiplex position (stuff area).
FIG. 6 is a diagram illustrating a specific example of a configuration of a receiving station that receives an FEC frame.
FIG. 7 is a diagram showing a data format after error correction.
FIG. 8 is a diagram showing smoothing by a smoothing processing unit 325.
FIG. 9 is a diagram showing a transition of the remaining amount of the frame conversion memory 323.
FIG. 10 is a diagram showing a phase comparison result time chart.
FIG. 11 is a block diagram of an embodiment of a staff determination processing unit.
12 is a diagram illustrating a change in the remaining amount of FIFO memory and a stuff threshold based on the control of the stuff determination processing unit in FIG. 11;
FIG. 13 is a block diagram of another embodiment of the staff determination processing unit.
14 is a diagram illustrating a change in a remaining amount of FIFO memory, a stuff threshold, and a stuff alarm threshold based on the control of the stuff determination processing unit in FIG. 13;
FIG. 15 is a diagram for explaining the operation of the embodiment in FIG. 13;
FIG. 16 is a block diagram of an embodiment on the FEC frame transmitting side in which independent synchronization and dependent synchronization coexist.
FIG. 17 is a diagram for explaining the timing of the phase comparison control pulse in the embodiment of FIG. 16;
FIG. 18 is a block diagram of an embodiment for solving the problem of generating the same code in transmission data in an initial state.
FIG. 19 is a block diagram of an embodiment for solving the problem of generating the same code in transmission data at the time of alarm recovery.
[Explanation of symbols]
23, 35 Speed conversion memory (FIFO memory)
22 SDH termination
24, 34 light control unit
25, 38 Read control unit
26 FEC frame generation unit
27 FIFO Remaining Calculator
32 FEC frame end
39 SDH frame generator
36 clock phase comparator

Claims (5)

In the transmission device of the frame signal in the optical signal transmission system,
A speed conversion memory capable of simultaneously writing and reading,
A write control unit that outputs a write address for writing main signal data to the speed conversion memory,
A read control unit that outputs a read address for reading the main signal data from the speed conversion memory,
A header and a frame generation unit that generates a frame signal by adding an error correction code to the main signal data read from the speed conversion memory,
A write address and a read address output from the write control unit and the read control unit are compared, a remaining amount of the speed conversion memory is obtained, and it is determined whether a stuff operation is necessary for a frame signal generated by the frame generation unit. A staff determination circuit
Furthermore, it has a free-running oscillator,
The frame generator, according to the determination output of the stuff determination circuit, inserts the presence or absence information of the stuff operation in the header of the frame signal, the read control unit, the read control unit in response to the clock output from the free-running oscillator An apparatus for transmitting a frame signal, which outputs a read address. In claim 1,
The stuff determination circuit sets a + direction threshold value between the maximum capacity of the speed conversion memory and the maximum remaining amount transition value, and sets a negative direction between the 0 capacity of the speed conversion memory and the minimum remaining amount transition position. A threshold value is provided, and control is performed such that the stuff is increased when the remaining amount of the speed conversion memory exceeds the + direction threshold, and further reduced when the remaining amount of the speed conversion memory is equal to or less than the − direction threshold. The transmitting device of the frame signal to be described. In claim 2,
Further, the stuff determination circuit provides a + alarm threshold between the maximum capacity of the speed conversion memory and the + direction threshold, and provides a-alarm between the 0 capacity of the speed conversion memory and the-direction threshold. A frame signal transmitting apparatus, wherein a threshold is provided, and an alarm is output when the remaining amount of the speed conversion memory exceeds the + direction alarm threshold and when the remaining amount is equal to or less than the-direction alarm threshold. In claim 3,
A frame signal transmitting apparatus, wherein when the stuff determination circuit outputs an alarm, the frame generation unit does not insert information indicating whether a stuff operation is present in a header of the frame signal. In the receiving apparatus of the frame signal in the optical signal transmission system,
A speed conversion memory capable of simultaneously writing and reading,
A write control unit that outputs a write clock for writing a frame signal to the speed conversion memory,
A read control unit that outputs a read clock for reading a frame signal from the speed conversion memory,
A phase comparator for calculating a phase difference between a write clock and a read clock output from the write control unit and the read control unit;
An oscillator whose oscillation frequency is controlled to be changed according to the output of the phase comparator,
The read-side control unit outputs a clock having a frequency corresponding to an oscillation output of the oscillator.

Images