JP2004266745A - Output circuit, receiving circuit, interface device and digital camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of signal lines which are necessary for transferring serial image signals and the number of input and output pins and the like. <P>SOLUTION: An interface device 26 is composed of an output circuit 27A which transfers a serial image signal and a receiving circuit 27B which receives a transfer signal SD. A pixel clock generating circuit of the output circuit 27A generates a pixel clock signal PCLK. A bit clock generating circuit 30 generates a bit clock signal BCLK of a frequency N<SB>1</SB>/N<SB>2</SB>times (N<SB>1</SB>and N<SB>2</SB>are positive integers, and N<SB>1</SB>is an integral multiple of N<SB>2</SB>) as high as the frequency of the pixel clock signal PCLK and supplies it to a dynamicizer circuit 32. The dynamicizer circuit 32 converts the N<SB>1</SB>(=8)-bit wide serial image signal PD into the N<SB>2</SB>(=2)-bit wide transfer signal SD. A staticizer circuit 40 of the receiving circuit 27B converts the transfer signal SD into the N<SB>1</SB>-bit wide serial image signal PD by using the bit clock signal BCLK and the pixel clock signal PCLK. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an interface device used for data transfer in a digital camera or the like.
[0002]
[Prior art]
2. Description of the Related Art In an imaging apparatus such as a digital still camera or a digital video camera, light transmitted through an optical system is detected by an imaging element such as a CCD sensor or a CMOS sensor and is photoelectrically converted into an image signal. After the image signal is A / D converted to a digital signal, it is subjected to various image processing such as pixel interpolation, color space conversion, contour enhancement and resolution conversion. The signal subjected to the image processing is transferred to a display device such as an LCD (Liquid Crystal Display) or an EVF (Electronic View Finder) provided in the eyepiece, and displayed as an image. Alternatively, the signal that has undergone the image processing is written into a nonvolatile memory or the like after being encoded according to a predetermined format.
[0003]
When a captured image is displayed on a display device such as an EVF or LCD, an image signal is transferred and displayed after being encoded into a format required by the display device. For this reason, an interface circuit that exchanges data between the encoder that encodes the image signal and the display device is required. The interface circuit includes an output circuit that transfers an output signal of an encoder, and a receiving circuit that receives a transfer signal from the output circuit and outputs the signal to a display device. The related technology of this type of interface circuit is described in, for example, Japanese Patent Application Laid-Open No. 2000-232370. Note that Patent Document 1 describes a receiving circuit as a “DA conversion circuit”.
[0004]
[Patent Document 1]
JP-A-2000-232370
[0005]
[Problems to be solved by the invention]
However, in the above-described interface circuit, if the number of signal lines required for data transfer is large, the number of input / output pins also increases. As a result, the area of the substrate on which the signal lines are provided increases, and the power consumption and the circuit scale increase.
[0006]
In general, a display device supporting full-color display has a plurality of color filters such as three primary colors for each pixel. However, some display devices mounted on a digital camera or the like include one color filter for each pixel. Some have only color filters. FIG. 13 is a diagram schematically showing an arrangement of color filters of this type of display device. In FIG. 13, R, G, and B represent a red filter, a green filter, and a blue filter, respectively. Since this type of display device cannot directly display a color image signal having three color components for each pixel, it is necessary to convert the format of the color image signal according to the arrangement of the color filters of the display device. Hereinafter, the image signal after the format conversion is referred to as a “serial image signal”.
[0007]
In view of the above situation, an object of the present invention is to reduce the number of signal lines and the number of input / output pins required for data transfer, and to mount an interface device suitable for transferring serial image signals and this interface device. The point is to provide a digital camera.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a first invention is an interface device including an output circuit for transferring a serial image signal, and a receiving circuit for receiving a signal transferred from the output circuit, The signal is a signal generated by sampling one color component signal for each pixel from a plurality of color component signals constituting one pixel according to a predetermined format, and the output circuit is configured to output the serial image signal A pixel clock generation circuit for generating a pixel clock signal synchronized with the phase of the pixel clock signal; ₁ / N ₂ Times (N ₁ , N ₂ Is a positive integer; N ₁ Is N ₂ A bit clock generating circuit for generating a bit clock signal having a frequency of N. ₁ The bit width of the color component signal is represented by N ₂ A parallel-to-serial conversion circuit that converts the signal into a bit-width signal and outputs the signal, wherein the receiving circuit is transferred from the output circuit using the bit clock signal and the pixel clock signal transferred from the output circuit. Signal N ₁ It has a serial-parallel conversion circuit for converting the color component signal into a bit-width color component signal.
[0009]
In a second aspect, in the interface device according to the first aspect, at least one of a vertical synchronizing signal and a horizontal synchronizing signal is included in lower bits of the color component signal and transmitted from the output circuit to the receiving circuit. Will be transferred.
[0010]
In a third aspect, in the interface device according to the first or second aspect, only a vertical synchronization signal is transferred from the output circuit to the reception circuit, and the reception circuit uses the received vertical synchronization signal to perform horizontal synchronization. A frame counter for generating a signal;
[0011]
A fourth invention is an output circuit for transferring a serial image signal generated by sampling one color component signal for each pixel from a plurality of color component signals constituting one pixel according to a predetermined format. A pixel clock generating circuit for generating a pixel clock signal synchronized with the phase of the serial image signal; ₁ / N ₂ Times (N ₁ , N ₂ Is a positive integer; N ₁ Is N ₂ A bit clock generating circuit for generating a bit clock signal having a frequency of N. ₁ The bit width of the color component signal is represented by N ₂ And a parallel-to-serial conversion circuit that converts the signal into a bit-width signal and outputs the signal.
[0012]
A fifth invention is the output circuit according to the fourth invention, wherein the N ₁ / N ₂ A plurality of bit clock generation circuits that generate a plurality of the bit clock signals so that the double frequency is different from each other, and a clock selector that selects and outputs any one of the plurality of the bit clock signals, A plurality of parallel-to-serial conversion circuits, each of which synchronizes with the plurality of bit clock signals, converts the color component signal into a plurality of signals, and outputs the plurality of signals, and output signals of the plurality of parallel-serial conversion circuits And a data selector for selecting an output signal of the serial-parallel conversion circuit synchronized with the bit clock signal selected by the clock selector and outputting the selected signal as a transfer signal.
[0013]
According to a sixth aspect, in the output circuit according to the fourth or fifth aspect, at least one of a vertical synchronizing signal and a horizontal synchronizing signal is transferred while being included in lower-order bits of the color component signal.
[0014]
According to a seventh aspect of the present invention, the N clock transmitted together with the bit clock signal and the pixel clock signal is used. ₂ Bit width (N ₂ Is a positive integer) and receives the N clock signal transferred using the bit clock signal and the pixel clock signal. ₂ Bit width signal is N ₁ Bit width (N ₁ Is a positive integer; N ₁ Is N ₂ A serial-to-parallel conversion circuit that converts a color image signal into a serial image signal of the same number. The bit clock signal is a signal generated by sampling, and the bit clock signal has a frequency N of a frequency of the pixel clock signal synchronized with a phase of the serial image signal. ₁ / N ₂ It is characterized by being a signal having twice the frequency.
[0015]
According to an eighth aspect of the present invention, the N ₂ Bit width (N ₂ Is a positive integer), and receives the pixel clock signal by N ₁ / N ₂ A PLL circuit that generates a bit clock signal by multiplying, and the N clock transferred using the bit clock signal and the pixel clock signal. ₂ Bit width signal is N ₁ Bit width (N ₁ Is a positive integer; N ₁ Is N ₂ And a serial-parallel conversion circuit for converting the serial image signal into a serial image signal of the same number. The serial image signal is one color component signal for each pixel from among a plurality of color component signals constituting one pixel. , And the pixel clock signal is synchronized with the phase of the serial image signal.
[0016]
A ninth aspect of the present invention is the reception circuit according to the seventh or eighth aspect, further comprising a frame counter for generating a horizontal synchronization signal using the transferred vertical synchronization signal.
[0017]
A tenth invention is a digital camera equipped with the interface device according to any one of the first to third inventions, and a display device for displaying a serial image signal defined by the first invention transferred by the interface device. is there.
[0018]
An eleventh invention is a digital camera equipped with an output circuit according to any one of the fourth to sixth inventions, and a display device for displaying the serial image signal specified by the fourth invention transferred by the output circuit. is there.
[0019]
A twelfth invention is directed to a digital camera including the receiving circuit according to any one of the seventh to ninth inventions, and a display device for displaying the serial image signal defined by the seventh invention received by the receiving circuit. It is.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0021]
<Configuration of digital camera>
First, a configuration example of a digital camera incorporating the interface device according to the embodiment of the present invention will be described, and then the interface device according to each embodiment will be described in detail.
[0022]
FIG. 1 is a block diagram schematically showing the configuration of the digital camera 1. The digital camera 1 includes an optical mechanism 10 having a lens group, a prism, an AF (auto focus; automatic focusing) function, an automatic exposure adjustment function, and the like. Light reflected from a subject passes through the optical mechanism 10 and passes through an optical LPF (low-pass filter) 11 to be received by a CCD image sensor 12.
[0023]
A PLL (Phase-Locked Loop) circuit 17 generates a clock signal by multiplying or dividing the oscillation signal supplied by the oscillator 17A, and supplies the clock signal to the timing generator (TG) 16, the output circuit 27A, the CPU 18, and the like. . The timing generator 16 uses the clock signal supplied from the PLL circuit 17 to supply various control signals to the drive circuit 15 and the RPU (real-time processing unit) 14.
[0024]
The CCD image sensor 12 operates upon receiving a drive signal from the drive circuit 15, converts incident light into an analog signal, and outputs the analog signal to the analog signal processing circuit 13. Note that a CMOS image sensor may be used instead of the CCD image sensor 12. The analog signal processing circuit 13 includes a CDS (Correlated Double Sampling; correlated double sampling) circuit, an AGC (Automatic Gain Control; automatic gain control) circuit, and an A / D conversion circuit. In general, the CCD image pickup device 12 alternately outputs a reference signal having a reference level of a normal black level and an image signal including the reference signal in a time-division manner. The CDS circuit samples the reference signal and the image signal in order to remove a noise component in the image signal, and extracts and outputs a difference signal between the two signals. The AGC circuit outputs a signal obtained by optimizing the signal level of the differential signal input from the CDS circuit. The A / D conversion circuit samples the input signal from the AGC circuit and quantizes the signal with a predetermined quantization bit number. And outputs the converted digital image signal (raw image data; Raw Image Data).
[0025]
The RPU 14 is an integrated circuit that operates in synchronization with a clock signal supplied from the timing generator 16. The RPU 14 performs processing such as defective pixel correction processing, shading correction processing, pixel interpolation processing, gamma correction processing, color space conversion processing, contour enhancement processing, and resolution conversion processing on the image signal input from the analog signal processing circuit 13. It has a function to execute various digital image processing in real time.
[0026]
The image signal output from the RPU 14 is transferred to the main memory 21 via the bus 9 and buffered. The data transfer via the bus 9 may be performed under the control of a DMA (Direct Memory Access) controller 19 connected to the bus 9 instead of the CPU 18. The CPU 18 operates in synchronization with a clock signal supplied from the PLL circuit 17, reads an image signal from the main memory 21, and performs various image processing. Also, the CPU 18 activates the compression / decompression processing unit 20 to compress and encode the image signal according to the JPEG (Joint Photographic Expert Group) method or the motion JPEG method, and then to compress the compressed data via the interface 22 into the memory card 23. To an external device such as a personal computer via the external interface 24.
[0027]
The CPU 18 can further control the image data sequentially output from the RPU 14 to be displayed as a moving image on the LCD 29 functioning as a finder. That is, image data output from the RPU 14 after being subjected to resolution conversion in accordance with the resolution of the LCD 29 is buffered in the main memory 21, and then sequentially transferred to the display module 25 via the bus 9. The display module 25 outputs the image data to the interface device 26 in frame units or subframe units.
[0028]
The interface device 26 includes an output circuit 27A and a receiving circuit 27B. The output circuit 27 </ b> A receives the N input from the display module 25 as described later in detail. ₁ Bit width signal is N ₂ Bit width (N ₁ , N ₂ Is a positive integer; N ₁ Is N ₂ (Integral multiple of the transfer signal) and sends it to the receiving circuit 27B. The receiving circuit 27B converts the received transfer signal to the original N signal. ₁ The signal is converted into a bit width signal and supplied to the LCD drive circuit 28. Then, the LCD drive circuit 28 receives the input N ₁ Control is performed such that an image signal having a bit width is written to the LCD 29. As a result, the LCD 29 displays the captured image as a still image or a moving image.
[0029]
On the other hand, the user of the digital camera 1 can perform framing, exposure adjustment, setting of a shutter speed, and determination of a photographing timing of a subject while visually recognizing the image displayed on the LCD 29. When the user presses a release button (not shown) at the moment of shooting, the CPU 18 detects the state and controls the RPU 14 to output high-resolution image data. The high-resolution image data output from the RPU 14 is subjected to compression encoding and the like by the above-described compression / decompression processing unit 20, then transferred to the card interface 22 via the bus 9, and written to the memory card 23.
[0030]
The interface device 26 mounted on the digital camera 1 having the above configuration will be described in detail below.
[0031]
<First embodiment>
FIG. 2 is a block diagram schematically illustrating the interface device 26 according to the first embodiment of the present invention. The output circuit 27A includes a bit clock generation circuit 30, a pixel clock generation circuit 31, and a parallel / serial conversion circuit 32, and the reception circuit 27B includes a serial / parallel conversion circuit 40.
[0032]
In the present embodiment, the LCD 29 has a color filter having the arrangement shown in FIG. 13 and corresponds to the display of the serial image signal. Since the signal transferred to the display module 25 is a color image signal including a plurality of color component signals such as R, G, and B for each pixel, the display module 25 adjusts to the color filter arrangement of the LCD 29. , One color component signal is sampled for each pixel from the color image signal to generate a serial image signal, which is supplied to the interface device 26.
[0033]
An 8-bit serial image signal PD, a 1-bit vertical synchronization signal VD, and a 1-bit horizontal synchronization signal HD are input from the display module 25 to the interface device 26. The vertical synchronizing signal VD and the horizontal synchronizing signal HD are transferred from the output circuit 27A to the receiving circuit 27B.
[0034]
The pixel clock generation circuit 31 generates a pixel clock signal PCLK having a frequency of 13.5 MHz using a clock signal (not shown) supplied from the PLL circuit 17. Further, the bit clock generation circuit 30 generates a bit clock signal BCLK having a frequency of 54.0 MHz, which is four times the frequency of 13.5 MHz of the pixel clock signal PCLK. The bit clock signal BCLK is transferred from the output circuit 27A to the receiving circuit 27B and is supplied to the parallel / serial conversion circuit 32. The timing chart of FIG. 3 shows a signal waveform example of the pixel clock signal PCLK and the bit clock signal BCLK.
[0035]
The parallel-serial conversion circuit 32 converts the serial image signal PD having an 8-bit width into a transfer signal SD having a 2-bit width in synchronization with the bit clock signal BCLK, and outputs the signal. The transfer signal SD is transferred from the output circuit 27A to the receiving circuit 27B. Here, the ratio of the frequency between the pixel clock signal PCLK and the bit clock signal BCLK (= 54.0 MHz / 13.5 MHz = 4) is the ratio of the bit width between the serial image signal PD and the transfer signal (= Adjustment is made so as to match (8 bit width / 2 bit width = 4).
[0036]
As shown in FIG. 3, the serial image signal PD is a series of color component signals..., P synchronized with the pixel clock signal PCLK. ₀ [7: 0], P ₁ [7: 0], P ₂ [7: 0],... In the example of FIG. 3, the color component signal P ₀ [7: 0], P ₁ [7: 0], P ₂ [7: 0] are B (blue signal), R (red signal), and G (green signal), respectively. Note that the color component signal P _i [7: 0] (i is an integer) represents eight 1-bit signals P _i [7], P _i [6], P _i [5], ..., P _i This is a parallel signal obtained by bundling [0].
[0037]
The parallel / serial conversion circuit 32 outputs the color component signal P input in synchronization with the bit clock signal BCLK. _i [7: 0], which is transferred to a 2-bit transfer signal P _i [1: 0], P _i [3: 2], P _i [5: 4], P _i [7: 6] is serially converted and sequentially output. In the example of FIG. ₁ Color component signal P at ₁ [7: 0] is the next cycle T ₂ Is a 2-bit width transfer signal P ₁ [1: 0], P ₁ [3: 2], P ₁ [5: 4], P ₁ [7: 6].
[0038]
On the other hand, in the receiving circuit 27B, the serial-parallel conversion circuit 40 uses the bit clock signal BCLK and the pixel clock signal PCLK transferred from the output circuit 27A to fetch a 2-bit width transfer signal SD, and converts this to an 8-bit width. Is converted in parallel to the serial image signal PD and output.
[0039]
Since such an interface device 26 converts an 8-bit color component signal serially arranged for each pixel into a 2-bit width transfer signal and transfers the signal, the number of signal lines required for data transfer and the input / output The number of pins can be greatly reduced.
[0040]
FIG. 4 is a diagram schematically illustrating a configuration example of the serial-parallel conversion circuit 40. In general, when transferring a clock from the output circuit 27A to the receiving circuit 27B, the timing at which the clock reaches the receiving circuit 27B may be shifted, and the phase of the transfer signal SD with respect to the bit clock signal BCLK may be shifted. In such a case, the display image deteriorates. As described below, the serial-parallel conversion circuit 40 in FIG. 4 has a function of correcting a phase shift of the transfer signal SD with respect to the bit clock signal BCLK.
[0041]
4 includes shift registers 50 and 53, selectors 51 and 54, and D latches 52 and 55. The serial-parallel conversion circuit 40 receives a 2-bit transfer signal SD, a bit clock signal BCLK, a pixel clock signal PCLK, and switching control signals Ad0 and Ad1. Here, the switching control signals Ad0 and Ad1 are supplied from the CPU 18. The upper one bit of the transfer signal SD is input to one shift register 50, and the lower one bit is input to the other shift register 53.
[0042]
The shift register 50 is configured by connecting seven D flip-flops 50A to 50G in seven stages in series, and can hold signals corresponding to seven cycles of the bit clock signal BCLK in parallel. The output terminal Q of the D flip flop of each stage is connected to the input terminal D of the next stage D flip flop except for the last stage. Similarly, the shift register 53 is configured by connecting seven D flip-flops 53A to 53G in seven stages in series, and can hold signals corresponding to seven cycles of the bit clock signal BCLK in parallel. Each time the pulse of the bit clock signal BCLK is input, the D flip-flops of the shift register 50 and the shift register 53 move the held signal to the next stage.
[0043]
The selector 51 has four input terminals 0 to 4 numbered “0”, “1”, “2”, and “3”, and the four input terminals 4 according to the signal levels of the switching control signals Ad0 and Ad1. One of the input terminals 0 to 4 is selected, and a 4-bit signal input to the selected input terminal is output to the D latch 52. Output signals of the first to fourth D flip-flops 50A to 50D are combined and input to the input terminal 0 of the selector 51. The output signals of the second to fifth D flip-flops 50B to 50E are combined and input to the input terminal 1 of the selector 51, and the input terminal 2 of the third to sixth stages is connected to the input terminal 2. The output signals of the D flip-flops 50C to 50F are combined and input, and the input terminal 3 receives the combined output signals of the fourth to seventh stages of the D flip-flops 50D to 50G.
[0044]
The selector 54 also has four input terminals 0 to 4 numbered "0", "1", "2", and "3", and the four terminals are switched according to the signal levels of the switching control signals Ad0 and Ad1. One of the input terminals 0 to 4 is selected, and a 4-bit signal input to the selected input terminal is output to the D latch 55. The output signals of the first to fourth D flip-flops 53A to 53D are combined and input to the input terminal 0 of the selector 54, and the second to fifth stages are input to the input terminal 1 of the selector 54. The output signals of the D flip-flops 53B to 53E are combined and inputted, and the output signals of the D flip-flops 53C to 53F of the third to sixth stages are combined and input to the input terminal 2 thereof. Output signals of the fourth to seventh D flip-flops 53D to 53G are combined and input to the input terminal 3.
[0045]
The D latches 52 and 55 latch and output the 4-bit signals input from the selectors 51 and 54 each time a pulse of the pixel clock signal PCLK is input. The 4-bit output signals of the D latches 52 and 55 are combined and output as a serial image signal PD to the outside.
[0046]
In the serial-parallel conversion circuit 40 having such a configuration, the phase of each 1-bit signal constituting the transfer signal SD can be corrected by setting the signal levels of the switching control signals Ad0 and Ad1. Since the phase shift of the transfer signal SD is predicted at the design stage or development stage of the digital camera 1 or detected at the time of circuit inspection, the switching control signals Ad0 and Ad1 are adjusted in advance so as to correct the phase shift. Will be done.
[0047]
In the first embodiment, an 8-bit color component signal is converted into a 2-bit width transfer signal. However, the present invention is not limited to this. In general, a positive integer N of 2 or more is used. ₁ , N ₂ (N ₁ Is N ₂ N), N ₁ The bit width color component signal is N ₂ It is possible to easily change the configuration of the interface device 26 so that the signal is converted into a bit-width transfer signal and transferred. In such a case, the configuration of the bit clock generation circuit 30 is determined by the frequency N of the pixel clock signal PCLK. ₁ / N ₂ What is necessary is just to change to generate the bit clock signal BCLK having the double frequency.
[0048]
Next, a first modification of the first embodiment will be described. FIG. 5 is a block diagram schematically showing a configuration of the interface device 26 according to the first modification. This interface device 26 has substantially the same configuration as the interface device 26 shown in FIG. In the first modification, the horizontal synchronizing signal HD and the vertical synchronizing signal VD are included in the lower first bit and the lower second bit of the serial image signal PD, respectively. Further, in the receiving circuit 27B, the horizontal synchronizing signal HD and the vertical synchronizing signal VD are extracted from the serial image signal PD output from the serial-parallel conversion circuit 40. Therefore, the number of signal lines and the number of pins can be further reduced as compared with the case where the horizontal synchronization signal HD and the vertical synchronization signal VD are directly transferred.
[0049]
Next, Modification 2 of the first embodiment will be described. FIG. 6 is a block diagram schematically showing a configuration of the interface device 26 according to the second modification. The interface device 26 also has substantially the same configuration as the interface device 26 shown in FIG. 2, but in the second modification, the receiving circuit 27B uses the vertical synchronization signal VD transferred from the output circuit 27A to output a horizontal synchronization signal. A frame counter 42 for generating an HD is provided. This eliminates the need to transfer the horizontal synchronizing signal HD from the output circuit 27A to the receiving circuit 27B, so that the number of signal lines and the number of input / output pins can be further reduced.
[0050]
Next, a third modification of the first embodiment will be described. FIG. 7 is a block diagram schematically showing a configuration of the interface device 26 according to the third modification. This interface device 26 has substantially the same configuration as the interface device 26 shown in FIG. In the third modification, the vertical synchronizing signal VD is included in the lower one bit of the serial image signal PD and transferred in the output circuit 27A. The signal VD is extracted. The receiving circuit 27B includes a frame counter 42 that generates a horizontal synchronization signal HD using the extracted vertical synchronization signal VD. With such a configuration, the number of signal lines and the number of input / output pins can be reduced as much as possible.
[0051]
<Second embodiment>
Next, a second embodiment of the present invention will be described. 8 to 11 are block diagrams schematically showing the configuration of the interface device 26 according to the second embodiment and its modification. 8 to 11, components 30, 31, 32, and 40 having the same reference numerals as those in FIG. 1 have the same functions as the components of the first embodiment, and will not be described in detail. Omitted.
[0052]
The output circuit 27A of FIG. 8 includes a bit clock generation circuit 30, a pixel clock generation circuit 31, and a parallel / serial conversion circuit 32. The reception circuit 27B includes a serial / parallel conversion circuit 40 and a PLL (Phase-Locked Loop) circuit 41. It comprises. The PLL circuit 41 converts the input signal to N ₁ / N ₂ It has the function of multiplying. In the present embodiment, the PLL circuit 41 generates a bit clock signal BCLK by multiplying the pixel clock signal PCLK transferred from the output circuit 27A by four, and supplies the bit clock signal BCLK to the serial-parallel conversion circuit 40. Therefore, it is not necessary to transfer the bit clock signal BCLK from the output circuit 27A to the receiving circuit 27B, so that the number of signal lines and the number of input / output pins can be reduced. The other configuration is the same as that of the interface device 26 shown in FIG.
[0053]
Next, FIG. 9 is a block diagram schematically illustrating a configuration of the interface device 26 according to the first modification. In the first modification, the horizontal synchronizing signal HD and the vertical synchronizing signal VD are included in the lower first bit and the lower second bit of the serial image signal PD, respectively. Further, in the receiving circuit 27B, the horizontal synchronizing signal HD and the vertical synchronizing signal VD are extracted from the serial image signal PD output from the serial-parallel conversion circuit 40. This makes it possible to further reduce the number of signal lines and the number of pins as compared with the case where the horizontal synchronization signal HD and the vertical synchronization signal VD are directly transferred.
[0054]
Next, FIG. 10 is a block diagram schematically illustrating a configuration of the interface device 26 according to the second modification. In the second modification, the receiving circuit 27B includes a frame counter 42 that generates the horizontal synchronization signal HD using the vertical synchronization signal VD transferred from the output circuit 27A. This eliminates the need to transfer the horizontal synchronizing signal HD from the output circuit 27A to the receiving circuit 27B, so that the number of signal lines and the number of input / output pins can be further reduced.
[0055]
Next, FIG. 11 is a block diagram schematically illustrating a configuration of the interface device 26 according to the third modification. In the third modification, the vertical synchronizing signal VD is included in the lower one bit of the serial image signal PD and transferred in the output circuit 27A. The signal VD is extracted. The receiving circuit 27B includes a frame counter 42 that generates a horizontal synchronization signal HD using the extracted vertical synchronization signal VD. With such a configuration, the number of signal lines and the number of input / output pins can be reduced as much as possible.
[0056]
<Third embodiment>
Next, a third embodiment of the present invention will be described. FIG. 12 is a block diagram schematically illustrating a configuration of an interface device 26 according to the third embodiment. The output circuit 27A includes a pixel clock generation circuit 62, bit clock generation circuits 60 and 61, parallel / serial conversion circuits 64 and 65, a clock selector 63, and a data selector 66, and the reception circuit 27B includes a serial / parallel conversion circuit 67. It comprises.
[0057]
The interface module 26 receives an 8-bit serial image signal PD, a 1-bit vertical synchronization signal VD, and a 1-bit horizontal synchronization signal HD from the display module 25 (FIG. 1). The vertical synchronizing signal VD and the horizontal synchronizing signal HD are transferred from the output circuit 27A to the receiving circuit 27B.
[0058]
The pixel clock generation circuit 62 generates a pixel clock signal PCLK having a frequency of 13.5 MHz using a clock signal (not shown) supplied from the PLL circuit 17. The output circuit 27A includes two types of bit clock generation circuits 60 and 61, each generating a clock having a frequency different from each other. One bit clock generation circuit 60 generates a bit clock signal BCLK1 having a frequency of 54.0 MHz, which is four times the frequency of 13.5 MHz of the pixel clock signal PCLK, and supplies it to the parallel / serial conversion circuit 65 and the clock selector 63. The other bit clock generation circuit 61 generates a bit clock signal BCLK2 having a frequency of 27 MHz which is twice the frequency of 13.5 MHz of the pixel clock signal PCLK and supplies it to the parallel / serial conversion circuit 64 and the clock selector 63. are doing.
[0059]
The clock selector 63 selects and outputs one of the two bit clock signals BCLK1 and BCLK2 according to a selection control signal supplied from a controller (not shown). The output signal of the clock selector 63 is transferred to the receiving circuit 27B.
[0060]
Further, the parallel-serial conversion circuit 65 converts the serial image signal PD having an 8-bit width into a 2-bit signal in synchronization with the bit clock signal BCLK1, and outputs the 2-bit signal to the data selector 66. The operation of the parallel / serial conversion circuit 65 is the same as that of the parallel / serial conversion circuit 32 shown in FIG. Here, the ratio of the frequency between the pixel clock signal PCLK and the bit clock signal BCLK1 (= 54.0 MHz / 13.5 MHz = 4) is between the serial image signal PD and the output signal of the parallel / serial conversion circuit 65. It is adjusted to match the bit width ratio (= 8 bit width / 2 bit width = 4).
[0061]
The other parallel / serial conversion circuit 64 converts the serial image signal PD having an 8-bit width into a 4-bit signal in parallel with the bit clock signal BCLK2, and outputs the 4-bit signal to the data selector 66. Here, the ratio of the frequency between the pixel clock signal PCLK and the bit clock signal BCLK2 (= 27.0 MHz / 13.5 MHz = 2) is between the serial image signal PD and the output signal of the parallel / serial conversion circuit 64. It is adjusted to match the bit width ratio (= 8 bit width / 4 bit width = 2). The upper 2-bit signal of the 4-bit signal output from the parallel / serial conversion circuit 64 is transferred to the receiving circuit 27B as a transfer signal SD1, and the lower 2-bit signal of the 4-bit signal is output to the data selector 66.
[0062]
The data selector 66 selects one of a 2-bit signal input from the parallel / serial conversion circuit 64 and an output signal of the parallel / serial conversion circuit 65 according to a selection control signal supplied from the controller, and outputs the selected signal as a transfer signal SD2. I do. When the clock selector 63 selects the bit clock signal BCLK1, the data selector 66 selects the output signal of the parallel / serial conversion circuit 65 synchronized with the bit clock signal BCLK1, and the clock selector 63 selects the bit clock signal BCLK2. Is selected so that the output signal of the parallel-to-serial conversion circuit 64 synchronized with the bit clock signal BCLK2 is selected.
[0063]
In FIG. 12, four types of signal lines for transmitting a bit clock signal, a pixel clock signal, and signals SD1 and SD2 are used, and a configuration example suitable for achieving high-speed data transfer is shown. The clock selector 63 selects the bit clock signal BCLK2, and the serial / parallel conversion circuit 67 takes in the transfer signals SD1 and SD2 using the bit clock signal BCLK2 and the pixel clock signal PCLK transferred from the output circuit 27A. . Then, the serial-parallel conversion circuit 67 converts the 4-bit signal obtained by combining the two transfer signals SD1 and SD2 into an 8-bit width serial image signal PD in parallel using the input bit clock signal BCLK2 and outputs the signal. This configuration example is effective when the resolution of the LCD 29 is high or when the frame rate is high. On the other hand, when the resolution of the LCD 29 is low or the frame rate is low, the clock selector 63 may select the bit clock signal BCLK1 and transfer only the signal SD1 to the receiving circuit 27B without transferring the signal SD2. . In such a case, it is possible to transfer the image signal using a smaller number of signal lines.
[0064]
As described above, according to the third embodiment, the serial image signal PD can be converted into either a 4-bit signal or a 2-bit signal according to the system of the digital camera 1, and the transfer speed can be set in two stages. Can be switched. In addition, data can be transferred between the output circuit 27A and the receiving circuit 27B with a small number of signal lines.
[0065]
In the present embodiment, a configuration in which the transfer speed can be switched in two stages has been described. However, in the present invention, the configuration of the interface device 26 can be switched in L stages (L is an integer of 3 or more). Configuration can be easily changed. In such a case, the output circuit 27A includes L bit clock generation circuits that generate L bit clock signals having different frequencies from each other, and includes L parallel serial conversion circuits that operate in synchronization with each bit clock signal. Will be prepared. Further, the clock selector 63 is changed to have a function of selecting any one of the K bit clock signals, and the data selector 66 is configured to select any one of the output signals of the K parallel-serial conversion circuits. Changed to have the ability to select
[0066]
In addition, the present embodiment employs a configuration in which the horizontal synchronization signal HD and the vertical synchronization signal VD are directly transferred from the output circuit 27A to the reception circuit 27B. Instead of this configuration, as a modified example of the present embodiment, as shown in FIGS. 5 to 7, the horizontal synchronization signal HD and the vertical synchronization signal VD are included in the lower bits of the serial image signal PD and transferred. 27B may include a frame counter 42 that generates the horizontal synchronization signal HD using the vertical synchronization signal VD.
[0067]
【The invention's effect】
As described above, according to the interface device of the present invention, N ₁ N bits of serial image signal ₂ Since the signal is converted into a bit-width signal and transferred, the number of signal lines and the number of input / output pins required for the transfer of dot-sequential data can be significantly reduced. Therefore, it is possible to realize an interface device with a small circuit scale and low power consumption.
[0068]
Further, according to the digital camera equipped with the interface device according to the present invention, the number of signal lines and the number of input / output pins required for data transfer to the display device are reduced, so that a digital camera having a compact circuit configuration can be realized. is there.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a configuration of a digital camera according to an embodiment of the present invention.
FIG. 2 is a block diagram schematically showing an interface device according to the first embodiment of the present invention.
FIG. 3 is a timing chart showing waveforms of various signals in the interface device.
FIG. 4 is a diagram schematically illustrating a configuration example of a serial-parallel conversion circuit.
FIG. 5 is a block diagram schematically showing a configuration of an interface device according to a first modification of the first embodiment.
FIG. 6 is a block diagram schematically illustrating a configuration of an interface device according to a second modification of the first embodiment.
FIG. 7 is a block diagram schematically showing a configuration of an interface device according to a third modification of the first embodiment.
FIG. 8 is a block diagram schematically showing a configuration of an interface device according to a second embodiment of the present invention.
FIG. 9 is a block diagram schematically illustrating a configuration of an interface device according to a first modification of the second embodiment.
FIG. 10 is a block diagram schematically showing a configuration of an interface device according to a second modification of the second embodiment.
FIG. 11 is a block diagram schematically showing a configuration of an interface device according to a third modification of the second embodiment.
FIG. 12 is a block diagram schematically showing a configuration of an interface device according to a third embodiment of the present invention.
FIG. 13 is a diagram schematically illustrating a color filter array of a color display device that displays a serial image signal.
[Explanation of symbols]
1 Digital camera
26 Interface device
27A output circuit
27B receiving circuit
30, 60, 61 bit clock generation circuit
31, 62 pixel clock generation circuit
32,64,65 parallel / serial conversion circuit
40,67 series-parallel conversion circuit
41 PLL circuit
42 frame counter

Claims (12)

An interface device including an output circuit for transferring a serial image signal and a receiving circuit for receiving a signal transferred from the output circuit,
The serial image signal is a signal generated by sampling one color component signal for each pixel from a plurality of color component signals forming one pixel according to a predetermined format,
The output circuit includes:
A pixel clock generation circuit that generates a pixel clock signal synchronized with the phase of the serial image signal,
A bit clock generation circuit for generating a bit clock signal having a frequency N ₁ / N ₂ times (N ₁ , N ₂ is a positive integer; N ₁ is an integer multiple of N ₂ ) times the frequency of the pixel clock signal;
And a parallel-serial conversion circuit for outputting the color component signal of said bit clock signal synchronized to N _1-bit width into a signal of N _2-bit wide,
The receiving circuit,
By using the bit clock signal and the pixel clock signal transferred from the output circuit comprises a serial-parallel conversion circuit for converting the signal transferred from the output circuit to the color component signals of N _1-bit width, characterized in that Interface device. 2. The interface device according to claim 1, wherein at least one of a vertical synchronizing signal and a horizontal synchronizing signal is included in lower bits of the color component signal and transferred from the output circuit to the receiving circuit. . The interface device according to claim 1 or 2,
Only a vertical synchronization signal is transferred from the output circuit to the receiving circuit,
The interface device, wherein the receiving circuit includes a frame counter that generates a horizontal synchronization signal using the received vertical synchronization signal. An output circuit for transferring a serial image signal generated by sampling one color component signal for each pixel from a plurality of color component signals forming one pixel according to a predetermined format,
A pixel clock generation circuit that generates a pixel clock signal synchronized with the phase of the serial image signal,
A bit clock generation circuit for generating a bit clock signal having a frequency N ₁ / N ₂ times (N ₁ , N ₂ is a positive integer; N ₁ is an integer multiple of N ₂ ) times the frequency of the pixel clock signal;
Output circuit, characterized in that it and a parallel-serial conversion circuit for outputting the color component signal of said bit clock signal synchronized to N _1-bit width into a signal of N ₂ bits wide. The output circuit according to claim 4,
A plurality of bit clock generation circuits for generating a plurality of the bit clock signals so that the N ₁ / N ₂ times frequencies are different from each other;
A clock selector for selecting and outputting any of the plurality of bit clock signals;
A plurality of the parallel-to-serial conversion circuits, each of which is in synchronization with a plurality of the bit clock signals, and converts and outputs the color component signal to a plurality of signals;
A data selector that selects an output signal of the serial-parallel conversion circuit synchronized with the bit clock signal selected by the clock selector from among the output signals of the plurality of parallel / serial conversion circuits and outputs the output signal as a transfer signal; An output circuit comprising: 6. The output circuit according to claim 4, wherein at least one of a vertical synchronizing signal and a horizontal synchronizing signal is transferred while being included in lower-order bits of the color component signal. Bit clock signal and the pixel clock signal with the transferred N ₂ bits wide (N ₂ is a positive integer) a receiving circuit for receiving a signal,
The bit clock signal and using the pixel clock signal, a signal transferred the N ₂ bit wide N _1-bit width (N ₁ is a positive integer; integer multiple of N ₁ is N ₂₎ into serial image signal Serial-parallel conversion circuit,
The serial image signal is a signal generated by sampling one color component signal for each pixel from a plurality of color component signals constituting one pixel,
The bit clock signal is a signal having the pixels N _{1 /} N ₂ times the frequency of the clock signal synchronized with the serial image signal phase,
A receiving circuit, characterized in that: It transferred N ₂ bits wide with a pixel clock signal (N ₂ is a positive integer) a receiving circuit for receiving a signal,
A PLL circuit for generating a bit clock signal by the pixel clock signal N _{1 /} N ₂ multiplication,
The bit clock signal and using the pixel clock signal, a signal transferred the N ₂ bit wide N _1-bit width (N ₁ is a positive integer; integer multiple of N ₁ is N ₂₎ into serial image signal A serial-to-parallel conversion circuit,
The serial image signal is a signal generated by sampling one color component signal for each pixel from a plurality of color component signals constituting one pixel,
2. The receiving circuit according to claim 1, wherein the pixel clock signal is synchronized with a phase of the serial image signal. 9. The receiving circuit according to claim 7, further comprising a frame counter that generates a horizontal synchronization signal using the transferred vertical synchronization signal. A digital camera comprising the interface device according to any one of claims 1 to 3, and a display device for displaying the serial image signal transmitted by the interface device. A digital camera comprising the output circuit according to any one of claims 4 to 6, and a display device for displaying the serial image signal transmitted by the output circuit. A digital camera, comprising: the receiving circuit according to claim 7; and a display device that displays the serial image signal received by the receiving circuit.

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