JP2004265447A - Method of writing data in nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To extend the lifetime of a chip by preventing the number of times of writings from being increased due to erroneous writing or rewriting. <P>SOLUTION: A method of writing data in a nonvolatile semiconductor memory device 1 provided with an EEPROM memory cell array divided into physical blocks 2 composed of a plurality of pages comprises; a step of referring to a management table 20 to specify a physical block which corresponds to a logical page designated by a host 3 and where data are written; a step of writing data in the specified physical block 2; and a step of setting a pointer 21 pointing a physical page where data are next written in the block 2. When the pointer 21 is set, the pointer is incremented from a physical page on the source side in the specified physical block 2 toward a physical page on the drain side. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

 The present invention relates to a data writing method for a nonvolatile semiconductor memory device using a NAND type EEPROM among electrically rewritable nonvolatile semiconductor memory elements (EEPROM).

 Currently, magnetic disk devices are widely used as secondary storage devices of computers. In recent years, electrically rewritable non-volatile semiconductor memories (EEPROMs) have been used for their reliability against mechanical strength, low power consumption, Taking advantage of its portability and high-speed access, it has been used to replace magnetic disks.

However, since there are functional differences between the magnetic disk device and the EEPROM, in order to replace the conventional magnetic disk device as it is, it is necessary to perform control to fill this.

 As one of the EEPROMs, a NAND type EEPROM that can be highly integrated is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones to form one unit, which is connected to a bit line. The memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrally formed in a p-type substrate or a p-type well formed in an n-type substrate. The drain side of the NAND cell is connected to a bit line via a selection gate, and the source side is also connected to a source line (reference potential wiring) via a selection gate (FIG. 12). In general, a set of memory cells connected to the same word line is called one page, and a set of pages sandwiched between a pair of drain-side and source-side select gates is one NAND block. Or, it is simply called one block (FIG. 13) .One block is usually the minimum unit that can be independently erased.

 The operation of the NAND type EEPROM is as follows. Data erasure is performed simultaneously on memory cells in one NAND block. That is, all the control gates of the selected NAND block are set to the reference potential VSS, and the high voltage VPP (for example, 20 V) is applied to the p-type well and the n-type substrate. As a result, electrons are emitted from the floating gate to the substrate in all the memory cells, and the threshold value shifts in the negative direction. Usually, this state is defined as "1" state. Chip erasing is performed by setting all NAND blocks to a selected state.

 The data write operation is performed sequentially from the memory cell located farthest from the bit line. A high voltage VPP (for example, 20 V) is applied to a selected control gate in the NAND block, and an intermediate potential VM (for example, 10 V) is applied to other non-selected gates. VSS or VM is applied to the bit line according to data. When VSS is applied to the bit line ("0" write), the potential is transmitted to the selected memory cell, and electron injection occurs in the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. Normally, this state is defined as "0" state. Electron injection does not occur in the memory cell in which VM is applied to the bit line ("1" write), so that the threshold value does not change and remains negative. The data read operation is performed by setting the control gate of the selected memory cell in the NAND block to VSS, setting the other control gates and the selection gate to VCC, and detecting whether a current flows in the selected memory cell.

 In a NAND type EEPROM, data writing must be performed in order from a page near the source line to a page on the drain side. The necessity will be described below with reference to FIG. When "1" is written, the intermediate potential VM (about 10 V) is transferred to the drain of the selected memory cell, and the erase state (that is, the negative threshold value) is maintained without injecting electrons. FIG. 14 shows a case where the control gate 1 is in the selected state (VPP). Therefore, the control gate 2 is not selected and is supplied with VM. VM ("1" write) is also applied to the drain. FIG. 14A shows a case where writing is performed from the source side, and FIG. 14B shows a case where writing is performed from the drain side. In the case of FIG. 14A, since the threshold value of the drain-side cell Ma2 is negative, the drain potential VM is reliably transferred to the source-side cell Ma1. However, in the case of FIG. 14B, assuming that the "0" write operation has already been performed on the drain-side cell Mb2 and that the drain-side cell Mb2 has a positive threshold value (for example, 3.5 V), "1" is written on the source-side cell Mb1. At this time, only the voltage obtained by subtracting the threshold voltage of the cell Mb2 from the VM is transferred to the cell Mb1. Therefore, in the cell Mb1, there is a possibility that the potential difference between the control gate and the substrate becomes large and erroneous writing occurs. As described above, the means for sequentially writing from the source side is important in preventing erroneous writing.

 In a conventional magnetic disk device, the unit of access such as data reading and writing is a sector. The track formed on the circumference of the medium is divided into several tens of sectors, and these sectors are sequentially numbered (addressed) in the direction of rotation. Assuming that there are 50 sectors in one track, the first access writes data for four sectors from the fifth sector, and the second access writes data for four sectors from the first sector. Is On the other hand, the access unit of the NAND type EEPROM is a page. Taking a 4M-bit NAND type EEPROM as an example, one page is composed of 512 bytes and one block is composed of eight pages. Therefore, in applications where the magnetic disk device is replaced with a NAND EEPROM, conversion is easy if one sector of the disk is mapped to one page of the NAND EEPROM. However, as in the case of the magnetic disk, if access is performed such that the fourth page is written from the fifth page from the source side in one block and then the first page to the fourth page is written, erroneous writing occurs as described above. there is a possibility.

 One method for avoiding this is that, in the second access, the first page written from the fifth page to the fourth page is saved once in a buffer, then this block is erased, and the first page written to the eight pages from the first page. It is the procedure of writing data.

However, this operation wastes a limited number of times of rewriting the EEPROM. Another method is to make the access unit of the NAND type EEPROM a block of the erase unit. In this case, in order to rewrite a part of the data of the block as described above, the already written data in the block is once read into the buffer, and the data to be rewritten is overwritten on the buffer. A procedure of erasing a block and writing data of eight pages from the first page is performed.

 As described above, in the NAND type EEPROM, data access is performed in units of pages corresponding to sectors of the magnetic disk. However, when random data is written in page units as in the case of a magnetic disk, the write order in a block is reduced. However, there is a problem that writing may be performed incorrectly out of the rules. In order to avoid this, if the data previously written to the buffer is taken up and the block is erased and then rewritten, the number of times of rewriting is increased and the life of the chip is shortened. When the access unit is blocked, data writing is performed at once for all pages in the block. At this time, data to be written is transferred from the buffer to the NAND EEPROM, but not all data in the buffer is valid. That is, when writing to a certain block and the writing is the first writing to the block, or when invalidating the data written to the block, it is not necessary to read the data in the block prior to rewriting. . Therefore, at this time, if there is no data to be written in only some of the pages, the data for the remaining pages is invalid. Normally, no data is set in the invalid portion, so that there is data left "erased" when the buffer was previously used, and this data is written as it is. In the conventional magnetic disk drive, there is no difference in writing time between writing "1" and writing "0" as data. However, in the case of a NAND-type EEPROM, as described above, all data is "1" in the erased state, and electrons are injected only when data "0" is written. Also, since the time required for electron injection is not constant for each bit, the process proceeds while verifying whether "0" has been normally written. Therefore, if the data in the page are all "1", the writing is completed instantaneously. Further, since no electron injection occurs, stress on the oxide film is reduced. As described above, in consideration of the characteristics of the NAND type EEPROM, if all invalid data portions are set to "1", if this data is spread over one page, it is not necessary to waste time writing the page. However, since the conventional input / output system is for a magnetic disk having no such characteristics, no consideration has been given to this point.

 The present invention has been made in view of the above-described problems, and prevents an increase in the number of write operations due to erroneous write due to reversal of a write order and a rewrite operation, and also prevents unnecessary stress from being applied to an insulating film of a memory cell. Accordingly, it is an object of the present invention to provide a data writing method for a nonvolatile semiconductor memory device that can improve the life of a chip and further minimize the time required for writing.

 In order to achieve the above object, the features of the embodiment of the present invention are as follows. (A) A nonvolatile semiconductor memory device provided with a NAND type EEPROM memory cell array divided into physical blocks composed of a plurality of pages. (B) referring to a management table to specify a physical block to which data is to be written corresponding to a logical page specified by the host; and (c) specifying a physical block to which the specified physical block is to be written. And (d) setting a pointer indicating a physical page in the block to which data is to be written next, and (e) specifying the physical block specified in the setting of the pointer. Of a non-volatile semiconductor memory device that increments from a physical page on the source side to a physical page on the drain side And summarized in that a chromatography data write method.

 First, at the time of writing data to the memory means, regardless of the order of accessing the pages from the host system or the like, the rules regarding the writing order, that is, writing is always performed from the page on the source side in the block. This shortens the life of the chip due to erroneous writing due to the page written on the drain side or the like being written first, or increasing the number of writings by erasing the data written on the drain side and then rewriting. Is avoided.

 Second, when writing data to a block, data in an area of the buffer where no valid data is present is initialized so that all data is the same as data in an erased state. As a result, writing of a page filled with only invalid data is completed in the shortest time, and unnecessary stress is not applied to the insulating film of the memory cell, thereby avoiding shortening the life of the chip.

(First Embodiment)
FIG. 1 is a block diagram showing an entire configuration of a nonvolatile semiconductor memory device to which a data writing method for a nonvolatile semiconductor memory device according to a first embodiment of the present invention is applied. In FIG. 1, reference numeral 1 denotes a NAND type EEPROM module as a memory means, which is constituted by a memory cell array divided into blocks composed of a plurality of pages. The EEPROM module 1 is connected to a host system (not shown) via a host interface 3 connected by data lines.

 A multiplexer 10 and a data buffer 11 are provided on the data line. In the host interface 3, a data register 4, an address register 5, a count register 6, a command register 7, a status register 8, and an error register 9 are provided. 12 is a control logic, 13 is an ECC (error correction code) generator / checker, 14 is an address generator, 15 is a CPU having a function as control means, 16 is a work RAM from which a page management table described later is read, and 17 is a work RAM. This is a control program ROM. The control program ROM 17 stores a series of control programs for writing data and the like.

 The memory device according to the present embodiment uses a page management table for allocating and managing a page position in a block of data recorded in the EEPROM module 1 which is a nonvolatile memory area. This table is recorded in the EEPROM module 1 together with other user data, but is automatically read into the working RAM 16 when the apparatus is started. The contents of this table are updated each time data is written to the EEPROM module 1. The updated table is written back to the EEPROM module 1 each time or at the end of use of the device. It shall be.

 FIG. 2 manages the correspondence between the page address (logical page) and the physical position (physical page) in the block, and the physical position of the next page to be used in accordance with the rules regarding the writing order of the EEPROM module 1. 1 is an example of a page management table 20 as a management means for pointing to a. The page management table 20 is divided into n areas as shown in FIG. 2A, and each area 18 corresponds to each block of the EEPROM module 1. Here, for simplicity, assuming that the NAND type EEPROM constituting the memory device is one 4-Mbit EEPROM, n, that is, the number of blocks is 128. These areas 18 are further composed of one pointer 21 serving as point means and a flag area 22 of the number of pages (= 8) as shown in FIG. The pointer 21 is used to sequentially write to pages in a block from the source side, and indicates the most source side page to which writing has not yet been performed. If this value exceeds the number of pages per block, (In the case of 9 in this example), it is assumed that writing cannot be performed unless block erasure is performed. The logical page flag 22 is set to “0” if the logical page has not been written yet, and if it has been written, the physical position actually written is set to what physical number from the source side. It indicates whether the page was a page.

 The outline of the operation when data is recorded will be described using a specific example. If nothing has been written to a certain block yet, the contents of the pointer and the flag in the area 18 of the page management table 20 corresponding to the certain block are as shown in FIG. At this time, assume that data for three pages from the fifth logical page of this block is written. First, since the value of the pointer 21 is 1, the contents of the fifth logical page are written to the physical page on the source side, the value of the flag 22 of the fifth logical page is updated to 1, and the value of the pointer 21 is updated. Is also incremented to indicate the second page from the source side. This operation is further repeated for two pages, and updated as shown in FIG. Next, assuming that writing is performed for five pages from the first logical page to the same block, since the pointer 21 points to the fourth physical page, writing for five pages is performed from here, and the table is changed as shown in FIG. Update as in c). As a result, the pointer 21 becomes 9, so that the next writing to this block requires a process of saving data that is not rewritten in a buffer, erasing the block, and writing it back with new data. For example, in the state of FIG. 3C, if data of two pages is rewritten from the first logical page, the contents of the third logical page to the seventh logical page which are not rewritten are taken into the buffer and block erase is performed. The pointer 21 is also initialized to 1. After that, data for seven pages in the buffer is written to the block. FIG. 3D shows the contents of the updated table in this case. Even if the content of the pointer is not 9, even when the number of pages to be written is larger than the number of remaining pages (for example, a write request for six pages from the third logical page in the state of FIG. 3B) ), The same processing needs to be performed. When reading data, the correspondence between the page address in the block and the physical position is determined from the page management table 20, and necessary data is accessed.

 Next, the operation of this device will be described using a flowchart. The host system sets the access start address in the address register 5 in the host interface 3 of FIG. 1, the sector length of the data to be accessed in the count register 6, and finally sets the command such as read / write in the command register 7. . When an access command is written in the command register 7 of the host interface 3, the CPU 15 in the controller reads the command in the command register 7 and executes a series of control programs for executing commands stored in the control program ROM 17. In the following description, for simplicity, it is assumed that the sector length specified by the host system and the page length in the EEPROM module 1 match.

 FIG. 4 is a flowchart showing a procedure for reading data from the EEPROM module 1. First, the CPU 15 of FIG. 1 refers to the start address set in the host interface 3 and the address conversion table in the page management table 20 to determine the physical address of the EEPROM module 1 to be read (step 101). . Next, data is read from the EEPROM module 1 to the data buffer 11 (step 102). Next, error processing and data transfer from the data buffer 11 to the host system, which will be described in detail later, are executed (steps 103 to 105).

 FIG. 5 is a flowchart showing a procedure for reading data from the EEPROM module to the data buffer. The CPU 15 accesses the EEPROM module 1 through the multiplexer 10 to set the read mode, and sets the data buffer 11 to the read mode (steps 201 and 202). The physical address of the EEPROM module 1 to be read is set in the address generator 14 (step 203). Then, an area in which the read data is to be stored is determined in the data buffer 11, and the start address thereof is set as a write address to the data buffer 10 (step 204). Thereafter, a command is sent to the control logic 12 to execute a predetermined sequence for reading data.

 The control logic 12 sets the multiplexer 10 so that the read data from the EEPROM module 1 flows to the data buffer 11, and reads data of one sector while incrementing the contents of the address generator 14 (Step 205). Further, the ECC generator / checker 13 is controlled so as to detect an error by using these data and the ECC code read out accompanying thereto. When the data for one sector is read, the CPU 15 checks the ECC generator / checker 13 to check the data for errors (step 206). If no error is detected, or if an error is detected and correction can be performed, the data is transferred from the data buffer 11 to the host system. If an uncorrectable error is detected, the data is not transferred to the host system, and the CPU 15 writes a code indicating that an error has occurred in the status register 8 in the host interface 3 into the error register 9. Is set to indicate the content of the error, and the host system is notified that the execution of the command has been abnormally terminated, and the process is terminated (steps 207 to 210).

 FIG. 6 is a flowchart showing a procedure for transferring data from the data buffer to the host system. The CPU 15 sets the start address of the area in which the data read in the data buffer 11 is stored as an address to be read from the buffer (steps 301 and 302). Command to perform the transfer. The control logic 12 controls the data buffer 11 and the host interface 3 to transfer one sector of data to the host system (step 303). When this is completed, the address register 5 is advanced by one sector and the count register 6 1 is subtracted, and the CPU 15 is notified that the transfer is completed. As long as data to be transferred remains in the host system, the CPU 15 repeats this control. When all the read data is transferred, the CPU 15 sets a code indicating that there is no error in the status register 8 in the host interface 3, notifies the host system that the execution of the instruction has been completed, and ends the processing. .

 FIGS. 7 and 8 are flowcharts showing a procedure for writing data to the EEPROM module 1. The CPU 15 determines a block on the EEPROM module 1 to which the host system is to write from the start address set in the host interface 3 (step 401). If the number of unused pages in the block of the EEPROM module 1 specified by the host system is smaller than the number of pages to be written and the request from the host system does not rewrite all the data of this block, the rewriting in the block is performed. Data that cannot be read is read into the data buffer (steps 402 to 404). The procedure for reading data from the EEPROM to the data buffer 11 has been described above with reference to the flowchart in FIG. The process of FIG. 5 is repeated until all data of the non-overwritten portion in the block is read into the buffer. Unless the number of unused pages in the block is equal to or greater than the number of pages to be written, block erasure is performed thereafter (step 405). Next, transfer of write data from the host system to the data buffer 11, write processing of data from the data buffer 11 to the EEPROM module 1, error processing, and the like, which will be described in detail later, are performed. Initialization is performed (steps 406 to 411).

 FIG. 9 shows a procedure for transferring write data from the host system to the data buffer. The CPU 15 sets the data buffer 11 to the write mode (step 501), and sets an address on the data buffer 11 where data transferred from the host system is stored as a write address to the buffer (step 502). After that, the control logic 12 is instructed to transfer one sector of data from the host system. The control logic 12 controls the data buffer 11 and the host interface 3 to receive one sector of data from the host system, and when this is completed, notifies the CPU 15 that the transfer has been completed (step 503). The process of FIG. 9 is continued as long as data to be transferred from the host system remains and data for the block for which the EEPROM module 1 is to be written in the data buffer 11 is insufficient. When the transfer from the host system is completed, the CPU 15 refers to the pointer of the page management table of the block corresponding to the start address set in the host interface 3 and, as described above, stores the 1 stored in the data buffer 11. The page position of the corresponding block on the EEPROM module 1 to which the data for the page is to be written is determined and writing is performed.

 FIG. 10 is a flowchart showing a procedure for writing one page of data in the data buffer to the EEPROM module. The CPU 15 initializes the EEPROM module 1 and the data buffer 11 if necessary (steps 601 and 602), and sets the head address of the page to be written to the address generator 14 (step 603). Sets the head address of the data to be written as the read address of the buffer (step 604). Then, a command is sent to the control logic 12 to execute a predetermined sequence for writing data. The control logic 12 sets the multiplexer 10 so that write data from the data buffer 11 flows to the EEPROM module 1, and writes data while incrementing the contents of the address generator 14 (step 605). Also, the ECC generator / checker 13 is controlled to generate an ECC code from these data, and this code is recorded together with the data (step 606). The process of FIG. 10 is continued while incrementing the pointer of the page management table until a write error occurs or data is to be written to the corresponding block or data has been written. If the data cannot be written normally, necessary error processing is performed, and writing is performed again (steps 607 and 608). When the writing is completed normally, the contents of the page management table are updated. If all the data requested by the host system has been recorded or the processing has been interrupted due to the inability to recover from the error, the CPU 15 sets a predetermined code in the status register 8 in the host interface 3 and sets the predetermined code in the host system. Notifies that instruction execution has been completed.

 In this embodiment, the EEPROM module is controlled by a controller operable in parallel with the host system via the host interface. However, the EEPROM module is controlled directly by the CPU of the host system. May be taken.

(Second embodiment)
FIG. 11 is a block diagram showing a nonvolatile semiconductor memory device to which the data writing method of the nonvolatile semiconductor memory device according to the second embodiment of the present invention is applied. The CPU 15 accesses the EEPROM module 1 through the interface 25. For access, a buffer 30 provided in a part of the RAM 26 is used. Now, assuming that the EEPROM module 1 is composed of a 4M-bit NAND type EEPROM, one block is 4 kbytes, so the size of the buffer 30, that is, the unit of input / output is 4 kbytes. Portions corresponding to 31 to 38 in the buffer 30 are portions corresponding to pages in a block of the NAND type EEPROM, but are not treated as independent data in this device.

 First, consider a case where a part of data of a certain block 2 in the EEPROM module 1 is rewritten. Since the data of the non-rewritable portion of the block 2 must be left, it must be read in advance. However, in this apparatus, since the access unit is one block, all the data of the block 2 is transferred to the buffer 30. Next, data is rewritten on the buffer 30, and at the same time, the block 2 of the EEPROM module 1 is erased. Then, the contents of the buffer 30 are written in one block in order from the page on the source side.

 Next, consider a case where the contents of block 2 are invalidated and only data for three pages are written. In this case, since the data in block 2 is discarded, there is no need to read it out in advance. Block 2 is immediately erased. Assuming that three pages of data are to be written in the positions of pages 31 to 33, the CPU 15 first sets data in this part. At this time, the data obtained when the EEPROM module was accessed before this access remains in the buffers 34 to 38 in the buffer 30. Therefore, if the data in the buffer 30 is written to the block 2 as it is, the contents of the pages 34 to 38 containing the originally meaningless data are verified and written as they are, and wasteful time is wasted. Therefore, the CPU 15 sets “1”, which is data at the time of erasing the EEPROM module, in 34 to 38 in the buffer 30 before writing to the block 2. As described above, in the present embodiment, when data is written, the data in the area where no valid data exists in the buffer 30 is initialized so as to be the same as the data in the erased state. In addition, it is possible to avoid giving unnecessary stress to the oxide film of the NAND type EEPROM.

 In this embodiment, the EEPROM module 1 is controlled directly by the CPU 15 on the bus 27 via the interface 25. However, the EEPROM module 1 is interposed between the interface 25 and the It may take a form controlled by an operable controller. In addition, the present embodiment can be variously modified and used without departing from the gist thereof.

1 is a block diagram showing a nonvolatile semiconductor memory device applied to a data writing method of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 3 is a diagram illustrating a configuration of a page management table according to the first embodiment. It is a figure for explaining operation of the above-mentioned page management table. 6 is a flowchart for explaining a process of reading data from an EEPROM module in the first embodiment. 5 is a flowchart for explaining a process of reading data from the EEPROM module to the data buffer in the first embodiment. 5 is a flowchart for explaining a process of transferring read data from a data buffer to a host system in the first embodiment. 5 is a flowchart for explaining a process of writing data to an EEPROM module in the first embodiment. 5 is a flowchart for explaining a process of writing data to an EEPROM module in the first embodiment. 6 is a flowchart for explaining a process of transferring write data from the host system to the data buffer in the first embodiment. 5 is a flowchart for describing a process of writing data in a data buffer to an EEPROM module in the first embodiment. FIG. 9 is a block diagram illustrating a nonvolatile semiconductor memory device applied to a data writing method for a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. 3 is an equivalent circuit diagram showing one NAND cell of the EEPROM. FIG. 3 is an equivalent circuit diagram showing a memory cell array of the EEPROM. FIG. 3 is a diagram for explaining a write operation of a NAND type EEPROM.

Explanation of reference numerals

1: EEPROM module (memory means)
2 Block 3 Host interface 4 Data register 5 Address register 6 Count register 7 Command register 8 Status register 9 Error register 10 Multiplexer 11 data buffer 12 control logic 13 ECC generator / checker 14 address generator 15 CPU (control means)
16 ... Work RAM
17 ... Control program ROM
18 area (block)
20 page management table 21 serving as management means Pointer pointer (pointer)
22 ... Flag (area)
25 Interface 26 RAM
27 bus 30 buffers 31, 32, 33, 34, 35, 36, 37, 38 pages 101 to 105, 201 to 210, 301 to 303, 401 to 411, 501 to 503, 601 to 608 ... Steps

Claims (4)

A method of writing data to a non-volatile semiconductor memory device having a NAND type EEPROM memory cell array divided into physical blocks composed of a plurality of pages,
Referring to the management table to identify a physical block to which data is to be written corresponding to the logical page specified by the host;
Writing data to the specified physical block,
Setting a pointer indicating a physical page to which data is to be written next in the block, wherein in the setting of the pointer, a physical page on the drain side and a physical page on the drain side in the specified physical block are set. A data writing method for a non-volatile semiconductor memory device, comprising:   2. The method according to claim 1, further comprising, prior to the specifying, reading the management table from the memory cell array to a RAM.   3. The method according to claim 2, wherein the step of reading the data into the RAM is performed when the nonvolatile semiconductor memory device is started.   4. The data writing method for a nonvolatile semiconductor memory device according to claim 1, wherein the ECC code is written together with the data.

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