JP2004241443A - Manufacturing method of semiconductor apparatus - Google Patents

Manufacturing method of semiconductor apparatus Download PDF

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Publication number
JP2004241443A
JP2004241443A JP2003026504A JP2003026504A JP2004241443A JP 2004241443 A JP2004241443 A JP 2004241443A JP 2003026504 A JP2003026504 A JP 2003026504A JP 2003026504 A JP2003026504 A JP 2003026504A JP 2004241443 A JP2004241443 A JP 2004241443A
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Japan
Prior art keywords
film adhesive
semiconductor wafer
semiconductor
semiconductor element
dicing
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JP2003026504A
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Japanese (ja)
Inventor
Kiyoshi Mita
清志 三田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Application filed by Kanto Sanyo Semiconductors Co Ltd, Sanyo Electric Co Ltd filed Critical Kanto Sanyo Semiconductors Co Ltd
Priority to JP2003026504A priority Critical patent/JP2004241443A/en
Publication of JP2004241443A publication Critical patent/JP2004241443A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve a film adhesive agent 11 in bonding strength to a semiconductor device 12. <P>SOLUTION: The front and rear surface of a semiconductor wafer 10 are cleaned with a plasma cleaning machine 20 to remove organic deposits attached to the semiconductor wafer 10. Then, the semiconductor wafer 10 is pasted onto a dicing sheet 26 through the intermediary of the film adhesive agent 11, and the semiconductor wafer 10 is divided together with the film adhesive agent 11 into semiconductor devices 12 by dicing. The semiconductor device 12 where the film adhesive agent 11 is transferred on its rear surface is picked up by a collet 30 and mounted on a mounting surface. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、プラズマ照射を用いて半導体ウェハの洗浄を行うことにより、ダイボンドの工程やワイヤボンドの工程の歩溜まりを向上させることができる回路装置の製造方法に関するものである。
【０００２】
【従来の技術】
図７および図８を参照して、従来の回路装置の製造方法に関して説明する。一般的な半導体を内蔵する回路装置は、次のような工程で製造される。先ず、シリコン、ガリウム、ヒ素等の半導体ウェハをダイシングシートに貼り付け、ダイシングにより個々の半導体素子に切り分る。次に、半導体素子をピックアップして、リードフレームまたは基板上に載置して、電気的接続を行う。最後に絶縁性樹脂等で封止されて半導体素子を有する回路装置が製造される。
【０００３】
図７を参照して、半導体素子１００をピックアップする工程を説明する。台座１０４上に載置されたダイシングシート１０１には、半導体ウェハが貼り付けられ、格子状にダイシングすることにより、個々の半導体素子１００に分割されている。先ず、ピックアップされる半導体素子１００が載置される箇所のダイシングシート１０１の裏面を、台座１０４に装着された突き上げ棒１０５で突き上げる。このことにより、半導体素子１００裏面とダイシングシート１０１との接着面積を小さくして、両者の接着力を小さくしている。次に、吸着力を有するコレット１０３により、半導体素子１００を吸着して輸送する。
【０００４】
図８を参照して、コレット１０３により吸着及び輸送が行われた半導体素子１００は、実装面に実装される。具体的には、実装基板１０６の表面に形成された導電路等に、絶縁性接着剤１０７等を介して固着される。この後に、金属細線で電気的接続を行う工程、封止を行う工程等を経て、パッケージ化された回路装置が製造されていた。
【０００５】
しかしながら、半導体素子１００がモバイル用などの小型のものであった場合、適量の絶縁接着剤１０７を塗布するのが困難である場合があった。このことから、液状の接着剤の替わりにフィルム状の接着剤（ダイアッタチシート）を使用することが提案された（例えば、特許文献１を参照）。即ち、半導体ウェハをダイアッタチシートを介してダイシングシート１０１に張り合わせ、ダイアッタチシートも含めてダイシングを行い、ダイアッタチシートを伴った半導体素子１００を実装することで、実装の工程を行う。その後に、ダイアッタチシートは、加熱されることで、粘着力を増し、半導体素子１００と実装面との接着が可能となる。
【０００６】
【特許文献１】
特開２００２−２９４１７７号公報
【０００７】
【発明が解決しようとする課題】
しかしながら、ダイアッタチシートを用いた半導体素子１００の実装方法では、ダイアッタチシートを介してダイシングシート１０１に接着された半導体素子１００をピックアップする工程に於いて、半導体素子１００裏面にダイアッタチシートが転写せず、ダイアッタチシートがダイシングシート１０１に残存してしまう問題があった。ダイアッタチシートが半導体素子１００裏面に転写しないで、ピックアップされた場合、ダイボンドの工程で半導体素子１００の固着が行われない問題が発生する。更に、部分的にダイアッタチシートが転写して、ダイボンドの工程が行われたとしても、半導体素子１００が安定した状態で固着されず、ワイヤボンディングの工程で、金属細線が正常に接続されない問題が発生する。
【０００８】
上記した問題は、特に海外から輸入された半導体ウェハや長期間保存された半導体ウェハに於いて顕著に発生した。この原因は、半導体ウェハが保管または輸送される場合、多数枚が層間紙を介して積層されて梱包され、この層間紙に含有される有機性の薬剤が、半導体ウェハに付着してしまうことにある。このことから、半導体ウェハとダイアタッチシートとの接着強度が充分に確保されず、上記のような問題が多発していた。
【０００９】
本発明は上記した問題を鑑みて成されたものであり、本発明の主な目的は、プラズマ照射により半導体ウェハを洗浄することにより、半導体素子裏面に確実にダイアタッチシート等のフィルム接着剤を転写することができる回路装置の製造方法を提供することにある。
【００１０】
【課題を解決するための手段】
本発明の回路装置の製造方法は、半導体ウェハをプラズマ洗浄することによりその表面の付着物を除去する工程と、フィルム接着剤を介して半導体ウェハをダイシングシートに貼り付ける工程と、前記フィルム接着剤も含めて前記半導体ウェハをダイシングして個別の半導体素子に切り離す工程と、前記フィルム接着剤が裏面に残存した前記半導体素子をピックアップする工程と、前記フィルム接着剤を介して前記半導体素子を実装面に実装する工程とを具備することを特徴とする。
【００１１】
【発明の実施の形態】
図１から図６を参照して、本発明の回路装置の製造方法を説明する。第１の工程は、図１を参照して、半導体ウェハ１０をプラズマ洗浄することによりその表面の付着物を除去することにある。
【００１２】
先ず、プラズマ洗浄機２０の構成に関して説明する。プラズマ洗浄機２０は筐体により内部が密閉され、供給部２１から内部にプラズマソースガスが供給され、排気部２２によりプラズマ反応を行ったプラズマソースガスを排出する。また、プラズマ洗浄機２０内部には、テーブル状の第１の電極２３Ａおよび第２の電極２３Ｂが設けられ、一方の電極が高周波の電源に接続されて、他方の電極が接地されている。ここでは、第１の電極２３Ａが高周波の電源に接続され、第２の電極２３Ｂが接地されている。従って、第１の電極２３Ａと第２の電極２３Ｂに挟まれる領域のソースガスがプラズマとなり、洗浄能力を発揮する。
【００１３】
本工程でプラズマ洗浄が行われる半導体ウェハ１０は、マガジン２４に収納されて第２の電極２３Ｂ上に載置される。マガジン２４は、半導体ウェハ１０と第２の電極２３Ｂとが導通してしまうのを防止するために、絶縁材から成る。半導体ウェハ１０は、マガジン２４に縦方向に複数個が整列して載置され、半導体ウェハ１０の主面の方向は、ソースガスがその表面に沿って流動する方向に合わせてある。
【００１４】
プラズマによる半導体ウェハ１０の洗浄方法は、先ず、プラズマ洗浄機２０内部に、供給部２１からソースガスを導入する。ここでは、半導体ウェハ１０表面に付着した有機性の付着物を除去するために、ソースガスとして酸素ガスを用いる。ソースガスとしては、アルゴンやヘリウム等の他の気体を用いることも可能である。次に、第１の電極２３Ａに高周波の電流を印加することにより、第１の電極２３Ａおよび第２の電極２３Ｂに挟まれる領域にプラズマを発生させて、半導体ウェハ１０の表面および裏面の洗浄を行う。半導体ウェハ１０の表面および裏面に付着した付着物と反応した酸素ガスは、二酸化炭素となり、排気部２２から外部に放出される。また、上記したプラズマ洗浄に替えて、紫外線を照射することにより、半導体ウェハ１０に付着した有機性の付着物を除去することも可能である。
【００１５】
第２の工程は、図２を参照して、フィルム接着剤１１を介して半導体ウェハ１０をダイシングシート２６に貼り付け、フィルム接着剤１１も含めて半導体ウェハ１０をダイシングして個別の半導体素子１２に切り離すことにある。
【００１６】
図２（Ａ）を参照して、枠状に形成された金属枠２５にダイシングシート２６は連結されており、ダイシングシート２６の中央部付近にフィルム接着剤１１を介して半導体ウェハ１０が貼り付けられる。
【００１７】
図２（Ｂ）を参照して、格子状にダイシングを行うことにより、半導体ウェハ１０を各半導体素子１２に分割する。ここでのダイシングは、半導体ウェハ１０およびフィルム接着剤１１が分割される深さまで行われ、ダイシングシート２６の表面部分までダイシングを行っても良い。また、ダイシングを行った後あるいはダイシングの工程に先行して、ダイシングシート２６の裏面からフィルム接着剤１１に紫外線を照射する。このことにより、フィルム接着剤１１の弾性率を向上させることができ、後の工程に於いて、半導体素子１２裏面へのフィルム接着剤１１の転写を向上させることができる。これは、弾性率が向上することにより、フィルム接着剤１１が部分的にダイシングシートに残るのを防止できるからである。
【００１８】
第３の工程は、図３および図４を参照して、フィルム接着剤１１が裏面に残存した半導体素子１２をピックアップすることにある。
【００１９】
先ず、図３を参照して、フィルム接着剤１１を介して半導体ウェハが貼り付けられたダイシングシート２６は、台座２８上に載置されている。そして、ダイシングシート２６が周辺方向に引っ張られることで、各半導体素子１２間には間隙が形成される。ピックアップされる予定の半導体素子１２に対応する箇所のダイシングシート２６を、台座２８に装着された突き上げ棒２９で突き上げることにより、ダイシングシート２６を局所的に持ち上げる。このことにより、ピックアップされる半導体素子１２の裏面に密着したフィルム接着剤１１裏面と、ダイシングシート２６との接着面積を小さくすることができるので、両者の密着強度を低減することができる。
【００２０】
次に、図４を参照して、突き上げ棒２９により突き上げられた半導体素子１２の表面を吸着力を有するコレット３０で吸着して、裏面にフィルム接着剤１１が転写した半導体素子１２を吸着する。上述した第１の工程で、半導体素子１２裏面は洗浄されていることから、半導体素子１２裏面とフィルム接着剤１１との密着強度は充分に確保されている。従って、半導体素子１２をピックアップする工程に於いて、半導体素子１２裏面に転写するべきフィルム接着剤１１が、ダイシングシート２６に残存するのを防止することができる。また、フィルム接着剤１１が部分的にダイシングシート２６に残存してしまうのも防止することができる。
【００２１】
第４の工程は、図５および図６を参照して、フィルム接着剤１１を介して半導体素子１２を実装面に実装することにある。
【００２２】
裏面にフィルム接着剤１１が転写された半導体素子１２は、コレット３０により、実装面に実装される。ここでは、実装基板３１上の導電路に実装されるが、実装面としては、リードフレーム等でも良い。ここで、フィルム接着剤１１は、半導体素子１２を実装するための接着剤として機能する。実装が行われた半導体素子１２は仮圧着が行われ、約１２０℃の温度下で圧着されることにより、実装面の凹凸に対して、フィルム接着剤１１の裏面が密着される。その後に、約１６０℃の温度で２時間程度キュアすることにより、フィルム接着剤１１を硬化させる。以上の工程により、半導体素子１２の固着が行われる。
【００２３】
図６を参照して、ワイヤボンディングを行うことにより、半導体素子２０の表面に形成された電極と導電路３２とを、金属細線３３で電気的に結合する。半導体素子１２は、一定の厚みでフィルム接着剤１１により実装されているので、半導体素子１２の表面に形成された電極の位置の縦方向および横方向の変動量は少ない。従って、ワイヤボンディングを安定して行うことができる。この後に、封止を行う工程等を経て、半導体素子１２を内蔵する回路装置が製造される。
【００２４】
【発明の効果】
本発明の回路装置の製造法によれば、プラズマ洗浄により半導体ウェハ１０の裏面に付着した付着物を除去することにより、裏面にフィルム接着剤１１が密着した半導体素子１２をダイシングシート２６からピックアップする工程に於いて、フィルム接着剤１１を半導体素子１２裏面に転写することができる。具体的には、プラズマ照射を行わない場合、半導体素子１２をダイシングシート２６からピックアップする工程で、フィルム接着剤１１がダイシングシート２６に残ってしまう確率が０．４％程度であった。それに対して、本発明では、ウェハ１０のプラズマ洗浄を行うことにより、フィルム接着剤１１がダイシングシート２６に残ってしまう確率を０％にすることができた。
【００２５】
また、フィルム接着剤１１を用いた半導体素子１２の実装が確実に行われたことにより、ワイヤボンディングの工程に於いても、歩溜まりを向上させることができた。
【００２６】
更にまた、プラズマ洗浄を行う工程に於いて、ソースガスとして酸素ガスを用いることにより、半導体ウェハ１０の表面および裏面に付着した有機性の付着物を除去できると同時に、プラズマ洗浄により半導体ウェハ１０のメタル部分が痛んでしまうのを防止することができた。
【図面の簡単な説明】
【図１】本発明の半導体装置の製造方法を説明する断面図である。
【図２】本発明の半導体装置の製造方法を説明する平面図（Ａ）、断面図（Ｂ）である。
【図３】本発明の半導体装置の製造方法を説明する断面図である。
【図４】本発明の半導体装置の製造方法を説明する断面図である。
【図５】本発明の半導体装置の製造方法を説明する断面図である。
【図６】本発明の半導体装置の製造方法を説明する断面図である。
【図７】従来の半導体装置の製造方法を説明する断面図である。
【図８】従来の半導体装置の製造方法を説明する断面図である。
【符号の説明】
１０ 半導体ウェハ
１１ フィルム接着剤
１２ 半導体素子
２０ プラズマ洗浄機[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a circuit device capable of improving the yield of a die bonding process and a wire bonding process by cleaning a semiconductor wafer using plasma irradiation.
[0002]
[Prior art]
With reference to FIGS. 7 and 8, a method for manufacturing a conventional circuit device will be described. A circuit device incorporating a general semiconductor is manufactured by the following steps. First, a semiconductor wafer made of silicon, gallium, arsenic, or the like is attached to a dicing sheet, and cut into individual semiconductor elements by dicing. Next, the semiconductor element is picked up, mounted on a lead frame or a substrate, and is electrically connected. Finally, a circuit device having a semiconductor element is manufactured by being sealed with an insulating resin or the like.
[0003]
The step of picking up the semiconductor element 100 will be described with reference to FIG. A semiconductor wafer is attached to a dicing sheet 101 placed on the pedestal 104, and is divided into individual semiconductor elements 100 by dicing in a lattice shape. First, the back surface of the dicing sheet 101 where the semiconductor element 100 to be picked up is placed is pushed up by a push-up rod 105 mounted on a pedestal 104. As a result, the bonding area between the back surface of the semiconductor element 100 and the dicing sheet 101 is reduced, and the bonding strength between the two is reduced. Next, the semiconductor element 100 is adsorbed and transported by the collet 103 having an adsorbing force.
[0004]
Referring to FIG. 8, semiconductor element 100 that has been sucked and transported by collet 103 is mounted on a mounting surface. Specifically, it is fixed to a conductive path or the like formed on the surface of the mounting substrate 106 via an insulating adhesive 107 or the like. Thereafter, a packaged circuit device has been manufactured through a process of performing electrical connection with a thin metal wire, a process of performing sealing, and the like.
[0005]
However, when the semiconductor element 100 is of a small size such as for mobile use, it may be difficult to apply an appropriate amount of the insulating adhesive 107. For this reason, it has been proposed to use a film-like adhesive (diattach sheet) instead of a liquid adhesive (for example, see Patent Document 1). That is, the mounting process is performed by bonding the semiconductor wafer to the dicing sheet 101 via the die attach sheet, performing dicing including the die attach sheet, and mounting the semiconductor element 100 with the die attach sheet. . Thereafter, the die attach sheet is heated to increase the adhesive force, and the semiconductor element 100 and the mounting surface can be bonded.
[0006]
[Patent Document 1]
JP 2002-294177 A
[Problems to be solved by the invention]
However, in the method of mounting the semiconductor element 100 using the die attach sheet, in the step of picking up the semiconductor element 100 adhered to the dicing sheet 101 via the die attach sheet, the die attach There is a problem that the sheet is not transferred and the diattach sheet remains on the dicing sheet 101. When the die attach sheet is picked up without being transferred to the back surface of the semiconductor element 100, there is a problem that the semiconductor element 100 is not fixed in the die bonding process. Furthermore, even if the die attach sheet is partially transferred and the die bonding process is performed, the semiconductor element 100 is not fixed in a stable state, and the fine metal wires are not connected properly in the wire bonding process. Occurs.
[0008]
The above-mentioned problems have been particularly noticeable in semiconductor wafers imported from overseas or stored for a long time. The cause is that when semiconductor wafers are stored or transported, many sheets are stacked and packed via interlayer paper, and organic chemicals contained in the interlayer paper adhere to the semiconductor wafer. is there. For this reason, the bonding strength between the semiconductor wafer and the die attach sheet has not been sufficiently ensured, and the above-described problems have frequently occurred.
[0009]
The present invention has been made in view of the above-described problems, and a main object of the present invention is to clean a semiconductor wafer by plasma irradiation to securely apply a film adhesive such as a die attach sheet to the back surface of a semiconductor element. It is an object of the present invention to provide a method for manufacturing a circuit device capable of transferring.
[0010]
[Means for Solving the Problems]
The method for manufacturing a circuit device according to the present invention includes the steps of: removing a deposit on a surface of the semiconductor wafer by plasma cleaning; attaching a semiconductor wafer to a dicing sheet via a film adhesive; Dicing the semiconductor wafer including the semiconductor wafer into individual semiconductor elements, picking up the semiconductor elements with the film adhesive remaining on the back surface, and mounting the semiconductor elements via the film adhesive. And a mounting step.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
With reference to FIGS. 1 to 6, a method for manufacturing a circuit device according to the present invention will be described. In the first step, referring to FIG. 1, the semiconductor wafer 10 is subjected to plasma cleaning to remove deposits on its surface.
[0012]
First, the configuration of the plasma cleaning machine 20 will be described. The inside of the plasma cleaning machine 20 is hermetically sealed by a housing, a plasma source gas is supplied from a supply unit 21 to the inside, and a plasma source gas that has undergone a plasma reaction is exhausted by an exhaust unit 22. Further, a table-like first electrode 23A and a second electrode 23B are provided inside the plasma cleaning machine 20, one of the electrodes is connected to a high-frequency power source, and the other electrode is grounded. Here, the first electrode 23A is connected to a high-frequency power supply, and the second electrode 23B is grounded. Therefore, the source gas in a region sandwiched between the first electrode 23A and the second electrode 23B becomes plasma, and exhibits a cleaning ability.
[0013]
The semiconductor wafer 10 subjected to the plasma cleaning in this step is housed in the magazine 24 and placed on the second electrode 23B. The magazine 24 is made of an insulating material in order to prevent conduction between the semiconductor wafer 10 and the second electrode 23B. A plurality of the semiconductor wafers 10 are placed in a magazine 24 in a line in the vertical direction, and the direction of the main surface of the semiconductor wafer 10 is adjusted to the direction in which the source gas flows along the surface.
[0014]
In the method of cleaning the semiconductor wafer 10 by plasma, first, a source gas is introduced from the supply unit 21 into the plasma cleaning machine 20. Here, an oxygen gas is used as a source gas in order to remove organic deposits attached to the surface of the semiconductor wafer 10. As the source gas, another gas such as argon or helium can be used. Next, by applying a high-frequency current to the first electrode 23A, a plasma is generated in a region sandwiched between the first electrode 23A and the second electrode 23B, and the front and back surfaces of the semiconductor wafer 10 are cleaned. Do. The oxygen gas that has reacted with the deposits attached to the front and back surfaces of the semiconductor wafer 10 becomes carbon dioxide and is discharged from the exhaust unit 22 to the outside. Further, instead of the above-described plasma cleaning, it is also possible to remove organic deposits adhered to the semiconductor wafer 10 by irradiating ultraviolet rays.
[0015]
In the second step, referring to FIG. 2, the semiconductor wafer 10 is attached to the dicing sheet 26 via the film adhesive 11 and the semiconductor wafer 10 including the film adhesive 11 is diced to separate the individual semiconductor elements 12. To be separated.
[0016]
Referring to FIG. 2 (A), dicing sheet 26 is connected to metal frame 25 formed in a frame shape, and semiconductor wafer 10 is attached to the vicinity of the center of dicing sheet 26 via film adhesive 11. Can be
[0017]
Referring to FIG. 2B, dicing is performed in a lattice shape to divide semiconductor wafer 10 into respective semiconductor elements 12. The dicing here is performed to a depth at which the semiconductor wafer 10 and the film adhesive 11 are divided, and the dicing may be performed to the surface of the dicing sheet 26. Further, after dicing or prior to the dicing step, the film adhesive 11 is irradiated with ultraviolet rays from the back surface of the dicing sheet 26. Thus, the elasticity of the film adhesive 11 can be improved, and the transfer of the film adhesive 11 to the back surface of the semiconductor element 12 can be improved in a later step. This is because the improvement in the elastic modulus can prevent the film adhesive 11 from partially remaining on the dicing sheet.
[0018]
The third step is to pick up the semiconductor element 12 having the film adhesive 11 remaining on the back surface with reference to FIGS.
[0019]
First, referring to FIG. 3, dicing sheet 26 to which a semiconductor wafer is attached via film adhesive 11 is placed on pedestal 28. When the dicing sheet 26 is pulled in the peripheral direction, a gap is formed between the semiconductor elements 12. The dicing sheet 26 at a location corresponding to the semiconductor element 12 to be picked up is pushed up by a push-up rod 29 mounted on a pedestal 28, so that the dicing sheet 26 is locally lifted. As a result, the bonding area between the back surface of the film adhesive 11 adhered to the back surface of the semiconductor element 12 to be picked up and the dicing sheet 26 can be reduced, so that the bonding strength between the two can be reduced.
[0020]
Next, referring to FIG. 4, the surface of the semiconductor element 12 pushed up by the push-up rod 29 is sucked by the collet 30 having an attraction force, and the semiconductor element 12 to which the film adhesive 11 is transferred to the back surface is sucked. Since the back surface of the semiconductor element 12 has been cleaned in the first step described above, the adhesion strength between the back surface of the semiconductor element 12 and the film adhesive 11 is sufficiently ensured. Therefore, in the step of picking up the semiconductor element 12, the film adhesive 11 to be transferred to the back surface of the semiconductor element 12 can be prevented from remaining on the dicing sheet 26. Further, it is possible to prevent the film adhesive 11 from partially remaining on the dicing sheet 26.
[0021]
The fourth step is to mount the semiconductor element 12 on the mounting surface via the film adhesive 11 with reference to FIGS.
[0022]
The semiconductor element 12 with the film adhesive 11 transferred to the back surface is mounted on a mounting surface by the collet 30. Here, it is mounted on the conductive path on the mounting board 31, but the mounting surface may be a lead frame or the like. Here, the film adhesive 11 functions as an adhesive for mounting the semiconductor element 12. The mounted semiconductor element 12 is temporarily press-bonded and pressed at a temperature of about 120 ° C., so that the back surface of the film adhesive 11 adheres to the unevenness of the mounting surface. Thereafter, the film adhesive 11 is cured by curing at a temperature of about 160 ° C. for about 2 hours. Through the above steps, the semiconductor element 12 is fixed.
[0023]
Referring to FIG. 6, by performing wire bonding, the electrode formed on the surface of semiconductor element 20 and conductive path 32 are electrically coupled by thin metal wire 33. Since the semiconductor element 12 is mounted with the film adhesive 11 with a constant thickness, the amount of fluctuation in the vertical and horizontal directions of the positions of the electrodes formed on the surface of the semiconductor element 12 is small. Therefore, wire bonding can be performed stably. Thereafter, a circuit device incorporating the semiconductor element 12 is manufactured through a sealing step and the like.
[0024]
【The invention's effect】
According to the method of manufacturing a circuit device of the present invention, the semiconductor elements 12 having the film adhesive 11 adhered to the back surface are picked up from the dicing sheet 26 by removing the deposits adhered to the back surface of the semiconductor wafer 10 by plasma cleaning. In the process, the film adhesive 11 can be transferred to the back surface of the semiconductor element 12. Specifically, when plasma irradiation is not performed, the probability that the film adhesive 11 remains on the dicing sheet 26 in the step of picking up the semiconductor element 12 from the dicing sheet 26 is about 0.4%. On the other hand, in the present invention, the probability that the film adhesive 11 remains on the dicing sheet 26 can be reduced to 0% by performing the plasma cleaning of the wafer 10.
[0025]
Further, since the semiconductor element 12 was securely mounted using the film adhesive 11, the yield could be improved in the wire bonding step.
[0026]
Furthermore, in the step of performing the plasma cleaning, by using an oxygen gas as a source gas, it is possible to remove organic deposits adhering to the front surface and the back surface of the semiconductor wafer 10 and, at the same time, to clean the semiconductor wafer 10 by the plasma cleaning. It was possible to prevent the metal part from being damaged.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
2A and 2B are a plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 5 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;
FIG. 6 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;
FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.
FIG. 8 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 11 Film adhesive 12 Semiconductor element 20 Plasma cleaning machine

Claims (4)

半導体ウェハをプラズマ洗浄することによりその表面の付着物を除去する工程と、
フィルム接着剤を介して半導体ウェハをダイシングシートに貼り付ける工程と、
前記フィルム接着剤も含めて前記半導体ウェハをダイシングして個別の半導体素子に切り離す工程と、
前記フィルム接着剤が裏面に残存した前記半導体素子をピックアップする工程と、
前記フィルム接着剤を介して前記半導体素子を実装面に実装する工程とを具備することを特徴とする半導体装置の製造方法。A step of removing deposits on the surface of the semiconductor wafer by plasma cleaning;
Attaching a semiconductor wafer to the dicing sheet via a film adhesive,
Dicing the semiconductor wafer, including the film adhesive, to separate individual semiconductor elements,
A step of picking up the semiconductor element in which the film adhesive remains on the back surface,
Mounting the semiconductor element on a mounting surface via the film adhesive. 酸素ガスを用いて前記プラズマ洗浄を行うことを特徴とする請求項１記載の半導体装置の製造方法。2. The method according to claim 1, wherein said plasma cleaning is performed using oxygen gas. 前記プラズマを行う工程では、前記半導体ウェハはプラズマ洗浄機内部に縦方向に載置され、前記半導体ウェハの主面に沿ってソースガスを移動させることを特徴とする請求項１記載の半導体装置の製造方法。2. The semiconductor device according to claim 1, wherein in the step of performing the plasma, the semiconductor wafer is placed in a vertical direction inside a plasma cleaning machine, and a source gas is moved along a main surface of the semiconductor wafer. 3. Production method. 前記半導体ウェハを貼り付けた後に、前記フィルム接着剤に紫外線を照射することにより、前記フィルム接着剤の弾性率を向上させることを特徴とする請求項１記載の半導体装置の製造方法。The method according to claim 1, wherein, after attaching the semiconductor wafer, the film adhesive is irradiated with ultraviolet rays to improve the elasticity of the film adhesive.
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WO2007091670A1 (en) * 2006-02-10 2007-08-16 Tokyo Seimitsu Co., Ltd. Apparatus and method for processing wafer
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WO2007099787A1 (en) * 2006-03-03 2007-09-07 Tokyo Seimitsu Co., Ltd. Wafer processing method
JP2008205387A (en) * 2007-02-22 2008-09-04 Tokyo Ohka Kogyo Co Ltd Treatment method of support plate
JP2012156553A (en) * 2012-05-10 2012-08-16 Tokyo Ohka Kogyo Co Ltd Support plate processing method
US8492256B2 (en) 2010-04-14 2013-07-23 Fuji Electric Co., Ltd. Method of manufacturing semiconductor apparatus
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JP2015233066A (en) * 2014-06-09 2015-12-24 株式会社ディスコ Method for dividing plate-like object
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Cited By (14)

* Cited by examiner, † Cited by third party
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WO2007091670A1 (en) * 2006-02-10 2007-08-16 Tokyo Seimitsu Co., Ltd. Apparatus and method for processing wafer
US7981770B2 (en) 2006-03-03 2011-07-19 Tokyo Seimitsu Co., Ltd. Wafer machining method for preparing a wafer for dicing
WO2007099787A1 (en) * 2006-03-03 2007-09-07 Tokyo Seimitsu Co., Ltd. Wafer processing method
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JP2008205387A (en) * 2007-02-22 2008-09-04 Tokyo Ohka Kogyo Co Ltd Treatment method of support plate
US8492256B2 (en) 2010-04-14 2013-07-23 Fuji Electric Co., Ltd. Method of manufacturing semiconductor apparatus
TWI489537B (en) * 2011-03-23 2015-06-21 Hitachi High Tech Instr Co Ltd Wafer picking machine picking method and wafer bonding machine
US9343338B2 (en) 2011-03-23 2016-05-17 Fasford Technology Co., Ltd. Pick-up method of die bonder and die bonder
JP2012156553A (en) * 2012-05-10 2012-08-16 Tokyo Ohka Kogyo Co Ltd Support plate processing method
JP2015233066A (en) * 2014-06-09 2015-12-24 株式会社ディスコ Method for dividing plate-like object
JP5887633B1 (en) * 2014-10-02 2016-03-16 富士ゼロックス株式会社 Manufacturing method of semiconductor piece
JP2018041823A (en) * 2016-09-07 2018-03-15 株式会社ディスコ Tape pasting method

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