JP2004222088A - W-cdma base station device delay control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize variance compensation of data delay among reception-side panels in a W-CDMA base station device by a relatively small circuit scale. <P>SOLUTION: Delay amounts of transmission lines between a down transmission-side panel 101 and a plurality of down reception-side panels 102 are preliminarily measured by the plurality of down reception-side panels 102 respectively and are transmitted from respective down reception-side panels 102 to the down transmission-side panel 101, and synchronizing signals to be inputted to corresponding spreading units 104 in the down transmission-side panel 101 are controlled by a synchronizing signal control circuit 108 in accordance with the transmitted delay amounts, and spreading timings of spreading units 104 corresponding to respective down reception-side panels 102 are shifted to absorb the delay variance of down reception data among the plurality of down reception-side panels 102. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a W-CDMA (Wideband-Code Division Multiple Access) base station apparatus, and more particularly, to a downlink transmission side panel (spreading multiplex panel) installed in a base station and a service area of the base station. Control technology in a W-CDMA base station apparatus in which downlink receiving panels (modulation / demodulation and power amplification panels) respectively installed on a plurality of antennas are connected by a cable through an LVDS (Low Voltage Differential Signaling) signal. About.
[0002]
[Prior art]
A W-CDMA base station apparatus usually includes a base station and a plurality of antennas arranged at different positions in the service area of the base station. The base station has one transmission-side panel (spread multiplexing). Panel, and a receiving panel (modulation / demodulation, power amplification panel) is provided for each antenna. The transmission side panel of the base station and the reception side panel of each antenna are connected by a cable that passes a bidirectional high-speed digital signal by LVDS or optical communication.
[0003]
When high-speed digital communication is performed between a single transmitting-side panel and a plurality of receiving-side panels, the base-band signal has a delay variation due to various factors such as a large difference in connection distance between the panels and a cable condition. Will occur. If the system is capable of performing subsequent processing while maintaining temporal variations in signals processed by a plurality of receiving panels, there is no problem if delay variations occur. For example, diversity transmission or IPDL (Idle Period) In the case of a system such as a Down Link service in which the subsequent processing must not be performed while retaining the delay variation of data between the receiving panels, a circuit for correcting the generated delay must be added.
[0004]
Conventionally, in a mobile communication system including a master base station and a plurality of slave base stations connected to a public line network, and a plurality of mobile terminal stations communicating via these slave base stations, each slave base station includes: The provision of means for synchronizing the transmission timing of the slave base station with the transmission timing of the master base station corrects variations in propagation delay between the base stations (for example, see Patent Document 1). Also in the base station apparatus, a circuit for correcting the delay variation between the antennas on which the receiving-side panels (modulation / demodulation and power amplification panels) are installed is arranged at the receiving-side reception port, and the delay variation of each receiving panel is reduced. There has been proposed a method of performing correction and suppressing variation between receiving panels.
[0005]
FIG. 3 is a block diagram illustrating an example of a conventional delay amount correction system of a W-CDMA base station device.
[0006]
In FIG. 3, in the W-CDMA base station apparatus, one downlink transmission side panel (spreading multiplex panel) 201 and a plurality of downlink reception side panels (modulation / demodulation, power amplification panels) 202 are each LVDS (Low). They are connected by cables 203 and 216 that pass a voltage differential signaling (Voltage Differential Signaling) signal.
[0007]
In the downlink transmitting side panel (spreading multiplexing panel) 201, the downlink signal transmitting side takes into account channelization code spreading processing, scrambling spreading processing, and amplitude data that gives amplitude to the spread signal, by applying data input from a higher-level device. A spreader unit 204 that performs user multiplexing of the obtained data and outputs a baseband signal of a frame synchronization signal, and a serializer (Ser) that converts a parallel signal output from the spreader unit 204 into a serial signal and outputs the serial signal to the cable 203 A receiving unit 202 that receives a serial signal input from the receiving panel 202 via the cable 216, performs serial / parallel conversion, and transmits the converted parallel signal to the despreader on the host device side. A deserializer (Des) unit 206 for outputting is provided.
[0008]
Downlink receiving-side panels (modulation / demodulation, power amplification panels) 202 convert downlink transmission serial data input from a downlink transmission-side panel (spreading multiplexing panel) 201 via a cable 203 into parallel data. A deserializer (Des) unit 209 for conversion, a FIFO memory 210 for temporarily storing the converted parallel data, and a delay amount for transmission data read from the FIFO memory 210 by measuring a delay amount of transmission data received from the downlink transmission side panel. , A pointer control unit 212 that controls Read / Write of the FIFO memory 210 by a control signal from the delay control circuit 211, and modulates spread data received from the downlink transmission panel 201. The modulation circuit unit 214 demodulates the received uplink signal. Cormorant a demodulation circuit 215, and a serializer (Ser) portion 217 for converting the parallel upstream data input from the demodulation circuit 215 into serial data to the cable 216.
[0009]
The spread data output from the downlink transmission side panel 201 is input to the downlink reception side panel 202 via the cable 203, is input to the deserializer (Des) unit 209, and is subjected to the serial / parallel conversion processing, and the original transmission speed is obtained. And output to the output modulation circuit 214 as a parallel baseband signal. If there is a delay variation due to a factor such as the length of each cable 203, a delay variation occurs in transmission data between the downlink receiving panels 202 when the serial / parallel conversion processing is performed here.
[0010]
In order to measure the delay variation, the parallel signal output from the deserializer (Des) unit 209 is also input to the delay control circuit unit 211. The delay control circuit 211 determines the amount of delay of the transmission data and how much to delay the downlink data, and outputs the result to the pointer control unit 212. The pointer control unit 212 controls the Read / Write signal of the FIFO memory 210, thereby controlling the delay amount of the transmission parallel data output from the FIFO memory, thereby absorbing the variation in the delay amount between the receiving panels 202. I do.
[0011]
[Patent Document 1]
JP-A-9-148978
[Problems to be solved by the invention]
In the above conventional example, when designing the receiving side panel 202, if the variation of the delay amount is assumed to be small and the capacity of the FIFO memory 210 is too small, the delay variation may not be absorbed. For this reason, it is necessary to install a FIFO memory 210 having a sufficient number of stages to absorb the maximum delay amount that can occur in the entire system even for a system having a connection relationship in which little delay occurs. However, there is a problem that the circuit scale of the receiving side panel 202 increases.
[0013]
As described above, when a circuit for delay correction is provided on the receiving side panel, it is necessary to provide a memory device such as a FIFO memory for temporarily storing transmission data, and in that case, transmitted data becomes large. When the delay difference between the panels increases, the capacity of the FIFO memory must be designed to be large. In addition, it is necessary to arrange a circuit for correction for each receiving panel, and there is a problem that the larger the number of connected receiving panels, the larger the overall circuit scale becomes.
[0014]
SUMMARY OF THE INVENTION An object of the present invention is to provide a W-CDMA base station apparatus for performing high-speed digital communication between one transmitting panel and a plurality of receiving panels in order to correct the data delay variation among the receiving panels. In a relatively small circuit scale.
[0015]
[Means for Solving the Problems]
The present invention relates to a system for performing bidirectional high-speed digital signal transmission such as LVDS or optical communication between one downlink transmitting panel and a plurality of downlink receiving panels in a W-CDMA base station. When there is delay variation in downlink reception data, the delay amount of the transmission path to each downlink reception panel is measured in advance by each downlink reception panel, and the measured delay amount is downlinked from each downlink reception panel. By delaying the spread timing of the spread signal transmitted to the transmitting panel and output to each downlink receiving panel in the downlink transmitting panel according to the delay amount received from each downlink receiving panel, the delay in the downlink receiving panel is delayed. It is characterized by receiving data at a common timing without correcting the amount.
[0016]
By using the present invention, it is possible to reduce the circuit scale (FIFO memory and the like) for delay correction required for the downlink receiving side panel.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a W-CDMA base station apparatus delay control circuit of the present invention.
[0018]
In the W-CDMA base station, one downlink transmitting side panel (spreading multiplex panel) 101 and a plurality of downlink receiving side panels (modulation / demodulation, power amplification panels) 102 are connected to LVDS or optical communication cables 103 and 116. Connected.
[0019]
In the downlink transmission-side panel (spreading multiplex panel) 101, the downlink signal transmission side takes into account channelization code spreading processing, scrambling spreading processing, and amplitude data that gives amplitude to the spread signal, by inputting data input from a higher-level device. A spreader unit 104 that performs user multiplexing of the obtained data and outputs a baseband signal of a frame synchronization signal, and a serializer (Ser) that performs parallel / serial conversion of a parallel signal input from the spreader unit 104 and outputs the converted signal to a cable 103 It comprises a unit 105.
[0020]
The upstream signal receiving side receives a serial upstream signal input from the receiving side panel 102 via the cable 116 and performs a serial / parallel conversion on a deserializer (Des) unit 106 and a signal received by the downstream transmitting side panel 102. And a control circuit 108 for individually shifting the intra-base station synchronization signal for each spreader according to the delay amount data transmitted from the downlink receiving panel 102. The control circuit 108 also includes a buffer unit for storing the amount of delay measured and transmitted by the downlink receiving panel 102.
[0021]
A downlink receiving side panel (modulation / demodulation, power amplification panel) 102 is a deserializer (Des) unit 109 that performs serial / parallel conversion of downlink transmission serial data input from the downlink transmission side panel (spreading multiplex panel) 101 to parallel data. And a "down-going inter-panel synchronization signal" input to each of the receiving panels 102 at a common timing, and the bit width is sufficient to absorb the delay amount between the panels. A counter 110, a frame synchronization Bit Detect section 111 for detecting a frame synchronization position added by the spreader 104 of the downlink transmission panel from a frame synchronization Bit input from the downlink transmission panel 101, and a frame synchronization Bit Detect section 111 The input serial frame synchronization bit and the counter 110 The frame synchronization Bit position acquisition unit 112 detects the position of the input frame synchronization bit by comparing the input frame synchronization bit with the counter value, and outputs the detected counter value, and the frame synchronization bit detected by the frame synchronization bit position acquisition unit 112. A selector unit 113 for selecting position information and an uplink signal; a serializer (Ser) unit 117 for performing parallel / serial conversion of parallel uplink data input from the selector unit 113; It comprises a modulation circuit section 114 for performing modulation and a demodulation circuit section 115 for demodulating a received uplink signal.
[0022]
FIG. 2 is a flowchart showing an operation up to establishment of synchronization in the embodiment of the present invention. Hereinafter, the operation of the embodiment of the present invention will be described with reference to FIGS.
[0023]
After turning on the power to the downlink transmission side panel 101 and the downlink reception side panel 102, the following processing is performed before starting the original downlink and uplink data processing, and the transmission timing of the downlink transmission side panel 101 is shifted, and each downlink is transmitted. The reception timings between the receiving panels 102 are aligned.
[0024]
In the downlink transmitting side panel 101, first, an intra-base station synchronization signal input to the panel is input to the spreader 104. Spreader 104 inserts a frame synchronization signal into one bit of the originally output parallel signal, and inserts and outputs ALL “0” into the remaining bits. The parallel signal output from the spreader 104 is input to a serializer (Ser) unit 105 and is converted into a serial signal by parallel / serial conversion, and is transmitted via a downlink data cable 103 connected to a predetermined downlink receiving panel 102. You.
[0025]
On the other hand, after the power is turned on, each of the downlink receiving side panels 102 starts counting up the counter 110 using the downlink receiving side inter-panel synchronization signal which is common to the downlink receiving side panels 102 as a load signal. The signal to which only the frame synchronization signal transmitted from the downlink transmitting side panel 101 described above is inserted is received by each downlink receiving side panel 102, and is subjected to serial / parallel conversion by the deserializer (Des) unit 109 to be returned to a parallel signal. Of the received parallel signals, only 1 bit in which the frame synchronization signal is inserted is extracted and input to the frame synchronization Bit Detect unit 111.
[0026]
The 1-bit signal input to the input frame synchronization Bit Detect section 111 detects the position of the frame synchronization Bit inserted in the transmission side panel 101 from the pattern inserted in the transmission side panel 101, and outputs the position. The output signal is input to the frame synchronization Bit position acquisition unit 112. The count value counted up by the counter 110 is input to the frame synchronization Bit position acquisition unit 112.
[0027]
The frame synchronization bit position acquisition unit 112 latches the count value input from the counter 110 when the frame synchronization signal detected by the frame synchronization bit detect unit 111 is input. The latched count value is the delay amount data. The latched signal (delay amount data) is input to the selector 113. Two types of data, delay amount data and uplink received data demodulated by the demodulation circuit unit 115, are input to the selector unit 113. During this synchronization establishment operation, the delay amount data is selected and the serializer (Ser) unit is selected. 117 is output.
[0028]
The parallel delay amount data input to the serializer (Ser) unit 117 is subjected to parallel / serial conversion and output to the upstream data cable 116. The upstream data cable 116 is connected to the deserializer (Des) unit 106 of the downstream transmitter panel 101, and the deserializer (Des) unit 106 converts the delay amount data that has been converted into a serial signal into a parallel signal.
[0029]
The delay amount data converted into the parallel signal is output to the selector 107. The selector 107 is a one-input two-output selector, and selects to output the delay amount data to the synchronization signal control unit 108 during the synchronization establishing operation, and to output the uplink reception data to the host device during the normal operation. I do.
[0030]
The synchronization signal control unit 108 has a table in which a value indicating how much the intra-base station synchronization signal is shifted with respect to the delay amount data transmitted from the receiving side panel 102 is written. , And outputs to the spreader 104 by shifting the intra-base station synchronization signal by the value written in the table.
[0031]
In the spreader 104, the synchronization signal that is input to the spreader 104 and serves as a reference for spreading is shifted, so that the spreading timing is shifted, and the parallel data to be transmitted is also shifted accordingly.
[0032]
The above operation is performed for the number of reception-side panels 102 connected to the transmission-side panel 101, and the synchronization signals input to the respective spreaders 104 are individually controlled according to the respective delay amount data. As a result, data received by the receiving panel 102 can be received at a common timing.
[0033]
After the above operation controls the synchronization signal input to each spreader 104 of the downlink transmission side panel 101, and each downlink reception side panel can receive at a common timing, the downlink transmission side panel 101 The selector 107 of the panel 101 and the selector 113 of the downlink receiving side panel 102 are switched and controlled so that the original operations of spreading, modulation and demodulation can be performed.
[0034]
The setting of the synchronization establishing operation in the present embodiment is performed when the operation of the W-CDMA base station device is started or when the W-CDMA base station device is added. Since the data is received at the timing, the operation can be performed in a state where the delay variation of the data between the receiving side panels is eliminated.
[0035]
【The invention's effect】
According to the present invention, the memory device on the receiving side and the memory control circuit are not required, so that the delay correction circuit required for the receiving side panel can be reduced, and each receiving side panel can be reduced with a relatively small circuit scale. It is possible to correct delay variation between the two.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a flowchart for explaining the operation of the present embodiment.
FIG. 3 is a block diagram showing a conventional example.
[Explanation of symbols]
101, 201 Downlink transmitting side panel (spreading multiplex panel)
102, 202 Downlink receiving side panel (modulation / demodulation, power amplification panel)
103, 116, 203, 216 Cables 104, 204 Spreaders 105, 117, 205, 217 Serializer (Ser) units 106, 109, 206, 209 Deserializer (Des) units 107, 113 Selector 108 Synchronous signal control circuit 110 Counter 111 Frame Synchronization Bit Detect section 112 Frame synchronization Bit position acquisition section 114, 214 Modulation circuits 115, 215 Demodulation circuit 210 FIFO memory 211 Delay control circuit 212 Pointer control section

Claims (8)

A W-CDMA base station apparatus that performs bidirectional high-speed digital signal transmission by LVDS or optical communication between one spread-multiplexing panel (downlink transmission panel) and a plurality of modulation / demodulation and power amplification panels (downlink reception panel). A delay control method,
The delay amount of the transmission path between the downlink transmission side panel and the plurality of downlink reception side panels is measured in advance by the plurality of downlink reception side panels, respectively, and the measured delay amount is measured by the downlink reception side panel from each of the downlink reception side panels. By transmitting to the transmitting panel, controlling the synchronization signal input to the corresponding spreader in the downlink transmitting panel by the delay amount, by shifting the spread timing of the spreader corresponding to each downlink receiving panel. A delay control method for a W-CDMA base station apparatus, wherein a delay variation of downlink reception data in the plurality of downlink reception-side panels is absorbed. Channelization code spreading processing and scrambling spreading processing of data input from a higher-level device, and user multiplexing of data including amplitude data that gives amplitude to the spread signal, and outputting a baseband signal of a frame synchronization signal. (N ≧ 2) spreaders, n first serializers each converting a parallel signal input from each spreader into a serial signal, and n modulation / demodulation and power amplification panels (downstream reception side) A spread multiplexing panel (downstream transmitting side panel) having n first deserializers which receive serial upstream signals input from the panel), convert the signals into parallel signals, and output the signals to the host device,
A second deserializer that converts down transmission serial data transmitted from the down transmission panel to parallel data, a modulation circuit that modulates the parallel data output from the second deserializer, Said n modulation / demodulation and power amplifying panels (downward receiving panels) each having a demodulation circuit for demodulating and a second serializer for converting the parallel data of the demodulated uplink signal into a serial signal;
In a delay control system of a W-CDMA base station device including n downlink data cables and uplink data cables for connecting the downlink transmission panel and the n downlink reception panels,
Each of the n downlink receiving panels measures a delay amount of a frame synchronization signal received from a corresponding spreader of the downlink transmitting panel, and transmits the measured delay amount data to the downlink transmitting panel. Equipped with a delay measuring means,
The downlink transmitting side panel receives the delay amount data measured by the downlink receiving side panel, and, based on the received delay amount data, spreads a base station synchronization signal supplied to the n spreaders. A W-CDMA base station apparatus delay control system, comprising n synchronization signal control means for performing control to shift each of them individually. The synchronization delay measuring means can load the signal by the “synchronization signal between downlink receiving panels” input at a common timing to the n downlink receiving panels to absorb the delay amount between the panels. A frame synchronization Bit Detect section for detecting a frame synchronization position added by the spreader from a frame synchronization Bit transmitted from the downlink transmission side panel, and a frame synchronization Bit Detect section A frame synchronization bit position acquisition unit that latches the count value input from the counter when the frame synchronization signal detected in step (b) is input, and outputs the latched count value as delay amount data; Two types of data of the uplink reception data demodulated by the demodulation circuit section are input, and the synchronization establishment operation is performed. The W-CDMA base station apparatus delay control system according to claim 2, further comprising a first selector that selects the delay amount data and outputs the selected data to the second serializer. The synchronization signal control means has a table in which a value of how much the intra-base station synchronization signal is shifted with respect to the delay amount data transmitted from the downlink reception side panel is written, and the input delay amount A synchronization signal control circuit that refers to the table based on data and shifts the synchronization signal in the base station by the value written in the table to output to the spreader, and via the first deserializer during synchronization establishment operation The W-CDMA base station apparatus delay control system according to claim 2, further comprising a second selector configured to output the input delay amount data to the synchronization signal control circuit. . Channelization code spreading processing and scrambling spreading processing of data input from a higher-level device, and user multiplexing of data including amplitude data that gives amplitude to the spread signal, and outputting a baseband signal of a frame synchronization signal. (N ≧ 2) spreaders, n first serializers each converting a parallel signal input from each spreader into a serial signal, and n modulation / demodulation and power amplification panels (downstream reception side) A spread multiplexing panel (downstream transmitting side panel) having n first deserializers which receive serial upstream signals input from the panel), convert the signals into parallel signals, and output the signals to the host device,
A second deserializer that converts down transmission serial data transmitted from the down transmission panel to parallel data, a modulation circuit that modulates the parallel data output from the second deserializer, Said n modulation / demodulation and power amplifying panels (downward receiving panels) each having a demodulation circuit for demodulating and a second serializer for converting the parallel data of the demodulated uplink signal into a serial signal;
The downlink reception used in a delay control system of a W-CDMA base station apparatus including n downlink data cables and uplink data cables for connecting the downlink transmission panel and the n downlink reception panels. The side panel,
A synchronization delay measuring means for measuring a delay amount of a frame synchronization signal received from a corresponding spreader of the downlink transmission side panel and transmitting the measured delay amount data to the downlink transmission side panel. Downlink receiving side panel. The synchronization delay measuring means can load the signal by the “synchronization signal between downlink receiving panels” input at a common timing to the n downlink receiving panels to absorb the delay amount between the panels. A frame synchronization Bit Detect section for detecting a frame synchronization position added by the spreader from a frame synchronization Bit transmitted from the downlink transmission side panel, and a frame synchronization Bit Detect section A frame synchronization bit position acquisition unit that latches the count value input from the counter when the frame synchronization signal detected in step (b) is input, and outputs the latched count value as delay amount data; Two types of data of the uplink reception data demodulated by the demodulation circuit section are input, and the synchronization establishment operation is performed. The downlink receiving side panel according to claim 5, further comprising: a selector for selecting delay amount data and outputting the selected data to the second serializer. Channelization code spreading processing and scrambling spreading processing of data input from a higher-level device, and user multiplexing of data including amplitude data that gives amplitude to the spread signal, and outputting a baseband signal of a frame synchronization signal. (N ≧ 2) spreaders, n first serializers each converting a parallel signal input from each spreader into a serial signal, and n modulation / demodulation and power amplification panels (downstream reception side) A spread multiplexing panel (downstream transmitting side panel) having n first deserializers which receive serial upstream signals input from the panel), convert the signals into parallel signals, and output the signals to the host device,
A second deserializer that converts down transmission serial data transmitted from the down transmission panel to parallel data, a modulation circuit that modulates the parallel data output from the second deserializer, Said n modulation / demodulation and power amplifying panels (downward receiving panels) each having a demodulation circuit for demodulating and a second serializer for converting the parallel data of the demodulated uplink signal into a serial signal;
The downlink transmission used in a delay control system of a W-CDMA base station apparatus including n downlink data cables and uplink data cables for connecting the downlink transmission panel and the n downlink reception panels. The side panel,
The delay amount data measured by the downlink receiving side panel is received, and based on the received delay amount data, control is performed to shift the synchronization signal in the base station supplied to the n spreaders individually for each spreader. A downlink transmitting side panel comprising n pieces of synchronization signal control means. The synchronization signal control means has a table in which a value of how much the intra-base station synchronization signal is shifted with respect to the delay amount data transmitted from the downlink reception side panel is written, and the input delay amount A synchronization signal control circuit that refers to the table based on data and shifts the synchronization signal in the base station by the value written in the table to output to the spreader, and via the first deserializer during synchronization establishment operation The downlink transmission side panel according to claim 7, further comprising: a selector for outputting the input delay amount data to the synchronization signal control circuit.

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