JP2004219712A - Wiring structure for display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a remarkable deterioration in reliability of wiring due to corrosion. <P>SOLUTION: Wiring structure for a display panel is provided with an array substrate AR and a wiring part W electrically and mutually connecting two terminals in the array substrate AR. The wiring part W, in particular, comprises a first conductor layer W1 formed on the array substrate AR, an insulating film 7 formed on the first conductor layer W1 and a second conductor layer W2. The second conductor layer W2 is formed on the insulating film 7 in a manner that the second conductor layer W2 is superposed on the first conductor layer W1, is joined to the first conductor layer W1 in both end regions adjacent to the two terminals connected by at least the wiring part W and insulated from the first conductor layer W1 by the insulating film 7 at the part except these joining parts. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a flat display device incorporated in a mobile device used, for example, indoors and outdoors, and more particularly to a wiring structure for a display panel of the flat display device.
[0002]
[Prior art]
In recent years, a liquid crystal display device is a flat display device having excellent features such as thinness, light weight, and low power consumption, and is used in a mobile device such as a PDA (Personal Digital Assistance) or a mobile phone integrated with the PDA. Have been.
[0003]
Generally, a liquid crystal display device has a liquid crystal display panel having a structure in which a liquid crystal layer is sandwiched between a pair of display panel substrates, that is, an array substrate and a counter substrate. In an active matrix type liquid crystal display panel, an array substrate is formed of a thin film transistor (TFT: Thin Film Transistor) formed on a glass substrate using amorphous silicon or polysilicon semiconductor, and the switching element is formed on the glass substrate. It has a connected pixel electrode, a scanning line, and a signal line, and the counter substrate has a counter electrode formed over a glass substrate. The array substrate and the counter substrate are bonded together with an adhesive disposed along the outer edge of the substrate as an outer edge sealing member for sealing the liquid crystal material.
[0004]
By the way, the number of users of mobile devices has been increasing rapidly in recent years, and accordingly, further reduction in the weight and thickness of liquid crystal display panels has been required. In order to meet this demand, the scanning line driving circuit and the signal line driving circuit are sometimes built in the array substrate. Since the signal line driver circuit must operate at a higher speed than the scan line driver circuit, the signal line driver circuit is formed, for example, as an IC chip and mounted on an array substrate by COG (Chip On Glass) technology. Here, the signal line driving circuit and the scanning line driving circuit are connected to an external control circuit via an external connection (OLB: Outer Lead Bonding) pad arranged on the outer edge of the array substrate. The external connection pads and the drive circuit are generally interconnected by a single-layer wiring, but may be interconnected by a multilayer wiring in which two conductor layers are stacked (for example, see Patent Document 1). . The single-layer wiring has a higher resistance than the multi-layer wiring and has a high possibility of disconnection, so that the yield is reduced.
[0005]
[Patent Document 1]
JP 2002-258768 A
[Problems to be solved by the invention]
However, conventional multilayer wiring is not sufficiently resistant to corrosion. For example, if corrosion occurs on one of the conductor layers on the side of the external connection pad, the corrosion is likely to proceed to the other conductor layer immediately, resulting in disconnection. This significantly deteriorates the reliability of the wiring.
[0007]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a display panel wiring structure that can prevent the reliability of wiring from being significantly deteriorated by corrosion.
[0008]
[Means for Solving the Problems]
According to the present invention, there is provided a display panel substrate, and a wiring portion for electrically interconnecting two terminals in the display panel substrate, wherein the wiring portion includes a first conductor layer formed on the display panel substrate, An insulating film formed on the first conductive layer, and a first conductive film formed on the insulating film so as to overlap the first conductive layer, at least in both end regions adjacent to two terminals connected by the wiring portion. There is provided a wiring structure for a display panel including a second conductor layer joined to a body layer and insulated from the first conductor layer by an insulating film at an area other than these joints.
[0009]
In this display panel wiring structure, the second conductor layer is joined to the first conductor layer at least in both end regions adjacent to the two terminals connected by the wiring portion, and the first conductor is attached to the first conductor layer by an insulating film except at these joint portions. Since it is insulated from the layer, a lower wiring resistance and a higher yield can be obtained as compared with the case where one of the first and second conductor layers is used as the wiring portion. Further, even if the second conductor layer is corroded, the first conductor layer and the second conductor layer are partially joined to each other instead of the entire region where the first conductor layer and the second conductor layer overlap. Breakage due to corrosion that progresses in one conductor layer can be suppressed. Therefore, it is possible to prevent the reliability of the wiring from being significantly degraded due to corrosion.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings. This liquid crystal display device is a flat display device incorporated as an image monitor in a mobile device such as a PDA (Personal Digital Assistance).
[0011]
FIG. 1 schematically shows the appearance of a liquid crystal display panel of the liquid crystal display device, and FIG. 2 shows a schematic circuit structure of the liquid crystal display device shown in FIG. This liquid crystal display device includes a liquid crystal display panel 1 and an external control circuit 2 for controlling the liquid crystal display panel 1. The liquid crystal display panel 1 has a structure in which a liquid crystal layer LQ is held between a pair of display panel substrates, that is, an array substrate AR and a counter substrate CT, and the external control circuit 2 is mounted on a circuit substrate independent of the liquid crystal display panel 1. Be placed.
[0012]
The array substrate AR includes m × n pixel electrodes PE arranged in a matrix, m scanning lines Y (Y1 to Ym) formed along rows of the plurality of pixel electrodes PE, and each pixel electrode PE. M × n formed of, for example, an N-channel polysilicon thin film transistor arranged near the intersection of n signal lines X (X1 to Xn), signal lines X1 to Xn, and scanning lines Y1 to Ym formed along the column Pixel switches 3, an auxiliary capacitance line CS arranged in parallel with the scanning lines Y1 to Ym and capacitively coupled to the pixel electrodes PE of the corresponding rows, a scanning line driving circuit 4 for driving the scanning lines Y1 to Ym, and a signal line X1. To Xn, and a plurality of external connection pads OLB used for connection between the external control circuit 2 and the array substrate AR.
[0013]
The counter substrate CT includes a single counter electrode CE arranged to face the m × n pixel electrodes PE and set to the common potential Vcom. This common potential Vcom is also applied to, for example, the auxiliary capacitance line CS.
[0014]
The external control circuit 2 receives the digital video signal and the synchronization signal supplied from the processing circuit of the mobile device, and generates a pixel display signal Vpix, a vertical scanning control signal YCT, and a horizontal scanning control signal XCT. The vertical scanning control signal YCT is supplied to the scanning line driving circuit 4, and the horizontal scanning control signal XCT is supplied to the signal line driving circuit 5 together with the display signal Vpix. The scanning line driving circuit 4 is controlled by the vertical scanning control signal YCT so as to sequentially supply the scanning signal to the scanning lines Y1 to Ym every vertical scanning (frame) period. The signal line drive circuit 5 converts a digital video signal input in one horizontal scanning period (1H) in which each scanning line Y is driven by a scanning signal from serial to parallel, and further converts the digital-to-analog converted display signal Vpix in analog form. The signals are controlled by the horizontal scanning control signal XCT so as to be supplied to the signal lines X1 to Xn, respectively.
[0015]
In this liquid crystal display device, the liquid crystal layer LQ is divided into m × n display pixels PX corresponding to the m × n pixel electrodes PE, and each display pixel PX includes two adjacent scanning lines Y and two display pixels PX. And the adjacent signal line X. The display screen is composed of these m × n display pixels PX. The scanning line driving circuit 4 and the signal line driving circuit 5 are arranged outside the m × n display pixels PX as shown in FIGS. 1 and 2, and the plurality of external connection pads OLB are arranged on the periphery of the array substrate AR. You. The signal line driving circuit 5 is disposed inside these external connection pads OLB. Each pixel switch 3 samples the display signal Vpix from the corresponding signal line X in response to the scanning signal from the corresponding scanning line Y and applies it to the corresponding pixel electrode PE. The potential of the pixel electrode PE and the potential of the counter electrode CE are sampled. The light transmittance of the corresponding display pixel PX is controlled based on the potential difference between the corresponding display pixel PX.
[0016]
FIG. 3 shows a planar structure of a wiring portion W formed on the array substrate AR shown in FIG. 2, FIG. 4 shows a cross-sectional structure of the array substrate AR along line IV-IV shown in FIG. 3, and FIG. FIG. 6 shows a cross-sectional structure of the array substrate AR along the line VV shown in FIG. 3, and FIG. 6 shows a cross-sectional structure of the array substrate AR along the line VI-VI shown in FIG.
[0017]
In the array substrate AR, the wiring portion W is formed to electrically connect the plurality of external connection pads OLB to connection terminals P of circuit components such as the scanning line driving circuit 4, the signal line driving circuit 5, and the auxiliary capacitance line CS. You. Although the wiring portion W is drawn linearly in FIG. 2, it is general that the wiring pattern is actually as shown in FIG. The wiring section W has a pair of conductor layers W1 and W2 formed as parallel wirings on the same path connecting each external connection pad OLB to the corresponding circuit component connection terminal P. As shown in FIGS. 4 to 6, the first conductor layer W1 is formed on the glass substrate 6 and covered with the insulating film 7. The second conductor layer W2 is formed on the insulating film 7 so as to overlap with the first conductor layer W1. Here, the conductor layer W1 is made of, for example, MoW, and the conductor layer W2 is made of, for example, Al. Further, each of conductor layers W1 and W2 has a thickness of, for example, 300 nm and a width of 50 μm. One end of the conductor layer W2 is formed integrally with the external connection pad OLB, and the other end is formed integrally with the circuit component connection terminal P. The conductor layer W2 is joined to the conductor layer W1 through contact holes H1 and H2 formed in the insulating film 7 at both end regions adjacent to these two terminals such as the external connection pad OLB and the circuit component connection terminal P, The insulating film 7 is insulated from the conductor layer W1 by the insulating film 7 other than at these joining portions. Each of the contact holes H1 and H2 is formed to have a size of, for example, 10 μm × 40 μm. The conductor layer W2 is further covered with an insulating protective film 8 formed by exposing the external connection pad OLB and the circuit component connection terminal P for the signal line drive circuit 5. The signal line drive circuit 5 is formed as an IC (integrated circuit) chip, and is mounted on a circuit component connection terminal P exposed at the other end of the conductor layer W2 by COG (Chip On Glass) technology.
[0018]
In the present embodiment, the conductor layer W2 is joined to the conductor layer W1 at both end regions adjacent to two terminals of the external connection pad OLE and the circuit component connection terminal P connected by the wiring portion W, and other than the joint portion. Since it is insulated from the conductor layer W1 by the insulating film 7, a lower wiring resistance and a higher yield can be obtained as compared with the case where one of the conductor layers W1 and W2 is used as the wiring portion W. Further, at least the external connection pad OLE and the circuit component connection terminal P for the signal line drive circuit 5 need to be exposed from the insulating protective film 8 and the like, and the possibility of corrosion is particularly high in the use environment of mobile devices. Even if the conductor layer W2 actually corrodes, the conductor layer W1 and the conductor layer W2 are joined only partially, not over the entire region where they overlap, so that the conductor layer W2 is separated from the conductor layer W1. The disconnection due to the corrosion progressing can be hardly generated. Therefore, it is possible to prevent the reliability of the wiring portion W from being significantly deteriorated due to corrosion.
[0019]
The present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist thereof.
[0020]
For example, in the above-described embodiment, the conductor layer W2 is joined to the conductor layer W1 at both end regions adjacent to two terminals of the external connection pad OLE connected by the wiring portion W and the circuit component connection terminal P, When one external connection pad OLE is connected to a plurality of circuit component connection terminals, the conductor layer W2 is joined to the conductor layer W1 at an end position adjacent to each circuit component connection terminal.
[0021]
Further, in the above embodiment, the external connection pad OLE is formed integrally with the conductor layer W2, but may be formed integrally with the conductor layer W1. Similarly, the circuit component connection terminal may be formed integrally with the conductor layer W1 instead of the conductor layer W2. Even if the conductor layer W1 is corroded as a result of such a configuration, the conductor layer W1 and the conductor layer W2 are joined only partially instead of in the entire region where the conductor layer W1 overlaps. Therefore, disconnection due to corrosion that progresses to the conductor layer W2 can be suppressed.
[0022]
Further, the conductor layer W1 and the conductor layer W2 need to be joined at least in both end regions adjacent to the two terminals connected by the wiring portion W. May be added.
[0023]
Furthermore, if the junction between the conductor layer W1 and the conductor layer W2 is partial, another conductor layer may be entirely joined and laminated to the conductor layer W1 or the conductor layer W2.
[0024]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a wiring structure for a display panel that can prevent the reliability of wiring from being significantly deteriorated by corrosion.
[Brief description of the drawings]
FIG. 1 is a diagram schematically illustrating an appearance of a liquid crystal display panel of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a schematic circuit structure of the liquid crystal display device shown in FIG.
FIG. 3 is a diagram showing a planar structure of a wiring portion formed on the array substrate shown in FIG. 2;
FIG. 4 is a diagram showing a cross-sectional structure of the array substrate taken along line IV-IV shown in FIG. 3;
FIG. 5 is a view showing a cross-sectional structure of the array substrate taken along line VV shown in FIG. 3;
FIG. 6 is a diagram showing a cross-sectional structure of the array substrate along a line VI-VI shown in FIG. 3;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display panel, 2 ... External control circuit, 3 ... Pixel switch, 4 ... Scan line drive circuit, 5 ... Signal line drive circuit, 6 ... Glass substrate, 7 ... Insulating film, 8 ... Insulating protective film, OLB ... Outside Connection terminal, P: Circuit component connection terminal, AR: Array substrate, CT: Counter substrate, LQ: Liquid crystal layer, PX: Display pixel, W: Wiring portion, W1: First conductor layer, W2: Second conductor layer , H1... Contact holes, H2... Contact holes.

Claims (3)

A display panel substrate, and a wiring portion for electrically interconnecting two terminals in the display panel substrate, wherein the wiring portion is a first conductor layer formed on the display panel substrate, and the first conductor An insulating film formed on the first conductive layer, and a first conductive material formed on the insulating film so as to overlap the first conductive material layer at least in both end regions adjacent to two terminals connected by the wiring portion; And a second conductor layer insulated from the first conductor layer by the insulating film at a portion other than these joint portions. The wiring section electrically connects an external connection terminal disposed on a periphery of the display panel substrate and a connection terminal of a drive circuit disposed inside the external connection terminal as the two terminals. The wiring structure for a display panel according to claim 1. The display panel wiring structure according to claim 2, wherein the display panel substrate includes a glass substrate, and the driving circuit includes an IC chip mounted on the glass substrate.

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