JP2004199658A - Digital signal processor, system, method, and host device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a configurable digital signal processor capable of flexibly coping with modification of specification. <P>SOLUTION: The digital signal processor is provided with an input part 2 which receives the respective input signals IN from a plurality of channels CH1, CH2, etc., a plurality of functional modules 3 capable of commonly receiving the signals from the input part 2 and to which signal processing is added depending on the unique functions, respectively, a module selection/control means 4 which sequentially selects the functional modules 3 corresponding to each of the plurality of channels and makes them perform the signal processing of the inputted signals IN and a memory means 5 which stores processing sequence information for sequentially specifying any of the functional modules 3 and parameter information for modifying the contents of the signal processing. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a digital signal processing device, a system and a method, and a host device.

  2. Description of the Related Art Digital signal processing systems in which predetermined signal processing is performed on each input signal input from each of a plurality of channels and applied to a host device are widely used in various electronic devices. Examples of corresponding electronic devices include test devices, audio devices, and in-vehicle computer control devices.

  In order to facilitate understanding of the present invention, the latter computer control device will be described as an example. In this device, sensors (throttle opening sensor, vehicle speed sensor, water temperature sensor, mode Analog signals from the changeover switch state sensor, the steering sensor, etc.) are individually input, that is, for each channel, to one host device, that is, a microcomputer (microcomputer), where digital arithmetic processing for optimal control of the vehicle is performed. Is done.

  In this case, since the host device (microcomputer) cannot directly receive the input signal from each channel without processing it, the host device (microcomputer) replaces each of the input signals before being input to the host device with each of the input signals. The above-described predetermined signal processing according to the property must be performed. The aforementioned “digital signal processing device” performs this predetermined signal processing. Here, an ECU (Electronic Control Unit), that is, the above-mentioned "digital signal processing system" is constructed by the host device, the digital signal processing device, and the input terminal group in the preceding stage of the digital signal processing device.

  In addition, as a well-known technique related to the present invention, there are the following Patent Documents 1 to 4. However, as will become clear from the description below, any of the known techniques "selects one or more functional modules sequentially for each of a plurality of channels selected in a predetermined order, and sets a configurable ( Configurable digital signal processing device ".

Japanese Patent No. 3015722 JP-A-3-203422 JP-A-1-232458 Patent No. 3335482

  There are two types of conventional digital signal processing devices implemented by the present applicant.

  In the first embodiment, the digital signal processing device is configured by a dedicated hardware circuit according to the above-described channel configuration.

  In the second embodiment, the digital signal processing device includes a fixed hardware circuit such as a microcomputer or a DSP (Digital Signal Processor) and software for operating the hardware circuit according to the above-described channel configuration. And a processing unit.

  However, in the digital signal processing device according to the second embodiment, when the digital signal processing system is changed or when the configuration of the channel is changed (for example, the input terminal is added), the digital signal processing device can be flexibly changed. Although it has the convenience of being able to cope, there is a problem that the processing speed by software processing is limited.

  Further, in the digital signal processing device according to the first embodiment, although the above processing speed is sufficiently satisfied, a digital signal processing circuit is required for each channel, so that the circuit scale becomes large. Therefore, there is a problem that the cost is high. Further, when the configuration of the above-mentioned channel is changed, there is a problem that a digital signal processing circuit corresponding to the change has to be newly made.

  Therefore, in view of the above problems, the present invention can flexibly cope with a change in the configuration of a digital signal processing system or a channel without changing the hardware, and has a small circuit scale. It is an object of the present invention to provide a digital signal processing device, a system and a method, and a host device that can perform high-speed processing as it is.

  FIG. 1 is a diagram showing a basic configuration of a digital signal processing device according to the present invention.

The basic configuration of the digital signal processing device 1 according to the present invention includes an input unit 2, a plurality of function modules 3 (A, B, C... N), and module selection / control means 4. In particular,
The input unit 2 receives input signals IN from a plurality of channels CH1, CH2,.
Each of the plurality of functional modules 3 can receive the signal in from the input unit 2 in common, and performs signal processing on the signal in received in a predetermined order by a function unique to each. ,
The module selection / control means 4 sequentially selects one or a plurality of function modules 3 corresponding to each of the plurality of channels CH1, CH2,... And causes the selected function module to perform signal processing of the input signal in. .

  More preferably, a memory means 5 is provided.

  The memory means 5 has a sequence memory 6 for rewritably holding processing sequence information for specifying one or a plurality of functional modules 3 to be selected for each channel (CH1, CH2,...).

  Still more preferably, the memory means 5 has a parameter memory 7 for rewritably storing parameter information for modifying the content of signal processing in each functional module 3.

  In the figure, reference numeral 8 denotes an output unit, and 9 denotes a shared bus.

  In this way, it is possible to form the digital signal processing device 1 configurable by sequentially selecting one or more functional modules 3 for each channel.

  Therefore, even if there is a change in the system configuration or the channel configuration, it is possible to flexibly cope with the change, and high-speed signal processing can be realized with a small circuit scale.

  FIG. 2 is a diagram showing the basic configuration of FIG. 1 more specifically. Note that the same components are denoted by the same reference numerals or symbols throughout the drawings.

  The input unit 2 receives an input signal IN corresponding to each channel (CH) and performs a time-division process on the separation unit (MPX: multiplexer) 11 and converts the analog (A) input signal IN into digital (D) data (in). , And transfers the digital data to the shared bus 9.

  The selection / control means 4 causes the functional modules (3A, 3B...) To perform signal processing corresponding to the channel via the shared bus 9 while referring to the contents of the memories 6 and 7. The processing result is temporarily stored in the processing result buffer 13 and then transmitted from the output distribution unit 14 to the outside. One example of this external device is the host device described above. Here, the shared bus 9 transfers address signals, data signals, control signals, and the like. Next, the processing operation will be described.

  FIG. 3 is a time chart for explaining the processing operation of FIG.

  In the figure, the horizontal axis indicates time. Each vertical dashed-dotted line indicates a sampling interval in the AD converter 12, and AD conversion of each input signal in (these are represented by ch1, ch2,...) On the channels CH1, CH2. (See “AD of ch1”, “AD of ch2” in the figure).

  In the figure, "A", "B", "C"... Indicate the functional modules 3A, 3B, 3C... In FIG. 2, respectively. The signals are sequentially processed in 3A and 3B (see “processing of ch1” in FIG. 3). That is, the data (in) that has passed through the AD of ch1 is signal-processed by the functional module 3A, and the signal-processed data is signal-processed by the functional module 3B. At this time, the A / D conversion of the input signal (IN) on the channel CH2 is performed in parallel (see “AD of ch2” in FIG. 3), and the data (in) of ch2 after the A / D conversion is, for example, The signal processing is sequentially performed by the functional modules 3A, 3C, and 3D (see “processing of ch2” in FIG. 3). Hereinafter, the same applies.

  To summarize the above, in the present invention, in a system for processing a plurality of digital input signals, a plurality of operation modules (3) are provided, and data (memory 6 and memory 6) defining how to process the digital input signals are provided. Based on 7), one or a plurality of arithmetic modules (3) are selected and processed. Here, a configurable processing system is realized.

  Here, “configurable” means that processing can be rewritten at the functional level in the processing system. For this purpose, a previously prepared processing module (functional block) is operated by switching the processing module for each input signal based on data (configuration data) describing the processing content.

  Hereinafter, each embodiment according to the present invention will be described in detail. In order to facilitate understanding of the present invention, a specific example of the above-described "processing system for a plurality of digital input signals" will be described. This is merely an example, but the “vehicle computer control system” described above. Of course, the present invention can be applied to a general digital data processing system.

  FIG. 4 is a diagram showing an example of one system to which the present invention is applied.

  In the figure, the whole block is an ECU (Electronic Control Unit), and analog signals from various sensors (throttle opening degree sensor and the like) are applied to the input terminal group of the ECU as each channel signal.

  These channel signals are subjected to pre-processing required for arithmetic processing in the microcomputer 10. This is the preprocessing IC, and corresponds to the digital signal processing device 1 of the present invention. The microcomputer corresponds to a host device described in more detail later.

  In this case, the plurality of functional modules (3) in the pre-processing IC (1) are, for example, a low-pass filter (LPF), a band-pass filter (BPF), a peak hold circuit, a comparator, and the like.

  That is, the sequence memory 6 stores a sequence map that defines which function (operation) module 3 is to process each input signal in.

  The signal processing operation in each functional module 3 according to the sequence map is as shown in FIG. However, the view of FIG. 7 is exactly the same as that of FIG. 3 described above.

  FIG. 5 is a diagram showing a writing means according to the present invention to be added to FIG.

  In this figure, newly added components are a sequence writing unit 71 and a parameter writing unit 72, and a sequence memory (flash memory or the like) 73 and a parameter memory (flash memory or the like) 74 in the host device 10.

The sequence writing means 71 rewrites the processing sequence information to be stored in the sequence memory 7 of FIG. 2 from outside the device (ECU).
The parameter writing means 72 rewrites the parameter information to be stored in the parameter memory 6 of FIG. 2 from outside the device (ECU) (see the route indicated by the solid arrow in FIG. 5).

As shown in FIG. 5, when cooperating with a host device 10 that receives data of a processing result of performing signal processing on an input signal, writing of processing sequence information to the sequence memory 7 in FIG. Done via
Writing of parameter information to the parameter memory 6 of FIG. 2 is performed via the host device 10 (see the route indicated by the dotted arrow in FIG. 5).

Alternatively, a plurality of types of predetermined processing sequence information is held in the sequence memory 73 in the host device 10, and the sequence writing means 71 designates the desired processing sequence information in the memory 73 and stores it in the sequence memory 73. 7 and write it.
Similarly, a plurality of types of predetermined parameter information are stored in a parameter memory 74 in the host device 10, and the parameter writing means 72 designates desired parameter information in the memory 74 and stores the parameter information in the parameter memory 6. (See the dashed line route in FIG. 5).

  The writing means 71 and 72 can also be used as means for inputting an original control program to be installed in the host device (microcomputer) 10.

  In FIG. 5, a further notable memory is a channel order memory 75.

  Each of the input signals from the channels CH1, CH2,..., CHk described above may be processed in order, such as CH1 → CH2 → CH3 →, or may be processed in an arbitrary predetermined order (for example, CH1 → CH3 →). CH2 →...). For this purpose, the channel order memory 75 holds the processing order information of each signal to be processed. A detailed example of the processing order of the channels will be described later.

  FIG. 6 is a diagram more specifically showing the selection / control means 4 shown in FIG. 2 and its periphery. Note that the arrangement of the functional modules 3 is different from that of FIG. 2 for convenience of explanation. Further, the above-described channel order memory 75 is placed at a position shown in the figure as an example.

  The module selection / control means 4 shown in FIG. 6 includes a memory read unit 81 and a module control unit 82 for controlling each of the functional modules 3 (A, B... N) according to the read information from the memory read unit 81. Comprising. Here, the memory reading unit 81 reads information from the sequence memory 7.

  On the other hand, the module control unit 82 controls each functional module 3 (A, B... N) according to the parameter information from the parameter memory 6.

  The memory read unit 81 reads information from the channel order memory 75.

  The module selection / control means 4 shown in FIG. 6 will be described more specifically below with reference to flowcharts and time charts. Before that, however, in order to facilitate understanding, an example of a vehicle-mounted device will be described. A specific example of each input signal of CH1, CH2, and a specific example of one or a plurality of functional modules 3 that process each input signal will be described.

  FIG. 7 is a diagram illustrating an example of an input signal of each channel and an example of a functional module that processes the input signal.

  In the figure, the left end corresponds to the above-described input unit 2, from which input signals from a plurality of channels CH1, CH2, CH3,.

  On the other hand, the upper end 3 of the figure represents the plurality of functional modules described above.

  The processing target of each channel is, for example, as follows.

CH1: engine speed CH2: water temperature CH3: stop (brake) lamp CH4: knock CH5: differential sensor The engine speed signal from the channel CH1 is first input to the low-pass filter (LPF) of the first-stage function module, and the filter is applied. The output is input to a comparator which is a next-stage functional module, and a processing result OUT1 is obtained. However, when going from the low-pass filter (LPF) to the comparator, the filter output from the low-pass filter (LPF) is temporarily buffered, and then when the comparator is selected by the module control unit (82 in FIG. 6). The filter output is read from the buffer and applied to the comparator. The buffer mentioned here may be in the selection / control means (4 in FIG. 6), in the output unit (8 in FIG. 6), or connected to the shared bus in FIG. May be provided independently.

  The unique parameter a11 is supplied to the low-pass filter (LPF) from the parameter memory 6 via the module control unit 82, and the unique parameter a12 is also supplied to the comparator via the module control unit 82 from the parameter memory 6 side. Supplied. These parameters a11, a12, etc. will be described again later in FIG. 22, etc., but a11, a12 in FIG. 7 and a11, a12 in FIG. 22 are simply symbols for distinction. Are not mutually equivalent.

  In FIG. 7, the parameter a11 sets a filter constant suitable for removing noise in a low-pass filter (LPF). The parameter a12 sets the comparison reference value of the comparator.

  The water temperature signal from the channel CH2 is also signal-processed by the LPF, which is a functional module for removing noise.

  The stop (brake) lamp signal from the channel CH3 is turned on / off by a comparator (OUT3) after noise removal (LPF).

  Since the knock signal from CH4, that is, the output signal from the knock sensor, needs to first extract a signal in a required frequency band, it is input to a band-pass filter (BPF), which is another functional module, and its output is output. In order to hold the peak value from among a large number of sample values, the signal is further input to a peak hold (P / H) circuit, which is a functional module, and becomes OUT4.

  The channel CH5 is a differential signal S + and S−, which are output signals from a specific sensor. The difference between these signals is output from the adder circuit and becomes OUT5.

  7 shows the input signals of the respective channels (CH1, CH2, CH3,...) And specific examples of the respective functional modules. Next, based on this, an operation example of the selection / control means 4 of FIG. This will be described with reference to FIGS.

FIG. 8 is a flowchart showing an operation example of the selection / control means 4 shown in FIG.
FIG. 9 is a time chart corresponding to the flowchart of FIG.
In FIG. 7, the case of the channel CH1, the corresponding functional module “LPF” (3A) and the corresponding functional module “comparator” (3B) will be described as an example (the same applies hereinafter).

Referring to FIGS. 6 to 9,
Step S11 (FIG. 8): The module selection / control means 4 reads the channel order information of the channel order memory 75 by the memory reading section 81.

  Step S12: In this example, the channel CH1 is designated, and the IDch1 is output (see (2) in FIG. 9).

  Step S13: The selection / control means 4 outputs the IDch1 to the input section 2, and the input data “CH1 data” of the channel CH1 is transferred to the shared bus 9.

  Step S14: The selection / control means 4 reads the sequence information of the sequence memory 7 by the memory reading section 81.

  Step S15: In this assumed example, the first sequence read out in step S11 is the functional module 3 (A), which is represented by IDa (see (1) in FIG. 9).

  Step S16: The module 3 (A) receiving the IDa via the shared bus 9 is started (see (1) in FIG. 9).

  Step S17: The functional module 3 (A) takes in the “CH1 data” on the shared bus 9 into itself.

  Step S18: The means 4 reads the corresponding parameter from the parameter memory 6 and transfers it to the shared bus 9 (see (2) in FIG. 9). In the above example, this parameter is a11 (FIG. 7).

  Step S19: The target signal processing is executed in the functional module 3 (A) using the CH1 data and a11 (see “Operation A” in FIG. 9 (2)). Then, the calculation result is output (see “OUTa” in (2) of FIG. 9).

  Step S20: At this time, the functional module 3 (A) outputs an operation end signal indicating the end of the operation to the shared bus 9 (see Ea in (3) of FIG. 9). Here, the operation by the LPF in FIG. 7 is completed, and the operation proceeds to the next-stage comparator.

  Step S21: The selection / control means 4 reads the sequence information of the sequence memory 7 by the memory reading section 81.

  Step S22: In this assumed example, the second sequence read in step S21 is the function module 3 (B), which is represented by IDb (see (1) in FIG. 9).

  Step S23: The module 3 (B) receiving the IDb via the shared bus 9 is started (see (1) in FIG. 9).

  Step S24: The functional module 3 (B) reads out and takes in the operation result OUTa from the buffer described above.

  Step S25: The means 4 reads the corresponding parameter from the parameter memory 6 and transfers it to the shared bus 9 (see (2) in FIG. 9). In the above example, this parameter is a12 (FIG. 7).

  Step S26: The target signal processing is executed in the functional module 3 (B) using OUTa and a12 (see “Operation B” in (2) of FIG. 9). Then, the calculation result is output (see (2) in FIG. 9 and “OUT1” in FIG. 7).

  Step S27: At this time, the functional module 3 (B) outputs an operation end signal indicating the end of the operation to the shared bus 9 (see Eb in (3) of FIG. 9).

  Here, step S14 in FIG. 8 will be supplementarily described. This channel order reading is for setting the order of channels to be signal processed. As described above, the input signals from the channels CH1, CH2,..., CHk may be processed in order, such as CH1 → CH2 → CH3 →, or may be processed in accordance with an arbitrary predetermined order. You may.

  A specific example of the latter will be described with reference to FIG.

  Channel CH1 is an input signal relating to the engine speed and requires frequent signal processing such as every two samples, while channel CH3 is a stop (brake) ramp signal and CH4 is a knock sensor signal, such as every 12 samples. Signal processing may be performed at relatively slow timing. The middle channel CH2 is a water temperature signal, and the signal processing may be performed at timings such as every six samples in the middle. This is illustrated in FIG.

  FIG. 10 is a diagram illustrating an example of the channel processing order. The designation of the channel processing order for every two samples, every six samples, every twelve samples, and the like described above is clearly shown. This is repeated every cycle, with the sampling in FIG. 10 as one cycle.

  In the setting of the channel processing order and the sequential setting of the function modules 3 (FIG. 7), in the case of a car, an optimal setting is appropriately set for each of various types of vehicles. According to the present invention, any type of vehicle can be easily handled by simply rewriting the contents of the parameter memory 6, the sequence memory 7, and the channel order memory 75 from outside. That is, it is not necessary to recreate the “pre-processing IC” shown in FIGS. 4 and 5 for each of various types of vehicles.

[Example 1]
FIG. 11 is an apparatus configuration diagram for explaining Embodiment 1 according to the present invention.
FIG. 12 is a diagram showing the contents of the sequence memory 6 of FIG.
FIG. 13 is a time chart showing the processing operation based on the processing sequence of FIG.

  An example of the processing sequence map shown in FIG. 12 is shown in the sequence memory 6 of FIG. In the processing order 1, it is instructed that the signal processing in the functional module 3A and the signal processing in the functional module 3B are performed on the input channel CH1. The same applies to the second and subsequent processing orders.

That is, in the first embodiment, the processing content for the input signal in of each channel is described in the sequence memory 6 in advance, and processing is performed while reading out this data. The data is a map that describes the processing content for each operation cycle (processing order). Thus, by changing the description content in the memory 6, it is possible to flexibly cope with an external system (ECU).
[Example 2]
FIG. 14 is a diagram showing the contents of the sequence memory 6 for explaining the second embodiment according to the present invention.
FIG. 15 is a time chart showing the processing operation based on the processing sequence of FIG.

  The second embodiment is characterized in that the module selection / control means 4 rewrites the contents of one or both of the sequence memory 6 and the parameter memory 7 even during the operation of the digital signal processing device 1. . However, FIGS. 8 and 9 show only the change of the contents of the sequence memory 6.

  In this example, the module A → B has been changed from the module A → B to the module A → C in the middle of the input channel CH1. The processing order 1 'in FIG. 15 shows the operation by this change.

That is, according to the second embodiment, in the system of FIG. 11, the contents of the processing are changed by rewriting the contents of the sequence memory 6 during the operation of the system. For example, while each function (operation) module 3 is not using the shared bus 9, the contents of the memory 6 are directly rewritten from the selection / control means 4.
[Example 3]
FIG. 16 is an apparatus configuration diagram for explaining a third embodiment according to the present invention.
FIG. 17 is a diagram showing the contents of the sequence memory 6 of FIG.
FIG. 18 is a time chart showing the processing operation based on the processing sequence of FIG.

  In the third embodiment, the module selection / control means 4 selects a function module 3 to be selected for each channel (CH1, CH2,...) In accordance with a specified series of processing sequences, and also generates a new interrupt as an input signal IN. When an input signal is generated, an interrupt processing sequence is inserted into the designated series of processing sequences. Reference numeral 15 shown at the lower end of FIG. 17 shows the interrupt processing sequence.

  In this case, empty processing contents 16 are appropriately inserted in the sequence memory 6 in advance, and when an interrupt occurs, the interrupt sequence is executed using the empty closest to the interrupt. Referring to FIG. 18, the interrupt processing sequence is executed in a vacant portion of the processing order 4.

  That is, according to the third embodiment, the system shown in FIG. 11 cannot cope with a case where there is an input signal IN whose processing is to be performed at a timing that cannot be defined by the sequence map. Therefore, such an input signal is received by a predetermined input and is processed for interruption.

Note that the interrupt input may have a different system from the other inputs, or another input may be used as an interrupt.
[Example 4]
FIG. 19 is a processing operation time chart for explaining the fourth embodiment according to the present invention.

  The fourth embodiment is characterized in that the processing for the input signal of the channel that should have been processed in one processing sequence overlapping the insertion of the above-described interrupt processing sequence 15 (FIG. 17) is stopped. Is what you do.

  In FIG. 19, the processing of ch2 is skipped due to the above-mentioned suspension.

However, in this case, only the processing that does not significantly affect the processing result is skipped.
[Example 5]
FIG. 20 is a processing operation time chart for explaining the fifth embodiment according to the present invention.

  In the fifth embodiment, the processing for the input signal of the channel which should have been processed in one processing sequence overlapping with the insertion of the above-described interrupt processing sequence 15 is temporarily suspended, and as soon as the interrupt processing sequence ends. The processing is started.

Referring to FIG. 20, the hatched "BC" indicates signal processing by an interrupt, whereby the signal processing for ch2 and thereafter is postponed. Interrupts can be accepted with some delay in processing time.
[Example 6]
FIG. 21 is an apparatus configuration diagram of a sixth embodiment according to the present invention.
FIG. 22 is a diagram showing the contents of the parameter memory 7 of FIG.

  In the sixth embodiment, the parameter memory 7 previously holds parameter information set for each channel (CH1, CH2,...), And the parameter memory 7 is a shared memory that is referred to by all the function modules 3. It is a feature.

  According to the example shown in FIG. 22, the number of parameters making up the parameter information is three, and these parameters are used for input signals from input channels CH1 and CH3.

  In other words, according to the present invention, in the processing in the function (calculation) module 3, for example, if a filter is used, the filter constant is set as a parameter from the outside, so that the input can be performed even if the same filter calculation module is used. Different channels can be operated at different cutoff frequencies.

According to the sixth embodiment, the parameters (constant data) required for execution of the processing in the function (operation) module 3 defined in the input signal IN of each channel are described in advance in the parameter memory 7 for each input signal IN. This is read and processing is performed. This memory 7 is a shared memory that can be referred to from each module 3. By setting the parameter information of all the function (operation) modules 3 in the shared memory, the setting of the parameters can be performed collectively.
[Example 7]
FIG. 23 is an apparatus configuration diagram of Embodiment 7 according to the present invention.

  In the seventh embodiment, the parameter memory 7 (FIG. 21) is individual memories 7A, 7B, 7C built in each functional module 3, and these individual memories previously hold parameter information set for each channel. It is characterized by the following.

According to the seventh embodiment, an area for storing the parameters of each input (contents of the parameter memory 7) is provided in each module 3, so that the shared memory (FIG. 21) is accessed through the shared bus 9. Can also reduce the time.
Example 8
The eighth embodiment is characterized in that the operation characteristics in the signal processing are changed by modifying the content of the signal processing described above.

That is, this is a dynamic change of a parameter for each input signal. In the systems of the sixth and seventh embodiments, the operation characteristics of the process are rewritten by rewriting the contents (parameters) of the memory 7 (7A, 7B...) During the system operation. (For example, the filter cutoff frequency) can be changed.
[Example 9]
FIG. 24 is a diagram showing an apparatus configuration of a ninth embodiment according to the present invention.

  The ninth embodiment includes a shared bus 9 for connecting at least the input unit 2, the functional module 3, and the module selection / control means 4, and the shared bus 9 is provided for each data type handled in signal processing. It comprises a plurality of separated individual buses 21 to 23.

  Specifically, they are an inter-module bus 21, a parameter bus 22, and a temporary data 23.

The system of the present invention includes a plurality of function (operation) modules, a memory, an overall operation control unit, and the like. The configuration of a bus necessary for data transfer between them is as shown in Example 9 as an example. Can be. In other words, data can be transferred over a plurality of buses, and the time required to transfer data required for each function (operation) module can be reduced. In other words, a transfer bus for each data type, such as data transfer between modules (21), read / write of parameters (22), read / write of temporary data (previous value in internal calculation, etc.) (23), etc. have.
[Example 10]
FIG. 25 is a diagram showing a device configuration of a tenth embodiment according to the present invention.

  The tenth embodiment includes a shared bus 9 that connects at least the input unit 2, the functional module 3, and the module selection / control unit 4, and the shared bus 9 includes a plurality of types of data handled in signal processing. Is transferred in a time-division manner by a single bus 24.

That is, data transfer is performed by a single bus. In other words, in order to reduce the circuit scale of a bus for transferring data required for each function (operation) module, a single bus is used and all types of data are transferred using time division. I do.
[Example 11]
FIG. 26 is an apparatus configuration diagram for explaining Embodiment 11 according to the present invention.
FIG. 27A is a time chart illustrating a processing operation not according to the eleventh embodiment, and FIG. 27B is a time chart illustrating a processing operation according to the eleventh embodiment.

  In the eleventh embodiment, when at least two functional modules 3A and 3B are sequentially selected (“1” → “2”) and execute their respective signal processing, during the signal processing of the preceding functional module 3A, The parameter information to be used in the function module 3B in the row is acquired, and immediately after the signal processing in the preceding function module 3A ends, the function module 3B in the subsequent row uses the acquired parameter information. The signal processing is started.

  Considering the data input / output method in the functional module of the present invention, it is necessary to read configuration data each time to switch the operation for each input signal IN. However, if this operation takes a long time, the operation speed of the entire system is reduced. A first method for realizing this with a small number of clocks is the eleventh embodiment. This is the method when the same module is not used continuously.

Referring particularly to FIG. 27 (b), when setting a module, a module A to be currently processed and a module B to be processed next are designated as a pair. Then, after the parameter setting of the current module A is completed, the parameter setting of the next module B is immediately started (time t1), so that the parameter setting of the next module B is omitted after the processing of the current module A is completed. Therefore, time can be reduced. That is, when the module A is used in performing the current process and then the module B is used, parameters necessary for the module A are transmitted through the control bus 9c (FIG. 26). After that, the data is read from the data bus 9d (FIG. 26) to perform the arithmetic processing. In this case, since the control bus 9c is not used during the operation of the module A, the parameters for the module B can be set during the operation of the module A. Thus, when the operation result is output from the module A, the module B can immediately start the operation.
[Example 12]
FIG. 28 is an apparatus configuration diagram for explaining Embodiment 12 according to the present invention.
FIG. 29A is a time chart illustrating a processing operation not according to the twelfth embodiment, and FIG. 29B is a time chart illustrating a processing operation according to the twelfth embodiment.

  In the twelfth embodiment, when the first signal processing “1” and the second signal processing “2” are sequentially and sequentially executed in the same functional module (for example, A in FIG. 18), the first signal processing “ During execution of “1”, parameter information to be used in the second signal processing “2” is acquired, and immediately after the first signal processing “1” is completed, the acquired parameter information is used. The second signal processing “2” is started.

  This is a case in which the same module is used continuously. Each module 3 has a plurality of parameter storage registers 26, takes in the parameter setting values of the current module A, and subsequently performs the next parameter setting. It is. When the next processing is performed in the module A, the setting is immediately completed by switching the register 26, so that the setting time can be reduced.

Depending on the processing, the same module may be used a plurality of times, but if the setting parameters are different, it is necessary to discard the previously used parameters and set new parameters. Therefore, first, the parameters of the module A are transmitted, and while the arithmetic processing is being performed, the second parameters are transmitted from the vacant control bus 9c, and the parameters are transmitted to the plurality of registers 26 prepared for storage. Save the value. When the second operation of the module A is performed, it is not necessary to perform a bus access for taking in the parameter value, so that the operation can be performed with a small number of clocks. During the second operation of the module A, another register 26 is writable, so that the vacant control bus 9c can be used. Therefore, even when the same module is used three or more times, the operation can be performed with a small number of clocks.
[Example 13]
FIG. 30 is an apparatus configuration diagram for explaining Embodiment 13 according to the present invention.

  In the thirteenth embodiment, when the output data obtained in the above-described first signal processing is returned to the functional module 3 and used for the above-described second signal processing, the output data is not sent out of the functional module. For example, the gate 25 is opened by the enable signal EN and returned by the signal path 27 in the function module. Note that BD is a bus driver.

The thirteenth embodiment is also a case where the same module is continuously used as in the twelfth embodiment. When an output value is output to the bus 9 once, it is referred to as <1> output to the data bus 9d and <2> input from the data bus 9d. It is necessary to access the data bus. Therefore, when the same module 3 is used a plurality of times, the wiring (27) is internally connected, and the bus 9 is not used for data input / output. Naturally, the processing speed improves.
[Example 14]
FIG. 31 is an apparatus configuration diagram for explaining Embodiment 14 according to the present invention.

  The fourteenth embodiment and the later-described embodiments 15 and 16 include a low-speed communication line 28 and a high-speed communication line 29 as communication lines for transmitting a processing result by signal processing to an external host device 10. It is characterized by the following.

  More specifically, the low-speed communication line 28 is a communication line that performs the above-described transmission at a fixed cycle when a transmission request REQ1 is received from the host device 10, while the high-speed communication line 29 is a communication line from the host device 10. This is a communication line for performing the above-described transmission every time in response to the transmission request REQ2.

In this way, the data transmitted at a constant period and the data transmitted when requested from the outside (10) do not overlap, and the communication speed and the amount of communication data can be suppressed.
[Example 15]
According to the fifteenth embodiment, the low-speed communication line 28 and the high-speed communication line 29 are each configured by a parallel line.

  In the fifteenth embodiment, a parallel port output interface (I / F) is provided, and an I / F for outputting the processing result of the system (1) to the outside (10) is constituted by a parallel port. ) Can be arbitrarily extracted by designating a signal (address, ID code, etc.) for identifying the data to be extracted.

In the case of this embodiment, high-speed communication can be performed, and the clock speed of the communication line can be suppressed.
[Example 16]
According to the sixteenth embodiment, each of the low-speed communication line 28 and the high-speed communication line 29 is constituted by a serial line.

  The sixteenth embodiment has a serial port output interface I / F. Since the I / F that outputs the processing result of the system (1) to the outside (10) is constituted by a serial port, From 10), a signal that can identify the data to be taken out is received, and corresponding data is output, or data is output in a predetermined order.

In the case of this embodiment, the number of communication lines can be reduced.
[Example 17]
FIG. 32 is an apparatus configuration diagram for explaining Embodiment 17 according to the present invention.
FIG. 33 is a diagram showing a communication data format on the communication line 30 of FIG.

  The output unit 8 (see FIG. 1) according to the seventeenth embodiment assigns an ID indicating which one of a plurality of channels (CH1, CH2,...) Is the processing result of the input signal IN from the processing result. And further transmitting the data.

  The ID is shown as “ID code” at the left end of the lower column of FIG.

  According to the seventeenth embodiment, since it is possible to identify which input signal has been processed, it is not necessary to determine the transmission order and the like.

  Further, only necessary data can be output to the host device 10.

Referring to FIG. 32, the processing result data from each functional module 3 is temporarily captured by the processing result capturing unit 32. At this time, since the selection / control means 4 knows which channel the input processing result is for the input signal, the selection / control means 4 transmits the channel signal to the ID code generator 31. The ID code indicates the channel, and the ID code is added to the data of the fetched processing result in the transmission unit 33 and further transmitted to the communication line 30.
[Example 18]
FIG. 34 is an apparatus configuration diagram for explaining Embodiment 18 according to the present invention.

  The eighteenth embodiment has the same effect as the above-described seventeenth embodiment. However, in the eighteenth embodiment, the output unit 8 (see FIG. 1) outputs the processing result for each of the input signals of a plurality of channels to each of them. The transmission is sequentially performed in accordance with the transmission order assigned to the channel.

  According to the eighteenth embodiment, there is no need to attach data for identifying which input signal IN has been processed, and only the processing result need be transmitted. Further, since the ID code is not required, the amount of transmission data can be reduced.

Referring to FIG. 34, the difference from FIG. 32 is that a transmission order storage memory 34 has been introduced. Is transmitted to the communication line 30.
[Example 19]
FIG. 35 is an apparatus configuration diagram for explaining Embodiment 19 according to the present invention.

  The present embodiment 19 and embodiments 20 to 23 described below deal with a case where it is required to always process accurate data even when a failure occurs in the system. Condition can be maintained.

  First, in the nineteenth embodiment, a shared bus 9 for connecting at least a plurality of functional modules 3 is provided, and when the plurality of functional modules 3 is an active functional module group 41, the active functional module group 41 and the mirror are connected. The spare function module group 42 is connected via the shared bus 9, and when it is determined that any of the function modules 3 (for example, A) in the active function module group 41 has a failure, the spare function module group 42 And selecting and using the corresponding function module 3 '(A).

  That is, two or more identical modules are connected as spares to each module to the shared bus 9, and when the receiver side (for example, the host device 10) or itself (1) detects a failure of the system, the failure is immediately performed. The use of the module (A) determined to be stopped is stopped, and a spare module is used.

Referring to FIG. 35, when there is “abnormality detection”, sequencer 43 issues a command for instructing which module should be used for signal processing. In the example of this figure, since an abnormality is detected in the active module 3A, only this (3A) is replaced with the spare module 3 '(A).
[Example 20]
FIG. 36 is an apparatus configuration diagram for explaining Embodiment 20 according to the present invention.

In the twentieth embodiment, at least a shared bus 9 connecting at least a plurality of function modules 3 is provided, and when the plurality of function modules 3 are used as a group of active function modules 41, a spare mirror forming a mirror with the group of current function modules 41 is provided. The function module group 42 is connected via the shared bus 9, and when it is determined that any of the function modules 3 (for example, A) in the working function module group 41 has a failure, the function module group 42 is switched to the spare function module group 42. It is characterized in that it is used. That is, all the active modules 3 currently in use are collectively replaced with the spare module 3 '.
[Example 21]
In the twenty-first embodiment, when the signal processing in the digital signal processing device 1 is completed, a record of a functional module having a failure is held, and when the digital signal processing device 1 is restarted, the record is also stored. In this case, a normal function module is selected and used.

In other words, even when the system is restarted, for example, by turning off the power once after detecting the failure, the failure information can be stored and the module can be operated using the module without failure.
[Example 22]
In the twenty-second embodiment, when there is an external host device 10 to which a processing result by signal processing is to be transmitted, an ID indicating a module that has generated each processing result is added to data of each processing result and transmitted to the host device 10. It is characterized in that the host device 10 judges whether there is a failure and receives from the host device 10 specific information specifying a functional module having a failure.

That is, information (such as an ID code) for identifying the module used for the processing is added to the output data to the receiver (10), and the faulty module is specified by the receiver (10), and the spare module is identified. Information for switching to the module is transmitted from the receiver side (10) to the apparatus 1.
[Example 23]
FIG. 37 is a diagram showing data for explaining Embodiment 23 according to the present invention.

  In the twenty-third embodiment, when there is an external host device 10 to which the processing result of the above-described signal processing is to be transmitted, the processing sequence information to be held in the sequence memory 6 is read from the host device 10, and when the reading is completed, The host device 10 gives predetermined data to the digital signal processing device 1 and runs the reading processing sequence. The host device 10 receives the processing result and compares it with a predetermined expected value to determine whether the two match. When the reading process sequence is normal.

  The twenty-third embodiment and the later-described embodiments 24-26 relate to failure diagnosis.

  When reading the sequence data from the outside (10) of the present system (1), it is necessary to confirm whether the sequence data has been correctly received. This is the check method of the twenty-third embodiment. That is, a method of operating the sequence one or more times using predetermined data to confirm whether or not the sequence data has been correctly downloaded, and comparing the data received by the receiver (10) with an expected value stored in advance. Take.

  Referring to FIG. 37, reference numeral 44 denotes sequence data transmitted from the host device (recipient side) 10. This sequence is run in the digital signal processing device (system) 1, and the result is sent back to the host device 10. In step 10, comparison is made with the processing result expected value data prepared in advance. That is, since the output result when predetermined data is input can be calculated in advance, it is stored in the receiver as an expected value, and it is checked whether or not it matches the actual output result.

Note that the lower left part of FIG. 37 shows the content of the signal processing in the functional module 3. However, this is only an example.
[Example 24]
The twenty-fourth embodiment is characterized in that, in the twenty-third embodiment, when the above-mentioned comparisons do not match, the above-described processing sequence information is retransmitted from the host device 10 and the same confirmation is performed again. Thereby, detection accuracy can be improved.
[Example 25]
The twenty-fifth embodiment is characterized in that, in the twenty-fourth embodiment, when the inconsistency is not resolved, an alarm is sent to an external user. The user referred to here is, for example, a driver of a vehicle equipped with the above-mentioned ECU, or a product inspector in a production plant of the ECU or a production inspector of a vehicle equipped with the ECU.
[Example 26]
The twenty-sixth embodiment differs from the twenty-third embodiment in that the above-described processing sequence information read from the host device 10 is directly used as a check unit (check program) in the host device 10 or an external device having a function equivalent to the function of the check unit. The processing sequence information is returned to the apparatus, and when the returned processing sequence information matches the transmitted processing sequence information, it is confirmed that the above-described reading processing sequence is normal.
[Example 27]
FIG. 38 is an apparatus configuration diagram for explaining Embodiment 27 according to the present invention.
FIG. 39 is a diagram showing an example of the data structure of the data used in FIG.

  The twenty-seventh embodiment and the later-described embodiments 28 to 30 relate to failure diagnosis for determining whether or not the function module 3 has been used correctly.

  First, in the twenty-seventh embodiment, at the end of the signal processing in each selected functional module 3, the individual module check bit 47 (FIG. 39) indicating the normal end of the signal processing is set to each functional module (A, B, C). , D) for each of the functional modules 3 by determining whether or not the bit string matches the expected bit string.

  That is, this is a failure diagnosis method in which a passing module check bit is provided in the data string 46 to determine whether the functional module 3 has been used correctly.

  When the modules 3 are operated in any combination as in the present invention, it is necessary to know whether the modules 3 to be used are used properly. However, it is difficult to confirm during actual operation.

  Therefore, in the present invention, a dedicated bit for failure determination is provided, and a check is performed when the module passes, so that a failure or non-passage of the module can be detected.

Referring to FIG. 38, after the operation in each module 3 is completed, when transmitting the resulting data to the data bus 9d, each check bit 47 is set.
(Example 28)
In the embodiment 28, the individual module check bit 47 in the embodiment 27 is replaced by an accumulation module check bit 48.

That is, when the signal processing in each of the selected functional modules 3 is completed, the cumulative module check bit 48 (FIG. 39) indicating the cumulative value sequentially added or subtracted each time the signal processing is normally completed in each functional module 3 Is generated, and the failure determination of the functional module 3 is performed by determining whether the cumulative value matches the expected cumulative value.
[Example 29]
Embodiment 29 is different from Embodiment 27 or 28 in that, when there is an external host device 10 to which the processing result of the above-described signal processing is to be transmitted, the expected value of the failure determination described above is transmitted from the host device 10. It is obtained based on a processing sequence.

That is, since the host device 10 indicates which module (CH1, CH2,...) To use which module 3, the host device 10 checks the result of giving it to determine whether the module is used as instructed. You can check.
[Example 30]
Embodiment 30 is characterized in that, in Embodiment 27 or 28 described above, the expected value of the above-described failure determination is obtained based on the processing sequence originally held by the digital signal processing device 1.
[Example 31]
FIG. 40 is a sequence diagram for explaining Embodiment 31 according to the present invention.

  The present embodiment 31 and later-described embodiments 32 to 35 relate to failure detection in the digital signal processing device 1, and detect a failure by incorporating a so-called test pattern.

In the thirty-first embodiment, a test processing sequence 50 (FIG. 40) is incorporated in the above-described processing sequence information, and the test processing sequence 50 is run at a predetermined cycle, and a plurality of functional modules 3 An operation check is performed. That is, since each process is executed with a time interval, a sequence for performing a test is incorporated in advance, and the test is executed at regular intervals. The cycle at which the test is performed does not need to be limited to one cycle of the process 51 required for control, and may be executed anywhere in the process. It may be executed a plurality of times.
[Example 32]
FIG. 41 is a sequence diagram for explaining Embodiment 32 according to the present invention.

  In the working example 32, the test processing sequence 50 is incorporated in the above-described processing sequence information, and the signal processing pause period is set between two adjacent signal processings (“processing 2” and “processing 3”). When 52 exists, the test processing sequence 50 is run during the idle period 52 to check the operation of the plurality of functional modules 3.

That is, when there is room in the processing, a test sequence operation is performed. If there is a margin in the processing, if there is a time gap between the processings, the test sequence can be operated using the margin time.
(Example 33)
FIG. 42 is a sequence diagram for explaining Embodiment 33 according to the present invention.

  In the embodiment 33, the test processing sequence 50 is incorporated in the above-described processing sequence information, and when a test command (command) is applied from the outside (for example, the host device 10), the application timing coincides with the application timing. The signal processing is stopped (stop period 53), the test processing sequence is forcibly executed, and the operation of a plurality of functional modules 3 is confirmed.

That is, the operation is confirmed by receiving a command (command) from the outside at an arbitrary timing. During the operation, the test is forcibly executed by the command from the outside, and other processing is stopped.
(Example 34)
FIG. 43 is a sequence diagram for explaining Embodiment 34 according to the present invention.

  In the thirty-fourth embodiment, a test processing sequence 50 is incorporated in the above-described processing sequence information, and when a test command (instruction) is applied from the outside, the signal processing corresponding to the application timing is not performed. The process is postponed (arrow 54 in FIG. 43), the test processing sequence 50 is forcibly executed, and the operation of a plurality of functional modules 3 is confirmed.

That is, the operation is confirmed by receiving a command (instruction) from the outside at an arbitrary timing. During the operation, a test is forcibly executed from the outside by an instruction from the host device 10, for example, and other processing is delayed. Things.
[Example 35]
FIG. 44 is a sequence diagram for explaining Embodiment 35 according to the present invention.

  In the embodiment 35, the test processing sequence 50 is incorporated in the above-described processing sequence information, and when a test command is applied from the outside, the test process is waited until a pause 52 in which signal processing is paused. The operation processing sequence 50 is executed to check the operations of the plurality of functional modules 3.

That is, the operation is confirmed by receiving a command (instruction) from the outside at an arbitrary timing. During the operation, a test is forcibly executed from the outside by an instruction from the host device 10, for example, and the next pause period ( The test is executed after waiting for idle time.
(Example 36)
As described above, various aspects of the digital signal processing device 1 according to the present invention have been described in detail through Embodiments 1 to 35. Here, the present invention will be described from another viewpoint.

The technical idea of the present invention can be grasped not only as a device configuration but also as a signal processing technique. The first point is as follows, that is, in the digital signal processing device 1 including at least the input unit 2 and the plurality of functional modules 3,
(I) giving each of the plurality of functional modules 3 a unique signal processing function;
(Ii) providing an input signal IN for each of a plurality of channels (CH1, CH2,...) Input to the input unit 2 to one or a plurality of functional modules 3 selected for each channel to perform signal processing; It is in.

further,
A series of processing sequences for designating one or a plurality of functional modules 3 to be used for each of the above channels is stored in advance (sequence memory 6), and the series of processing sequences are sequentially read to execute signal processing. To do.

Furthermore, parameter information for modifying the content of the signal processing in each of the functional modules 3 is stored in advance (parameter memory 7), and the corresponding parameter information according to the nature of the input signal IN for each channel is stored. And executing signal processing.
[Example 37]
By further developing the technical idea of the present invention described in the embodiment 36, a digital signal processing system can be further constructed.

  Embodiment 37 and Embodiment 38 described below relate to such a digital signal processing system.

  FIG. 45 is a diagram showing a first digital signal processing system according to embodiment 37 of the present invention.

  A first digital signal processing system 61 according to the 37th embodiment is provided with a communication interface 66 capable of transmitting and receiving a processing result of signal processing to the above-described digital signal processing device 1 and is similar to the digital signal processing device. Are provided (1-1, 1-2, 1-3,... In FIG. 45), and these are cascade-connected via respective communication interfaces 66.

  Referring to FIG. 45, when a plurality of processing apparatuses 1 exist, one of the processing apparatuses 1 is used as a master apparatus 1-1, and the other apparatuses are used as slave apparatuses 1-2, 1-3,. The devices are connected, and the processing results of all the slave devices 1-2, 1-3,... Are aggregated in the master device 1-1. Therefore, only by connecting the master device 1-1 to the outside (10), it is possible to take out the processing results from all the devices 1-2, 1-3,.

  When each processing device 1 is an IC, as shown in FIG. 45, each IC includes a processing circuit 63 (corresponding to module 3), a memory 64 (corresponding to, for example, 13 in FIG. 2), and a data reading circuit 65 (for example, FIG. 14) and the communication interface 66 described above, and a transmission request is sent from the master IC (1-1) to the processing result of the slave ICs (1-2, 1-3 ...). By sending the signal, data of the processing result can be read.

As described above, even if a plurality of ICs (1-1, 1-2, 1-3,...) Are used, the number of communication lines 30 with the outside (10) is necessary for the number of these ICs. Only one system is required. The number of slave ICs is not limited as long as the propagation delay on the signal line 67 allows.
[Example 38]
FIG. 46 is a diagram showing a second digital signal processing system according to Embodiment 38 of the present invention.

  The second digital signal processing system 62 based on the present embodiment 38 is provided with a communication interface 68 capable of transmitting and receiving the processing result of the signal processing to the digital signal processing device 1 described above. A plurality of similar digital signal processing devices 1 are provided (1-1, 1-2, 1-3... In FIG. 40), one of which is a master digital signal processing device 1-1, and the other is a slave digital signal processing device. The signal processing devices (1-2, 1-3,...) Are star-connected to each other through the respective communication interfaces 68 around the master / digital signal processing device 1-1. is there.

  Referring to FIG. 46, when a plurality of the present processing apparatuses 1 exist, one of the processing apparatuses 1 is referred to as a master apparatus 1-1, and the others are referred to as slave apparatuses 1-2, 1-3. (1-1, 1-2, 1-3,...) Are connected, and the processing results of all the slave devices 1-2, 1-3,. Therefore, the processing results from all the devices 1-2, 1-3,... Can be taken out only by connecting the master device 1-1 to the outside (10).

here,
When each processing device 1 is an IC, as shown in FIG. 46, each IC has the above-described circuits 63, 64, and 65 and the communication interface 68 described above. By transmitting a transmission request signal for the processing result of each slave IC directly, data of the processing result can be read.

As described above, even if a plurality of ICs (1-1, 1-2, 1-3,...) Are used, the number of communication lines 30 with the outside (10) is necessary for the number of these ICs. Only one system is required. Further, as compared with the above system 61 (FIG. 45), the results of any IC can be obtained at the same response speed.
(Example 39)
Embodiments 1 to 38 so far have been mainly directed to a preprocessing IC (digital signal processing device 1), for example, with reference to FIG.

  This embodiment 39 and embodiments 40 to 42 to be described later are directed to the microcomputer (host device 10) itself with reference to FIG.

  FIG. 47 is a flowchart showing the operation of the host device 10 according to the embodiment 39 of the present invention.

  The thirty-ninth embodiment and the forty-fourth embodiment described below are mainly aimed at realizing fail-safe.

  Even when a system such as the ECU shown in FIG. 4 breaks down, it is necessary to perform the minimum required operation. For example, in the use of the ECU for controlling the engine of a vehicle, even if the ECU fails, it is not sufficient to perform an optimum fuel injection control or the like, but it is sufficient if the ECU can manage to reach the repair shop. In such a case, the data in the processing may not always be an accurate value.

  Whether the value output from the device 1 is normal is judged by the host device 10 on the receiving side, and when it is judged that there is an abnormality, the abnormality is notified from the receiving side (10) to the device 1. Then, the product (automobile) on which the device 1 is mounted can ensure the minimum necessary operation.

  FIG. 47 shows that for data determined to be abnormal, the output value from the present apparatus 1 is discarded, and a default value prepared in advance by the receiver apparatus 10 is used.

  That is, the host device 10 according to the thirty-ninth embodiment is a host device that receives the data of the processing result by the signal processing transmitted from the digital signal processing device 1 described above. Is discarded, and a default value stored in advance is used instead.

Referring to FIG.
Step S11: The host device 10 receives the data N transmitted from the device 1. The data N is data calculated by the above-described signal processing N (N = 1, 2, 3, 4,...).

Step S12: If the host device 10 determines that the data N is within the normal range (YES),
Step S13: The host device 10 performs a predetermined calculation process using the data N.

  Step S14: If the result of the above step S12 is NO, the received data N is discarded, and the above-mentioned predetermined arithmetic processing is performed using the default value D instead. The point of the embodiment 39 lies in this step S14.

Step S15: Further, the data (N + 1) is received, and the next arithmetic processing is started.
[Example 40]
FIG. 48 is a flowchart illustrating the operation of the host device 10 according to the working example 40 of the invention.
FIG. 49 is a flowchart showing the operation of the signal processing device 1 in cooperation with the operation of FIG.

  FIGS. 48 and 49 show that the receiver (10) informs the device (1) of the output value determined to be abnormal, so that the device 1 outputs the default value of the output value. To do.

  That is, the host device 10 according to the fortieth embodiment is a host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device 1 described above, and determines that the data of the processing result is abnormal. The signal processing that caused the abnormal data is specified, the specified information is returned to the signal processing device 1, and the default value D previously stored in the device 1 corresponding to the specified signal processing is returned. To use.

  Referring to FIG. 48, step S21 is a feature of the present embodiment 40, and the “notification” in S21 activates the flowchart of FIG.

Referring to FIG.
Step S31: The device 1 receives a signal transmitted from the host device 10, which is the recipient of the processing result.

Step S32: It is determined whether the received signal is an abnormal signal resulting from step S21 in FIG. 48, and if YES,
Step S33: The above-described processing sequence (for example, see the processing order 1, 2, 3,... In FIG. 14) in which the host device 10 processes the data N determined to be abnormal is based on the same processing sequence thereafter. As a processing result, a default value prepared in advance in the apparatus 1 is output.

Step S34: The apparatus 1 enters a further processing sequence.
[Example 41]
The forty-first embodiment corresponds to the twenty-second embodiment described above, but the host device 10 in the forty-first embodiment receives the data of the processing result by the signal processing transmitted from the digital signal processing device 1 described above. The host device receives an ID indicating the functional module 3 that has generated each processing result transmitted from the device 1 in addition to the data of each processing result. Then, when it is determined that there is a failure in a certain functional module 3 (for example, B), the ID of the functional module (B) is transmitted to the device 1 to specify the failure location.
[Example 42]
The last embodiment 42 corresponds to the above-described embodiment 23. However, the host device 10 in the present embodiment 42 converts the data of the processing result by the signal processing transmitted from the digital signal processing device 1 described above. The above-mentioned processing sequence information for designating one or a plurality of functional modules 3 to be selected corresponding to each channel (CH1, CH2,...) Is transmitted to and read from the device 1. Further, predetermined data is transmitted to execute the processing sequence. The device 10 receives the processing result data from the device 1 and compares it with a predetermined expected value. Then, the normality of the read processing sequence information is determined based on the comparison result.

  INDUSTRIAL APPLICABILITY The digital signal processing circuit according to the present invention can be used in a system that requires a plurality of types of functional modules to perform desired signal processing on a plurality of types of input signals. In this case, a single IC can flexibly cope with any combination of an input signal and a functional module.

1 is a diagram illustrating a basic configuration of a digital signal processing device according to the present invention. FIG. 2 is a diagram more specifically showing the basic configuration of FIG. 1. 3 is a time chart for explaining the processing operation of FIG. 2. 1 is a diagram illustrating an example of a system to which the present invention is applied. FIG. 5 is a diagram showing a writing unit according to the present invention to be added to FIG. 4. FIG. 3 is a diagram more specifically showing the selection / control means 4 shown in FIG. 2 and its periphery. FIG. 2 is a diagram illustrating an example of an input signal of each channel and an example of a functional module that processes the input signal. 7 is a flowchart showing an operation example of the selection / control means 4 shown in FIG. 9 is a time chart corresponding to the flowchart of FIG. It is a figure showing an example of a channel processing order. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an apparatus configuration diagram for explaining a first embodiment according to the present invention. FIG. 12 is a diagram showing the contents of a sequence memory 6 in FIG. 11. 13 is a time chart showing a processing operation based on the processing sequence of FIG. FIG. 9 is a diagram showing contents of a sequence memory 6 for explaining a second embodiment according to the present invention. 15 is a time chart illustrating a processing operation based on the processing sequence in FIG. 14. FIG. 8 is a device configuration diagram for explaining a third embodiment according to the present invention. FIG. 17 is a diagram showing contents of a sequence memory 6 of FIG. 16. 18 is a time chart illustrating a processing operation based on the processing sequence in FIG. 17. 14 is a processing operation time chart for explaining Embodiment 4 according to the present invention. 14 is a processing operation time chart for explaining Embodiment 5 according to the present invention. FIG. 13 is a configuration diagram of an apparatus according to a sixth embodiment of the present invention. FIG. 22 is a diagram showing the contents of a parameter memory 7 of FIG. 21. FIG. 13 is a device configuration diagram of a seventh embodiment according to the present invention. FIG. 16 is a diagram illustrating a device configuration of a ninth embodiment according to the present invention. It is a figure showing the device composition of Example 10 by the present invention. FIG. 16 is an apparatus configuration diagram for explaining an eleventh embodiment according to the present invention. (A) is a time chart showing a processing operation not according to the eleventh embodiment, and (b) is a time chart showing a processing operation according to the eleventh embodiment. FIG. 16 is an apparatus configuration diagram for explaining Embodiment 12 according to the present invention. (A) is a time chart illustrating a processing operation not according to the twelfth embodiment, and (b) is a time chart illustrating a processing operation according to the twelfth embodiment. FIG. 16 is an apparatus configuration diagram for explaining Embodiment 13 according to the present invention. FIG. 19 is an apparatus configuration diagram for explaining Embodiment 14 according to the present invention. FIG. 24 is an apparatus configuration diagram for explaining Embodiment 17 according to the present invention. FIG. 33 is a diagram showing a communication data format on a communication line 30 in FIG. 32. FIG. 27 is an apparatus configuration diagram for explaining Embodiment 18 according to the present invention. FIG. 32 is an apparatus configuration diagram for explaining Embodiment 19 according to the present invention. FIG. 19 is an apparatus configuration diagram for explaining Embodiment 20 according to the present invention. FIG. 25 is a diagram showing data for explaining Example 23 according to the present invention. FIG. 27 is an apparatus configuration diagram for explaining Embodiment 27 according to the present invention. FIG. 39 is a diagram showing an example of a data structure of data used in FIG. 38. FIG. 35 is a sequence diagram for explaining Embodiment 31 according to the present invention. FIG. 32 is a sequence diagram for explaining Embodiment 32 according to the present invention. FIG. 39 is a sequence diagram for explaining Example 33 according to the present invention. FIG. 35 is a sequence diagram for explaining Example 34 according to the present invention. FIG. 35 is a sequence diagram for explaining Example 35 according to the present invention. FIG. 37 is a diagram illustrating a first digital signal processing system according to Embodiment 37 of the present invention. FIG. 39 is a diagram illustrating a second digital signal processing system according to Embodiment 38 of the present invention. 40 is a flowchart illustrating an operation of the host device 10 according to the embodiment 39 of the present invention. 35 is a flowchart illustrating an operation of the host device 10 according to the embodiment 40 of the present invention. FIG. 50 is a flowchart illustrating an operation of the signal processing device 1 cooperating with the operation of FIG. 48.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... Digital signal processing apparatus 2 ... Input part 3 ... Function module 4 ... Selection / control means 5 ... Memory means 6 ... Sequence memory 7, 7A, 7B, 7C ... Parameter memory 8 ... Output part 9 ... Shared bus 10 ... Host device (Microcomputer)
11 Separation part (MPX)
12 AD conversion unit 13 Processing buffer 14 Output distribution unit 15 Interrupt processing sequence 21, 22, 23 Individual bus 24 Single bus 26 Parameter register 27 Signal path 28 Low speed communication line 29 ... High-speed communication line 30 ... Communication line 41 ... Current module group 42 ... Spare module group 47 ... Individual module check bit 50 ... Test processing sequence 52 ... Pause period 53 ... Stop period 61 ... First digital signal processing system 62 ... Second digital signal processing system 66 Communication interface 67 Cascade connection line 68 Communication interface 69 Star connection line 71 Sequence writing means 72 Parameter writing means 73 Sequence memory 74 Parameter memory 75 Channel order memory 81 Read memory 82 ... module control unit

Claims (58)

An input for receiving each input signal from a plurality of channels;
A plurality of functional modules each of which can receive a signal from the input unit in common, and which performs signal processing by a function unique to each of the signals received in a predetermined order,
Module selection / control means for sequentially selecting one or a plurality of the function modules corresponding to each of the plurality of channels, and performing signal processing of the input signal for the selected function module;
A digital signal processing device comprising:   It further includes a memory unit, and the memory unit has a sequence memory that rewritably holds processing sequence information for designating the one or more functional modules to be selected for each of the channels. The digital signal processing device according to claim 1.   The digital device according to claim 1, further comprising a memory unit, wherein the memory unit includes a parameter memory for rewritably storing parameter information for modifying the content of the signal processing in each of the functional modules. Signal processing device.   3. The digital signal processing device according to claim 2, further comprising a sequence writing unit that rewrites the processing sequence information to be held in the sequence memory from outside the device.   4. The digital signal processing device according to claim 3, further comprising parameter writing means for rewriting the parameter information to be stored in the parameter memory from outside the device.   When cooperating with a host device that receives data of a processing result of performing the signal processing on the input signal, writing the processing sequence information to the sequence memory is performed via the host device. The digital signal processing device according to claim 4.   When cooperating with a host device that receives data of a processing result of performing the signal processing on the input signal, writing the parameter information to the parameter memory is performed via the host device. Item 6. The digital signal processing device according to item 5.   A plurality of types of predetermined processing sequence information are held in the host device, and the sequence writing means designates the desired processing sequence information and transfers and writes it to the sequence memory. The digital signal processing device according to claim 6.   A plurality of types of predetermined parameter information are held in the host device, and the parameter writing means specifies desired parameter information, and transfers the parameter information to the parameter memory to write the parameter information. Item 8. A digital signal processing device according to item 7.   2. The digital signal processing apparatus according to claim 1, further comprising a channel order memory that holds processing order information of each signal to be subjected to the signal processing.   The module selection / control means includes a memory reading unit, and a module control unit that controls each of the functional modules according to information read from the memory reading unit, and the memory reading unit includes information on the sequence memory. 3. The digital signal processing device according to claim 2, wherein the digital signal is read.   The digital signal processing apparatus according to claim 11, wherein the module control unit controls each of the functional modules according to parameter information from the parameter memory.   The module selection / control means includes a memory read unit and a module control unit that controls each of the functional modules according to read information from the memory read unit. The digital signal processing device according to claim 10, wherein information is read.   4. The digital signal according to claim 2, wherein the module selection / control means rewrites the contents of one or both of the sequence memory and the parameter memory even during the operation of the digital signal processing device. Processing equipment.   The module selection / control means selects the functional module to be selected for each of the channels in accordance with a specified series of processing sequences, and when a new interrupt input signal is generated as the input signal, the specified module is designated. 2. The digital signal processing device according to claim 1, wherein an interrupt processing sequence is inserted into the series of processing sequences.   16. The digital signal processing according to claim 15, wherein the processing for the input signal of the channel that should have been processed in one of the processing sequences overlapping the insertion of the interrupt processing sequence is stopped. apparatus.   The processing for the input signal of the channel, which should have been processed in one processing sequence overlapping with the insertion of the interrupt processing sequence, is temporarily suspended, and the processing is started as soon as the interrupt processing sequence ends. The digital signal processing device according to claim 15, wherein:   4. The parameter memory according to claim 3, wherein the parameter memory holds the parameter information set for each of the channels in advance, and the parameter memory is a shared memory referred to by all of the function modules. 5. Digital signal processing device.   4. The parameter memory according to claim 3, wherein the parameter memory is an individual memory built in each of the function modules, and the individual memory holds the parameter information set for each of the channels in advance. Digital signal processing device.   15. The digital signal processing device according to claim 14, wherein an operation characteristic in the signal processing is changed by the modification.   A shared bus connecting at least the input unit, the functional module, and the module selection / control means, and the shared bus is a plurality of individual buses separated for each data type handled in the signal processing; The digital signal processing device according to claim 1, comprising:   A shared bus connecting at least the input unit, the function module, and the module selection / control means, and the shared bus transfers a plurality of types of data handled in the signal processing in a time-division manner 2. The digital signal processing device according to claim 1, wherein the digital signal processing device comprises a single bus.   When at least two of the function modules are sequentially selected and execute respective signal processing, during the signal processing in the preceding function module, the parameter information to be used in the subsequent function module is acquired. 4. The signal processing according to claim 3, wherein immediately after the signal processing in the preceding functional module is completed, the signal processing in the subsequent functional module is started using the acquired parameter information. Digital signal processing device.   When the first signal processing and the second signal processing are sequentially and sequentially executed in the same functional module, the parameter information to be used in the second signal processing during the execution of the first signal processing. 4. The digital signal processing apparatus according to claim 3, wherein the second signal processing is started using the obtained parameter information immediately after the first signal processing is completed. .   When the output data obtained in the first signal processing is returned to the function module for use in the second signal processing, the output data is transmitted through a signal path in the function module without being sent out of the function module. The digital signal processing device according to claim 24, wherein the digital signal is returned.   2. The digital signal processing device according to claim 1, further comprising a low-speed communication line and a high-speed communication line as communication lines for transmitting a processing result of the signal processing to an external host device.   The low-speed communication line is a communication line that performs the transmission at a fixed cycle when a transmission request is received from the host device, and the high-speed communication line is the communication line each time in response to a transmission request from the host device. The digital signal processing device according to claim 26, wherein the digital signal processing device is a communication line that performs transmission.   27. The digital signal processing device according to claim 26, wherein the low-speed communication line and the high-speed communication line are each configured by a parallel line.   27. The digital signal processing device according to claim 26, wherein the low-speed communication line and the high-speed communication line are each configured by a serial line.   An output unit that transmits a processing result by the signal processing to the outside, the output unit includes an ID indicating a processing result of the input signal from any one of the plurality of channels. 2. The digital signal processing device according to claim 1, wherein the digital signal processing device further transmits the processing result data.   An output unit that transmits a processing result by the signal processing to the outside, the output unit sequentially transmits a processing result of each of the input signals of the plurality of channels in accordance with a transmission order assigned to each of the channels. The digital signal processing device according to claim 1, wherein:   At least a shared bus for connecting the plurality of function modules is provided, and when these plurality of function modules are set as active function modules, a spare function module group that forms a mirror with the active function modules is connected via the shared bus. 2. A function module in the spare function module group is selected and used when it is determined that any of the function modules in the working function module group has a failure. A digital signal processing device according to claim 1.   At least a shared bus for connecting the plurality of function modules is provided, and when these plurality of function modules are set as active function modules, a spare function module group that forms a mirror with the active function modules is connected via the shared bus. 2. The digital signal processing device according to claim 1, wherein when it is determined that any of the function modules in the working function module has a failure, the function module is switched to the spare function module and used. .   When the signal processing in the digital signal processing device is completed, a record of the functional module having the failure is held, and when the digital signal processing device is restarted, the normal function is used based on the record. The digital signal processing device according to claim 33, wherein a function module is selected and used.   When the signal processing in the digital signal processing device is completed, a record of the functional module group having the failure is kept, and when the digital signal processing device is restarted, a normal operation is performed based on the record. 35. The digital signal processing device according to claim 34, wherein the functional module group is selected and used.   When there is an external host device to which the processing result by the signal processing is to be transmitted, an ID indicating the module that has generated each of the processing results is added to the data of each processing result, and the data is transmitted to the host device. 34. The digital signal processing device according to claim 32, wherein the device determines whether or not the failure has occurred, and receives, from the host device, identification information identifying the functional module having the failure.   When there is an external host device to which the processing result of the signal processing is to be transmitted, the processing sequence information to be held in the sequence memory is read from the host device, and when the reading is completed, the digital signal processing is performed by the host device. The read processing sequence is executed by giving predetermined data to the apparatus, and the result of the processing is received by the host apparatus and compared with a predetermined expected value. The digital signal processing device according to claim 2, wherein it is confirmed that there is a digital signal.   38. The digital signal processing device according to claim 37, wherein when the comparisons do not match, the host device retransmits the processing sequence information and performs the same confirmation again.   39. The digital signal processing device according to claim 38, wherein when the mismatch is not resolved, an alarm is sent to an external user.   The processing sequence information read from the host device is returned to the checking device in the host device or an external device equivalent to the checking device as it is, and the returned processing sequence information matches the transmitted processing sequence information. 38. The digital signal processing device according to claim 37, wherein when the value is removed, it is confirmed that the reading processing sequence is normal.   At the end of the signal processing in each of the selected functional modules, an individual module check bit indicating the normal end of the signal processing is generated for each of the functional modules, and the bit sequence matches the expected bit sequence. 3. The digital signal processing device according to claim 2, wherein a determination is made as to whether the functional module is faulty.   Upon completion of the signal processing in each of the selected functional modules, each time the signal processing is normally completed in each of the functional modules, a cumulative module check bit indicating an accumulated value sequentially added or subtracted is generated. 3. The digital signal processing device according to claim 2, wherein a failure determination of the functional module is performed by determining whether a value matches an expected cumulative value.   43. An external host device to which a processing result by the signal processing is to be transmitted, the expected value of the failure determination is obtained based on the processing sequence transmitted from the host device. A digital signal processing device according to claim 1.   43. The digital signal processing device according to claim 41, wherein the expected value of the failure determination is obtained based on the processing sequence originally held by the digital signal processing device.   The method according to claim 2, wherein a test processing sequence is incorporated in the processing sequence information, and the operation of the plurality of functional modules is confirmed by running the test processing sequence at a predetermined cycle. Digital signal processing device.   In the processing sequence information, a test processing sequence is incorporated, and when there is a pause period of signal processing between two adjacent signal processes, the test processing sequence is run during the pause period. 3. The digital signal processing device according to claim 2, wherein operation confirmation of a plurality of functional modules is performed.   A test processing sequence is incorporated in the processing sequence information, and when a test command is applied from outside, the signal processing that matches the application timing is stopped and the test processing sequence is forcibly applied. The digital signal processing device according to claim 2, wherein the digital signal processing device executes the operation to check operations of the plurality of functional modules.   A test processing sequence is incorporated in the processing sequence information, and when a test command is applied from the outside, the signal processing that matches the application timing is postponed to force the test processing sequence. The digital signal processing device according to claim 2, wherein the digital signal processing device executes the operation to check operations of the plurality of functional modules.   In the processing sequence information, a test processing sequence is incorporated, and when a test command is applied from the outside, the test processing sequence is executed after waiting for an idle time to suspend the signal processing, 3. The digital signal processing device according to claim 2, wherein operation confirmation of a plurality of functional modules is performed.   2. The digital signal processing device according to claim 1, further comprising: a communication interface capable of transmitting and receiving the processing result of the signal processing; and providing a plurality of digital signal processing devices similar to the digital signal processing device to each of the communication interfaces. A digital signal processing system comprising a cascade connection of these via an interface.   The digital signal processing device according to claim 1, further comprising a communication interface capable of transmitting and receiving the processing result of the signal processing, and a plurality of digital signal processing devices similar to the digital signal processing device being provided, and one of them being provided. A master digital signal processing device, and the other as a slave digital signal processing device, and these are star-connected through the respective communication interfaces, with the master digital signal processing device at the center. Digital signal processing system. In a digital signal processing device including at least an input unit and a plurality of functional modules,
Each of the plurality of functional modules has a unique signal processing function,
A digital signal processing method, wherein an input signal for each of a plurality of channels, which is input to the input unit, is provided to one or a plurality of the functional modules selected for each of the channels to perform signal processing.   A series of processing sequences for designating one or more functional modules to be used for each of the channels is held in advance, and the series of processing sequences are sequentially read to execute the signal processing. 53. The digital signal processing method according to claim 52.   Parameter information for modifying the content of the signal processing in each of the functional modules is stored in advance, and the parameter information corresponding to the property of the input signal for each channel is read out to execute the signal processing. 53. The digital signal processing method according to claim 52, wherein: A host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device according to claim 1,
When there is an abnormality in the data resulting from the processing, the host device discards the data and uses a previously stored default value instead. A host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device according to claim 1,
When it is determined that there is an abnormality in the data of the processing result, the signal processing that caused the abnormal data is identified, and this identification information is returned to the digital signal processing device to respond to the identified signal processing. A host device for using a previously stored default value. A host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device according to claim 1,
When the ID indicating the functional module that generated the processing result transmitted from the digital signal processing device in addition to the data of each processing result is received, and when it is determined that there is a failure in the functional module, A host device for transmitting an ID of a functional module to the digital signal processing device to specify a failure location. A host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device according to claim 1,
Transmits and reads processing sequence information for specifying the one or more functional modules to be selected for each of the channels to the digital signal processing device, and further transmits predetermined data to execute the processing sequence. A host device that receives the processing result data from the digital signal processing device and compares the data with a predetermined expected value to determine the normality of the read processing sequence information.

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