JP2004186790A - Solid-state imaging apparatus and drive method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus and a drive method thereof for enhancing the immunity against an external disturbing noise by suppressing a fixed pattern noise caused by fluctuation in a threshold voltage of transistors and the capacitance of capacitors being components of a read system. <P>SOLUTION: The solid-state imaging apparatus is configured such that a floating switch 28 is provided between a ground level Vref2 and ground side terminals of a reset capacitor CapN and a signal level capacitor CapS for each column of an imaging pixel 10, the ground side terminals being connected in common, so as to disconnect the capacitors from a ground line, the floating switch 28 is turned off when respective sample signals (N) and (S+N) stored in the reset capacitor CapN and the signal level capacitor CapS are read on a horizontal signal line of a horizontal output section 50 so as to disconnect the reset capacitor CapN and the signal level capacitor CapS from the ground line thereby bringing the capacitors into a floating state. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having a readout circuit including an active element for each pixel, such as a CMOS image sensor, and a method of driving the solid-state imaging device. 1. Field of the Invention The present invention relates to a solid-state imaging device including a circuit having a configuration in which two systems of capacitors for respectively storing level signals are provided for each column of a pixel portion, and a difference between charges stored in these capacitors is taken out, and a driving method thereof. .
[0002]
[Prior art]
2. Description of the Related Art In recent years, video cameras and electronic cameras have become widespread, and CCD and CMOS solid-state imaging devices have been used for these cameras.
Among them, the CMOS type image sensor is provided with an imaging pixel unit configured by two-dimensionally arranging a plurality of pixels on one semiconductor chip, and a peripheral circuit unit disposed outside the imaging pixel unit. Each pixel of the imaging pixel unit has a photoelectric conversion element (photodiode) and a readout circuit using various MOS transistors such as an FD unit and a transfer / amplification unit. The light incident on each pixel is photoelectrically converted by the photodiode. A signal charge is generated, the signal charge is transferred to the FD section by a transfer transistor, and a potential change of the FD section is detected and amplified by an amplifying transistor, thereby outputting a signal for each pixel to a peripheral circuit section from a signal line. (For example, see Non-Patent Document 1).
[0003]
[Non-patent document 1]
"Analysis and Reduction of Signal Readout Circuitry Temporal Noise in CMOS Image Sensors for Low-Light Levels Levels", "IEEE TRANSLATION CONTROLS." 47. NO. 5 MAY 2000 pp. 949-950
[0004]
Hereinafter, a conventional solid-state imaging device and a driving method thereof will be described with reference to FIGS.
FIG. 9 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a conventional CMOS image sensor and a part of a driving circuit for reading out signals from the pixel portion.
The solid-state imaging device shown in this circuit diagram includes a pixel 90, a sampling circuit 200 for noise suppression, a horizontal output unit 201, a horizontal scanning circuit 101, and the like.
[0005]
The pixel 90 is supplied with a photodiode 91 as a photoelectric conversion element, a floating diffusion (FD) 92 for obtaining a potential change according to the amount of charge transferred from the photodiode 91, and a transfer pulse φTX. A transfer MOS transistor 93 connected to the photodiode 91 to transfer the signal charge transferred from the photodiode 91 to the FD unit 92, and a reset MOS transistor connected to the power supply Vdd when the reset pulse φRST is supplied. A transistor 94; an amplifying MOS transistor 95 for converting to an electric signal corresponding to a potential change of the FD section 92; and a selecting MOS for supplying an output signal of the amplifying MOS transistor 95 to a vertical signal line 96 by supplying a vertical selection pulse φVSEL. And a transistor 97. To have.
[0006]
The sampling circuit 200 is for removing or suppressing noise components such as reset noise. The sampling circuit 200 is connected in parallel between the vertical signal line 96 and the ground, and is a reset level sample obtained from the FD unit 92 at the time of reset. A reset level capacitor CapN for accumulating a signal and a signal level capacitor CapS for accumulating a signal level sample signal (image signal) obtained from the FD unit 92 by a signal charge from the photodiode 91 are provided.
A switch 98 turned on by a selection pulse φOPN is connected in series to the vertical signal line 96 side of the reset level capacitor CapN, and turned on by a selection pulse φOPS to the vertical signal line 96 side of the signal level capacitor CapS. A switch 99 is connected in series.
Horizontal scanning is performed between the vertical signal line 96 side end of the reset level capacitor CapN and the horizontal signal line 100a and between the vertical signal line 96 side end of the signal level capacitor CapS and the horizontal signal line 100b. Selection switches 102a and 102b that are turned on by a horizontal switching pulse φHSWn from the circuit 101 are connected in series.
[0007]
The horizontal output unit 201 extracts a difference between a sample signal value output from the reset level capacitor CapN to the horizontal signal line 100a and a sample signal value output from the signal level capacitor CapS to the horizontal signal line 100b. An OP amplifier 103 is provided.
A capacitor 104a and its reset switch 105a are connected in parallel between an output terminal, which is a feedback loop of the differential OP amplifier 103, and the horizontal signal line 100a. Between a certain output terminal and the horizontal signal line 100b, a capacitor 104b and its reset switch 105b are connected in parallel.
In FIG. 9, reference numeral 106 denotes a constant current source for supplying a driving current to the pixel 90. The constant current source 106 is connected to the vertical signal line 96 for each pixel column.
[0008]
Next, the operation of the solid-state imaging device configured as described above will be described with reference to a timing chart shown in FIG. Each of the pulse signals shown in FIGS. 10A to 10J is generated from a timing generator (not shown) provided to the solid-state imaging device.
When reading out signals from the pixels 90 constituting the solid-state imaging device, first, a vertical selection pulse φVSEL having a waveform shown in FIG. 10B synchronized with a reference clock φCLK shown in FIG. The supply turns on the selection MOS transistor 97. In this state, when a reset pulse φRST having a waveform shown in FIG. 9C is applied to the gate of the reset MOS transistor 94, the reset MOS transistor 94 is turned on, and the potential of the FD section 92 is changed to the power supply potential Vdd. Simultaneously with the reset, the selection switch 98 is turned on by the selection pulse φOPN having the waveform shown in FIG. Accordingly, when the amplification MOS transistor 95 is turned on, a current corresponding to the potential obtained from the FD unit 92 at the time of reset flows through the amplification MOS transistor 95, the selection MOS transistor 97, and the selection switch 98 to the reset level capacitor CapN. , The reset level sample signal (N) is stored in the reset capacitor CapN.
[0009]
Next, a transfer pulse φTX having the waveform shown in FIG. 7E is applied to the gate of the transfer MOS transistor 93, so that the transfer MOS transistor 93 is turned on and the selection switch 99 is turned on at the same time as shown in FIG. It is turned on by the waveform selection pulse φOPS. As a result, the signal charge accumulated in the photodiode 91 is transferred to the FD section 92 through the transfer MOS transistor 93, and the current corresponding to the signal level obtained from the FD section 92 is transferred by the signal charge to the amplification MOS transistor 95 and the selection MOS transistor. It flows to the signal level capacitor CapS through the switch 97 and the switch 99. As a result, the signal level sample signal (S + N) including the noise component is accumulated in the signal level capacitor CapS.
The sampling and holding of the reset-level sample signal (N) and the signal-level sample signal (S + N) are performed for each column of the imaging pixel unit and during a blanking period of horizontal scanning.
[0010]
Then, the reading of the signal corresponding to the difference between the sample signal (N) at the reset level after the sample hold and the sample signal (S + N) at the signal level is performed for each column of the imaging pixel unit within the valid period shown in FIG. Done.
That is, in the valid period shown in FIG. 10, first, the reset switches 105a and 105b of the differential OP amplifier 103 are turned on by the differential OP amplifier reset pulse φOPRST synchronized with the reference clock φCLK, whereby the differential OP amplifier 103 The electric charge stored in the capacitors 104a and 104b is released to initialize the differential OP amplifier 103. Thereafter, horizontal switching pulses φHSW1 to φHSWn, φHSWn + 1 are sequentially transmitted from the horizontal scanning circuit 101 for each column of the imaging pixel unit, and the switches 102a and 102b in each column are sequentially turned on. Each of the sample signal (N) and the sample signal (S + N) accumulated in the level capacitor CapS is input to the differential OP amplifier 103, and the difference between the two sample signals from the differential OP amplifier 103, that is, the sample Only a signal component corresponding to the difference (S + NN-S) between the signal (N) and the sample signal (S + N) is output.
[0011]
Next, another example of the conventional solid-state imaging device will be described with reference to FIGS.
FIG. 11 is a circuit diagram showing a pixel of a solid-state imaging device and a part of a driving circuit for reading out a signal of the pixel in another conventional example.
The solid-state imaging device shown in this circuit diagram includes a pixel 90, a sampling circuit 202 for noise suppression (corresponding to CDS: correlated double sampling), a horizontal output unit 203, a horizontal scanning circuit 101, a constant current source 106, and the like. I have.
The pixel 90 includes a photodiode 91, an FD unit 92, a transfer MOS transistor 93, a reset MOS transistor 94, an amplification MOS transistor 95, and a selection MOS transistor 97, as in the case shown in FIG.
[0012]
The CDS section 202 is for removing or suppressing noise components such as reset noise, and is turned on by a clamp capacitor C11 and a sample hold capacitor C12, a clamp switch 111 turned on by a clamp pulse φCLP, and a sample hold pulse φSH. And a selection switch 102 which is turned on by a horizontal switching pulse φHSWn from the horizontal scanning circuit 101.
Further, the horizontal output unit 203 includes a differential OP amplifier 103A that extracts a sample signal of the sample-and-hold capacitor C12. An inverting input terminal of the differential OP amplifier 103A is connected to the horizontal signal line 100, and a reference potential Vref is applied to a non-inverting output terminal.
A capacitor 104a and its reset switch 105a are connected in parallel between an output terminal, which is a feedback loop of the differential OP amplifier 103A, and the horizontal signal line 100.
[0013]
Next, the operation of the solid-state imaging device configured as described above will be described with reference to a timing chart shown in FIG. Each of the pulse signals shown in FIGS. 12A to 12J is generated from a timing generator (not shown) attached to the solid-state imaging device.
When reading signals from the pixels 90 constituting the solid-state imaging device, first, a vertical pulse φVSEL having a waveform shown in FIG. 12B synchronized with a reference clock φCLK shown in FIG. As a result, the selection MOS transistor 97 is turned on. In this state, a reset pulse φRST having a waveform shown in FIG. 9C is applied to the gate of the reset MOS transistor 94, so that the reset MOS transistor 94 is turned on and the clamp switch 111 is simultaneously turned to the state shown in FIG. When turned on by the clamp pulse φCLP having the waveform shown, the potential of the FD section 92 is reset to the power supply potential Vdd, and at the same time, a sample signal of this reset level is accumulated in the clamp capacitor C11. Is clamped to the clamp voltage Vclp. At this time, the sample hold switch 112 is turned on by the sample hold pulse φSH having the waveform shown in FIG.
[0014]
Next, a transfer pulse φTX having a waveform shown in FIG. 12E is applied to the gate of the transfer MOS transistor 93, and when the transfer MOS transistor 93 is turned on, the signal charges accumulated in the photodiode 91 are transferred to the transfer MOS transistor 93. The data is transferred to the FD unit 92 through the transistor 93. Accordingly, a sample signal having a signal level corresponding to the signal charge of the photodiode 91 is input to the clamping capacitor C11.
Here, when the output side of the clamping capacitor C11 is clamped at the clamp voltage Vclp, the input side and the output side of the clamping capacitor C11 are held at different potentials. , The input-side potential variation appears as an output-side potential variation, and this potential variation is sampled and held by the sample and hold capacitor C12 when the sample and hold switch 112 is turned on. At this time, the sample signal sampled into the sample-and-hold capacitor C12 is only a signal component from which a noise component has been removed or suppressed.
Then, the sample and hold of the output value of the clamp capacitor C11 by the sample and hold capacitor C12 is performed for each column of the imaging pixel unit within the valid period shown in FIG.
[0015]
That is, in the valid period shown in FIG. 12, first, the reset switch 105 of the differential OP amplifier 103A is turned on by the differential OP amplifier reset pulse φOPRST synchronized with the reference clock φCLK, whereby the capacitor 104 of the differential OP amplifier 103A is turned on. , And the differential OP amplifier 103A is initialized. Thereafter, horizontal switching pulses φHSW1 to φHSWn, φHSWn + 1 are sequentially transmitted from the horizontal scanning circuit 101 for each column of the imaging pixel unit, and the switches 102 in each column are sequentially turned on. The sample signal is input to the differential OP amplifier 103A. As a result, only the signal component from which the noise component has been removed or suppressed is output from the differential OP amplifier 103A.
[0016]
[Problems to be solved by the invention]
However, as shown in FIG. 9, two systems of reset level capacitors CapN and CapS for respectively storing a reset level sample signal (N) and a signal level sample signal (S + N) are provided for each column of the pixel unit. And the differential function of taking out the difference (S + N−N = S) between the sample signal (N) and (S + N), or the reset level as shown in FIG. Of the sample signal N (or the sample signal S + N at the signal level), and then read out the sample signal S + N at the signal level (or the sample signal N at the reset level) to obtain the difference between the sample signal N and the pixel signal. With one read-out system (clamp & sample hold type) To have a look out circuit, the variation in the threshold voltage Vth and capacitance value of the transistor which is a component, there is a problem that vertical stripe-shaped fixed pattern noise (FPN) occurs.
[0017]
For example, in the above-mentioned differential type, a capacitor is used as a sample-and-hold means. In a case where reading to a horizontal signal line is performed by using electric charges, variation in capacitance value between the reset level capacitor and the signal level capacitor may occur. Due to the difference between the horizontal signal line potential and the capacitor potential, even if the signal level is 0, it appears as FPN.
In the case of the clamp & sample hold type, the above problem can be avoided by setting the clamp potential equal to the horizontal line potential. However, this circuit type having a single-ended output has a large size (for example, 1/6 inch optical system). However, there is a problem that there is no resistance to noise from a horizontal signal line having a length of about 2 mm), for example, noise through a substrate due to the mixed mounting of a digital signal processor (DSP).
[0018]
SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device capable of suppressing fixed pattern noise due to variations in threshold voltage and capacitance value of a transistor as a readout constituent element and improving resistance to disturbance noise, and a method of driving the same. Is to provide.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, a solid-state imaging device according to the present invention includes an imaging pixel unit in which a plurality of pixels including a photoelectric conversion element and a readout circuit thereof are arranged in a plurality of rows and columns, and a readout circuit of the imaging pixel unit. And a column signal processing circuit including a capacitor for sequentially reading the reset level and signal level signals of each pixel and separately storing the read reset level and signal level signals. A column selection circuit for selecting a reset level sample signal sampled and held by a capacitor of the signal processing circuit and a signal level sample signal for each pixel column and outputting the selected signal to a horizontal signal line; and a reset read to the horizontal signal line. A horizontal output unit that outputs a difference between the level sample signal and the signal level sample signal.
[0020]
Further, the present invention provides an imaging pixel portion in which a plurality of pixels including a photoelectric conversion element and a readout circuit thereof are arranged in a plurality of rows and columns, and a readout circuit of the imaging pixel portion is selected for each pixel column, and And a column signal processing circuit including a capacitor that separately accumulates the read reset level and signal level signals, and a sampled and held by the column signal processing circuit capacitor. A column selection circuit for selecting a reset level sample signal and a signal level sample signal for each pixel column and outputting the same to a horizontal signal line; a reset level sample signal and a signal level sample signal read out to the horizontal signal line And a horizontal output unit that outputs a difference between the reset level and the reset level. One end of a capacitor for sampling and holding the signal level is connected to the readout circuit through a vertical signal line, and the other end of both capacitors is commonly connected to and disconnected from a ground potential by a floating switch, and the reset When reading out the level and the signal level to the horizontal signal line, the two capacitors are separated from the ground potential to be in a floating state.
[0021]
In the solid-state imaging device and the method of driving the same according to the present invention, one end of the capacitor for sampling and holding the reset level and one end of the capacitor for sampling and holding the signal level are connected to the readout circuit through a vertical signal line, and the other ends of both capacitors are shared. It is configured so that it can be disconnected and connected to the ground potential by a floating switch, and when reading the reset level and signal level to the horizontal signal line, both capacitors are separated from the ground potential so as to be in a floating state, so it is necessary to use a read-related component It is possible to suppress fixed pattern noise caused by variations in the threshold voltage and the capacitance value of a certain transistor, and to improve resistance to disturbance noise.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a solid-state imaging device and a driving method thereof according to the present invention will be described.
The embodiments described below are preferred specific examples of the present invention, and various technically preferred limitations are added. However, the scope of the present invention is not limited to the embodiments described below. It is not limited to these embodiments unless otherwise specified.
[0023]
In this embodiment, two columns of reset level capacitors and signal level capacitors for storing the reset level sample signal (N) and the signal level sample signal (S + N) are provided for each column of the pixel portion, and By extracting the difference (S + NN-S) between the charges stored in these capacitors, only the signal component is output, thereby suppressing the fixed pattern noise and enabling the resistance to disturbance noise. .
Hereinafter, specific examples of the present invention will be described.
[0024]
FIG. 1 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a CMOS image sensor according to a first embodiment of the present invention and a part of a driving circuit for reading out signals of the pixel portion. FIG. 5 is a timing chart for explaining the operation of the solid-state imaging device according to the first embodiment.
The solid-state imaging device according to the present embodiment is of a differential type, and includes a pixel 10, a sampling circuit 40 for noise suppression, a horizontal output unit 50, and a horizontal scanning circuit 21 which constitute a column signal processing circuit described in the claims. (Corresponding to the column selection circuit of the item).
[0025]
The pixel 10 is supplied with a photodiode 11 as a photoelectric conversion element, a floating diffusion unit (FD unit) 12 for obtaining a potential change according to the amount of charge transferred from the photodiode 11, and a transfer pulse φTX. A transfer MOS transistor 13 that is connected to the photodiode 11 to transfer the signal charge transferred from the photodiode 11 to the FD unit 12 and a reset MOS transistor that connects the FD unit 12 to the power supply Vdd when the reset pulse φRST is supplied. A transistor 14, an amplifying MOS transistor 15 that outputs a voltage corresponding to a potential change of the FD unit 12, and a selecting MOS transistor that outputs an output signal of the amplifying MOS transistor 15 to a vertical signal line 16 by supplying a vertical selection pulse φVSEL. 17 and That.
The FD section 12 and the MOS transistors 13, 14, 15, and 17 constitute a readout circuit of the imaging pixel section. In addition, the imaging pixel unit is configured by arranging a plurality of pixels in a matrix in a plurality of rows and columns.
[0026]
The sampling circuit 40 is for removing or suppressing noise components such as reset noise, is connected in parallel between the vertical signal line 16 and the ground potential Vref2, and has a reset level obtained from the FD section 12 at the time of reset. And a signal level capacitor CapS for storing a sample signal (image signal) of a signal level obtained from the FD unit 92 by the signal charge from the photodiode 91.
A selection switch 18 that is turned on by the selection pulse φOPN is connected in series to a connection side of the reset level capacitor CapN with the vertical signal line 16, and a selection switch 18 connected to the vertical signal line 16 of the signal level capacitor CapS is A selection switch 19 turned on by the selection pulse φOPS is connected in series.
A floating switch 28 that is turned on by a floating pulse φFLTSW is connected in series to the connection side of the reset level capacitor CapN and the signal level capacitor CapS with the ground potential Vref2.
The ground potential Vref2 is set to a value that approximates the dark signal level of the pixel.
[0027]
In addition, between the connection end of the reset level capacitor CapN and the selection switch 18 and the horizontal signal line 20a of the horizontal output unit 50, and between the connection end of the signal level capacitor CapS and the selection switch 19 and the horizontal output unit 50. Select switches 22a and 22b which are turned on by a horizontal switching pulse φHSWn from the horizontal scanning circuit 21 are connected in series with the horizontal signal line 20b.
[0028]
The horizontal output unit 50 calculates a difference between a sample signal (N) output from the reset level capacitor CapN to the horizontal signal line 20a and a sample signal (S + N) output from the signal level capacitor CapS to the horizontal signal line 20b. The differential OP amplifier 23 for extracting (S + NN−S) is provided.
The horizontal signal line 20a is connected to the inverting input terminal of the differential OP amplifier 23, and the horizontal signal line 20b is connected to the non-inverting input terminal of the differential OP amplifier 23.
A capacitor 24a and its reset switch 25a are connected in parallel between the output terminal, which is a feedback loop of the differential OP amplifier 23, and the horizontal signal line 20a. A capacitor 24b and a reset switch 25b are connected in parallel between the output terminal and the horizontal signal line 20b.
In FIG. 1, reference numeral 26 denotes a constant current source for supplying a drive current to the pixel 10, and the constant current source 26 is connected to the vertical signal line 16 for each pixel column.
[0029]
Next, the operation of the solid-state imaging device configured as described above will be described with reference to FIG. Each of the pulse signals shown in FIGS. 2A to 2K is generated from a timing generator (not shown) provided with the solid-state imaging device.
When reading out signals from the pixels 10 constituting the solid-state imaging device, first, a vertical pulse φVSEL having a waveform shown in FIG. 2B synchronized with the reference clock φCLK shown in FIG. By doing so, the selection MOS transistor 17 is turned on. In this state, when a reset pulse φRST having a waveform shown in FIG. 4C is applied to the gate of the reset MOS transistor 14, when the reset MOS transistor 14 is turned on, the potential of the FD section 12 is changed to the power supply potential Vdd. Simultaneously with the reset, the selection switch 18 is turned on by the selection pulse φOPN having the waveform shown in FIG. 10D, and the floating switch 28 is turned on by the floating pulse φFLTSW having the waveform shown in FIG. Accordingly, when the amplification MOS transistor 15 is turned on, a current corresponding to the potential obtained from the FD unit 12 at the time of resetting is supplied to the reset level through the amplification MOS transistor 15, the selection MOS transistor 17, and the selection switch 18 and the floating switch 28. The reset level sample signal (N) flows through the capacitor CapN and is stored in the reset level capacitor CapN. Then, when the reset level sample signal (N) is input to the reset level capacitor CapN, the output of the reset level capacitor CapN is clamped to the ground potential Vref2.
[0030]
Next, a transfer pulse φTX having a waveform shown in FIG. 2E is applied to the gate of the transfer MOS transistor 13 to turn on the transfer MOS transistor 13 and, at the same time, the selection switch 19 is turned on as shown in FIG. It is turned on by the waveform selection pulse φOPS. As a result, the signal charge accumulated in the photodiode 11 is transferred to the FD section 12 through the transfer MOS transistor 13, and a current corresponding to the potential obtained from the FD section 12 by the signal charge is amplified by the amplification MOS transistor 15 and the selection MOS transistor 17. Then, the current flows to the signal level capacitor CapS through the selection switch 19 and the floating switch 28. As a result, the signal level sample signal (S + N) including the noise component is accumulated in the signal level capacitor CapS. When the signal level sample signal (S + N) is input to the signal level capacitor CapS, the output of the signal level capacitor CapS is clamped to the ground potential Vref2.
The sampling and holding of the reset-level sample signal (N) and the signal-level sample signal (S + N) are performed for each column of the imaging pixel unit and during a blanking period of horizontal scanning.
[0031]
Then, the signal (S + NN = S) corresponding to the difference between the sample signal (N) at the reset level after the sample and hold and the sample signal (S + N) at the signal level is read within the valid period shown in FIG. Is performed for each column of the imaging pixel unit.
That is, in the effective period shown in FIG. 2, first, the floating switch 28 is turned off, and the reset level capacitor CapN and the signal level capacitor CapS are separated from the ground potential Vref2 to be in a floating state. In this state, the reset switches 25a and 25b of the differential OP amplifier 23 are turned on by the differential OP amplifier reset pulse φOPRST synchronized with the reference clock φCLK, and are stored in the capacitors 24a and 24b of the differential OP amplifier 23. The charge is released, and the differential OP amplifier 23 is initialized. Thereafter, horizontal switching pulses φHSW1 to φHSWn, φHSWn + 1 are sequentially transmitted from the horizontal scanning circuit 21 for each column of the imaging pixel unit, and when the selection switches 22a and 22b of each column are turned on in order, the reset level capacitors CapN and The sample signals (N) and (S + N) stored in the signal level capacitor CapS are input to the differential OP amplifier 23 through the horizontal signal lines 20a and 20b. As a result, only the signal component corresponding to the difference between the two sample signals, that is, the difference (S + N−N = S) between the sample signal (N) and the sample signal (S + N) is output from the differential OP amplifier 23.
[0032]
When a parasitic capacitance exists in each electrode of the capacitors CapN and CapS, a complete floating state cannot be obtained. As a result, variations in the capacitance of the capacitor appear as fixed pattern noise (FPN) in the form of vertical stripes. Therefore, in this case, it is desirable that the ground potential Vref2 be approximated to the dark signal level of the pixel in order to reduce the influence of FPN.
[0033]
According to the first embodiment, the reset-side capacitor CapN and the signal-level capacitor CapS share the ground-side terminal of each column of the captured image section, and are connected to the ground potential Vref2 from the ground line. A floating switch 28 is provided so as to be detachable, and when the respective sample signals (N) and (S + N) stored in the reset capacitor CapN and the signal level capacitor CapS are read out to the horizontal signal line of the horizontal output unit 50, the floating switch 28 is floated. Since the switch 28 is turned off and the reset capacitor CapN and the signal level capacitor CapS are separated from the ground line so as to float, only the differential charge between the sample signal (N) and (S + N) flows to the horizontal signal line. As a result, it is possible to suppress fixed pattern noise caused by variations in the threshold voltage and the capacitance value of the transistor that is a constituent element of the readout system, and to improve resistance to common-mode noise and disturbance noise mixed in from the horizontal signal line. Can be.
Further, according to the first embodiment, since a differential interface can be performed, it is possible to provide a solid-state imaging device having good compatibility with high bit A / D and the like.
[0034]
Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 3 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a CMOS image sensor according to a second embodiment of the present invention and a part of a driving circuit for reading out signals from the pixel portion. FIG. 9 is a timing chart for explaining the operation of the solid-state imaging device according to the second embodiment.
The solid-state imaging device according to the present embodiment is of a differential type, and includes a pixel 10, a noise suppression sampling circuit 60, a horizontal output unit 50, and a horizontal scanning circuit 21 which constitute a column signal processing circuit described in the claims. It is comprised including.
[0035]
The pixel 10 includes a photodiode 11, an FD section 12, a transfer MOS transistor 13, a reset MOS transistor 14, an amplification MOS transistor 15, and a selection MOS transistor 17, as in the case shown in FIG.
[0036]
The sampling circuit 60 is for removing or suppressing noise components such as reset noise, and includes a reset level capacitor CapN for storing a reset level sample signal read from the pixel 10 through a read circuit; A signal level capacitor CapS for storing a sample signal of a signal level read through a read circuit is provided.
The input electrodes of the reset level capacitor CapN and the signal level capacitor CapS are connected to the vertical signal line 16 via a common floating switch 27 which is turned on by a floating pulse φFLTSW. The output electrodes of the reset level capacitor CapN and the signal level capacitor CapS are connected to the ground potential Vref2 via separate floating switches 28a and 28b which are turned on by the floating pulse φFLTSW.
[0037]
A selection switch 18 that is turned on by a selection pulse φOPN is connected in series between the input side electrode of the reset level capacitor CapN and the floating switch 27, and further connected to the input side electrode of the signal level capacitor CapS. A selection switch 19 that is turned on by a selection pulse φOPS is connected in series with the floating switch 27.
Further, between the output electrode of the reset level capacitor CapN and the horizontal signal line 20a of the horizontal output unit 50 and between the output electrode of the signal level capacitor CapS and the horizontal signal line 20b of the horizontal output unit 50. Are connected in series with selection switches 22a and 22b which are turned on by a horizontal switching pulse φHSWn from the horizontal scanning circuit 21.
[0038]
As in the case shown in FIG. 1, the horizontal output unit 50 outputs a sample signal value output from the reset level capacitor CapN to the horizontal signal line 20a and a sample signal output from the signal level capacitor CapS to the horizontal signal line 20b. A differential OP amplifier 23 for extracting a difference from a signal value is provided.
As shown in FIG. 1, a capacitor 24a and a reset switch 25a are connected in parallel between the output terminal, which is the feedback route of the differential OP amplifier 23, and the horizontal signal line 20a. As shown in FIG. 1, a capacitor 24b and a reset switch 25b are connected in parallel between the output terminal, which is the feedback route of the dynamic OP amplifier 23, and the horizontal signal line 20b.
In FIG. 3, reference numeral 26 denotes a constant current source for supplying a drive current to the pixel 10, and the constant current source 26 is connected to the vertical signal line 16 for each pixel column.
[0039]
Next, the operation of the solid-state imaging device configured as described above will be described with reference to FIG. Each of the pulse signals shown in FIGS. 4A to 4K is generated from a timing generator (not shown) provided with the solid-state imaging device.
When reading signals from the pixels 10 constituting the solid-state imaging device, first, a vertical pulse φVSEL having a waveform shown in FIG. 4B synchronized with the reference clock φCLK shown in FIG. By doing so, the selection MOS transistor 17 is turned on. In this state, when a reset pulse φRST having a waveform shown in FIG. 4C is applied to the gate of the reset MOS transistor 14, when the reset MOS transistor 14 is turned on, the potential of the FD section 12 is changed to the power supply potential Vdd. Simultaneously with the reset, the selection switch 18 is turned on by the selection pulse φOPN having the waveform shown in FIG. 4D, and the floating switches 27 and 28a and 28b are turned on by the floating pulse φFLTSW having the waveform shown in FIG. As a result, when the amplification MOS transistor 15 is turned on, a current corresponding to the potential obtained from the FD unit 12 at the time of resetting flows through the amplification MOS transistor 15, the selection MOS transistor 17, the floating switch 27, the switch 18, and the floating switch 28a. The signal flows to the reset level capacitor CapN, and the reset level sample signal (N) is stored in the reset level capacitor CapN. Then, when the reset level sample signal (N) is input to the reset level capacitor CapN, the output of the reset level capacitor CapN is clamped to the ground potential Vref2.
[0040]
Next, a transfer pulse φTX having a waveform shown in FIG. 4E is applied to the gate of the transfer MOS transistor 13, so that the transfer MOS transistor 13 is turned on, and at the same time, the selection switch 19 is turned on as shown in FIG. It is turned on by the waveform selection pulse φOPS. As a result, the signal charge accumulated in the photodiode 11 is transferred to the FD section 12 through the transfer MOS transistor 13, and a current corresponding to the potential obtained from the FD section 12 by the signal charge is amplified by the amplification MOS transistor 15 and the selection MOS transistor 17. Then, the current flows to the signal level capacitor CapS through the selection switch 19 and the floating switch 28b. As a result, the signal level sample signal (S + N) including the noise component is accumulated in the signal level capacitor CapS. When the signal level sample signal (S + N) is input to the signal level capacitor CapS, the output of the signal level capacitor CapS is clamped to the ground potential Vref2.
The sampling and holding of the reset-level sample signal (N) and the signal-level sample signal (S + N) are performed for each column of the imaging pixel unit and during a blanking period of horizontal scanning.
[0041]
Then, the reading of the signal (S + N−N = S) corresponding to the difference between the sample signal (N) at the reset level and the sample signal (S + N) at the signal level after the sample hold is performed within the valid period shown in FIG. This is performed for each column of the imaging pixel unit.
That is, in the valid period shown in FIG. 4, first, the floating switches 27 and 28a and 28b are turned off, and at the same time, the selection switches 18 and 19 are turned on to connect the reset level capacitor CapN and the signal level capacitor CapS to the vertical signal line. 16 and the ground potential Vref2 to be in a floating state. In this state, the reset switches 25a and 25b of the differential OP amplifier 23 are turned on by the differential OP amplifier reset pulse φOPRST synchronized with the reference clock φCLK, and are stored in the capacitors 24a and 24b of the differential OP amplifier 23. The charge is released, and the differential OP amplifier 23 is initialized. Thereafter, horizontal switching pulses φHSW1 to φHSWn, φHSWn + 1 are sequentially transmitted from the horizontal scanning circuit 21 for each column of the imaging pixel unit, and when the selection switches 22a and 22b of each column are turned on in order, the reset level capacitors CapN and The sample signals (N) and (S + N) stored in the signal level capacitor CapS are input to the differential OP amplifier 23 through the horizontal signal lines 20a and 20b. As a result, the differential OP amplifier 23 outputs only a signal component corresponding to the difference between the two voltages, that is, the difference (S + N−N = S) between the sample signal (N) and the sample signal (S + N).
[0042]
Note that the ground potential Vref2 is equal to the reference potential Vref of the horizontal signal line. Thus, the fixed pattern noise caused by the DC charge in the dark due to the parasitic capacitance, which can be in the first embodiment, can be almost eliminated.
[0043]
According to the second embodiment, both capacitors are connected from the ground line to the ground potential Vref2 between the ground-side terminal of the reset capacitor CapN and the signal-level capacitor CapS for each column of the imaging pixel unit. Floating switches 28a and 28b for disconnecting are provided, and a floating switch 27 for disconnecting both capacitors from the vertical signal line 16 is provided at a connection end between the reset capacitor CapN and the vertical signal line 16 of the signal level capacitor CapS. N) and the sample signal (S + N) are sampled and held by the respective capacitors CapN and CapS, the floating switches 27 and 28a and 28b are turned on to connect the capacitors CapN and CapS to the ground potential Vref2, and the capacitors CapN and CapN. When the voltage sampled and held at S is read out to the horizontal signal line of the horizontal output unit 50, the floating switches 27, 28a and 28b are turned off, and the capacitors CapN and CapS are separated from the ground line and the vertical signal line 16 so as to float. Therefore, only the difference charge between the sample signal (N) and the sample signal (S + N) flows through the horizontal signal line. As a result, it is possible to suppress fixed pattern noise caused by variations in the threshold voltage and the capacitance value of the transistor that is a constituent element of the readout system, and to improve resistance to common-mode noise and disturbance noise mixed in from the horizontal signal line. Can be.
[0044]
In particular, when the ground potential Vref2 and the reference potential Vref of the horizontal signal line are made equal, strictly speaking, clock feedthrough by a switch for disconnecting from the ground potential and clock feedthrough by a switch for resetting the differential OP amplifier 23 are performed by: The DC level shifts, and the DC charge flows accordingly. When the reference potential Vref and the ground potential Vref2 are set so as to cancel this DC level shift, DC charge does not flow, and fixed pattern noise caused by this can be eliminated.
In addition, according to the second embodiment, since a differential interface can be performed, a solid-state imaging device having good compatibility with high bit A / D and the like can be provided.
[0045]
Next, a third embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a CMOS image sensor according to a third embodiment of the present invention and a part of a driving circuit for reading out signals from the pixel portion. FIG. 13 is a timing chart for explaining the operation of the solid-state imaging device according to the third embodiment.
The solid-state imaging device according to the present embodiment is of a differential type, and includes a pixel 10, a noise suppression sampling circuit 70, a horizontal output unit 50, and a horizontal scanning circuit 21 which constitute a column signal processing circuit described in the claims. It is comprised including.
[0046]
The pixel 10 includes a photodiode 11, an FD section 12, a transfer MOS transistor 13, a reset MOS transistor 14, an amplification MOS transistor 15, and a selection MOS transistor 17, as in the case shown in FIG.
[0047]
The sampling circuit 70 is for removing or suppressing noise components such as reset noise, and includes a reset level capacitor CapN for accumulating a reset level sample signal read from the pixel 10 through a readout circuit; A signal level capacitor CapS for storing a sample signal of a signal level read through a read circuit is provided.
The input electrodes of the reset level capacitor CapN and the signal level capacitor CapS are connected to the vertical signal line 16 via a common floating switch 27 which is turned on by a floating pulse φFLTSW. The output electrode of the reset level capacitor CapN is connected to the ground potential Vref2 via the selection switch 18 which is turned on by the selection pulse φOPN. The output side electrode of the signal level capacitor CapS is connected to the ground potential Vref2 via the selection switch 19 which is turned on by the selection pulse φOPS.
[0048]
Further, between the output electrode of the reset level capacitor CapN and the horizontal signal line 20a of the horizontal output unit 50 and between the output electrode of the signal level capacitor CapS and the horizontal signal line 20b of the horizontal output unit 50. Are connected in series with selection switches 22a and 22b which are turned on by a horizontal switching pulse φHSWn from the horizontal scanning circuit 21.
[0049]
As in the case shown in FIG. 1, the horizontal output unit 50 outputs a sample signal value output from the reset level capacitor CapN to the horizontal signal line 20a and a sample signal output from the signal level capacitor CapS to the horizontal signal line 20b. A differential OP amplifier 23 for extracting a difference from a signal value is provided.
As shown in FIG. 1, a capacitor 24a and a reset switch 25a are connected in parallel between the output terminal, which is the feedback route of the differential OP amplifier 23, and the horizontal signal line 20a. As shown in FIG. 1, a capacitor 24b and a reset switch 25b are connected in parallel between the output terminal, which is the feedback route of the dynamic OP amplifier 23, and the horizontal signal line 20b.
In FIG. 5, reference numeral 26 denotes a constant current source for supplying a drive current to the pixel 10, and the constant current source 26 is connected to the vertical signal line 16 for each pixel column.
[0050]
Next, the operation of the solid-state imaging device configured as described above will be described with reference to FIG. Each of the pulse signals shown in FIGS. 6A to 6K is generated from a timing generator (not shown) provided with the solid-state imaging device.
When reading signals from the pixels 10 constituting the solid-state imaging device, first, a vertical pulse φVSEL having a waveform shown in FIG. 6B synchronized with a reference clock φCLK shown in FIG. By doing so, the selection MOS transistor 17 is turned on. In this state, when a reset pulse φRST having a waveform shown in FIG. 4C is applied to the gate of the reset MOS transistor 14, when the reset MOS transistor 14 is turned on, the potential of the FD section 12 is changed to the power supply potential Vdd. Reset. At the same time, the selection switch 18 is turned on by the selection pulse φOPN having the waveform shown in FIG. 10D, and the floating switch 27 is turned on by the floating pulse φFLTSW having the waveform shown in FIG. As a result, when the amplification MOS transistor 15 is turned on, a current corresponding to the potential obtained from the FD unit 12 at the time of resetting passes through the amplification MOS transistor 15, the selection MOS transistor 17, the floating switch 27, and the selection switch 18 for the reset level. The reset level sample signal (N) flows through the capacitor CapN and is stored in the reset level capacitor CapN. Then, when the reset level sample signal (N) is input to the reset level capacitor CapN, the output of the reset level capacitor CapN is clamped to the ground potential Vref2.
[0051]
Next, a transfer pulse φTX having a waveform shown in FIG. 6E is applied to the gate of the transfer MOS transistor 13, so that the transfer MOS transistor 13 is turned on, and at the same time, the selection switch 19 is turned on as shown in FIG. It is turned on by the waveform selection pulse φOPS. As a result, the signal charge accumulated in the photodiode 11 is transferred to the FD section 12 through the transfer MOS transistor 13, and a current corresponding to the potential obtained from the FD section 12 by the signal charge is amplified by the amplification MOS transistor 15 and the selection MOS transistor 17. The signal flows to the signal level capacitor CapS through the floating switch 27 and the selection switch 19. As a result, the signal level sample signal (S + N) including the noise component is accumulated in the signal level capacitor CapS. When the signal level sample signal (S + N) is input to the signal level capacitor CapS, the output of the signal level capacitor CapS is clamped to the ground potential Vref2.
The sampling and holding of the reset-level sample signal (N) and the signal-level sample signal (S + N) are performed for each column of the imaging pixel unit and during a blanking period of horizontal scanning.
[0052]
Then, the reading of the signal (S + N−N = S) corresponding to the difference between the sample signal (N) at the reset level and the sample signal (S + N) at the signal level after being sampled and held is performed within the valid period shown in FIG. This is performed for each column of the imaging pixel unit.
That is, in the effective period shown in FIG. 6, first, the floating switch 27 and the selection switches 18 and 19 are turned off to disconnect the reset level capacitor CapN and the signal level capacitor CapS from the vertical signal line 16 and the ground potential Vref2. State. In this state, the reset switches 25a and 25b of the differential OP amplifier 23 are turned on by the differential OP amplifier reset pulse φOPRST synchronized with the reference clock φCLK, and are stored in the capacitors 24a and 24b of the differential OP amplifier 23. The charge is released, and the differential OP amplifier 23 is initialized. Thereafter, horizontal switching pulses φHSW1 to φHSWn, φHSWn + 1 are sequentially transmitted from the horizontal scanning circuit 21 for each column of the imaging pixel unit, and when the selection switches 22a and 22b of each column are turned on in order, the reset level capacitors CapN and The sample signals (N) and (S + N) stored in the signal level capacitor CapS are input to the differential OP amplifier 23 through the horizontal signal lines 20a and 20b. As a result, the differential OP amplifier 23 outputs only a signal component corresponding to the difference between the two voltages, that is, the difference (S + N−N = S) between the sample signal (N) and the sample signal (S + N).
[0053]
According to the third embodiment, the same operation and effect as those of the second embodiment can be obtained, and the number of switches in the sampling circuit 70 can be reduced as compared with the second embodiment. be able to.
[0054]
Next, a fourth embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a CMOS image sensor according to a fourth embodiment of the present invention and a part of a driving circuit for reading out signals from the pixel portion. 16 is a timing chart for explaining the operation of the solid-state imaging device according to the fourth embodiment.
The solid-state imaging device according to the present embodiment is of a clamp-and-sample-hold type, and includes a pixel 10 and a noise suppression sampling circuit 80 (CDS: Corresponding double sampling) constituting a column signal processing circuit described in claims. ) 80, a horizontal output unit 50, a horizontal scanning circuit 21, and the like.
[0055]
The pixel 10 includes a photodiode 11, an FD section 12, a transfer MOS transistor 13, a reset MOS transistor 14, an amplification MOS transistor 15, and a selection MOS transistor 17, as in the case shown in FIG.
[0056]
The sampling circuit 80 is for removing or suppressing noise components such as reset noise, and is turned on by a clamp capacitor C1 and a sample and hold capacitor C2, a clamp switch 30 turned on by a clamp pulse φCLP, and a sample and hold pulse φSH. And a selection switch 22a, 22b which is turned on by a horizontal switching pulse φHSWn from the horizontal scanning circuit 21.
[0057]
The input side electrode of the clamp capacitor C1 is directly connected to the vertical signal line 16 via the sample hold switch 31, and the output side electrode of the clamp capacitor C1 is connected to the clamp potential Vclp via the clamp switch 30. ing. The input side electrode of the sample hold capacitor C2 is connected to the output side electrode of the clamp capacitor C1 via a sample hold switch 31, and the output side electrode of the sample hold capacitor C2 is connected via a floating switch 32. Is connected to the clamp potential Vclp.
The input-side electrode of the sample-and-hold capacitor C2 is connected to the horizontal signal line 20a of the horizontal output unit 50 via a selection switch 22a, and the output-side electrode of the sample-and-hold capacitor C2 is connected via a selection switch 22b. It is connected to the horizontal signal line 20b of the horizontal output unit 50.
[0058]
The horizontal output unit 50 includes a differential operational amplifier 23. Non-inverting input terminals and inverting input terminals of the differential operational amplifier 23 are connected to horizontal signal lines 20a and 20b, respectively. Both ends of the sample-and-hold capacitor C2 are connected via the selection switches 22a and 22b, respectively.
A capacitor 24a and its reset switch 25a are connected in parallel between the output terminal, which is a feedback route of the differential OP amplifier 23, and the horizontal signal line 20a. A capacitor 24b and a reset switch 25b are connected in parallel between the output terminal and the horizontal signal line 20b.
In FIG. 7, reference numeral 26 denotes a constant current source for supplying a drive current to the pixel 10, and the constant current source 26 is connected to the vertical signal line 16 for each pixel column.
[0059]
Next, the operation of the solid-state imaging device configured as described above will be described with reference to FIG. Each of the pulse signals shown in FIGS. 8A to 8K is generated from a timing generator (not shown) provided with the solid-state imaging device.
When reading signals from the pixels 10 constituting the solid-state imaging device, first, a vertical pulse φVSEL having a waveform shown in FIG. 8B is supplied to the gate of the selection MOS transistor 17 in synchronization with the reference clock φCLK shown in FIG. By doing so, the selection MOS transistor 17 is turned on. In this state, when a reset pulse φRST having a waveform shown in FIG. 4C is applied to the gate of the reset MOS transistor 14, when the reset MOS transistor 14 is turned on, the potential of the FD section 12 is changed to the power supply potential Vdd. Reset. At the same time, the reset-level sample signal is accumulated in the clamp capacitor C1, and at this time, the output of the clamp capacitor C1 is clamped to the clamp voltage Vclp. At this time, the sample hold switch 31 is turned on by the sample hold pulse φSH having the waveform shown in FIG.
[0060]
Next, when a transfer pulse φTX having a waveform shown in FIG. 8E is applied to the gate of the transfer MOS transistor 13, when the transfer MOS transistor 13 is turned on, the signal charges stored in the photodiode 11 are transferred to the transfer MOS transistor 13. The data is transferred to the FD unit 12 through the transistor 13. Accordingly, a sample signal having a signal level corresponding to the signal charge of the photodiode 11 is input to the clamping capacitor C11.
[0061]
Here, when the output side of the clamp capacitor C11 is clamped to the clamp voltage Vclp, the input side and the output side of the clamp capacitor C11 are held at different potentials, so that the signal level is applied to the input side of the clamp capacitor C11. , The potential change on the input side appears as a potential change on the output side, and this potential change is sampled and held by the sample and hold capacitor C2 when the sample and hold switch 31 is turned on. At this time, the sample signal sampled into the sample-and-hold capacitor C2 is only a signal component from which noise components have been removed or suppressed.
Then, the sample and hold of the output value of the clamp capacitor C1 by the sample and hold capacitor C2 is performed for each column of the imaging pixel unit within the valid period shown in FIG.
[0062]
That is, in the valid period shown in FIG. 8, first, the reset switches 25a and 25b of the differential OP amplifier 23 are turned on by the differential OP amplifier reset pulse φOPRST synchronized with the reference clock φCLK, so that the differential OP amplifier 23 The electric charge stored in the capacitors 24a and 24b is released to initialize the differential OP amplifier 23. Thereafter, horizontal switching pulses φHSW1 to φHSWn, φHSWn + 1 are sequentially transmitted from the horizontal scanning circuit 21 for each column of the imaging pixel unit, and the selection switches 22a and 22b of each column are sequentially turned on. The held sample signal is input to the differential OP amplifier 23 through the horizontal signal lines 20a and 20b. As a result, only the signal component from which the noise component has been removed or suppressed is output from the differential OP amplifier 23.
[0063]
According to such a fourth embodiment, the reset-level sample signal read from the pixel is sampled using the clamp capacitor C1 provided for each column of the imaging pixel unit, and the clamp capacitor C1 is sampled. Is clamped to the clamp voltage Vclp, and then the signal of the signal level is output from the pixel 10 and the signal of the signal level is output to the clamping capacitor C1. At this point, the output value of the clamping capacitor C1 is sampled and held. C2, the output value of the clamp capacitor C1 is held by the sample-and-hold capacitor C2, and the signal held by the sample-and-hold capacitor C2 is output to the differential OP amplifier 23 to reduce the signal component. Since it is taken out, the readout component With a fixed pattern noise due to variations in threshold voltage and capacitance values can be suppressed in Njisuta can improve resistance to disturbance noise.
Further, by making the clamp potential Vclp substantially equal to the reference potential Vref of the horizontal signal line, the dark FPN due to capacitance variation can be suppressed. In particular, it is desirable to set the clamp potential Vclp and the reference potential Vref so as to cancel the DC level shift corresponding to the clock feedthrough described in the second embodiment.
Further, according to the fourth embodiment, since a differential interface can be performed, it is possible to provide a solid-state imaging device having good compatibility with high-bit A / D and the like and a driving method thereof.
[0064]
【The invention's effect】
As described above, according to the solid-state imaging device and the method of driving the same according to the present invention, it is possible to suppress fixed pattern noise caused by variations in the threshold voltage and the capacitance of the transistor as a readout constituent element, and Immunity to common-mode noise and disturbance noise mixed in from the signal line can be improved.
Further, according to the present invention, since a differential interface can be performed, it is possible to provide a solid-state imaging device having good matching with high bit A / D and the like and an output circuit thereof.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a CMOS image sensor according to a first embodiment of the present invention and a part of a driving circuit for reading out signals from the pixel portion.
FIG. 2 is a timing chart for explaining the operation of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a CMOS image sensor according to a second embodiment of the present invention and a part of a driving circuit for reading out signals from the pixel portion.
FIG. 4 is a timing chart for explaining the operation of the solid-state imaging device according to the second embodiment of the present invention.
FIG. 5 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a CMOS image sensor according to a third embodiment of the present invention and a part of a driving circuit for reading out signals from the pixel portion.
FIG. 6 is a timing chart for explaining the operation of the solid-state imaging device according to the third embodiment of the present invention.
FIG. 7 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a CMOS image sensor according to a fourth embodiment of the present invention and a part of a driving circuit for reading out signals from the pixel portion.
FIG. 8 is a timing chart for explaining the operation of the solid-state imaging device according to the fourth embodiment of the present invention.
FIG. 9 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a conventional CMOS image sensor and a part of a driving circuit for reading out a signal of the pixel portion.
10 is a timing chart for explaining the operation of the conventional solid-state imaging device shown in FIG.
FIG. 11 is a circuit diagram showing a pixel portion of a solid-state imaging device applied to a conventional CMOS image sensor and a part of a driving circuit for reading out signals from the pixel portion.
12 is a timing chart for explaining the operation of the conventional solid-state imaging device shown in FIG.
[Explanation of symbols]
10 ... pixel, 11 ... photodiode, 12 ... FD section, 13 ... transfer MOS transistor, 14 ... reset MOS transistor, 15 ... amplification MOS transistor, 17 ... selection MOS transistor, 18, 19 ... Selection switch 16, vertical signal line, 20a, 20b horizontal signal line, 21 horizontal scanning circuit, 22a, 22b selection switch, 23 differential OP amplifier, 27, 28, 28a, 28b, 32 floating switch, 30 clamp switch, 31 sample hold switch, 40, 60, 70, 80 sampling circuit, 50 horizontal output unit, CapN reset level capacitor, CapS signal Reset level capacitor, C1 ... Clamp capacitor, C2 ... Signal level capacitor Sita.

Claims (9)

An imaging pixel unit in which a plurality of pixels including a photoelectric conversion element and its readout circuit are arranged in a plurality of rows and columns,
A column including a capacitor that selects a readout circuit of the imaging pixel unit for each pixel column, sequentially reads out reset level and signal level signals of each pixel, and separately stores the read reset level and signal level signals A signal processing circuit;
A column selection circuit for selecting a reset level sample signal and a signal level sample signal sampled and held by a capacitor of the column signal processing circuit for each pixel column, and outputting the selected signal to a horizontal signal line;
A horizontal output unit that outputs a difference between the sample signal of the reset level and the sample signal of the signal level read out to the horizontal signal line,
A solid-state imaging device comprising: One end of the capacitor for sampling and holding the reset level of the column signal processing circuit and one end of the capacitor for sampling and holding the signal level are connected to the readout circuit through a vertical signal line, and the other ends of both capacitors are commonly connected to a ground potential. The read and reset levels and the signal level are read out to the horizontal signal line by disconnecting the two capacitors from the ground potential to bring them into a floating state. The solid-state imaging device according to claim 1. The solid-state imaging device according to claim 2, wherein the ground potential is approximated to a dark signal level of the pixel. The readout circuit of the pixel, a transfer transistor for reading the signal charge of the photoelectric conversion element, an amplification transistor that detects the signal charge read by the transfer transistor in a floating diffusion unit and outputs an electric signal, 2. The solid-state imaging device according to claim 1, further comprising: a selection transistor for selecting an amplification transistor for each pixel row; and a reset transistor for resetting a potential of a floating diffusion portion of the amplification transistor. The solid-state imaging device according to claim 1, wherein the column signal processing circuit includes a sampling circuit that removes noise by calculating a difference between a reset level and a signal level of the pixel. The column signal processing circuit includes a reset level capacitor that stores a sample signal of the pixel reset level, a signal level capacitor that stores a sample signal of the pixel signal level, and a reset level signal from the pixel. A selection switch for selectively inputting to the reset level capacitor and selectively inputting a signal of the signal level from the pixel to the signal level capacitor; a sample signal value of the reset level capacitor and a sample of the signal level capacitor A differential OP amplifier that outputs a difference from the signal value, and a selection switch that outputs a sample signal value of the reset level capacitor and a sample signal value of the signal level capacitor in each pixel column to the differential OP amplifier. The solid-state imaging device according to claim 1, wherein: The column signal processing circuit includes a clamp capacitor for sequentially inputting a reset level sample signal and a signal level sample signal for the pixel, and a clamp capacitor when the reset level sample signal is input to the clamp capacitor. A clamp switch for clamping an output to a predetermined clamp level, a sample and hold capacitor for holding an output value of the clamp capacitor when a sample signal of a signal level is input to the clamp capacitor after being clamped by the clamp switch, A sample and hold switch for outputting an output value of the clamp capacitor to the sample and hold capacitor, an output circuit for converting a hold value of the sample and hold capacitor to an output signal, and a sample and hold capacitor The solid-state imaging device according to claim 1, characterized by having a selection switch for outputting a sample signal values of data to said output circuit. An imaging pixel unit in which a plurality of pixels including a photoelectric conversion element and its readout circuit are arranged in a plurality of rows and columns,
A column including a capacitor that selects a readout circuit of the imaging pixel unit for each pixel column, sequentially reads out reset level and signal level signals of each pixel, and separately stores the read reset level and signal level signals A signal processing circuit;
A column selection circuit for selecting a reset level sample signal and a signal level sample signal sampled and held by a capacitor of the column signal processing circuit for each pixel column, and outputting the selected signal to a horizontal signal line;
A method for driving a solid-state imaging device, comprising: a horizontal output unit that outputs a difference between a sample signal of a reset level and a sample signal of a signal level read out to the horizontal signal line,
One end of the capacitor for sampling and holding the reset level and one end of the capacitor for sampling and holding the signal level are connected to the readout circuit through a vertical signal line, and the other ends of both capacitors are commonly connected to a ground potential by a floating switch. When the reset level and the signal level are read out to the horizontal signal line, the two capacitors are separated from the ground potential to be in a floating state.
A method for driving a solid-state imaging device. 9. The method according to claim 8, wherein the ground potential is approximated to a dark signal level of the pixel.

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