JP2004179255A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit where transmission of substrate noise can effectively be shielded from a digital circuit to an analog circuit and noise can effectively be shielded even if an area ratio of the analog circuit and the digital circuit shows any value. <P>SOLUTION: In a rectangular semiconductor substrate 11, a guard band 14 is arranged between a digital circuit part 12 becoming a substrate noise source and an analog circuit 13 which is to be shielded from substrate noise by leaving a distance between both circuits. A buffer zone 15 where a circuit in which substrate noise does not occur and whose characteristic is not affected even if substrate noise is received is to be arranged or nothing is arranged is disposed between both circuits Thus, transmission of substrate noise from the digital circuit to the analog circuit can effectively be shielded, and effective noise shielding is possible even if the area ratio of the analog circuit and the digital circuit shows any value. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed on the same semiconductor substrate. In particular, the characteristics of the analog circuit are easily affected by the substrate potential. And a noise control technique for preventing the noise from being applied to the substrate.
[0002]
With the recent improvement in the frequency characteristics of the CMOS process, there is an increasing demand for realizing a system including digital signal processing on a single chip by configuring an RF circuit using a CMOS process.
[0003]
Conventional noise control techniques include a trench isolation method, a guard ring method, a triple well structure, and a pattern arrangement on an integrated circuit.
Each of these techniques is effective in reducing noise to some extent, but in the RF front-end section that needs to receive weak signals on the order of nV, there is a possibility that the above-mentioned existing techniques alone cannot solve the problem. is there. There is a need for an effective technique for suppressing substrate noise and achieving good reception sensitivity.
[0004]
Conventionally, as this noise control technique, there has been proposed a semiconductor integrated circuit in which measures are taken using a contrivance in pattern arrangement and a guard ring method (for example, Patent Document 1).
[0005]
[Patent Document 1]
JP 2000-101021 A
[Problems to be solved by the invention]
However, the semiconductor integrated circuit described in Patent Document 1 has the following disadvantages.
[0007]
1. Deterioration of noise cutoff effect due to guard band arrangement position In the second embodiment of Patent Document 1, it is only described that "the noise is further suppressed by providing a dedicated guard band". The relative position of the digital circuit and the guard band is important.
[0008]
FIG. 1 is a diagram showing a result of simulating a noise attenuation amount due to a difference in arrangement positions of a noise source and a guard band.
In FIG. 1, the horizontal axis represents time t (unit: ns), and the vertical axis represents noise amplitude NA (unit: mV).
Also, in FIG. 1, the curve indicated by A represents the noise attenuation when the distance is 100 μm from the noise source, and the curve indicated by B represents the noise attenuation when the distance is 10 μm from the noise source.
[0009]
As shown in FIG. 1, when the guard band is arranged at a distance of 10 μm from the noise source, the noise amplitude is about 10 mV, whereas when the guard band is arranged at a distance of 100 μm, the noise is attenuated to about 2 mV. .
If the digital circuit and the guard band are arranged too close to each other, the potential of the guard band will rather fluctuate.
[0010]
2. Deterioration of noise blocking effect due to use of N-well for planar separation In Patent Document 1, as a modification of the guard band, the n-well is used for horizontal planar separation.
However, in such a usage, the effect of noise reduction is small.
[0011]
FIG. 2 is a diagram illustrating a simulation result of noise attenuation when a p-type guard band or an n-type well layer guard band is arranged at a position 200 μm away from a noise source.
In FIG. 2, the horizontal axis represents the distance D (unit: μm) from the noise source, and the vertical axis represents noise N (unit: dB).
In FIG. 2, a curve indicated by A represents a noise attenuation amount when a p-type guard band is arranged, and a curve indicated by B represents a noise attenuation amount when a guard band is arranged by an n-type well layer. I have.
[0012]
With the n-type guard band, the noise level is restored, and the effect of noise attenuation is not recognized.
In addition, there is a description that the n-type well layer having a small noise reduction effect is "fixed to a power supply potential independent of other circuits", but this is merely a waste of bonding pads.
[0013]
3. Limitation of application range due to limitation of analog / digital circuit arrangement In Patent Document 1, an IC is divided into two parts, and an analog circuit and a digital circuit are respectively arranged above and below.
If the digital circuit is significantly larger than the analog circuit, no reference is made to the location of the analog circuit on the IC chip.
[0014]
An object of the present invention is to be able to effectively block the propagation of substrate noise from a digital circuit to an analog circuit, and to effectively block noise regardless of the area ratio between the analog circuit and the digital circuit. An object of the present invention is to provide a semiconductor integrated circuit.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a semiconductor integrated circuit in which a digital circuit unit serving as a substrate noise source and an analog circuit unit to be shielded from substrate noise are mixedly mounted on the same semiconductor substrate. A guard band is arranged between the unit and the analog circuit unit at a distance from both circuits, and a buffer zone for suppressing the influence of substrate noise is arranged between both circuit units.
[0016]
Preferably, the buffer zone is a buffer zone in which a circuit that does not generate substrate noise and does not affect the characteristics even when the substrate noise is received is disposed or nothing is disposed.
[0017]
Preferably, the guard bands are formed on the analog circuit section side, and the guard bands have independent ground connections and are multiplexed at intervals.
[0018]
Further, the guard band has a substrate contact arranged in a ring shape.
Further, the guard band is arranged so that the substrate contact and the side wall of the semiconductor substrate form a ring.
[0019]
Preferably, the innermost guard band is a deep n-well contact array with an independent power connection to the p-well of the n-channel transistor inside.
Preferably, an analog circuit most sensitive to substrate noise is arranged in the deep n-well.
[0020]
Preferably, the analog circuit section is disposed at an edge of the semiconductor substrate.
[0021]
Preferably, the analog circuit section is disposed at one corner of the semiconductor substrate.
[0022]
The analog circuit section is formed on the semiconductor substrate so as to form a substantially square shape.
[0023]
According to the present invention, for example, guard bands formed on the digital circuit section and the analog circuit section are arranged at a distance.
This means that when the digital circuit and the guard band are arranged very close to each other, the potential fluctuation due to the digital circuit is propagated to the guard band, and rather, the ground potential fluctuates. Further, even if the guard band is grounded by a dedicated pad, the potential fluctuation in the guard band is not preferable because the guard band is electrically connected to the ground of another analog circuit outside the IC.
Further, a buffer zone where no wiring and a diffusion layer capable of changing the substrate potential are provided at a distance from the region.
In the buffer zone, a region including a device and a wiring as a dummy pattern, and a region including a direct current (DC) element and a wiring which does not dynamically fluctuate electrically can also be applied as the buffer zone, thereby reducing substrate noise. It is effective from the point of view.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[0025]
FIG. 3 is a diagram showing one embodiment of a semiconductor integrated circuit according to the present invention.
[0026]
As shown in FIG. 3, the semiconductor integrated circuit 10 includes a rectangular semiconductor substrate 11, a digital circuit unit (DGT) 12 serving as a substrate noise source, and an analog circuit unit (ANLG) to be shielded from substrate noise. A guard band 14 is arranged at a distance from both circuits with respect to the circuit 13 and a circuit which does not generate substrate noise and which does not affect the characteristics even when the substrate noise is received is arranged between both circuit portions. The buffer zone 15 in which nothing is arranged is used.
In FIG. 3, ANL1 indicates a first analog circuit, and ANL2 indicates a second analog circuit.
[0027]
In the present embodiment, the analog circuit section 13 to be shielded from substrate noise is arranged, for example, in a square shape at the lower left corner of the semiconductor substrate 11 in the drawing.
The digital circuit section 12 is disposed so as to form a substantially L-shape in which the square analog circuit section 13 of the semiconductor substrate 11 is cut out.
Therefore, in the analog circuit section 13, the left side section 13L and the lower side section 13B of the analog circuit section 13 in the drawing are shared with the side section of the semiconductor substrate 11 itself. The analog circuit section 13 is configured such that the upper side section 13U and the right side section 13R interpose the buffer zone section 15 so that the minimum two notched side sections 12a and 12b of the digital circuit section 12 serving as a substrate noise source. And are arranged to face only.
[0028]
Further, in the present embodiment, in the analog circuit section 13, the guard band 14 has independent ground connections, that is, connection wirings WR131 and WR132 for the GND connection dedicated pads GP131 and GP132, and is multiplexed at intervals. In the form, it is provided twice.
Further, in the analog circuit section 13, the guard band 14 is arranged so that the substrate contacts CNT1 and CNT2 are combined with the side wall of the semiconductor substrate 11 to form a ring.
Note that it is also possible to arrange the substrate contacts in a ring shape.
[0029]
Further, in the analog circuit section 13, the innermost guard band is a contact row of a deep n-well having a power supply connection inside the p-well of the n-channel transistor and independent of the p-well of the n-channel transistor, that is, a connection wiring WR133 to the power supply dedicated pad PP131. In the deep n-well n-WL, an analog circuit 131 most sensitive to substrate noise is arranged.
[0030]
Hereinafter, the guard band 14 and the buffer zone 15 in the semiconductor integrated circuit 10 according to the present embodiment, the layout shape of the analog circuit section 13, the layout position of the analog circuit section 13, and the substrate noise in the deep n-well n-WL will be described. The arrangement of the most sensitive analog circuit 13 will be described in more detail with reference to the drawings.
First, the guard band arrangement position and the buffer zone will be described.
[0031]
Guard band arrangement position and buffer zone As shown in the simulation of FIG. 1, when the digital circuit and the guard band are arranged very close to each other, a potential change due to the digital circuit is propagated to the guard band, and rather, the ground potential. Will fluctuate.
Even if the guard band is grounded by a dedicated pad, the potential fluctuation in the guard band is not preferable because the guard band is electrically connected to the ground of another analog circuit outside the IC. From the above viewpoint, the digital circuit section 12 and the guard band 14-1 are arranged at a distance.
In the present embodiment, the distance is 100 μm width.
In the present embodiment, the buffer zone 15 in which the wiring and the diffusion layer capable of changing the substrate potential are not placed at all is provided in the region at a distance.
In the buffer zone, a region including elements and wirings as dummy patterns and a region including direct current (DC) elements and wirings that do not dynamically fluctuate electrically are also buffer zones.
Naturally, this area becomes a dead space, but physically increasing the distance between the analog circuit section 13 and the digital circuit section 12 is effective from the viewpoint of reducing substrate noise.
In addition, from the simulation of FIG. 1, when the p-type guard band is arranged, attenuation of about −12 dB can be expected, which is effective as a guard band.
[0032]
Arrangement of Guard Bands with Spacing In the case where guard bands can be multiplexed, the effect of shielding is higher when guard bands are arranged at intervals than when guard bands are adjacently arranged. This will be described with reference to FIGS.
[0033]
FIG. 4 shows that the guard bands 14-1 of the substrate contact CNT1 are arranged in quadruplicate at 50 μm, separated from the noise source NS by 1900 μm to the guard band on one side, and the guard band on the other side from the observation point SP. FIG. 3 is a diagram showing a case where the distance is 1900 μm to the center.
FIG. 5 shows a quadruple arrangement of the guard bands 14-1 of the substrate contact CNT1 at 500 μm, a distance of 1200 μm from the noise source NS to the guard band on one side, and a guard band on the other side from the observation point SP. FIG. 3 is a diagram showing a case where the distance is 2900 μm.
FIG. 6 is a diagram showing a result of simulating a noise attenuation amount by arranging a guard band between the noise source and the observation point as shown in FIGS.
In FIG. 6, the horizontal axis indicates the distance D (unit: μm) from the noise source, and the vertical axis indicates noise N (unit: dB).
In FIG. 6, the curve indicated by A represents the noise attenuation at a guard band interval of 50 μm, and the curve indicated by B represents the noise attenuation at a guard band interval of 500 μm.
[0034]
As can be seen from FIG. 6, an effective shield is more effective when the guard bands are arranged at intervals as shown in FIG. 5 than when the guard bands are arranged very close to each other as shown in FIG. Is obtained.
In this simulation, a difference of about 8 dB was observed.
[0035]
Next, the shape of the analog circuit section 13 will be described with reference to FIGS.
FIG. 7 is a diagram illustrating an example of guard band arrangement when the analog circuit units 13 are arranged in a rectangular shape, and FIG. 8 is an example of guard band arrangement when the analog circuit units 13 are arranged in a square shape. FIG.
[0036]
As shown in FIGS. 7 and 8, in order to secure the guard band interval, it is preferable that the shape of the analog circuit section 13 is closer to a square than a rectangle.
7 and 8 show that the occupied area is the same, and the arrangement of the guard band changes depending on the shape.
It is assumed that guard bands are arranged at intervals of 200 μm.
FIG. 7 shows only one inside 200 μm from the outermost periphery. On the other hand, in the case of FIG. 8, a double guard band can be arranged, and a more effective shield can be obtained.
[0037]
FIG. 9 shows how much the noise attenuation amount depends on a / b under the condition that the horizontal length of the analog circuit unit 13 is a and the vertical length is b, and guard bands are arranged at equal intervals in the same area. It is a figure showing the result of having simulated.
In FIG. 9, the horizontal axis represents a / b, and the vertical axis represents the noise attenuation amount NA (unit: dB).
[0038]
As can be seen from FIG. 9, the rectangular band shape makes it difficult to obtain a guard band area (FIG. 7), so that the noise attenuation is small, but the guard band shape is close to a square shape (near a / b ≒ 1). Since more can be formed (FIG. 8), the amount of noise attenuation is large.
[0039]
Thus, also from the viewpoint of the amount of noise attenuation, it is preferable that the shape of the analog circuit unit 13 is closer to a square than to a rectangle.
[0040]
Further, where to place an analog circuit relative to a digital circuit is also an important factor.
The arrangement position of the analog circuit unit 13 will be described with reference to FIGS.
Here, a case is considered in which a small-scale high-frequency analog circuit is arranged on an IC chip in a large-scale baseband digital circuit exceeding 500K gates, for example.
[0041]
FIG. 10 is a diagram showing an example of an arrangement in which a substantially square analog circuit unit 13 is arranged at a corner of a substrate, and two of them are surrounded by a digital circuit unit 12.
FIG. 11 is a diagram illustrating an example of an arrangement in which an analog circuit unit 13 having a substantially square shape is arranged at one edge of a substrate, and three sides of the analog circuit unit 13 are surrounded by a digital circuit unit 12.
FIG. 12 is a diagram illustrating an example of an arrangement in which an analog circuit unit 13 having a substantially square shape is arranged at the center of the substrate, and four sides of the analog circuit unit 13 are surrounded by the digital circuit unit 12.
[0042]
From these arrangement examples, it can be easily inferred that the arrangement in the corner of the board as shown in FIG. 10 has a smaller area in contact with the digital circuit section 12 than the arrangement examples in FIGS. Is done.
[0043]
FIG. 13 is a diagram showing a result of simulating a noise propagation state when the analog circuit section 13 is arranged at a corner of the board as shown in FIG.
Similarly, FIG. 14 is a diagram illustrating a result of simulating a noise propagation state when the analog circuit unit 13 is arranged at one edge of the substrate as in FIG.
FIG. 15 is a diagram showing a result of simulating the propagation state of noise when the analog circuit section 13 is arranged at the center of the substrate as shown in FIG.
In FIGS. 13 to 15, an area indicated by reference numeral NA indicates an area where noise is reduced.
[0044]
As can be seen from FIGS. 13 to 15, when the analog circuit section 13 is arranged at one edge of the board as shown in FIG. 11, there is also an effect of blocking noise, but when the analog circuit section 13 is arranged at the corner of the board as shown in FIG. However, the area in contact with the digital circuit section 12 is smaller than in the arrangement examples of FIGS. 11 and 12, and is less susceptible to substrate noise, and has the highest noise blocking effect.
[0045]
Next, the arrangement of the analog circuit 13 most sensitive to the substrate noise in the deep n-well n-WL will be described with reference to FIG.
In FIG. 16, p-Sub is a p-type substrate, n-DWL is a deep n-well, n-WL1 and n-WL2 are n-wells, p-WL is a p-well, 111 and 112 are n-type diffusion layers, and NT is n. Each shows a channel MOS (NMOS) transistor.
[0046]
In the analog circuit, a portion which is least likely to be affected by the substrate noise is separated from the substrate 11 by the deep n-well n-WL so that the portion is not affected by the substrate noise.
Specifically, as shown in FIG. 16, the NMOS transistor is surrounded by n-wells n-WL1 and n-WL2 as shown in FIG. 4, and is further separated from the p-type substrate 11 using the deep n-well n-WL. Then, it is connected to the power supply through the dedicated pad PP131.
[0047]
The n-well is coupled to the substrate by a junction capacitance, and the connection to the n-well has an impedance. Therefore, unless the substrate noise near the n-well is reduced, the noise shielding effect by the n-well is not sufficient.
Therefore, it is necessary to sufficiently lower the noise level before reaching the n-well. As a result, the buffer zone 15 which is a characteristic configuration of the present embodiment is provided, and the guard bands are multiplexed. Is returned to
[0048]
When a small-scale high-frequency analog circuit is arranged on an IC chip in a large-scale baseband digital circuit exceeding 500K gates, for example, a mixer or a low-noise amplifier is used as a deep n-well analog circuit as the most sensitive analog circuit. Separation from the substrate 11 by n-WL prevents influence of substrate noise.
[0049]
FIG. 17 is a circuit diagram showing a configuration example of a reception system front-end section of a wireless system including a large-scale baseband digital circuit exceeding 500K gates and a small-scale high-frequency analog circuit.
[0050]
As shown in FIG. 17, the reception system front end unit 200 includes an antenna 201, a SAW filter 202, a matching circuit (MTC) 203, a low noise amplifier (LNA) 204, a first VCO 205 as a first local oscillator, A first PLL 206, a first loop filter 207, a second VCO 208 as a second local oscillator, a second PLL 209, a second loop filter 210, mixers 211 to 214, band-pass filters (BPF) 215 to 217 , A synthesizer 218, and a comparator 219.
[0051]
Among these components, the low noise amplifier (LNA) 204 and the mixers 211 to 214 are separated from the substrate 11 by the deep n-well n-WL as the most sensitive analog circuits so that they are not affected by the substrate noise. Be placed.
[0052]
Also, a low noise amplifier (LNA) 204, a first VCO 205, a first PLL 206, a second VCO 208, a second PLL 209, mixers 211 to 214, band pass filters (BPF) 215 to 217, a combiner 218, and The comparator 219 is integrated on one chip.
Then, it has a configuration in which the RF section on the high frequency side in all stages and the intermediate frequency (IF) section in the subsequent stage are cascaded.
The RF unit includes a low-noise amplifier 204, a first VCO 205, a first PLL 206, a first loop filter 207, mixers 211 and 212, and band-pass filters 215 and 216.
Further, the IF unit includes a second VCO 208, a second PLL 209, a second loop filter 210, mixers 213, 214, a combiner 218, a band pass filter 2117, and a comparator 219.
[0053]
The first VCO 205 converts the output of the first PLL 206, which is phase-synchronized with the reference clock CLK from the crystal oscillator, into a first oscillation signal having a frequency of 1573 MHz to the mixers 211 and 212 according to the output signal of the first loop filter 207. Supply.
[0054]
The second VCO 208 converts the output of the second PLL 209, which is phase-synchronized with the reference clock CLK from the crystal oscillator, into a second oscillating signal having a frequency of 3 MHz to the mixers 213 and 214 in accordance with the output signal of the second loop filter 210. Supply.
[0055]
In the receiving system front-end unit 200, for example, a radio signal RF having a frequency of 1575 MHz is received by the antenna 201 and input to the mixers 211 and 212 via the SAW filter 202, the matching circuit 203, and the low-noise amplifier 104.
Then, in the mixers 211 and 212, the first VCO 205 mixes the first oscillation signal with the first oscillation signal. The first intermediate frequency of 2 MHz is extracted through the band-pass filters 215 and 216 and input to the mixers 213 and 214.
After being mixed with the second oscillation signal by the second VCO 208 in the mixers 213 and 214, they are combined in the combiner 218, and the second intermediate frequency of 1 MHz is obtained through the band-pass filter 217.
Then, the data of the comparator 219 is output to a baseband processing unit (not shown) based on the output of the bandpass filter 217.
[0056]
As described above, the guard band 14 is provided on the rectangular semiconductor substrate 11 between the digital circuit unit 12 serving as the substrate noise source and the analog circuit unit 13 to be shielded from the substrate noise. Since it is arranged in a space, and between the two circuit portions, a buffer zone portion 15 that does not generate substrate noise and that does not affect the characteristics even when receiving the substrate noise is disposed or nothing is disposed, The propagation of substrate noise from the digital circuit to the analog circuit can be effectively shielded.
In addition, there is an advantage that effective noise shielding is possible regardless of the area ratio between the analog circuit and the digital circuit.
[0057]
【The invention's effect】
As described above, according to the present invention, propagation of substrate noise from a digital circuit to an analog circuit can be effectively shielded.
In addition, there is an advantage that effective noise shielding is possible regardless of the area ratio between the analog circuit and the digital circuit.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a simulation result of a noise attenuation amount due to a difference in arrangement positions of a noise source and a guard band.
FIG. 2 is a diagram showing a result of simulating noise attenuation when a p-type guard band or an n-type well layer guard band is arranged at a position 200 μm away from a noise source.
FIG. 3 is a diagram showing one embodiment of a semiconductor integrated circuit according to the present invention.
FIG. 4 is a diagram illustrating a quadruple arrangement of guard bands of a substrate contact at 50 μm, a distance of 1900 μm from a noise source NS to a guard band on one side, and a distance of 1900 μm from an observation point SP to a guard band on the other side. FIG.
FIG. 5 is a diagram showing a quadruple arrangement of the guard bands of the substrate contact at 500 μm, 1200 μm from the noise source NS to the guard band on one side, and 2900 μm from the observation point SP to the guard band on the other side. FIG.
FIG. 6 is a diagram showing a result of simulating noise attenuation by arranging a guard band between a noise source and an observation point as shown in FIGS. 4 and 5;
FIG. 7 is a diagram showing an example of guard band arrangement when the analog circuit section is arranged in a rectangular shape.
FIG. 8 is a diagram illustrating an example of guard band arrangement when the analog circuit units are arranged in a square shape.
FIG. 9 shows how much the noise attenuation amount depends on a / b under the condition that the horizontal length of the analog circuit unit is a and the vertical length is b, and guard bands are arranged at equal intervals in the same area. It is a figure showing the result of having simulated.
FIG. 10 is a diagram showing an example of an arrangement in which a substantially square analog circuit section is arranged in the center of the substrate, and four sides of the analog circuit section are surrounded by digital circuit sections.
FIG. 11 is a diagram illustrating an example of an arrangement in which an analog circuit section having a substantially square shape is arranged at one edge of a substrate, and three sides are surrounded by digital circuit sections.
FIG. 12 is a diagram showing an example of an arrangement in which a substantially square analog circuit section is arranged at a corner of a board, and two sides of the analog circuit section are surrounded by a digital circuit section.
FIG. 13 is a diagram showing a result of simulating the propagation state of noise when the analog circuit section is arranged at the corner of the board as shown in FIG. 10;
FIG. 14 is a diagram illustrating a result of simulating the propagation state of noise when the analog circuit unit is arranged at one edge of the substrate as in FIG. 11;
FIG. 15 is a diagram showing a result of simulating the propagation state of noise when the analog circuit section is arranged at the center of the substrate as shown in FIG. 12;
FIG. 16 is a diagram for describing a configuration in which an analog circuit most sensitive to substrate noise in deep n-well n− is arranged.
FIG. 17 is a circuit diagram illustrating a configuration example of a reception front-end unit of a wireless system including a large-scale baseband digital circuit and a small-scale high-frequency analog circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor integrated circuit, 11 ... Semiconductor substrate, 12 ... Digital circuit part, 13 ... Analog circuit part, 14-1, 14-2 ... Guard band, 15 ... Buffer zone part, 200 ... Reception system front end part, 201 ... Antenna, 202 SAW filter, 203 Matching circuit (MTC), 204 Low noise amplifier (LNA), 205 First VCO, 206 First PLL, 207 First loop filter, 208 Second VCO, 209 ... second PLL, 210 ... second rope filter, 211-214 ... mixer, 215-217 ... band-pass filter (BPF), 218 ... synthesizer, 219 ... comparator.

Claims (13)

A semiconductor integrated circuit in which a digital circuit unit serving as a substrate noise source and an analog circuit unit to be shielded from substrate noise are mixedly mounted on the same semiconductor substrate,
A guard band is arranged between the digital circuit part and the analog circuit part at a distance from both circuits,
A semiconductor integrated circuit in which a buffer zone for suppressing the influence of substrate noise is arranged between both circuit sections. 2. The semiconductor integrated circuit according to claim 1, wherein the buffer zone is a buffer zone in which a circuit that does not generate substrate noise and has no effect on characteristics even when the substrate noise is received is disposed or nothing is disposed. 2. The semiconductor integrated circuit according to claim 1, wherein the guard band is formed on the analog circuit section side, and the guard band has an independent ground connection and is multiplexed at intervals. 2. The semiconductor integrated circuit according to claim 1, wherein said guard band has a substrate contact arranged in an annular shape. 4. The semiconductor integrated circuit according to claim 3, wherein said guard band has a substrate contact arranged in an annular shape. 5. The semiconductor integrated circuit according to claim 4, wherein said guard band is arranged so that said substrate contact and said side wall of said semiconductor substrate form a ring. 6. The semiconductor integrated circuit according to claim 5, wherein the guard band is arranged so that the substrate contact and the side wall of the semiconductor substrate form a ring. 4. The semiconductor integrated circuit according to claim 3, wherein the innermost guard band is a deep n-well contact row having an independent power supply connection to the p-well of the n-channel transistor inside. 9. The semiconductor integrated circuit according to claim 8, wherein an analog circuit most sensitive to substrate noise is arranged in said deep n-well. 2. The semiconductor integrated circuit according to claim 1, wherein said analog circuit section is arranged at an edge of said semiconductor substrate. 2. The semiconductor integrated circuit according to claim 1, wherein said analog circuit section is disposed at one corner of said semiconductor substrate. 11. The semiconductor integrated circuit according to claim 10, wherein the analog circuit section is formed on the semiconductor substrate so as to form a substantially square shape. 12. The semiconductor integrated circuit according to claim 11, wherein the analog circuit section is formed on the semiconductor substrate so as to form a substantially square shape.

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