JP2004119497A - Semiconductor manufacturing equipment and method therefor - Google Patents

Semiconductor manufacturing equipment and method therefor Download PDF

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Publication number
JP2004119497A
JP2004119497A JP2002277899A JP2002277899A JP2004119497A JP 2004119497 A JP2004119497 A JP 2004119497A JP 2002277899 A JP2002277899 A JP 2002277899A JP 2002277899 A JP2002277899 A JP 2002277899A JP 2004119497 A JP2004119497 A JP 2004119497A
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Prior art keywords
wafer
semiconductor manufacturing
manufacturing apparatus
light source
scattered light
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JP2002277899A
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Japanese (ja)
Inventor
Kozai Sai
蔡　高財
Yasuko Tabata
田端　康子
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Fujitsu Ltd
Winbond Electronics Corp
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Fujitsu Ltd
Winbond Electronics Corp
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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide semiconductor manufacturing equipment and a method wherein uniformity of critical size of a wafer edge is improved by compensation of flare effect emerging on the wafer edge. <P>SOLUTION: A problem of variations of wafer edge critical size is solved by using an exposure plate arranged on a retaining pin by which a wafer table of a stepper is made to progress and retreat. An inclination angle of the exposure plate is adjusted with the retaining pin, and the exposure plate is tilted together with a wafer, thereby maintaining the same plane as a wafer surface. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は一種の半導体製造装置と方法に係り、特に、ウエハエッジに出現するフレア効果を補償することによりウエハエッジ臨界寸法均一度を向上する半導体製造装置と方法に関する。
【０００２】
【従来の技術】
光学リソグラフィー工程で素子パターンを半導体ウエハ、例えばシリコンウエハ上に形成することは業界では周知であり且つ実用化されて久しい。一般にマスク上に使用されて光を感光材料に透過させる材料例えばホトレジストにはポジティブパターンとネガティブパターンが定義される。業界で実用化されている方法は、光反射材料クロムを光透過材料例えばガラス或いは石英に形成する。光反射材料クロムに反射されない光線はマスクを透過し並びにホトレジストが露光されてパターンが形成される。露光の領域が現像されるか或いは除去されるかは使用するホトレジスト材料がポジティブホトレジストであるかネガティブホトレジストであるかにより決まる。ホトレジストが除去された領域が暴露され、且つ続いて各種の技術例えばエッチング、イオンレイアウト或いは堆積技術により工程が進行されて例えばゲート電極、連接構造等の装置の特徴が形成される。しかし、表面に保留されたホトレジスト材料がマスクとされる場合はホトレジスト層の下の構造に対する更なる工程が必要となる。
【０００３】
集積回路の特徴の臨界寸法均一度は集積回路の信頼度と機能に対して十分に重要である。ウエハー上の集積回路臨界寸法均一度に影響する因子の一つは、ウエハ上のホトレジスト正面に散乱する光線である。光線の散乱は物理学の有名な現象であり、光線の散乱は到達目標の画像を弱化する。物理回折方向に沿わずに前進し伝播される光は散乱光と見なされる。散乱光は通常光ノイズ或いはフレア（Ｆｌａｒｅ）と見なされる。フレアは困った問題であり、且つ伝統的なリソグラフィー工程技術では多かれ少なかれこのフレア現象がある。伝統的なリソグラフィー工程装置中でフレアの形成される原因は非常に多く、時には工程に起因し、時には装置自体に関係がある。これらのフレア形成の原因は依然として不明である。
【０００４】
以上から、周知のとおり、リソグラフィー工程中、ウエハ上のホトレジストパターンのリソグラフィー工程は位置により改変される。ホトレジストパターンの臨界寸法変動が光散乱自体によるか或いはその他の因子と結合により形成されるかのいずれであっても、臨界寸法の位置による改変の現象は工程上、人々を困らせる問題である。これは、ホトレジストの形成するパターン特徴寸法例えばゲート電極或いはトレンチが、露光ホトレジスト上への照射の正常回折と異常散乱の光線の結合した照射量（Ｄｏｓｅ）により決定されることによる。ホトレジストパターンの位置による改変の露光差異はウエハ上の集積回路特徴寸法の変動或いは不均一をもたらす。集積回路特徴寸法の変動或いは不均一は集積回路の機能と信頼度に影響を与えうるため、除去しなければならない。例えば、集積回路特徴寸法の変動例えば線幅の差異は信号電流の不安定をもたらす。
【０００５】
工程上発現する光散乱により形成される集積回路特徴寸法の変動例えば線幅の差異は工程技術及び集積回路線幅の不断の縮小によりますます厳重となる。特に、それは線幅寸法が０．１３ミクロン以下に縮小され、及び、リソグラフィー工程に波長が１９３μｍのＡｒＦランプが光源として使用された時、この短波長の光散乱の形成する問題はさらに厳重となる。これはこのような短波長の照射量は非常に小さく且つ露光エネルギー量の変化が、もともと相当微小な特徴寸法を明らかに改変し並びに不均一な回路パターンを形成するか或いは臨界寸法均一度を下げることによる。図１から図５はフレア効果がいかに半導体ウエハの臨界寸法に影響を与えるか、及び、どこが臨界寸法変動の最も明らかな領域であるかを示す。図１は線幅とウエハ上の露光照射量（Ｅｘｐｏｓｕｒｅ　Ｄｏｓｅ）の相対関係を示す。図中にステッパ（Ｓｔｅｐｐｅｒ）に設定された三種類のステップ露光ギャップが表示されている。図１に示されるように、同じ露光照射量では、小さいステップ露光ギャップのほうが大きな線幅を形成する。図２はウエハエッジのダイ臨界寸法変動の状況を示す。図２に示される現象から推測されることは、ウエハエッジのダイ臨界寸法の変動の激化の原因はフレア効果でありうることである。図３は散乱光がいかに各一つのダイに対して露光を行い、及び各一つのウエハ四周の隣り合うダイの露光照射量を増加するかを示す。ウエハエッジ部分のダイ臨界寸法変動の現象は図３から図５により解釈できる。図３に示されるように、各ダイは散乱する光１０４が隣り合うダイを露光させる時に散乱する露光照射量を受け取るが、ウエハエッジのダイは同じ散乱する露光照射量を受け取っていない。このほか、図２に示される現象は図４から図５により更に解釈されうる。図４は伝統的なウエハ台中において、光源がレンズ２０２を透過して支持ピン２０６上に位置するウエハ２０４を露光させる状態を示す。支持ピン２０６はウエハ台２０８（Ｗａｆｅｒ　Ｓｔａｇｅ）に取り付けられると共にウエハの傾斜度を調整するのに用いられる。図５は図４中のウエハ２０４の平面図である。図５中、隣り合うダイの数は四つのウエハエッジ部分のダイより少なく、四周より散乱する露光照射量を均一に受け取ることはできず、これにより臨界寸法の変動を形成する可能性が非常に大きい。
【０００６】
以上の数々の問題を鑑み、上述の欠点を克服できる装置と方法の提出が非常に必要とされており、本発明はこの要求に符合するものである。
【０００７】
【発明が解決しようとする課題】
本発明の一つの目的は、ウエハエッジに出現するフレア効果を補償することによりウエハエッジ臨界寸法均一度を向上する半導体製造装置と方法を提供することにある。
【０００８】
本発明のもう一つの目的は、生産歩留りを高められる半導体製造装置と方法を提供することにある。
【０００９】
本発明のさらに一つの目的は、ウエハエッジが露光時に発生するフレア効果を補償できる半導体製造装置と方法を提供することにある。
【００１０】
【課題を解決するための手段】
請求項１の発明は、ウエハエッジ臨界寸法均一度を向上する半導体製造装置において、該半導体製造装置が、
ウエハをリソグラフィー工程中にあってウエハ台に固定する、ウエハを支持及び傾斜させる装置と、
該ウエハを支持及び傾斜させる装置によりウエハ台に固定されてウエハと一体に傾斜する、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置と、
を具えたことを特徴とする、半導体製造装置としている。
請求項２の発明は、請求項１に記載の半導体製造装置において、ウエハを支持及び傾斜させる装置がウエハ台を進退する支持ピンを具えたことを特徴とする、半導体製造装置としている。
請求項３の発明は、請求項１に記載の半導体製造装置において、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置が、二酸化けい素を形成した平板を具えたことを特徴とする、半導体製造装置としている。
請求項４の発明は、ウエハエッジ臨界寸法均一度を向上する半導体製造装置において、該半導体製造装置が、
リソグラフィー工程中にあってウエハと連帯して傾斜し露光される、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置と、
該光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置をリソグラフィー工程中にあってウエハと連帯して傾斜させ露光させる、該光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置をウエハ台に固定する装置と、
を具えたことを特徴とする、半導体製造装置としている。
請求項５の発明は、請求項４に記載の半導体製造装置において、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置が、炭化けい素を形成した平板を具えたことを特徴とする、半導体製造装置としている。
請求項６の発明は、請求項４に記載の半導体製造装置において、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置をウエハ台に固定する装置が、ウエハ台を進退する支持ピンを具えたことを特徴とする、半導体製造装置としている。
請求項７の発明は、ウエハエッジ臨界寸法均一度を向上する方法において、
ウエハをステッパのウエハ台上に提供するステップと、
ウエハ四周を囲む露光板を提供するステップと、
該ウエハと該露光板を露光させるステップと、
を具えたことを特徴とする、ウエハエッジ臨界寸法均一度を向上する方法としている。
【００１１】
【発明の実施の形態】
本発明はウエハエッジ臨界寸法均一度を向上できる半導体製造装置を提供する。この半導体製造装置は、ウエハを支持及び傾斜させる装置によりウエハをリソグラフィー工程中にあってウエハ台に固定し、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置であり、この光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置はウエハを支持及び傾斜させる装置により該ウエハ台上に固定され、並びにウエハと共に傾斜する。
【００１２】
本発明の別の実施例によると、本発明はウエハエッジ臨界寸法均一度を向上できる半導体製造装置を提供し、この半導体製造装置は光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置を具え、この光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置はリソグラフィー工程中にあってウエハと共に傾斜し及び露光され、該半導体製造装置はさらに、ウエハ周囲に投射される散乱光線を阻止並びに受け取る装置を一つのウエハ台に固定する装置を具え、これによりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置をウエハと共にリソグラフィー工程中にあって連帯して傾斜及び露光させる。
【００１３】
このほか本発明はリソグラフィー工程中にウエハエッジ臨界寸法均一度を向上する方法を提供する。このウエハエッジ臨界寸法均一度を向上する方法は、以下のステップを含む。まず、ウエハのステッパのウエハ台の上に提供する。続いてウエハ四周を囲む露光板を提供する。最後のウエハと該露光板を露光させる。
【００１４】
【実施例】
図６は本発明のウエハ台装置図である。光源はレンズ３０２を透過して支持ピン３０６上に位置するウエハ３０４を露光させる。支持ピン３０６はウエハ台３１２を進退可能でありウエハ３０４の傾斜度を調整するのに用いられる。露光板３０８は支持ピン３１０上に位置している。露光板３０８は光源より散乱する光線を阻止並びに受け取るのに使用される。支持ピン３１０は支持ピン３０６と共にウエハ台３１２を進退して露光板３０８とウエハ３０４に一つの平面を形成させることができる。図７と図８は露光板３０８とウエハ３０４の平面図である。露光板３０８は光源からの惨落光線を近隣ダイのように阻止並びに受け取るのに用いられ、並びにウエハエッジのフレア効果を補償し、これによりウエハエッジ臨界寸法均一度が高められ、すなわちウエハエッジ臨界寸法均一度の変動現象が有効に解消される。
【００１５】
露光板３０８は、例えば、炭化けい素層或いは二酸化けい素層を形成した平板とされうる。露光板３０８は任意の光源からの散乱光線を阻止並びに受け取れると共にウエハと連帯し傾斜しうる装置とされる。支持ピン３１０は支持ピン３０６と完全に同じであると共にウエハ台３１２を進退してウエハ３０４と露光板３０８の傾斜度を一つの平面となるように調整でき、また、任意のウエハ３０４と露光板３０８に一つの平面を形成させられる装置とされる。ステップ露光を実行する時、光源からの光線はウエハ３０４上の各一つのダイを露光させるにとどまらず、露光板３０８も露光させる。例えば、ウエハエッジのフレア効果を補償するため、露光はウエハ３０４の外周四周に延伸される。すなわち、余分の露光（Ｄｕｍｍｙ　Ｅｘｐｏｓｕｒｅ　Ｓｈｏｔ）がウエハエッジのダイ外周即ち露光板３０８に実行され、これによりウエハエッジのダイがウエハエッジ以外のダイと同じ露光照射量を獲得でき、これによりウエハエッジダイ臨界寸法の均一度が高められるか、甚だしくはウエハエッジダイ臨界寸法の均一度の変動現象が完全に除去される。図８に示されるウエハ３０４上の各一つの露光される外周はいずれも同様の余分の露光を伴う。
【００１６】
上述の本発明の説明は本発明の実施範囲を限定するものではなく、本発明の精神より離脱しない等しい効果の改変或いは修飾はいずれも本発明の請求範囲に属するものとする。
【００１７】
【発明の効果】
本発明はウエハエッジに出現するフレア効果の補償によりウエハエッジの臨界寸法均一度を向上する半導体製造装置と方法を提供している。
【図面の簡単な説明】
【図１】線幅とウエハ上の露光照射量（Ｅｘｐｏｓｕｒｅ　Ｄｏｓｅ）の関係図である。
【図２】ウエハエッジ部分のダイの臨界寸法変動の状況表示図である。
【図３】散乱光が各ダイに対して露光し各ダイの四周の隣接するダイの露光照射量を増加するかを表示する図である。
【図４】伝統的なウエハ台において光源がレンズを透過して支持ピン上のウエハを露光させる状態表示図である。
【図５】図４中のウエハの平面図である。
【図６】本発明のウエハ台装置図である。
【図７】本発明の露光板の平面図である。
【図８】図７中のウエハの平面図である。
【符号の説明】
１０２　ダイ
１０４　散乱光
２０２　レンズ
２０４　ウエハ
２０６　支持ピン
２０８　ウエハ台
３０２　レンズ
３０４　ウエハ
３０６　支持ピン
３０８　露光板
３１０　支持ピン
３１２　ウエハ台[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor manufacturing apparatus and method, and more particularly, to a semiconductor manufacturing apparatus and method for improving a wafer edge critical dimension uniformity by compensating for a flare effect appearing at a wafer edge.
[0002]
[Prior art]
Forming an element pattern on a semiconductor wafer, for example, a silicon wafer by an optical lithography process is well known in the art and has been used for a long time. Generally, a positive pattern and a negative pattern are defined for a material used on a mask to transmit light to a photosensitive material, for example, a photoresist. A method practiced in the industry is to form the light-reflective material chrome on a light-transmissive material, such as glass or quartz. Light rays that are not reflected by the light reflecting material chrome pass through the mask as well as expose the photoresist to form a pattern. Whether the exposed area is developed or removed depends on whether the photoresist material used is a positive photoresist or a negative photoresist. The areas from which the photoresist has been removed are exposed, and subsequently the process proceeds by various techniques, such as etching, ion layout or deposition techniques, to form device features such as gate electrodes, interconnecting structures, and the like. However, if the photoresist material retained on the surface is used as a mask, further processing of the structure below the photoresist layer is required.
[0003]
The critical dimension uniformity of integrated circuit features is sufficiently important to the reliability and function of the integrated circuit. One factor that affects the critical dimension uniformity of integrated circuits on a wafer is the light scattered in front of the photoresist on the wafer. Light scattering is a well-known phenomenon in physics, and light scattering weakens the target image. Light that travels and propagates along the direction of physical diffraction is considered scattered light. Scattered light is usually considered as light noise or flare. Flare is a problem and traditional lithographic process technology has more or less this phenomenon. The causes of flare formation in traditional lithographic process equipment are numerous, sometimes process-related, and sometimes related to the equipment itself. The cause of these flare formations remains unknown.
[0004]
As described above, as is well known, during the lithography process, the lithography process of the photoresist pattern on the wafer is changed depending on the position. Whether the critical dimension variation of the photoresist pattern is formed by light scattering itself or by a combination with other factors, the phenomenon of modification due to the position of the critical dimension is a problem in the process. This is due to the fact that the pattern feature size formed by the photoresist, for example, the gate electrode or trench, is determined by the combined dose (Dose) of the normal diffraction of the irradiation onto the exposed photoresist and the abnormally scattered light. Exposure differences in modification depending on the position of the photoresist pattern result in variations or non-uniformity of integrated circuit feature dimensions on the wafer. Variations or non-uniformities in integrated circuit feature dimensions may affect the function and reliability of the integrated circuit and must be removed. For example, variations in integrated circuit feature dimensions, such as differences in line width, result in signal current instability.
[0005]
Variations in integrated circuit feature dimensions, such as differences in line width, formed by light scattering emerging in the process become increasingly severe due to process technology and the ever-increasing reduction in integrated circuit line width. In particular, it has a reduced linewidth dimension to less than 0.13 microns, and the problem of this short wavelength light scattering formation becomes even more acute when an 193 μm wavelength ArF lamp is used as a light source in the lithography process. . This is because such short-wavelength radiation doses are very small and changes in exposure energy can significantly alter the inherently tiny feature dimensions and form non-uniform circuit patterns or reduce critical dimension uniformity. It depends. 1 to 5 show how the flare effect affects the critical dimension of a semiconductor wafer and where is the most obvious area of critical dimension variation. FIG. 1 shows a relative relationship between a line width and an exposure dose on a wafer. In the figure, three types of step exposure gaps set in the stepper (Stepper) are displayed. As shown in FIG. 1, for the same exposure dose, a smaller step exposure gap forms a larger line width. FIG. 2 shows the situation of the critical dimension change of the die at the wafer edge. It can be inferred from the phenomenon shown in FIG. 2 that the cause of the increase in the critical dimension of the die at the wafer edge may be the flare effect. FIG. 3 shows how scattered light exposes each one die and increases the exposure dose of adjacent dies on each wafer four rounds. The phenomenon of the critical dimension variation of the die at the wafer edge can be understood from FIGS. As shown in FIG. 3, each die receives the exposure dose at which the scattered light 104 scatters when exposing adjacent dies, but the die at the wafer edge do not receive the same scattered exposure dose. In addition, the phenomenon shown in FIG. 2 can be further interpreted with reference to FIGS. FIG. 4 shows a state in which a light source passes through a lens 202 and exposes a wafer 204 located on a support pin 206 in a traditional wafer stage. The support pins 206 are attached to a wafer stage 208 (Wafer Stage) and used to adjust the inclination of the wafer. FIG. 5 is a plan view of the wafer 204 in FIG. In FIG. 5, the number of adjacent dies is smaller than the dies at the four wafer edge portions, and the exposure dose scattered from four rounds cannot be received uniformly, so that the possibility of forming a critical dimension variation is very large. .
[0006]
In view of the above problems, there is a great need for an apparatus and method that can overcome the above disadvantages, and the present invention meets this need.
[0007]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor manufacturing apparatus and method for improving critical dimension uniformity of a wafer edge by compensating for a flare effect appearing at a wafer edge.
[0008]
Another object of the present invention is to provide a semiconductor manufacturing apparatus and method capable of improving the production yield.
[0009]
Still another object of the present invention is to provide a semiconductor manufacturing apparatus and method capable of compensating for a flare effect that occurs when a wafer edge is exposed at the time of exposure.
[0010]
[Means for Solving the Problems]
The invention according to claim 1 is a semiconductor manufacturing apparatus for improving wafer edge critical dimension uniformity, wherein the semiconductor manufacturing apparatus comprises:
Fixing the wafer to the wafer stage during the lithography process, a device for supporting and tilting the wafer,
A device fixed to the wafer stage and tilted integrally with the wafer by a device for supporting and tilting the wafer, a device for blocking and receiving scattered light projected from the light source around the wafer,
And a semiconductor manufacturing apparatus characterized by having:
According to a second aspect of the present invention, there is provided the semiconductor manufacturing apparatus according to the first aspect, wherein the device for supporting and tilting the wafer includes support pins for moving the wafer stage forward and backward.
According to a third aspect of the present invention, in the semiconductor manufacturing apparatus according to the first aspect, the device for blocking and receiving the scattered light projected from the light source around the wafer includes a flat plate on which silicon dioxide is formed. And a semiconductor manufacturing apparatus.
According to a fourth aspect of the present invention, there is provided a semiconductor manufacturing apparatus for improving uniformity of wafer edge critical dimension, wherein the semiconductor manufacturing apparatus comprises:
An apparatus that intercepts and receives scattered light projected from the light source to the periphery of the wafer during the lithography process and is tilted and exposed in solidarity with the wafer,
An apparatus for blocking and receiving scattered light projected from the light source to the periphery of the wafer during the lithography process while tilting and exposing the apparatus for blocking and receiving scattered light projected from the light source around the wafer. An apparatus for fixing to a wafer stage,
And a semiconductor manufacturing apparatus characterized by having:
According to a fifth aspect of the present invention, in the semiconductor manufacturing apparatus according to the fourth aspect, the device for blocking and receiving scattered light projected from the light source around the wafer includes a flat plate formed with silicon carbide. And a semiconductor manufacturing apparatus.
According to a sixth aspect of the present invention, in the semiconductor manufacturing apparatus according to the fourth aspect, the device for fixing the device for blocking and receiving the scattered light projected from the light source around the wafer to the wafer stage includes supporting pins for moving the wafer stage forward and backward. A semiconductor manufacturing apparatus characterized by having
The invention according to claim 7 is a method for improving the uniformity of critical dimension of a wafer edge,
Providing a wafer on a wafer holder of a stepper;
Providing an exposure plate surrounding the four circumferences of the wafer;
Exposing the wafer and the exposure plate;
And a method of improving the critical dimension uniformity of the wafer edge.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention provides a semiconductor manufacturing apparatus capable of improving the critical dimension uniformity of a wafer edge. This semiconductor manufacturing apparatus is an apparatus for fixing a wafer to a wafer stage during a lithography process by a device for supporting and tilting a wafer, and for preventing and receiving scattered light projected from the light source around the wafer. A device for blocking and receiving scattered light projected to the surroundings is fixed on the wafer stage by a device for supporting and tilting the wafer, and tilts with the wafer.
[0012]
According to another embodiment of the present invention, the present invention provides a semiconductor manufacturing apparatus capable of improving critical dimension uniformity of a wafer edge, the semiconductor manufacturing apparatus including an apparatus for blocking and receiving scattered light projected from a light source around a wafer. The apparatus for blocking and receiving scattered light projected from the light source around the wafer is tilted and exposed together with the wafer during the lithography process, and the semiconductor manufacturing apparatus further blocks and receives the scattered light projected around the wafer. An apparatus is provided for securing the receiving device to a wafer stage, thereby blocking and receiving the scattered light projected around the wafer so that the device with the wafer is tilted and exposed jointly during the lithographic process.
[0013]
In addition, the present invention provides a method for improving wafer edge critical dimension uniformity during a lithography process. The method of improving the critical dimension uniformity of the wafer edge includes the following steps. First, the wafer is provided on a wafer stage of a stepper. Subsequently, an exposure plate that surrounds the four circumferences of the wafer is provided. The last wafer and the exposure plate are exposed.
[0014]
【Example】
FIG. 6 is a diagram of a wafer stage apparatus of the present invention. The light source passes through the lens 302 and exposes the wafer 304 located on the support pins 306. The support pins 306 can move back and forth on the wafer table 312 and are used to adjust the inclination of the wafer 304. The exposure plate 308 is located on the support pins 310. Exposure plate 308 is used to block and receive light scattered from the light source. The support pins 310 together with the support pins 306 advance and retreat on the wafer table 312 to form one plane on the exposure plate 308 and the wafer 304. 7 and 8 are plan views of the exposure plate 308 and the wafer 304. Exposure plate 308 is used to block and receive the dimming light rays from the light source like neighboring dies, as well as to compensate for wafer edge flare effects, thereby increasing wafer edge critical dimension uniformity, ie, wafer edge critical dimension uniformity. Is effectively eliminated.
[0015]
The exposure plate 308 can be, for example, a flat plate on which a silicon carbide layer or a silicon dioxide layer is formed. The exposure plate 308 is a device that can block and receive scattered light from any light source, and is capable of tilting jointly with the wafer. The support pins 310 are completely the same as the support pins 306 and can adjust the inclination of the wafer 304 and the exposure plate 308 to be one plane by moving back and forth on the wafer table 312. 308 is a device that can form one plane. When performing the step exposure, the light beam from the light source not only exposes each one die on the wafer 304 but also exposes the exposure plate 308. For example, to compensate for the flare effect of the wafer edge, the exposure is extended around the outer circumference of the wafer 304. That is, an extra exposure shot is performed on the outer periphery of the die at the wafer edge, that is, on the exposure plate 308, so that the die at the wafer edge can obtain the same exposure dose as the dies other than the wafer edge, thereby reducing the critical dimension of the wafer edge die. Either the uniformity is enhanced, or severely, the phenomenon of variation in the critical dimension of the wafer edge die critical dimension is completely eliminated. Each exposed perimeter on the wafer 304 shown in FIG. 8 is accompanied by a similar extra exposure.
[0016]
The above description of the invention is not intended to limit the scope of the invention, and any alteration or modification of an equivalent effect that does not depart from the spirit of the invention falls within the scope of the invention.
[0017]
【The invention's effect】
The present invention provides a semiconductor manufacturing apparatus and method for improving critical dimension uniformity of a wafer edge by compensating for a flare effect appearing at the wafer edge.
[Brief description of the drawings]
FIG. 1 is a relationship diagram between a line width and an exposure dose on a wafer.
FIG. 2 is a view showing a state of a critical dimension variation of a die at a wafer edge portion.
FIG. 3 is a view showing whether or not scattered light is exposed to each die and the exposure dose of adjacent dies on the four circumferences of each die is increased.
FIG. 4 is a view showing a state in which a light source passes through a lens and exposes a wafer on a support pin in a traditional wafer stage.
FIG. 5 is a plan view of the wafer in FIG. 4;
FIG. 6 is a diagram of a wafer stage apparatus of the present invention.
FIG. 7 is a plan view of the exposure plate of the present invention.
FIG. 8 is a plan view of the wafer in FIG. 7;
[Explanation of symbols]
102 Die 104 Scattered light 202 Lens 204 Wafer 206 Support pin 208 Wafer table 302 Lens 304 Wafer 306 Support pin 308 Exposure plate 310 Support pin 312 Wafer table

Claims (7)

ウエハエッジ臨界寸法均一度を向上する半導体製造装置において、該半導体製造装置が、
ウエハをリソグラフィー工程中にあってウエハ台に固定する、ウエハを支持及び傾斜させる装置と、
該ウエハを支持及び傾斜させる装置によりウエハ台に固定されてウエハと一体に傾斜する、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置と、
を具えたことを特徴とする、半導体製造装置。In a semiconductor manufacturing apparatus for improving wafer edge critical dimension uniformity, the semiconductor manufacturing apparatus includes:
Fixing the wafer to the wafer stage during the lithography process, a device for supporting and tilting the wafer,
A device fixed to the wafer stage and tilted integrally with the wafer by a device for supporting and tilting the wafer, a device for blocking and receiving scattered light projected from the light source around the wafer,
A semiconductor manufacturing apparatus, comprising: 請求項１に記載の半導体製造装置において、ウエハを支持及び傾斜させる装置がウエハ台を進退する支持ピンを具えたことを特徴とする、半導体製造装置。2. The semiconductor manufacturing apparatus according to claim 1, wherein the apparatus for supporting and tilting the wafer includes support pins for moving the wafer table forward and backward. 請求項１に記載の半導体製造装置において、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置が、二酸化けい素を形成した平板を具えたことを特徴とする、半導体製造装置。2. The semiconductor manufacturing apparatus according to claim 1, wherein the device for blocking and receiving the scattered light projected from the light source around the wafer includes a flat plate formed with silicon dioxide. ウエハエッジ臨界寸法均一度を向上する半導体製造装置において、該半導体製造装置が、
リソグラフィー工程中にあってウエハと連帯して傾斜し露光される、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置と、
該光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置をリソグラフィー工程中にあってウエハと連帯して傾斜させ露光させる、該光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置をウエハ台に固定する装置と、
を具えたことを特徴とする、半導体製造装置。In a semiconductor manufacturing apparatus for improving wafer edge critical dimension uniformity, the semiconductor manufacturing apparatus includes:
An apparatus that intercepts and receives scattered light projected from the light source to the periphery of the wafer during the lithography process and is tilted and exposed in solidarity with the wafer,
An apparatus for blocking and receiving scattered light projected from the light source to the periphery of the wafer during the lithography process while tilting and exposing the apparatus for blocking and receiving scattered light projected from the light source around the wafer. An apparatus for fixing to a wafer stage,
A semiconductor manufacturing apparatus, comprising: 請求項４に記載の半導体製造装置において、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置が、炭化けい素を形成した平板を具えたことを特徴とする、半導体製造装置。5. The semiconductor manufacturing apparatus according to claim 4, wherein the device for blocking and receiving the scattered light projected from the light source around the wafer includes a flat plate formed with silicon carbide. 請求項４に記載の半導体製造装置において、光源よりウエハ周囲に投射される散乱光線を阻止並びに受け取る装置をウエハ台に固定する装置が、ウエハ台を進退する支持ピンを具えたことを特徴とする、半導体製造装置。5. The semiconductor manufacturing apparatus according to claim 4, wherein the device for fixing the device for blocking and receiving the scattered light beams projected from the light source to the periphery of the wafer to the wafer stage includes support pins for moving the wafer stage forward and backward. , Semiconductor manufacturing equipment. ウエハエッジ臨界寸法均一度を向上する方法において、
ウエハをステッパのウエハ台上に提供するステップと、
ウエハ四周を囲む露光板を提供するステップと、
該ウエハと該露光板を露光させるステップと、
を具えたことを特徴とする、ウエハエッジ臨界寸法均一度を向上する方法。In a method for improving critical dimension uniformity of a wafer edge,
Providing a wafer on a wafer holder of a stepper;
Providing an exposure plate surrounding the four circumferences of the wafer;
Exposing the wafer and the exposure plate;
A method for improving wafer edge critical dimension uniformity, characterized by comprising:
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