JP2004111856A - Nonvolatile organic semiconductor memory element, its manufacture, and noncontact information controlling and dysplaying device - Google Patents
Nonvolatile organic semiconductor memory element, its manufacture, and noncontact information controlling and dysplaying device Download PDFInfo
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/472—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only inorganic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】
【発明の属する技術分野】
本発明は、有機半導体を用いた記憶素子、高分子圧電体、これらを融合した有機物から成る不揮発性半導体記憶素子に関し、例えば、非接触式カード、スマートタグ、物流に応用される情報管理と情報表示が一体となったインテリジェントタグ等に適用して好適なものである。
【０００２】
【従来の技術】
近年、有機半導体材料は、Ｓｉ、ＧａＡｓ、に続く第三の半導体材料として注目され、活発な開発がなされている。有機物材料を用いる利点として、膜形成においては１５０℃以下の低温で成膜され、使用する基板の選択の自由度が向上することはもとより、比較的安価な製造装置にて簡便に作製可能であることが挙げられる。また、有機ＥＬ素子に観られるように、電気的なスイッチング以外に発光特性もあり、Ｓｉ単独、あるいはＧａＡｓ単独で成し得なかったモノリシックＯＥＩＣ（ｏｐｔｏｅｌｅｃｔｒｏｎｉｃ ｉｎｔｅｇｒａｔｅｄ ｃｉｒｃｕｉｔ＝光電ＩＣ）も実現のものになりつつある。
【０００３】
しかし、有機半導体材料は、その性能を示すキャリア移動度において１ｃｍ２Ｖ−１ｓ−１程であり、Ｓｉのそれと比較すると約２〜３桁低く、有機半導体から成る装置を現状のＳｉデバイスに置き換えることは困難であり、将来的に両者は住み分けされ、個々に発展していくものと予想される。即ち、有機半導体の最大の特徴である安価な製造コストと機能の融合化に基づき、演算の高度な機能ではなく、ローエンドユーザー向けの素子供給に特化されていくであろう。この様な中で、インテリジェントタグへの展開が、物流革命の要請により注目されてきた。
【０００４】
図６は、インテリジェントタグの一例を示す図で、従来の非接触ＩＣカードに表示機能を持たせたものである。すなわち、導電性高分子配線から成るアンテナ部１１、有機半導体素子から成る演算部（ＣＰＵ）１２、記憶部１３、有機ＥＬ素子から成る非接触ＩＣカードＩに表示部１４を持たせてインテリジェントタグＩＩとしたもので、このインテリジェントタグＩＩは、全て有機物から形成でき、低コストで製造できる特徴を有する。
【０００５】
従来技術に鑑みて、インテリジェントタグの実現にあたり、もっとも開発困難なものは不揮発性記憶素子である。従って、本発明は、このようなインテリジェントタグに観られる有機半導体材料を用いた半導体装置の不揮発性記憶素子の実現にある。
【０００６】
Ｓｉ半導体素子に観られる不揮発性記憶素子は大別すると２種あり、一つ目は浮遊ゲートにホットキャリアを注入し、この注入された電荷の作用によりトランジスタ動作点をシフトさせる、所謂ＥＥＰＲＯＭと、二つ目は強誘電体のヒステリシス特性を利用した素子である。強誘電体を用いた不揮発性記憶素子は２種類あり、現在製品化されているものはＦＲＡＭと呼ばれる強誘電体キャパシターの分極反転電流の差を検知する方式である。他方の方式は強誘電体ゲートトランジスタと呼ばれ、古くから提案されている（例えば、非特許文献１参照）ものの、いまだ実用化なされていない素子である。
【０００７】
ＥＥＰＲＯＭと同じ原理に基づき、有機半導体素子を構成した場合、以下の様な原理的に不可能な事態が発生する。これは絶縁性有機物のエレクトレット現象として知られることで、浮遊ゲートに相当する有機絶縁膜に電荷を注入した場合、永久分極を示し、一旦、書き込まれた情報は再度、消去／書き込みが出来なくなってしまうからである。
【０００８】
強誘電体ゲートトランジスタは１Ｔ（１トランジスタ）で記憶が可能であるのに対し、ＦＲＡＭの１つの記憶ビットは、１Ｔ１Ｃ（１トランジスタ、１キャパシター）で構成され、構造的に不利であり、従って、強誘電体ゲートトランジスタ構造で不揮発性有機半導体記憶素子を作製するのが好適と思われる。
【０００９】
また、低温で素子形成可能な有機半導体の特徴を用い、プラスチック基板上に、１５０℃以下のプロセス温度にて有機トランジスタを作製し、その特性向上の為に、無機酸化物や無機強誘電体材料をゲート絶縁膜として採用する提案がなされている（例えば、特許文献１参照）。
一般に、強誘電体は比誘電率が高いのでゲート絶縁膜直下のチャネル形成部への電界強度が稼げ好適に振る舞う。しかし、この特許文献１には、強誘電体の自発分極に基づく不揮発性メモリ動作については記載されていない。
良好な強誘電体自発分極を利用するには、１５０℃以上、好ましくは５００℃以上の熱プロセスが必要であり、その為には石英ガラス、Ｓｉウェハ等の耐熱性基板上に素子形成する必要がある。
【００１０】
Ｓｉ半導体を用いた強誘電体ゲートトランジスタは、ＭＦＳ（金属（Ｍｅｔａｌ）−強誘電体（Ｆｅｒｒｏｅｌｅｃｔｒｉｃｓ）−半導体（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ））構造が理想である。この場合、Ｓの半導体にはシリコン、Ｆの強誘電体には金属酸化物セラミックスが用いられる。一般に、金属酸化物セラミックの強誘電体は、その膜形成において、結晶化の為の熱が必要である（通常スパッタリングでは５００℃以上、ＣＶＤ（化学気相成長法）では４５０℃、ｓｏｌ−ｇｅｌ法では５５０℃など）。この時、下地シリコン材料と反応し、二酸化ケイ素膜が形成され、または、下地シリコン材料が強誘電体材料に拡散して特性劣化を招く。
【００１１】
このような特性劣化の対策として、ＭＦＩＳ（金属（Ｍｅｔａｌ）−強誘電体（Ｆｅｒｒｏｅｌｅｃｔｒｉｃｓ）−絶縁体（Ｉｎｓｕｌａｔｏｒ）−半導体（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ））構造が提案されているが、絶縁体の反電界による強誘電体分極情報の劣化が問題となり、実用化になっていない。
【００１２】
また、ＭＦＭＩＳ（金属（Ｍｅｔａｌ）−強誘電体（Ｆｅｒｒｏｅｌｅｃｔｒｉｃｓ）− 金属（Ｍｅｔａｌ）−絶縁体（Ｉｎｓｕｌａｔｏｒ）−半導体（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ））構造が提案されているものの、リーク電流による強誘電体分極情報の劣化により、これも実用になっていない。
【００１３】
【非特許文献１】
Ｊ．Ｌ．Ｍｏｌｌ ａｎｄ Ｙ．Ｔａｒｕｉ： ＩＥＥＥ Ｔｒａｎｓ．Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ （Ｓｏｌｉｄ−Ｓｔａｔｅ Ｒｅｓ．Ｃｏｎｆ．Ａｂｓ．）， ＥＤ−１０， ３３８ （１９６３）
【００１４】
【非特許文献２】
Ｌｉｎ ｅｔ ａｌ．ＩＥＥＥ ５４ｔｈ Ａｎｎｕａｌ Ｄｅｖｉｃｅ Ｒｅｓｅａｒｃｈ Ｃｏｎｆｅｒｅｎｃｅ， １９９６， ｐａｇｅ ８０
【００１５】
【非特許文献３】
Ｂｒｏｗｎ ｅｔ ａｌ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．７９， ４ （１９９６） ２１３６
【００１６】
【非特許文献４】
Ｓｉｒｒｉｎｇｈｕｓ ｅｔ ａｌ．ＳＣＩＥＮＣＥ ２９０ １５
（２０００） ２１２３
【００１７】
【非特許文献５】
Ｔ．Ｈｉｒａｉ ｅｔ ａｌ． Ｊｐｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ：３３（１９９４） ５２１９
【００１８】
【特許文献１】
特開２０００−２６９５１５号公報
【００１９】
【特許文献２】
特開平１１−２５１６０１号公報
【００２０】
【発明が解決しようとする課題】
上述のように、強誘電体の自発分極を用いた不揮発性記憶素子はＭＦＳ構造が理想的であるが、半導体材料にＳｉを用いた場合、理想的なＳｉ／強誘電体界面が形成できないので実用化に至らない。逆に言えば、Ｓｉ半導体を用いないでＭＦＳを作ることが、この解決策になる。
【００２１】
本発明は、上述のごとき実情に鑑みてなされたもので、有機半導体材料と強誘電体膜を用いて電界効果型トランジスタを構成し、この強誘電体膜の自発分極を利用して情報を記憶する不揮発性半導体記憶素子において、前記強誘電体膜を無機材料とすることによって、半導体材料にＳｉを用いないＭＦＳ素子を提供するものである。
【００２２】
また、本発明はＳｉウェハ上に絶縁膜を形成後、ゲート電極膜、強誘電体膜、有機半導体膜、を積層し、ソース・ドレイン電極膜を形成する不揮発性有機半導体記憶素子の好適な製造方法を提供するものである。
【００２３】
【課題を解決するための手段】
本発明は、有機半導体材料と強誘電体膜のゲート絶縁膜にて電界効果型トランジスタを形成し、前記強誘電体膜の自発分極を利用して情報を記憶する不揮発性半導体記憶素子において、前記強誘電体膜が無機材料からなること，更には、前記無機材料が鉛系強誘電体材料、又は、ビスマス層状強誘電体材料、又は、ニオブ酸塩系の強誘電体材料からなることを特徴としたものである。
【００２４】
また，本発明は、絶縁性の耐熱性基板及び／または絶縁膜を形成したＳｉウェハの上に、ゲート電極膜、無機材料、有機半導体膜、ソース・ドレイン電極膜を順次積層してなること、更には、前記ゲート電極膜の材料がＰｔ、Ｒｈ、Ｉｒ金属の単体、もしくはこれらの２成分または３成分合金材料であること、又は、Ｒｕ、Ｉｒ、Ｒｈの酸化物であること、又は、導電性の多元系複合金属酸化物からなること、又は、ＳｒＲｕＯ３であることを特徴としたものである。
【００２５】
更に、本発明は、有機半導体材料がアセン系材料群から選ばれる材料であること、又は、π共役高分子材料から選ばれる材料であることを特徴としたものである。
【００２６】
また、本発明は、有機半導体材料と無機材料からなる電界効果空トランジェスタ記憶素子と、高周波アンテナと、受信した高周波を電力に変換する素子と、情報演算素子と、表示素子とを備えたインテリジェントタグを特徴とするものである。
【００２７】
【発明の実施の形態】
図１は、有機半導体材料を用いた電界効果型トランジスタの構成例を示す図で、図示のように、基板１上にゲート電極２、強誘電体膜３、ソース電極４及びドレイン電極５、有機半導体層６の順に積層構成されている。ソース、ドレイン電極材料としてはＡｕ等の金属のほかに、ＰＥＤＯＴ（ポリエチレンジオキシチオフェン）、ポリアニリン等の導電性高分子材料を用いてもよい。ゲート電極２は後述する強誘電体材料の膜形成時に十分化学的に安定、かつ、熱的に安定であることが要求され、Ｐｔ族元素やその合金、Ｐｔ族元素の酸化物、または、導電性セラミックス材料が好ましい。
【００２８】
図２は、強誘電体のヒステリシス特性を示す図で、強誘電体は電界により分極構造が変化し２値の安定状態を保持するため、分極値において２値の状態を持つ。これは、強誘電体の自発分極によるものであり、一般に、図中、電界強度が０ＭＶ／ｍの時、Ｙ軸と交わる点を残留分極といい、＋Ｐｒ、−Ｐｒにて固有化される。
【００２９】
この様な強誘電体材料にはジルコン酸チタン酸鉛（ＰＺＴ）がある。この材料の結晶構造はペロブスカイト型構造を持ち、本発明でいう、鉛系強誘電体とは、ペロブスカイト型構造を持ち、一成分として酸化鉛を含むものを意味する。また、複合ペロブスカイト構造を持っても良い。ＰＺＴ５２／４８はジルコン酸鉛５２％、チタン酸鉛４８％の比率からなる固溶体である。この材料の強誘電体特性は、Ｐｒ＝３７μＣ／ｃｍ２、抗電界（Ｅｃ）＝１．５ＭＶ／ｍを持つ。
【００３０】
他の強誘電体材料としてＢｉ層状強誘電体材料がある。ＳｒＢｉ２Ｔａ２Ｏ９はＰｒ＝８μＣ／ｃｍ２、抗電界（Ｅｃ）＝０．８ＭＶ／ｍを持つ。
【００３１】
また、（Ｎａ０．５Ｋ０．５）ＮｂＯ３などはニオブ酸塩でパイロナイオベートと呼ばれ、Ｐｒ＝７μＣ／ｃｍ２、抗電界（Ｅｃ）＝０．３ＭＶ／ｍを持つ。
【００３２】
上記３種の強誘電体材料はＰＺＴが最も残留分極が大きく、且つ、抗電界が大きい、最も小さいのがパイロナイオベートで、その中間がビスマス層状構造強誘電体であり、所望する特性から、適宜材料の選定がなされるものである。
【００３３】
図３は、強誘電状態とトランジスタ動作の関係を示す図で、ゲート電極２に−の電圧が印加されると、図３（Ａ）に示すように、強誘電体層３は矢印で示す如く上向きに分極されており、したがって、有機半導体層６に逆極性電荷（＋電荷）が誘起・保持されている。この時、有機半導体層６がｐ型であれば、ソース電極４・ドレイン電極５間のチャネルが形成され、トランジスタはＯＮ状態になる。一方、ゲート電極２に＋の電圧が印加されると、図３（Ｂ）に示すように、強誘電体層３は矢印で示す如く、下向きに分極されており、チャネルは形成されない。この様に、強誘電体分極の方向によってチャネルコンダクタンスが２値を持つ。
【００３４】
本発明の強誘電体膜は、その膜形成温度が５００℃以上の高温で成されるため、耐熱性、かつ化学的に安定な電極膜が必要になる。Ｐｔは最も安定した元素として一般に知られているものの、鉛系強誘電体膜形成においては不十分な場合があり、Ｐｔ−Ｒｈ、Ｐｔ−Ｉｒなどの合金膜を用いることがある。
【００３５】
また、各種強誘電体材料は酸化物であり、膜形成時の下地金属の酸化反応が生じる場合には、あらかじめ金属酸化物電極を用いることが効果的である。この例として、ＲｕＯ２，ＩｒＯ２，ＲｈＯ２などが効果的であり、また複合酸化物としてＳｒＲｕＯ３やＬＳＣＯ（ランタンストロンチウムコバルタイト）や、コバルト酸化物の代わりにＭｎ酸化物を用いたＬＳＭＯなども知られている。ただし、ＬＳＣ０は７５０℃において一部Ｃｏの還元反応により導電性の劣化があり、耐熱性の観点からＳｒＲｕＯ３の方が優れている。
【００３６】
本発明の有機半導体材料としてベンゼン環の縮合多環式炭化水素化合物が用いられる。これを慣用的にアセン系材料と呼ぶ。図４は、アセン系材料の化学式を示す図で、図４（Ａ）はテトラセン、図４（Ｂ）はペンタセン、図４（Ｃ）はペリレンを示す。また、このハロゲン化やカルコゲン化誘導体も可能である。その中で、ペンタセンが好適である。ペンタセンは、例えば、非特許文献２，３にて言及されているが、これら材料は真空蒸着法にて簡便に形成可能できることが特徴である。
【００３７】
同様に、真空蒸着法にて形成可能な材料として、フタロシアニン及び金属置換フタロシアニン配位化合物等の低分子有機半導体材料も好適である（例えば特許文献２参照）。また、アセン系材料であるペリレンも有効である。
【００３８】
真空蒸着法を用いずに塗布・乾燥にて有機半導体膜を形成することは可能で、特にこれら好適な材料として、π共役高分子材料が挙げられる。ポリチオフェン材料はその典型的な化合物である。ポリチオフェン高分子は溶媒に対する溶解性が低いため、トルエン、クロロホルム等に可溶化させる為に、長鎖アルキル基を基本骨格に導入した長鎖アルキルポリチオフェンを用いてもよい。また、ポリチオフェン、フルオレン系化合物高分子の ｐｏｌｙ（９，９−ｄｉｏｃｔｙｌｆｌｕｏｒｅｎｅ−ｃｏ−ｂｉｔｈｉｏｐｈｅｎｅを用いてもよい（例えば、非特許文献４参照）。
【００３９】
強誘電体の分極状態によりソース・ドレイン間のチャネルコンダクタンスが変化する現象は、半導体／強誘電体／電極を積層した試料の印加電圧−静電容量変化の測定にて確認出来る（例えば、非特許文献５参照）。これは後述実施例において、この様な素子を作製し、図５に示す電圧−静電容量測定例とメモリーウィンドウの定義からその動作の確認を行った。
【００４０】
実施例１
シリコン基板上に熱酸化膜を配置して、上部積層素子との電気的絶縁を施した後、スパッタリング法で、基板温度６５０℃にてＰｔを１００ｎｍ成膜した。次に、強誘電体材料としてＰＺＴ（５２／４８）をスパッタリング法で、基板温度６００℃にて、１００ｎｍ成膜した。有機半導体膜としてペンタセン材料を真空蒸着法にて８０ｎｍ形成した。原料のペンタセン粉末は市販の粉末を昇華精製したものを用いた。ペンタセン蒸着膜はクライオポンプを用いた真空排気系で、チャンバー背圧１〜５×１０−５Ｐａにて実施した。前記ペンタセン粉末をＭｏ金属でできた抵抗加熱用ボートに乗せ、ボートと基板の距離を３０ｃｍに設置し、蒸着時のボート温度２００℃に加熱し、ペンタセンを昇華させ基板上に膜形成した。基板上の膜堆積量は水晶振動子センサーにて検知した。膜堆積速度は０．２ｎｍ／ｓである。上部電極として直径１ｍｍのＡｕ電極膜を形成し、Ｐｔ電極、強誘電体、半導体、上部電極からなる積層キャパシターを形成し、Ｃ−Ｖ特性をＹＨＰ社製インピーダンスアナライザ（４１９４Ａ）にて測定した。この時の測定周波数は１ｋＨｚ、交流振幅は０．０５Ｖ、挿引電圧は、外部直流電源を用い、最大±４０Ｖまで印加した。この時の、図５におけるメモリーウィンドウδＶはバイアス電圧−１７Ｖを中心に、最大幅１２Ｖを得た。
【００４１】
実施例２
下部電極形成までは実施例１と同じ、また有機半導体成膜も同じ。
強誘電体材料としてＳｒＢｉ２Ｔａ２Ｏ９をスパッタリング法で、基板温度６００℃にて、１００ｎｍ成膜した。ペンタセンを成膜後、上部電極として直径１ｍｍのＡｕ電極膜を形成し、Ｐｔ電極、強誘電体、半導体、上部電極からなる積層キャパシターを形成し、Ｃ−Ｖ特性をＹＨＰ社製インピーダンスアナライザ（４１９４Ａ）にて測定した。この時の測定周波数は１ｋＨｚ、交流振幅は０．０５Ｖ、挿引電圧は、外部直流電源を用い、最大±４０Ｖまで印加した。この時の、図５におけるメモリーウィンドウδＶはバイアス電圧−１２Ｖを中心に、最大幅８Ｖを得た。
【００４２】
実施例３
強誘電体材料に（Ｎａ０．５ Ｋ０．５）ＮｂＯ３をｓｏｌ−ｇｅｌ法にて膜厚１００ｎｍを形成した。ｓｏｌ−ｇｅｌ溶液をスピンコーティングで塗布・乾燥させた後、熱処理温度９００℃にて結晶化させた。同様の評価を行ったところ、図５におけるメモリーウィンドウδＶはバイアス電圧−６Ｖを中心に、最大幅４Ｖを得た。
用いる強誘電体により電気動作が異なるのは、強誘電体の持つ抗電界と残留分極の違いに起因しており、これにより、所望する特性を得るための各種強誘電体を用いることが可能となる。
【００４３】
実施例４
強誘電体の膜形成温度により用いられる下部電極材料が限定される。強薄膜形成に好適な電極材料を求めた結果を表１に記す。試験は熱酸化膜を配置したＳｉウェハに強誘電キャパシタ構造を形成し、強誘電特性を評価したものである。評価はＰｔ電極を用いた場合の強誘電体残留分極を基準に、それより３０％大きいもの（◎）、同等（○）、３０％減少（△）、残留分極消失（×）とした。
【００４４】
【表１】
実施例５
シリコン基板上に熱酸化膜を配置して、上部積層素子との電気的絶縁を施した後、スパッタリング法で、基板温度６５０℃にてＰｔを１００ｎｍ成膜した。次に、強誘電体材料としてＰＺＴ（５２／４８）をスパッタリング法で、基板温度６００℃にて、１００ｎｍ成膜した。有機半導体膜としてペリレン材料を真空蒸着法にて８０ｎｍ形成した。上部電極として直径１ｍｍのＡｕ電極膜を形成し、Ｐｔ電極、強誘電体、半導体、上部電極からなる積層キャパシターを形成し、実施例１と同様の評価を行った。この時の図５におけるメモリーウィンドウδＶはバイアス電圧−１６Ｖを中心に、最大幅１０Ｖを得た。
【００４６】
実施例６
π共役系高分子の ｐｏｌｙ（９，９−ｄｉｏｃｔｙｌｆｌｕｏｒｅｎｅ−ｃｏ−ｂｉｔｈｉｏｐｈｅｎｅを用い、実施例１と同様な素子構成を形成し、Ｃ−Ｖ特性を評価した。フルオレン系高分子化合物はトルエン、メトキシエタノール混合溶媒を用いて０．５ｗｔ％溶液を作製し、スピンコーティングにて膜厚８０ｎｍ形成した。この時のメモリーウィンドウδＶはバイアス電圧−３０Ｖを中心に、最大幅４Ｖを得た。
【００４７】
実施例７
熱酸化膜を配置したＳｉウェハにＰｔのゲート電極を１００ｎｍ形成し、ＰＺＴ（５２／４８）ゲート絶縁膜、１００ｎｍを形成し、ペンタセン半導体膜を８０ｎｍ形成後、Ａｕ蒸着膜（シャドウマスクを用いて）にてソース、ドレイン電極を形成した。これにより、強誘電体不揮発性記憶素子が出来る。
【００４８】
【発明の効果】
有機半導体材料を用いた、換言すれば、半導体材料にＳｉを用いないＭＦＳ不揮発性記憶素子の提供が可能になった。また、所望する電圧にて動作するＭＦＳ不揮発性記憶素子の提供が可能になった。更には、安定した強誘電特性を出現させることの出来る電極材料の提供が可能になった。
【図面の簡単な説明】
【図１】有機半導体材料を用いた電界効果型トランジスタの構成例を示す図である。
【図２】強誘電体のヒステリシス特性を示す図である。
【図３】強誘電状態とトランジスタ動作の関係を示す図である。
【図４】アセン系材料の化学式を示す図である。
【図５】電圧−静電容量測定例とメモリーウィンドウの関係を示す図である。
【図６】インテリジェントタグの一例を示す図である。
【符号の説明】
１…基板、２…ゲート電極、３…強誘電体層、４…ソース電極、５…ドレイン電極、６…有機半導体層、Ｉ…ＩＣカード、ＩＩ…インテリジェントタグ、１１…アンテナ、１２…ＣＰＵ、１３…記憶素子、１４…表示素子。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a storage element using an organic semiconductor, a polymer piezoelectric material, and a nonvolatile semiconductor storage element made of an organic material obtained by fusing these, for example, a non-contact card, a smart tag, information management and information applied to physical distribution. This is suitable for application to an intelligent tag or the like with integrated display.
[0002]
[Prior art]
In recent years, organic semiconductor materials have attracted attention as third semiconductor materials following Si and GaAs, and have been actively developed. The advantage of using an organic material is that the film is formed at a low temperature of 150 ° C. or less in the film formation, so that the degree of freedom in selecting a substrate to be used is improved, and the film can be easily manufactured with a relatively inexpensive manufacturing apparatus. It is mentioned. Further, as seen in the organic EL element, there is a light emitting characteristic in addition to the electrical switching, and a monolithic OEIC (optoelectronic integrated circuit) which cannot be achieved by Si alone or GaAs alone is also realized. It is getting.
[0003]
However, the organic semiconductor material has a carrier mobility indicating its performance of about 1 cm 2 V −1 s −1, which is about two to three orders of magnitude lower than that of Si. It is difficult to replace them, and it is expected that both will be separated and develop independently in the future. In other words, based on the integration of the inexpensive manufacturing cost and the function, which are the biggest features of the organic semiconductor, the device will be specialized in supplying elements for low-end users instead of advanced functions of arithmetic. Under these circumstances, the development of intelligent tags has attracted attention due to the demand of the distribution revolution.
[0004]
FIG. 6 is a diagram showing an example of an intelligent tag, in which a display function is added to a conventional non-contact IC card. That is, the
[0005]
In view of the prior art, the hardest to develop in implementing an intelligent tag is a non-volatile storage element. Therefore, the present invention resides in realizing a nonvolatile memory element of a semiconductor device using an organic semiconductor material found in such an intelligent tag.
[0006]
Non-volatile memory elements found in Si semiconductor elements are roughly classified into two types. The first type is a so-called EEPROM in which hot carriers are injected into the floating gate and the transistor operating point is shifted by the action of the injected charges. The second is an element utilizing the hysteresis characteristics of a ferroelectric. There are two types of non-volatile memory elements using ferroelectrics, and the one commercialized at present is a method for detecting a difference in polarization reversal current of a ferroelectric capacitor called FRAM. The other type is called a ferroelectric gate transistor, and has been proposed for a long time (for example, see Non-Patent Document 1), but has not yet been put to practical use.
[0007]
When an organic semiconductor element is configured based on the same principle as an EEPROM, the following principle is impossible. This is known as the electret phenomenon of an insulating organic material. When electric charge is injected into an organic insulating film corresponding to a floating gate, it shows permanent polarization, and once written information cannot be erased / written again. It is because.
[0008]
While a ferroelectric gate transistor can store data in 1T (one transistor), one storage bit of FRAM is composed of 1T1C (one transistor, one capacitor), which is structurally disadvantageous, and It seems suitable to fabricate a nonvolatile organic semiconductor storage element with a ferroelectric gate transistor structure.
[0009]
In addition, an organic transistor is manufactured at a process temperature of 150 ° C. or less on a plastic substrate using characteristics of an organic semiconductor that can form an element at a low temperature, and an inorganic oxide or an inorganic ferroelectric material is used to improve the characteristics. Is proposed as a gate insulating film (for example, see Patent Document 1).
In general, since a ferroelectric has a high relative permittivity, an electric field strength to a channel forming portion directly below a gate insulating film can be increased and the ferroelectric behaves suitably. However, Patent Document 1 does not describe a nonvolatile memory operation based on spontaneous polarization of a ferroelectric.
In order to utilize good ferroelectric spontaneous polarization, a thermal process of 150 ° C. or higher, preferably 500 ° C. or higher is required. For this purpose, it is necessary to form an element on a heat-resistant substrate such as quartz glass or a Si wafer. There is.
[0010]
An ideal ferroelectric gate transistor using an Si semiconductor has an MFS (Metal (Metal) -Ferroelectrics (Semiconductor)) structure. In this case, silicon is used for the semiconductor of S, and metal oxide ceramic is used for the ferroelectric of F. Generally, a ferroelectric of a metal oxide ceramic requires heat for crystallization in forming a film (usually 500 ° C. or higher for sputtering, 450 ° C. for CVD (chemical vapor deposition), sol-gel). 550 ° C in the method). At this time, it reacts with the underlying silicon material to form a silicon dioxide film, or the underlying silicon material diffuses into the ferroelectric material to cause deterioration in characteristics.
[0011]
As a countermeasure against such characteristic deterioration, an MFIS (Metal (Metal) -Ferroelectrics (Insulator) -Semiconductor (Semiconductor)) structure has been proposed. Deterioration of body polarization information has become a problem and has not been put to practical use.
[0012]
Further, although an MFMIS (Metal (Metal) -Ferroelectric (Ferroelectrics) -Metal (Metal) -Insulator (Semiconductor)) structure has been proposed, deterioration of ferroelectric polarization information due to leak current has been proposed. As a result, this has not become practical.
[0013]
[Non-patent document 1]
J. L. Moll and Y. Tarui: IEEE Trans. Electron Devices (Solid-State Res. Conf. Abs.), ED-10, 338 (1963).
[0014]
[Non-patent document 2]
Lin et al. IEEE 54th Annual Device Research Conference, 1996, page 80
[0015]
[Non-Patent Document 3]
Brown et al. J. Appl. Phys. 79, 4 (1996) 2136
[0016]
[Non-patent document 4]
Sirringhus et al. SCIENCE 290 15
(2000) 2123
[0017]
[Non-Patent Document 5]
T. Hirai et al. Jpn. J. Appl. Phys: 33 (1994) 5219
[0018]
[Patent Document 1]
JP 2000-269515 A
[Patent Document 2]
JP-A-11-251601
[Problems to be solved by the invention]
As described above, a nonvolatile memory element using spontaneous polarization of a ferroelectric material has an ideal MFS structure. However, when Si is used as a semiconductor material, an ideal Si / ferroelectric interface cannot be formed. It does not lead to practical use. Conversely, making MFS without using a Si semiconductor is the solution.
[0021]
SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and a field effect transistor is configured using an organic semiconductor material and a ferroelectric film, and information is stored using spontaneous polarization of the ferroelectric film. An object of the present invention is to provide an MFS element that does not use Si as a semiconductor material by making the ferroelectric film an inorganic material.
[0022]
Further, the present invention is suitable for manufacturing a nonvolatile organic semiconductor memory element in which a gate electrode film, a ferroelectric film, and an organic semiconductor film are laminated after forming an insulating film on a Si wafer to form source / drain electrode films. It provides a method.
[0023]
[Means for Solving the Problems]
The present invention provides a non-volatile semiconductor storage element which forms a field-effect transistor using an organic semiconductor material and a gate insulating film of a ferroelectric film and stores information using spontaneous polarization of the ferroelectric film. The ferroelectric film is made of an inorganic material, and the inorganic material is made of a lead-based ferroelectric material, a bismuth layered ferroelectric material, or a niobate-based ferroelectric material. It is what it was.
[0024]
Further, the present invention provides a method in which a gate electrode film, an inorganic material, an organic semiconductor film, and a source / drain electrode film are sequentially laminated on an insulating heat-resistant substrate and / or a Si wafer on which an insulating film is formed. Further, the material of the gate electrode film is a simple substance of Pt, Rh, or Ir metal, or a binary or ternary alloy material thereof, or an oxide of Ru, Ir, Rh, or a conductive material. It is characterized by being composed of a multi-component composite metal oxide having an intrinsic property or SrRuO 3 .
[0025]
Further, the present invention is characterized in that the organic semiconductor material is a material selected from the group of acene-based materials or a material selected from π-conjugated polymer materials.
[0026]
In addition, the present invention provides an intelligent device including a field-effect vacant-transistor storage element made of an organic semiconductor material and an inorganic material, a high-frequency antenna, an element for converting a received high-frequency power, an information processing element, and a display element. It features a tag.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a diagram showing a configuration example of a field-effect transistor using an organic semiconductor material. As shown, a gate electrode 2, a ferroelectric film 3, a source electrode 4 and a
[0028]
FIG. 2 is a diagram showing a hysteresis characteristic of the ferroelectric substance. The ferroelectric substance has a polarization state of two values because its polarization structure changes due to an electric field and a binary stable state is maintained. This is due to spontaneous polarization of the ferroelectric substance. In general, when the electric field intensity is 0 MV / m in the figure, a point intersecting with the Y axis is called remanent polarization, and is specified by + Pr and -Pr.
[0029]
Such ferroelectric materials include lead zirconate titanate (PZT). The crystal structure of this material has a perovskite structure, and a lead-based ferroelectric as referred to in the present invention means a material having a perovskite structure and containing lead oxide as one component. Further, it may have a composite perovskite structure. PZT52 / 48 is a solid solution having a ratio of 52% of lead zirconate and 48% of lead titanate. The ferroelectric properties of this material have Pr = 37 μC / cm 2 and coercive electric field (Ec) = 1.5 MV / m.
[0030]
As another ferroelectric material, there is a Bi-layered ferroelectric material. SrBi 2 Ta 2 O 9 has Pr = 8 μC / cm 2 and coercive electric field (Ec) = 0.8 MV / m.
[0031]
Further, (Na 0.5 K 0.5 ) NbO 3 or the like is a niobate and is called pyroniobate, and has Pr = 7 μC / cm 2 and coercive electric field (Ec) = 0.3 MV / m.
[0032]
Among the above three types of ferroelectric materials, PZT has the largest remanent polarization and the largest coercive electric field, the smallest is pyroniobate, and the middle is a bismuth layered structure ferroelectric. Materials are selected as appropriate.
[0033]
FIG. 3 is a diagram showing a relationship between the ferroelectric state and the transistor operation. When a negative voltage is applied to the gate electrode 2, as shown in FIG. The organic semiconductor layer 6 is polarized upward, so that an opposite polarity charge (+ charge) is induced and held in the organic semiconductor layer 6. At this time, if the organic semiconductor layer 6 is p-type, a channel is formed between the source electrode 4 and the
[0034]
Since the ferroelectric film of the present invention is formed at a high temperature of 500 ° C. or higher, an electrode film having heat resistance and being chemically stable is required. Although Pt is generally known as the most stable element, it may be insufficient in forming a lead-based ferroelectric film, and an alloy film such as Pt-Rh or Pt-Ir may be used.
[0035]
Various ferroelectric materials are oxides, and when an oxidation reaction of a base metal occurs during film formation, it is effective to use a metal oxide electrode in advance. For example, RuO 2 , IrO 2 , RhO 2 and the like are effective, SrRuO 3 and LSCO (lanthanum strontium cobaltite) as a composite oxide, and LSMO using a Mn oxide instead of a cobalt oxide. Is also known. However, LSC0 partially deteriorates in conductivity due to a reduction reaction of Co at 750 ° C., and SrRuO 3 is superior from the viewpoint of heat resistance.
[0036]
As the organic semiconductor material of the present invention, a fused polycyclic hydrocarbon compound having a benzene ring is used. This is conventionally called an acene-based material. 4A and 4B show chemical formulas of acene-based materials. FIG. 4A shows tetracene, FIG. 4B shows pentacene, and FIG. 4C shows perylene. Further, this halogenated or chalcogenated derivative is also possible. Among them, pentacene is preferred. Pentacene is mentioned, for example, in Non-Patent Documents 2 and 3, but is characterized in that these materials can be easily formed by a vacuum evaporation method.
[0037]
Similarly, as a material that can be formed by a vacuum evaporation method, a low-molecular organic semiconductor material such as phthalocyanine and a metal-substituted phthalocyanine coordination compound is also suitable (for example, see Patent Document 2). In addition, perylene, which is an acene-based material, is also effective.
[0038]
It is possible to form an organic semiconductor film by coating and drying without using a vacuum deposition method, and a particularly preferable example of these materials is a π-conjugated polymer material. Polythiophene material is that typical compound. Since the polythiophene polymer has low solubility in a solvent, a long-chain alkyl polythiophene having a long-chain alkyl group introduced into a basic skeleton may be used for solubilization in toluene, chloroform, or the like. Alternatively, polythiophene or poly (9,9-dioctylfluorene-co-bithiophene), a polymer of a fluorene-based compound, may be used (for example, see Non-Patent Document 4).
[0039]
The phenomenon that the channel conductance between the source and the drain changes depending on the polarization state of the ferroelectric substance can be confirmed by measuring the applied voltage-capacitance change of the sample in which the semiconductor / ferroelectric / electrode is laminated (for example, Non-Patent Document 1). Reference 5). In the examples described later, such an element was manufactured, and its operation was confirmed from the voltage-capacitance measurement example shown in FIG. 5 and the definition of the memory window.
[0040]
Example 1
After arranging a thermal oxide film on the silicon substrate to provide electrical insulation from the upper stacked element, Pt was deposited to a thickness of 100 nm at a substrate temperature of 650 ° C. by a sputtering method. Next, PZT (52/48) was formed as a ferroelectric material by sputtering at a substrate temperature of 600 ° C. to a thickness of 100 nm. A pentacene material was formed as an organic semiconductor film to a thickness of 80 nm by a vacuum evaporation method. The pentacene powder used as a raw material was obtained by sublimation purification of a commercially available powder. The pentacene vapor-deposited film was formed by a vacuum evacuation system using a cryopump at a chamber back pressure of 1 to 5 × 10 −5 Pa. The pentacene powder was placed on a resistance heating boat made of Mo metal, the distance between the boat and the substrate was set to 30 cm, and the boat was heated to 200 ° C. during vapor deposition to sublimate pentacene to form a film on the substrate. The film deposition amount on the substrate was detected by a quartz oscillator sensor. The film deposition rate is 0.2 nm / s. An Au electrode film having a diameter of 1 mm was formed as an upper electrode, a multilayer capacitor including a Pt electrode, a ferroelectric substance, a semiconductor, and an upper electrode was formed, and the CV characteristics were measured with an impedance analyzer (4194A) manufactured by YHP. At this time, the measurement frequency was 1 kHz, the AC amplitude was 0.05 V, and the sweep voltage was applied up to ± 40 V using an external DC power supply. At this time, the memory window δV in FIG. 5 has a maximum width of 12 V around the bias voltage of −17 V.
[0041]
Example 2
Up to the formation of the lower electrode, the same as in Example 1, and the same applies to the organic semiconductor film formation.
SrBi 2 Ta 2 O 9 was formed as a ferroelectric material by sputtering at a substrate temperature of 600 ° C. to a thickness of 100 nm. After forming pentacene, an Au electrode film having a diameter of 1 mm is formed as an upper electrode, a multilayer capacitor including a Pt electrode, a ferroelectric substance, a semiconductor, and an upper electrode is formed, and the CV characteristics are measured with a YHP impedance analyzer (4194A). ). At this time, the measurement frequency was 1 kHz, the AC amplitude was 0.05 V, and the sweep voltage was applied up to ± 40 V using an external DC power supply. At this time, the memory window δV in FIG. 5 has a maximum width of 8 V around the bias voltage of −12 V.
[0042]
Example 3
A ferroelectric material (Na0.5 K0.5) NbO 3 to form a film thickness of 100nm by sol-gel method. After the sol-gel solution was applied by spin coating and dried, it was crystallized at a heat treatment temperature of 900 ° C. As a result of the same evaluation, the memory window δV in FIG. 5 obtained a maximum width of 4 V around the bias voltage of −6 V.
The difference in the electrical operation depending on the ferroelectric used is due to the difference between the coercive electric field and the remanent polarization of the ferroelectric, which makes it possible to use various ferroelectrics to obtain the desired characteristics. Become.
[0043]
Example 4
The lower electrode material used is limited depending on the ferroelectric film forming temperature. Table 1 shows the results of finding electrode materials suitable for forming strong thin films. In the test, a ferroelectric capacitor structure was formed on a Si wafer on which a thermal oxide film was arranged, and the ferroelectric characteristics were evaluated. The evaluation was based on the ferroelectric remanent polarization in the case of using a Pt electrode, which was 30% larger (◎), equivalent (○), reduced by 30% (△), and disappeared remanent polarization (×).
[0044]
[Table 1]
Example 5
After arranging a thermal oxide film on the silicon substrate to provide electrical insulation from the upper stacked element, Pt was deposited to a thickness of 100 nm at a substrate temperature of 650 ° C. by a sputtering method. Next, PZT (52/48) was formed as a ferroelectric material by sputtering at a substrate temperature of 600 ° C. to a thickness of 100 nm. A perylene material was formed as an organic semiconductor film to a thickness of 80 nm by a vacuum evaporation method. An Au electrode film having a diameter of 1 mm was formed as an upper electrode, and a multilayer capacitor including a Pt electrode, a ferroelectric, a semiconductor, and an upper electrode was formed. The same evaluation as in Example 1 was performed. At this time, the memory window δV in FIG. 5 has a maximum width of 10 V around the bias voltage of −16 V.
[0046]
Example 6
Using a π-conjugated polymer poly (9,9-dioctylfluorene-co-bithiophene), a device configuration similar to that of Example 1 was formed, and the CV characteristics were evaluated. A 0.5 wt% solution was prepared using a mixed solvent, and the film was formed to a thickness of 80 nm by spin coating, and the maximum width of the memory window δV was 4 V around a bias voltage of −30 V.
[0047]
Example 7
A Pt gate electrode is formed to a thickness of 100 nm on a Si wafer on which a thermal oxide film is disposed, a PZT (52/48) gate insulating film is formed to a thickness of 100 nm, a pentacene semiconductor film is formed to a thickness of 80 nm, and then an Au deposited film (using a shadow mask). ) To form source and drain electrodes. Thereby, a ferroelectric nonvolatile memory element can be obtained.
[0048]
【The invention's effect】
It has become possible to provide an MFS nonvolatile memory element using an organic semiconductor material, in other words, not using Si as a semiconductor material. Further, it has become possible to provide an MFS nonvolatile memory element that operates at a desired voltage. Further, it has become possible to provide an electrode material capable of exhibiting stable ferroelectric characteristics.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a field-effect transistor using an organic semiconductor material.
FIG. 2 is a diagram showing a hysteresis characteristic of a ferroelectric.
FIG. 3 is a diagram showing a relationship between a ferroelectric state and transistor operation.
FIG. 4 is a view showing a chemical formula of an acene-based material.
FIG. 5 is a diagram illustrating a relationship between a voltage-capacitance measurement example and a memory window.
FIG. 6 is a diagram illustrating an example of an intelligent tag.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Gate electrode, 3 ... Ferroelectric layer, 4 ... Source electrode, 5 ... Drain electrode, 6 ... Organic semiconductor layer, I ... IC card, II ... Intelligent tag, 11 ... Antenna, 12 ... CPU, 13: storage element, 14: display element.
Claims (14)
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| JP2002275803A JP2004111856A (en) | 2002-09-20 | 2002-09-20 | Nonvolatile organic semiconductor memory element, its manufacture, and noncontact information controlling and dysplaying device |
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