JP2004094785A - Memory module and auxiliary module for memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory module capable of effectively utilizing a memory region of a memory which rejects access to all memory regions by only a preset number of address signals input from a computer body by permitting access through the computer body to the memory region to which access by only the address signals is rejected, and an auxiliary module for the memory. <P>SOLUTION: A circuit 30 for the memory is provided for inputting the preset number of address signals A0-A11 and a plurality of select signals CS0, CS1 from the computer body, generating a select signal CS for the memory and an additional address signal A12 added to the signals A0-A11 in accordance with the input signals CS0, CS1, and supplying the signal CS as well as the signal A12 and the signals A0-A11 to a 256 Mbit SDRAM (memory), thereby permitting access through the computer body to corresponding data. Thus, access can be gained through the computer body to the data corresponding to the generated additional address signal A12 and the preset number of input address signals A0-A11. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory module and a memory auxiliary module connectable to a computer main body.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a memory module of a computer is expanded by connecting a memory module to a socket (slot) of a computer main body. As the memory module, a 128 Mbyte DIMM (Dual Inline Memory Module) in which eight 128 Mbit (Synchronous Dynamic Random Access Memory) are mounted, or a 256 Mbyte DIMM in which sixteen 128 Mbit SDRAM are mounted are used. Has been. Usually, twelve address signal terminals A0 to A11 of a 128 Mbit SDRAM are provided, and twelve signal lines of a row address (Row Address) and ten signal lines of a column address (Column Address) can be connected. I have. When the address signals A0 to A11 are input from the computer main body, the data of the corresponding address can be read and written in all the 128 Mbit areas of all the SDRAMs.
In the 256 Mbyte DIMM, the SDRAM is divided into two blocks of SDRAM groups to form two banks (BANK). Then, in addition to the address signals A0 to A11, a plurality of chip select signals corresponding to each of a plurality of banks of the SDRAM group to be accessed are inputted, so that the corresponding bank and address are obtained for the entire 256 Mbyte area of the DIMM. Data can be read and written. As described above, by using a plurality of chip select signals for selecting one of the banks, it is possible to increase the memory capacity that can be handled by the computer main body.
Further, there is also known a module for switching a memory to be accessed according to a state of an uppermost address signal input from a computer main body, as disclosed in Japanese Patent No. 3022255 (see Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent No. 3022255 (paragraphs 0014-0054, FIG. 1-8)
[0004]
[Problems to be solved by the invention]
The above-described conventional technology has the following problems.
In recent years, 256-Mbyte DIMMs having eight 256-Mbit SDRAMs have been used. However, in order to access the entire memory area of the 256-Mbit SDRAM, it is necessary to input signals of row addresses A0 to A12 to the SDRAM. Can handle only a 128 Mbit area, which is half of the 256 Mbit of the SDRAM. Even if the module disclosed in Japanese Patent No. 3022255 is used, the same can be said, except that the memory to be accessed is switched according to the state of the highest address signal A11.
[0005]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is intended for a memory area that cannot access the entire memory area only by a predetermined number of address signals input from the computer body, but cannot be accessed only by the same address signal. It is an object of the present invention to provide a memory module and a memory auxiliary module which can be accessed from a computer main body and can effectively use a memory area.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 includes a plurality of select signals indicating a selected state or a non-selected state for each of a predetermined number of address signals and a plurality of memory spaces having a capacity corresponding to the predetermined number of address signals. A standardized memory module that can be connected to a computer that generates a signal. The memory module receives a memory select signal indicating a selected state or a non-selected state and a plurality of address signals greater than the predetermined number of address signals. A memory capable of accessing data corresponding to the plurality of address signals when the memory select signal is in a selected state, and the predetermined number of address signals and a plurality of select signals from the computer main body, The memory select signal is generated based on the signal and the predetermined number of addresses are generated. An additional address signal added to the address signal, and supplying the generated memory select signal and the generated additional address signal and a predetermined number of input address signals to the memory to access the corresponding data by the computer. And a memory circuit that is enabled from the main body.
[0007]
The standardized memory module is connected to the computer main body to enable access to the memory from the computer main body. A predetermined number of address signals and a plurality of select signals indicating a selected state or a non-selected state for each of a plurality of memory spaces having a capacity corresponding to the predetermined number of address signals are input from the computer main body to the memory circuit. You. On the other hand, the memory provided in the present memory module receives a memory select signal indicating a selected state or a non-selected state, and a plurality of address signals greater than the predetermined number of address signals, and selects the memory select signal. , Data corresponding to the plurality of address signals can be accessed.
[0008]
Here, the memory select signal is generated by the memory circuit based on the select signal. An additional address signal added to the predetermined number of address signals is also generated by the memory circuit based on the select signal. Since the generated memory select signal is supplied to the memory, the memory can be accessed when the memory select signal is in the selected state. Since the generated additional address signal is supplied to the memory together with the predetermined number of input address signals, the computer itself can access the data corresponding to the generated additional address signal and the predetermined number of input address signals. It becomes possible.
[0009]
That is, even in a memory in which all memory areas cannot be accessed only by a predetermined number of address signals input from the computer main body, address signals other than the predetermined number of address signals are generated based on the select signal. It becomes possible to access a memory area that cannot be accessed only by a signal from the computer main body. For example, when the computer outputs an address signal that allows only a DRAM of 128 Mbits or less to access the entire memory area, it becomes possible to access a memory area of more than 128 Mbits for a DRAM of 256 Mbits or more. Of course, the present invention is applicable to memories having various memory capacities.
Further, by generating the memory select signal, the number of memories accessible from the computer main body can be increased, so that the memory capacity that can be handled by the computer main body can be increased.
[0010]
Here, only one memory may be provided, or a plurality of memories may be provided. In addition to being capable of writing and reading data, a memory may be capable of only writing data, or may be capable of only reading data. Also corresponds to the accessible of the present invention. Therefore, various memories such as an SDRAM and a ROM can be adopted.
Further, it is preferable that the entire area of the memory can be accessed by adding an additional address signal to the predetermined number of address signals, so that the memory capacity can be effectively used. Therefore, it is not necessary to make the entire area of the memory accessible. Even in this case, by supplying the additional address signal to the memory, it is possible to access a memory area having a larger capacity than a memory space having a capacity corresponding to a predetermined number of address signals.
[0011]
Various configurations are possible for generating the memory select signal. As one example, the invention according to claim 2 is the memory circuit, wherein when any of the plurality of input select signals is in the selected state of the memory space, the memory select signal is set to the selected state of the memory. When all of the plurality of input select signals are in the non-selected state of the memory space, the memory select signal is set to the non-selected state of the memory.
In other words, a state in which one of the plurality of memory spaces is selected by the plurality of select signals, the state in which the memory select signal selects the memory, and a state in which all of the plurality of memory spaces are not selected by the plurality of select signals. As a result, the memory select signal enters a state in which no memory is selected.
[0012]
For example, when the select signal and the memory select signal are in a selected state when low and in a non-selected state when high, a plurality of select signals are input to an AND gate and the output from the same gate is selected for memory. It can be a signal. When the select signal and the memory select signal are in a selected state when high and in a non-selected state when low, a plurality of select signals are input to an OR gate and the output from the gate is selected for memory. It can be a signal. When the state of the selected signal and the state of the non-selected signal are different between the select signal and the memory select signal, the memory select signal can be generated using a NAND gate, a NOR gate, or the like.
[0013]
When the computer body generates two types of select signals indicating a selected state or a non-selected state for each of two memory spaces having a capacity corresponding to the predetermined number of address signals, as in the invention according to claim 3, The memory circuit may be configured so that one of the two types of select signals is input from the computer main body and supplied to the memory as the additional address signal. That is, with a simple configuration, one of the two types of select signals is used as an additional address signal and supplied to the memory.
Of course, when generating three or more types of select signals, it is also possible to generate an additional address signal from a plurality of select signals.
[0014]
Some computer bodies output a signal that causes a memory of a bank not used for power saving to sleep. According to a fourth aspect of the present invention, in the memory, a clock signal having a pulse shape and a memory clock enable signal indicating a valid state or an invalid state of the clock signal input are input, and the clock enable signal is in a valid state. The computer main body is sometimes operable based on the same clock signal, and the computer main body generates a plurality of clock enable signals indicating the valid state or the invalid state of the clock signal input for each of the clock signal and the plurality of memory spaces. The memory circuit inputs the clock signal and the plurality of clock enable signals from the computer main body, generates the memory clock enable signal based on the input plurality of clock enable signals, and generates the memory clock enable signal together with the input clock signal. Supply to the above memory There as formed.
[0015]
That is, a pulse-like clock signal and a plurality of clock enable signals indicating the valid or invalid state of the clock signal input for each of the plurality of memory spaces are input from the computer main body to the memory circuit. On the other hand, the memory receives a clock signal and a memory clock enable signal indicating whether the clock signal input is valid or invalid, and operates based on the clock signal when the clock enable signal is valid. It is possible.
Here, the memory clock enable signal is generated by the memory circuit based on the plurality of clock enable signals. Since the generated memory clock enable signal is supplied to the memory together with the clock signal, the memory can operate when the memory clock enable signal is in the valid state.
[0016]
Various configurations for generating the memory clock enable signal are conceivable. As an example, the invention according to claim 5 is the memory circuit, wherein the memory clock enable signal is set when any of the plurality of input clock enable signals is in a valid state of the clock signal input in the memory space. When the clock signal input of the memory is enabled, and when all of the plurality of input clock enable signals are in the disabled state of the clock signal input of the memory space, the memory clock enable signal is input to the memory clock signal input. In the invalid state.
[0017]
In other words, the memory clock enable signal is in a state in which the clock signal input of the memory is enabled in a state where any one of the clock signal inputs in the plurality of memory spaces is enabled by the plurality of clock enable signals, and the plurality of clock enable signals are enabled. The clock enable signal for the memory is in a state where the clock signal input of the memory is invalidated in a state where the clock signal inputs of all of the plurality of memory spaces are invalidated in the above. Note that the memory clock enable signal can be generated using an OR gate, an AND gate, a NOR gate, a NAND gate, or the like, like the memory select signal.
[0018]
According to a sixth aspect of the present invention, the additional address signal may be a signal capable of indicating an address higher than the address represented by the predetermined number of address signals. . That is, an additional address signal higher than the predetermined number of address signals is generated and supplied to the memory together with the predetermined number of address signals.
Here, the additional address signal may be an uppermost address signal of the plurality of address signals.
[0019]
By the way, even if a memory select signal is not supplied to a memory, by generating an additional address signal from the select signal, it is possible to access from a computer body to a memory area that cannot be accessed only by a predetermined number of address signals. Therefore, it may be configured as in the invention according to claim 7.
That is, a predetermined number of address signals and a select signal indicating a selected state or a non-selected state for each of a plurality of memory spaces having a capacity corresponding to the predetermined number of address signals are input from the computer main body to the memory circuit. You. On the other hand, the memory provided in the present memory module can access a plurality of address signals larger than the predetermined number of address signals and access data corresponding to the plurality of address signals.
[0020]
Here, the additional address signal added to the predetermined number of address signals is generated by the memory circuit based on the select signal. Since the generated address signal is supplied to the memory together with the predetermined number of input address signals, the computer body can access the generated address signal and data corresponding to the predetermined number of input address signals. Become.
That is, even in a memory in which all memory areas cannot be accessed only by a predetermined number of address signals input from the computer main body, address signals other than the predetermined number of address signals are generated based on the select signal. It becomes possible to access a memory area that cannot be accessed only by a signal from the computer main body.
[0021]
Further, even in a memory module before the memory is mounted, by mounting the memory, it becomes possible to access from the computer body to a memory area that cannot be accessed only by a predetermined number of address signals. Therefore, the present invention provides a computer which generates a plurality of select signals indicating a selected state or a non-selected state for each of a predetermined number of address signals and a plurality of memory spaces having a capacity corresponding to the predetermined number of address signals. A memory select signal that is connected to the main body and indicates a selected state or a non-selected state and a plurality of address signals greater than the predetermined number of address signals are input, and the plurality of addresses are selected when the memory select signal is in the selected state. In order to enable access from the computer main body to a memory capable of accessing data corresponding to the signal, the predetermined number of address signals and a plurality of select signals are input from the computer main body, and the input select signal The memory select signal is generated based on the Generating an additional address signal added to the address signal, and supplying the generated memory select signal and the generated additional address signal and a predetermined number of input address signals to the memory to access the corresponding data by the computer; It is configured to be possible from the main body.
[0022]
According to a ninth aspect of the present invention, there is provided a computer main body for generating a select signal indicating a selected state or a non-selected state for each of a predetermined number of address signals and a plurality of memory spaces having a capacity corresponding to the predetermined number of address signals. When a plurality of address signals that are connected and input to a plurality of address signals greater than the predetermined number of address signals are input to enable access from the computer main body to the memory capable of accessing the corresponding data, the computer main body And generates an additional address signal added to the predetermined number of address signals based on the input select signal, and stores the additional address signal and the input predetermined number of address signals in the memory. Access to the corresponding data by supplying the computer It is constituted to enable the body.
That is, the present invention is effective even for a memory auxiliary module having no memory. It is also possible to make the configuration described in claims 2 to 6 correspond to the auxiliary module for memory.
[0023]
【The invention's effect】
As described above, according to the first, seventh to ninth aspects of the present invention, even if the memory cannot access the entire memory area only by a predetermined number of address signals input from the computer main body, The memory area that cannot be accessed only by the address signal can be accessed from the computer main body, and the memory area can be effectively used.
According to the second aspect of the invention, it is possible to provide an example of appropriately generating a memory select signal.
According to the third aspect, an additional address signal can be generated with a simple configuration.
[0024]
According to the invention according to claim 4, when a plurality of clock enable signals are output from the computer main body to a plurality of memory spaces, it is possible to appropriately access the memory.
According to the invention of claim 5, it is possible to provide an example of appropriately generating a clock enable signal for memory.
According to the invention according to claim 6, the additional address signal can be generated with a simple configuration.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in the following order.
(1) Configuration of memory module:
(2) Function of memory module:
(3) Modification:
[0026]
(1) Configuration of memory module:
FIG. 1 is a front view showing the appearance of a memory module 10 according to one embodiment of the present invention. In addition, when explaining the positional relationship of up, down, left, and right, the description will be made with reference to FIG.
In the memory module 10, eight 256 Mbit SDRAMs 20, a plurality of gate ICs 31, a resistance circuit (not shown), and the like are mounted on a printed board 10a having a standardized shape. 168-pin terminals 40 each having 84 pins are formed on the lower edge of the substrate 10a on the front side and the rear side. The memory module 10 is an additional memory card for a desktop personal computer (PC), and can insert a 168-pin terminal 40 conforming to the DIMM specification into a connector (slot) 91 of a motherboard 90 of the desktop PC (computer body). It is. The connector 91 has 168 conductive portions corresponding to the arrangement of the terminals 40. The connector 91 has a shape in which a standardized 168-pin DIMM can be mounted. When the memory module 10 is inserted into the connector 91 from above, the memory module 10 can be attached substantially vertically to the motherboard 90 and can be connected to a desktop PC. As a result, the memory of the desktop PC can be increased.
[0027]
The desktop PC to which the memory module 10 is connected is not the latest model, but handles 256 Mbytes of memory capacity as two banks of 128 Mbytes each. Therefore, for example, the configuration is suitable for adding a 256 Mbyte DIMM on which 16 128 Mbit SDRAMs are mounted.
FIG. 2 shows a part of a wiring correspondence between a connector 91 of a desktop PC and a virtual memory space formed by using a conventional 256 Mbyte DIMM on which 16 128 Mbit SDRAMs are mounted. ing.
In the figure, 128M-bit virtual memories R11 to R18 and R21 to R28 are divided into eight blocks each of which is a group of an SDRAM group, and have two banks. Here, the upper SDRAM group in the figure is called BANK1, and the lower SDRAM group is called BANK2. The connector 91 has connection portions for various signal lines such as CLK, RAS, CAS, A0 to A11, D0 to D63, CS0, CS1, CKE1, and CKE2.
[0028]
Here, the CLK signal means a clock signal, and the PC generates a pulse-like clock signal of a predetermined frequency and supplies it to the CLK signal line.
A RAS (Row Address Strobe) signal means a signal for transmitting a timing of giving a row address to the SDRAM, and a CAS (Column Address Strobe) signal means a signal for transmitting a timing of giving a column address to the SDRAM. I have. The A0 to A11 signals mean a predetermined number (12 types) of address signals that specify addresses in the memory space. In a DIMM mounted with a 128 Mbit SDRAM capable of inputting / outputting 8-bit data, 12 types of address signals are supplied to the SDRAM as row addresses and 10 types of column signals are supplied as column addresses. The PC generates the RAS, CAS, and A0 to A11 signals and supplies them to the signal lines in accordance with the CLK signal.
[0029]
The D0 to D63 signals mean 64 types of data signals. The 64 data signal lines are divided into eight sets of eight data lines, and eight data signal lines are connected to each SDRAM in the SDRAM group.
The CS0 and CS1 signals are chip select signals (select signals) for selecting an SDRAM group to be accessed, and are signals indicating a selected state or a non-selected state for each of the SDRAM groups. This signal is a negative logic signal in which the selected state of the SDRAM group is represented by L (low) and the unselected state is represented by H (high). The CS0 and CS1 signals do not go low at the same time, and only one of them goes low when accessing the SDRAM.
[0030]
The CKE1 and CKE2 signals are clock enable signals indicating the valid state or invalid state of the CLK signal input for each of the two SDRAM groups, and are positive logic signals in which the valid state of the clock signal input is H and the invalid state is L. . The PC generates the CS0, CS1, CKE1, and CKE2 signals and supplies them to the signal lines in accordance with the CLK signal.
In addition to these, the connector 91 is also provided with connection portions such as signal lines for two types of extended address signals BA0 and BA1 and power supply lines.
The CLK, RAS, CAS, A0 to A11, and D0 to D63 signals are supplied to both BANK1 and BANK2, the CS0 and CKE0 signals are supplied to BANK1, and the CS1 and CKE1 signals are supplied to BANK2.
[0031]
FIG. 3 shows a terminal of a conventional 128 Mbit SDRAM corresponding to a virtual memory in each SDRAM group and a main part of a signal line connected to the terminal. Note that the terminal names are described in the SDRAM and the signal line names are described outside the SDRAM.
The SDRAM is a memory to which a select signal and signals A0 to A11 are input and data corresponding to the signals A0 to A11 can be accessed when the select signal is L (selected state). When the clock enable signal is input to the CKE terminal and the clock enable signal is H (valid state), operation is possible based on the CLK signal.
[0032]
For the virtual memory R11 in BANK1, CLK, RAS, CAS, A0 to A11, and D0 to D7 signal lines are respectively connected to a clock signal input terminal CLK, a row address signal input terminal RAS, a column address signal input terminal CAS, It is connected to the address signal input terminals A0 to A11 and the data signal input / output terminals D0 to D7, and the specification is such that corresponding signals are input and output from the terminals. It is to be noted that data signal input / output terminals D0 to D7 for different virtual memories R12 to R18 in the same BANK1 are connected to eight different data signal lines. The CS0 and CKE0 signal lines are connected to a chip select signal input terminal CS and a clock enable signal input terminal CKE, respectively. A chip select signal indicating a selected state or a non-selected state for BANK1 is input to the CS terminal. The specification is such that a clock enable signal indicating the valid state or invalid state of the clock signal input is input to the CKE terminal. The virtual memories R12 to R18 also have the specifications that the same CS0 and CKE0 signal lines are connected.
[0033]
On the other hand, the same signal lines as those of the virtual memory R11 are connected to the virtual memory R21 in the BANK2 for the CLK, RAS, CAS, A0 to A11, and D0 to D7 terminals. The CS1 and CKE1 signal lines are connected to the CS and CKE terminals, respectively. A chip select signal indicating a selected state or a non-selected state is input to the CS terminal for BANK2, and the clock signal input is enabled or disabled for BANK2. The specification is such that a clock enable signal indicating a state is input to the CKE terminal. The virtual memories R22 to R28 also have the specification that the same CS1 and CKE1 signal lines are connected.
The 128 Mbit SDRAM also has BA0 and BA1 terminals to which an extended address signal can be input. Accordingly, a total of 24 bits, ie, 12 bits as a row address, 10 bits as a column address, and 2 bits as an extension address, are input and output as 8-bit data corresponding to the address. , 128 Mbits of memory space.
[0034]
FIG. 4 is a timing chart showing a state of a signal output from the connector 91 by the desktop PC.
The desktop PC outputs a clock enable signal so that the memory of a bank not used for power saving is put to sleep. When accessing the SDRAM of BANK1, the CKE0 signal is raised from L to H in order to release the SDRAM from the sleep state (timing t1). When accessing the SDRAM, the CS0 signal falls from H to L (timing t2). When ending the access of the BANK1 to the SDRAM, the CS0 signal rises from L to H (timing t3). When the SDRAM of BANK1 is put into the sleep state, the CKE0 signal falls from H to L, and when the SDRAM of BANK2 is accessed, the CKE1 signal rises from L to H to release the SDRAM from the sleep state (timing t4). . When accessing the SDRAM of BANK2, the CS1 signal falls from H to L (timing t5), and when ending the access to the SDRAM, the CS1 signal rises from L to H (timing t6). To put the SDRAMs of both BANK1 and BANK2 into the sleep state, the signals CKE0 and CKE1 are set to the L state.
[0035]
As described above, this desktop PC is provided with two select signals for each of two memory spaces (128 Mbits × 8) corresponding to a predetermined number of address signals so that the CS0 and CS1 signals do not become L at the same time. Generate Also, two clock enable signals are generated for each of the two memory spaces so that the CKE0 and CKE1 signals do not become H at the same time.
[0036]
In recent years, 256-Mbyte DIMMs having eight 256-Mbit SDRAMs have been used. FIG. 5 shows a terminal of a 256 Mbit SDRAM and a main part of a signal line connectable to the terminal when the desktop PC is used.
The 256 Mbit SDRAM receives a memory select signal and a plurality of address signals A0 to A12 which are larger than a predetermined number of address signals A0 to A11, and outputs a signal A0 to A0 when the memory select signal is L (selected state). This is a memory from which data corresponding to the A12 signal can be accessed. When the clock enable signal for memory is input to the CKE terminal and the clock enable signal for memory is H (valid state), operation is possible based on the CLK signal.
[0037]
As shown in the figure, signals are directly input to CLK, RAS, CAS, and D0 to D7 terminals because corresponding signals exist. However, as for the address signal input terminal, since there is no signal corresponding to the A12 terminal, only the 128 Mbit area which is half of the memory capacity can be accessed. In addition, there is no signal corresponding to the CS and CKE terminals, and when the CS0 and CSK0 signals or the CS1 and CSK1 signals are input, only the 128 Mbit area can be accessed after all, and only the address signals A0 to A11 can be accessed. The computer that does not output data can handle only half the area of the 256 Mbit SDRAM.
The memory module 10 generates an address signal (additional address signal) of A12 higher than the A0 to A11 signals by a memory circuit to be described later. It is possible to access.
[0038]
FIG. 6 is a circuit diagram showing a main part of a circuit of the memory module 10. The 256 Mbit SDRAM 20 shown in the figure represents one of the eight SDRAMs 20 shown in FIG. 1 (for example, the leftmost SDRAM). In practice, a similar circuit is formed for all eight SDRAMs 20. The only difference between the SDRAMs 20 is the type of data signal line connected to the D0 to D7 terminals, and the same data signal line is connected to the remaining terminals. For simplicity of description, only the names of the signals to be input and output are described for the RAS, CAS, A0 to A11, and D0 to D7 terminals. It is connected to the.
[0039]
In the figure, a memory auxiliary module 12 is composed of a memory circuit 30 and a terminal 40. The memory circuit 30 includes an AND gate 31a and an OR gate 31b. The gates 31a and 31b are provided in the gate IC 31.
The CS0 terminal 41a and the CS1 terminal 41b in the terminal 40 are connected to the two input terminals of the AND gate 31a, respectively. The CS terminal of the SDRAM 20 is connected to the output terminal of the AND gate 31a. Then, the logical product of the CS0 and CS1 signals, which are the select signals for the 128 Mbit SDRAM, is supplied to the CS terminal of the 256 Mbit SDRAM 20 as the memory select signal CS.
That is, the memory module 10 changes the memory select signal CS to L (the selection state of the 256 Mbit SDRAM) when either the input CS0 or CS1 signal is L (the selection state of the memory space of the 128 Mbit virtual memory). When all of the input CS0 and CS1 signals are H (the non-selected state of the memory space of the 128-Mbit virtual memory), the CS signal is set to H (the non-selected state of the 256-Mbit SDRAM). In this circuit, a plurality of select signals are input, and a memory select signal can be appropriately generated based on the input plurality of select signals.
[0040]
In addition, CS1 is connected to the A12 terminal of the SDRAM 20. That is, when the CS1 signal is L, the A12 signal input from the A12 terminal is “0”, and when the CS0 signal is L, the CS1 signal is H and the A12 signal input from the A12 terminal is “1”. It becomes. In this circuit, a plurality of select signals are input, and based on the input select signals, an additional address signal A12 added to a predetermined number of address signals A0 to A11 can be generated with a simple configuration. The additional address signal A12 is a signal capable of representing an address higher than the address represented by the signals A0 to A11. Then, as shown in FIG. 7, half of the memory area of the 256 Mbit SDRAM 20 is assigned to the CS0 signal = L, that is, the BANK1, and the other half of the memory area is assigned to the CS1 signal = L, that is, the BANK2. Note that the same reference numerals are given to the memory areas allocated corresponding to the possible memories R11 to R18 and R21 to R28 described above. As shown in the figure, for example, it can be seen that the virtual memory R11 assigned to BANK1 and the virtual memory R21 assigned to BANK2 are provided inside the same 256 Mbit SDRAM 20 at the left end. In this manner, the same memory area of the SDRAM can be selectively used according to the select signal, and the present memory module can be treated as a pseudo-two-bank memory module using a 128 Mbit SDRAM.
When the A12 signal is generated from the two types of select signals CS0 and CS1 and input to the A12 terminal, the CS0 signal may be input to the A12 terminal instead of inputting the CS1 signal to the A12 terminal. .
[0041]
As described above, the memory circuit 30 receives the predetermined number of address signals A0 to A11 and the plurality of select signals CS0 and CS1 from the desktop PC, and generates the memory select signal CS and the additional address signal A12. , CS signal, an additional address signal A12, and a predetermined number of address signals A0 to A11 are supplied to the 256 Mbit SDRAM 20, thereby enabling access to corresponding data from the desktop PC.
Some desktop PCs output a plurality of clock enable signals that cause a 128 Mbit SDRAM in an unused bank to sleep. Therefore, the memory circuit 30 receives the CLK signal and the plurality of clock enable signals CKE0 and CKE1 from the desktop PC, generates the memory clock enable signal CKE based on the input CKE0 and CKE1 signals, and generates the SDRAM 20 together with the CLK signal. To supply.
[0042]
The CLK terminal of the SDRAM 20 is connected to the CLK terminal 41 c of the terminal 40. Therefore, the memory circuit 30 receives the CLK signal from the desktop PC and supplies it to the SDRAM 20.
The CKE0 terminal 41d and the CKE1 terminal 41e in the terminal 40 are connected to the two input terminals of the OR gate 31b, respectively. The output terminal of the OR gate 31b is connected to the CKE terminal of the SDRAM 20. Then, the logical sum of the CKE0 and CKE1 signals for the 128 Mbit SDRAM is supplied to the CKE terminal of the 256 Mbit SDRAM 20 as a CKE signal. That is, the memory module 10 changes the CKE signal to H (the clock signal of the 256 Mbit SDRAM) when one of the input CKE0 and CKE1 signals is H (the valid state of the clock signal input in the memory space of the 128 Mbit virtual memory). When the input CKE0 and CKE1 are all L (the clock signal input of the memory space of the 128 Mbit virtual memory is invalid), the CKE signal is set to L (the clock signal input of the 256 Mbit SDRAM is invalid). State).
[0043]
(2) Function of memory module:
Next, the operation of the memory module 10 will be described with reference to the timing chart shown in FIG. The timings t1 to t7 are the same as those in FIG.
When the CKE0 signal rises from L to H (timing t1) and the virtual memory of BANK1 is released from the sleep state, H is input to one of the input terminals of the OR gate 31b, and is output from the OR gate 31b. The CKE signal becomes H (valid state). Also, even if the CKE0 signal falls from H → L and the CKE1 signal rises from L → H (at timing t4), and the virtual memory of BANK2 is released from the sleep state, it remains connected to one of the input terminals of the OR gate 31b. Since H is input, the CKE signal output from the OR gate 31b becomes H (valid state). On the other hand, when the CKE1 signal falls from H to L (timing t7) to put the virtual memories of both BANKs 1 and 2 to sleep, L is input to both input terminals of the OR gate 31b, so that the output from the OR gate 31b is output. The CKE signal is L (invalid state).
[0044]
Then, in the 256 Mbit SDRAM 20, L is input to the CKE terminal only when the virtual memories of both the BANKs 1 and 2 are put into the sleep state, and the CLK signal input becomes invalid. On the other hand, when one of the virtual memories BANK1 and BANK2 is released from the sleep state, H is input to the CKE terminal, the CLK signal input becomes valid, and operation is performed based on the input CLK signal.
As described above, when a plurality of clock enable signals are output from the desktop PC to the memory space of the plurality of 128 Mbit virtual memories, it is possible to appropriately access the 256 Mbit SDRAM.
[0045]
When the CS0 signal falls from H to L while the CKE0 signal is at H (timing t2) and the virtual memory of BANK1 is accessed, L is input to one of the input terminals of the AND gate 31a. The CS signal output from the gate 31a becomes L (selected state). At this time, since the CS1 signal is H, the A12 signal becomes H meaning 1 and H is input to the A12 terminal of the SDRAM 20.
Further, even when the CS1 signal falls from H to L when the CKE1 signal is H (timing t5) and the virtual memory of BANK2 is accessed, L is input to one of the input terminals of the AND gate 31a. Therefore, the CS signal output from the AND gate 31a becomes L (selected state). At this time, since the CS1 signal is L, the A12 signal becomes L meaning 0, and L is input to the A12 terminal of the SDRAM 20.
[0046]
Then, when the 256 Mbit SDRAM 20 is in a state of accessing the virtual memories of both BANK 1 and 2 from the desktop PC, L is input to the CS terminal and can be accessed from the desktop PC.
Here, the A12 signal becomes 1 when the virtual memory of BANK1 is accessed, and the A12 signal becomes 0 when the virtual memory of BANK2 is accessed. It is possible to access data of 256 Mbits corresponding to the number of address signals A0 to A11.
[0047]
As described above, even in a 256 Mbit memory in which only a predetermined number of address signals A0 to A11 input from the computer main unit can access a memory area of 128 Mbits, additional addresses other than the A0 to A11 signals are generated based on the select signal. Since the signal A12 is generated, the memory area that could not be accessed conventionally can be accessed from the computer main body, and the memory area can be used effectively. As a result, even though the memory module uses a 256 Mbit SDRAM, it can be accessed from the computer main body as if it were a memory module having a two-bank configuration using a 128 Mbit SDRAM. At present, 256 Mbit SDRAMs have become the mainstream of SDRAMs, and it is becoming difficult to obtain 128 Mbit SDRAMs. However, the present invention enables effective use of a memory module equipped with 256 Mbit SDRAMs even in a computer that is not the latest model. It can be used for
Further, by generating the memory select signal CS from the plurality of select signals CS0 and CS1, the number of memories accessible from the computer main body can be increased, so that the memory capacity that can be handled by the computer main body can be increased. It is possible.
[0048]
(3) Modification:
Various modifications of the memory module of the present invention are conceivable.
The above-described memory module 10 is a DIMM without an ECC (Error Correction Code). However, a memory module with an ECC only increases the memory for the ECC, and the present invention is applicable. Of course, a SIMM or the like may be used instead of the DIMM.
The SDRAM also has a memory having 16 data signal input / output terminals. Even if such a memory is a memory that can input a plurality of address signals larger than a predetermined number of address signals generated by the computer main body, the memory area can be effectively used by applying the present invention. Becomes possible. Of course, the present invention can be applied to memories other than eight and sixteen data signal input / output terminals. Further, the present invention is applicable to a ROM or the like that can only read data.
Further, the present invention can be applied to a computer other than a computer that can handle up to a 128-Mbit memory using only a predetermined number of address signals. For example, in the case of a computer body capable of handling up to 64 Mbit memory, by applying the present invention, it is possible to handle 128 Mbit memory, and as described later, a memory having a memory capacity of 256 Mbit or more. Can also be handled. In addition, in the case of a computer main body that can handle up to a 256 Mbit memory, by applying the present invention, a memory having a memory capacity of 512 Mbit or more can be handled.
[0049]
When the select signal and the memory select signal are of positive logic, an OR gate 32a may be used instead of the AND gate 31a as shown in FIG. Then, when either the CS0 or CS1 signal is H (selected state), the memory select signal CS becomes H (selected state), and the SDRAM can be accessed.
When the clock enable signal and the memory clock enable signal have negative logic, an AND gate 32b may be used instead of the OR gate 31b as shown in FIG. Then, when one of the CKE0 and CKE1 signals is L (valid state), the CKE signal becomes L (valid state), and the SDRAM can operate based on the CLK signal.
[0050]
Further, the present memory module can be operated without supplying a memory select signal to the memory mounted on the memory module of the present invention. When the computer generates two types of select signals for each of two memory spaces with the capacity corresponding to the predetermined number of address signals, the memory select signal is not generated and the CS terminal of the mounted memory is always selected. It may be set as. Of course, the memory only needs to be able to access a corresponding data by inputting a plurality of address signals more than the predetermined number of address signals, and it is not necessary to provide the CS terminal.
In this case, the memory circuit receives a predetermined number of address signals and a select signal from the computer main body, generates an additional address signal added to the predetermined number of address signals based on the input select signal, and generates the additional address signal. A signal and a predetermined number of input address signals may be supplied to the memory to enable access to corresponding data from the computer main body. In the above example, by supplying one of the two types of select signals input from the computer body to the memory as an additional address signal, the memory area of the same memory can be selectively used according to the select signal. Can be used effectively.
[0051]
The additional address signal may be other than the address signal representing the highest address that can be input to the memory. FIG. 10 is a block diagram showing a main part of a signal input to a 256 Mbit SDRAM mounted on a memory module according to another modification. When the A11 and A12 terminals are not used for column address input but are used only for row address input, the A0 to A10 signals input from the terminals are input to the A0 to A10 terminals of a 256 Mbit SDRAM, and the A11 signal is input to the 256 Mbit SDRAM. The signal may be input to the A12 terminal and the CS1 signal may be input to the A11 terminal as an additional address signal. When the A10 to A12 terminals are SDRAMs used only for row address input, the A0 to A9 signals input from the 168 pin terminals are input to the A0 to A9 terminals of the SDRAM, and the A10 and A11 signals are respectively transmitted to the A11 of the SDRAM. , A12 terminal and the CS1 signal may be input to the A10 terminal as an additional address signal. Of course, when the A0 terminal is used only for the row address input, the CS1 signal input from the 168-pin terminal may be input to the A0 terminal as an additional address signal.
[0052]
Further, a plurality of additional address signals may be generated from three or more types of select signals for selecting three or more banks. FIG. 11 is a circuit diagram showing a main part of a circuit of a memory module according to another modification.
This memory module is a 512 Mbyte DIMM on which eight 512 Mbit SDRAMs are mounted. The 512 Mbit SDRAM is capable of inputting 14 types of address signals A0 to A13, two types more than the predetermined number of address signals A0 to A11 input from the desktop PC, and accesses the entire memory area of the SDRAM. This requires two more types of address signals. The 512 Mbit SDRAM shown in the figure is representative of one of the eight SDRAMs.
On the other hand, a desktop PC will be described as an example in which a memory capacity of 512 Mbytes is handled as four banks of 128 Mbytes.
[0053]
In the figure, the memory circuit 50 includes AND gates 51a to 51d and OR gates 51e to 51g.
The two input terminals of the AND gate 51a are connected to the CS0 and CS1 terminals in the 168 pin terminal 40, respectively, and the two input terminals of the AND gate 51b are connected to the CS2 and CS3 terminals in the 168 pin terminal 40, respectively. I have. The output terminals of the AND gates 51a and 51b are connected to the two input terminals of the AND gate 51c, respectively. The output terminal of the AND gate 51c is connected to the CS terminal of the SDRAM. That is, the memory module changes the memory select signal CS to L (selection of the 512 Mbit SDRAM) when any of the plurality of input select signals CS0 to CS3 is L (selection state of the memory space of the 128 Mbit virtual memory). State), and when all of the input CS0 to CS3 signals are H (the non-selection state of the memory space of the 128 Mbit virtual memory), the CS signal is set to H (the 512 Mbit SDRAM is not selected).
[0054]
The output terminal of the AND gate 51b is connected to the A13 terminal of the SDRAM. The CS1 and CS3 terminals in the terminal 40 are connected to the two input terminals of the AND gate 51d, respectively. The output terminal of the AND gate 51c is connected to the A12 terminal of the SDRAM.
That is, as shown in FIG. 12, when the CS0 to CS3 signals are 0, 1, 1, 1 in order, the A13 and A12 signals are 1, 1 respectively, and the CS0 to CS3 signals are 1, 0, 1, 1 in order. At some point, the A13 and A12 signals are 1, 0, respectively. When the CS0 to CS3 signals are 1,1,0,1 in order, the A13 and A12 signals are 0,1, respectively. When the CS0 to CS3 signals are 1,1,1,0 in order, the A13 and A12 signals are Each becomes 0,0. As described above, since the combination of the signals A13 and A12 is different when the signals CS0 to CS3 which are L are different, a plurality of select signals are input in the same circuit, and a predetermined number of address signals are determined based on the input select signals. Additional address signals A12 and A13 added to A0 to A11 can be generated. As a result, 1/4 of the memory area of the 512 Mbit SDRAM 20 is assigned to CS0 to CS3 signals = L, that is, BANK1 to BANK4.
[0055]
When the A13 signal is generated and input to the A13 terminal, the logical AND of the CS0 and CS1 signals may be input instead of the logical AND of the CS2 and CS3 signals. When generating the A12 signal and inputting it to the A12 terminal, instead of inputting the logical AND of the CS1 and CS3 signals, the logical AND of the CS0 and CS2 signals may be input.
Even in such a memory circuit 50, a predetermined number of address signals A0 to A11 and a plurality of select signals CS0 to CS3 are input from a desktop PC, and a memory select signal CS and additional address signals A12 and A13 are input. By supplying the CS signal, additional address signals A12 and A13, and a predetermined number of address signals A0 to A11 to the 512 Mbit SDRAM, it is possible to access the corresponding data in the entire memory area from the desktop PC. .
[0056]
The two input terminals of the OR gate 51e are connected to the CKE0 and CKE1 terminals in the terminal 40, respectively, and the two input terminals of the OR gate 51f are connected to the CKE2 and CKE3 terminals in the terminal 40, respectively. The output terminals of the OR gates 51e and f are connected to the two input terminals of the OR gate 51g, respectively. The output terminal of the OR gate 51g is connected to the CKE terminal of the SDRAM. That is, the memory module changes the memory clock enable signal CKE to H when any of the plurality of input clock enable signals CKE0 to CKE3 is H (the clock signal input in the memory space of the 128 Mbit virtual memory is valid). (When the clock signal input of the 512 Mbit SDRAM is valid), and when all of the input CKE0 to CKE3 signals are L (invalid state of the clock signal input in the memory space of the 128 Mbit virtual memory), the CKE signal is changed to L (512M Bit SDRAM clock signal input is invalid). Therefore, when a plurality of clock enable signals are output from the desktop PC to the memory space of the plurality of 128 Mbit virtual memories, the 512 Mbit SDRAM can be appropriately made accessible.
[0057]
Of course, if the computer itself handles three banks of 128 Mbytes each, the CS3 and CKE3 signals will not be input to the memory module, but of the 512 Mbit SDRAM using the circuit shown in FIG. It is possible to use a memory area of 128 × 3 = 384 Mbits. In this case, the entire memory area of the 512 Mbit SDRAM is not used, but a wider area than the 128 Mbit memory area accessible only by a predetermined number of address signals A0 to A11 can be handled from the computer main body. Therefore, the memory area of the 512 Mbit SDRAM can be used effectively.
[0058]
Even when a 1G (gigabit) SDRAM capable of inputting A0 to A14 signals is mounted on the memory module, the computer body can generate a predetermined number of address signals A0 to A11 and eight types of select signals CS0 to CS7. Then, the present invention can be applied. At this time, the memory circuit inputs the A0 to A11 signals and the CS0 to CS7 signals from the computer main body, generates the memory select signal CS and the additional address signals A12 to A14, and outputs the CS signal and the additional address signal A12. A14 to A14, by supplying a predetermined number of address signals A0 to A11 to the 1 Gbit SDRAM, it is possible to access the corresponding data in the entire memory area from the desktop PC. In addition, the memory clock enable signal CKE can be generated by inputting eight types of clock enable signals CKE0 to CKE7.
[0059]
Further, even in a memory module before the memory is mounted, by mounting the memory, a memory area that cannot be accessed only by a predetermined number of address signals can be accessed from the computer main body. Therefore, as shown in FIG. 6, the present invention is effective even with the memory auxiliary module 12 except for the SDRAM 20 from the memory module 10. Of course, the auxiliary module for memory may include a memory socket for mounting the memory, or may have a shape in which the memory can be soldered.
As described above, according to the present invention, according to various aspects, even if a memory cannot access the entire memory area only by a predetermined number of address signals input from the computer main body, the memory area cannot be accessed only by the same address signal. Can be accessed from the computer main body, and a memory module and a memory auxiliary module that can effectively use a memory area can be provided.
[Brief description of the drawings]
FIG. 1 is a front view showing the appearance of a memory module according to an embodiment of the present invention.
FIG. 2 is a diagram showing a part of a wiring correspondence between a connector of a desktop PC and a conventional 128 Mbit SDRAM.
FIG. 3 is a diagram showing a terminal of a conventional 128 Mbit SDRAM in each SDRAM group and a main part of a signal line connected to the terminal.
FIG. 4 is a timing chart illustrating a state of a signal output from a connector by a desktop PC.
FIG. 5 is a diagram showing a main part of a 256 Mbit SDRAM terminal and a signal line connectable to the terminal when the desktop PC is used.
FIG. 6 is a circuit diagram showing a main part of a circuit of the memory module.
FIG. 7 is a diagram schematically showing a state of a 128 Mbit memory space allocated to a 256 Mbit memory area;
FIG. 8 is a timing chart showing states of various signals.
FIG. 9 is a circuit diagram showing a main part of a circuit of a memory module according to a modification.
FIG. 10 is a block diagram showing a main part of a signal input to an SDRAM mounted on a memory module according to another modification.
FIG. 11 is a circuit diagram showing a main part of a circuit of a memory module according to another modification.
FIG. 12 is a table showing the correspondence between the states of CS0 to CS3 signals and A12 and A13 signals.
[Explanation of symbols]
10 ... Memory module
10a ... Printed circuit board
12 ... Auxiliary module for memory
20 ... 256 Mbit SDRAM
30 ... Memory circuit
31 ... Gate IC
31a… AND gate
31b… OR gate
40 ... 168 pin terminal
50 ... Memory circuit
90 ... Motherboard
91… Connector
R11 to R18, R21 to R28 ... virtual memory

Claims (9)

A standardized memory connectable to a computer body that generates a plurality of select signals indicating a selected state or a non-selected state for each of a predetermined number of address signals and a plurality of memory spaces each having a capacity corresponding to the predetermined number of address signals. Module
When a memory select signal indicating a selected state or a non-selected state and a plurality of address signals greater than the predetermined number of address signals are input and the memory select signal is in a selected state, data corresponding to the plurality of address signals Accessible memory,
The predetermined number of address signals and a plurality of select signals are input from the computer main body, and based on the input select signals, the memory select signal is generated and an additional address signal added to the predetermined number of address signals is generated. A memory circuit that enables the computer body to access corresponding data by supplying the generated memory select signal and the generated additional address signal and the input predetermined number of address signals to the memory. A memory module, comprising: The memory circuit sets the memory select signal to the memory select state when any of the input select signals is in the memory space select state, and all of the input plural select signals are in the memory select state. 2. The memory module according to claim 1, wherein the memory select signal is set to a non-selection state of the memory when the memory space is in a non-selection state. The computer body generates two types of select signals indicating a selected state or a non-selected state for each of two memory spaces having a capacity corresponding to the predetermined number of address signals,
3. The memory circuit according to claim 1, wherein the memory circuit inputs one of the two types of select signals from the computer main body and supplies the selected address signal to the memory as the additional address signal. Memory module. The memory is operable based on the clock signal when the clock enable signal is in a valid state by inputting a pulsed clock signal and a memory clock enable signal indicating a valid state or an invalid state of the clock signal input. And
The computer main body generates a plurality of clock enable signals indicating the valid state or the invalid state of the clock signal input for each of the clock signal and the plurality of memory spaces,
The memory circuit receives the clock signal and the plurality of clock enable signals from the computer main body, generates the memory clock enable signal based on the input plurality of clock enable signals, and generates the memory clock enable signal together with the input clock signal. The memory module according to claim 1, wherein the memory module is supplied to a memory. The memory circuit sets the memory clock enable signal to the valid state of the clock signal input of the memory when any of the plurality of input clock enable signals is in the valid state of the clock signal input in the memory space, The memory clock enable signal is set to an invalid state of the clock signal input of the memory when all of the plurality of input clock enable signals are in an invalid state of the clock signal input of the memory space. 5. The memory module according to 4. 6. The signal according to claim 1, wherein the additional address signal is a signal capable of representing an address higher than an address represented by the predetermined number of address signals. An auxiliary module for a memory according to claim 1. A standardized memory module connectable to a computer body that generates a select signal indicating a selected state or a non-selected state for each of a predetermined number of address signals and a plurality of memory spaces having a capacity corresponding to the predetermined number of address signals. So,
A memory capable of accessing a corresponding data by inputting a plurality of address signals greater than the predetermined number of address signals;
The predetermined number of address signals and the select signal are input from the computer main body, an additional address signal added to the predetermined number of address signals is generated based on the input select signal, and the additional address signal and the input predetermined number are generated. A memory circuit that supplies access to corresponding data from the computer main body by supplying the address signal to the memory. A selected number of address signals and a plurality of memory signals having a capacity corresponding to the predetermined number of address signals are connected to a computer main body that generates a plurality of select signals indicating a selected state or a non-selected state, and are connected to a selected state or a non-selected state. When a memory select signal indicating a state and a plurality of address signals greater than the predetermined number of address signals are input, data corresponding to the plurality of address signals can be accessed when the memory select signal is in a selected state. To make the memory accessible from the computer itself,
The predetermined number of address signals and a plurality of select signals are input from the computer main body, and based on the input select signals, the memory select signal is generated and an additional address signal added to the predetermined number of address signals is generated. By supplying the generated memory select signal, the generated additional address signal, and the input predetermined number of address signals to the memory, the computer can access the corresponding data from the memory. Auxiliary module for memory. A predetermined number of address signals and a plurality of memory spaces each having a capacity corresponding to the predetermined number of address signals are connected to a computer main body that generates a select signal indicating a selected state or a non-selected state. In order to enable access from the same computer to a memory that can access the corresponding data by inputting many address signals,
The predetermined number of address signals and the select signal are input from the computer main body, an additional address signal added to the predetermined number of address signals is generated based on the input select signal, and the additional address signal and the input predetermined number are generated. A memory auxiliary module, wherein access to corresponding data is enabled from the computer main body by supplying the address signal to the memory.

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