JP2004079645A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve operation speed and reduce consumption power by reducing a gate parasitic capacitance. <P>SOLUTION: By an ordinary process using an SOI substrate, an element isolation region 4, a gate G, a source/drain (S/D) and silicide of a MOS type SOI semiconductor device manufacture are formed, and an interlayer insulating film 7 is deposited (a). In order to exfoliate a Si substrate Al, H ions are implanted (b). After the upper and lower sides are reversed and the interlayer insulating film 7 side is stuck on the other Si substrate B, the Si substrate Al of the SOI substrate is exfoliated and removed (c). An interlayer insulating film 8 is added. A hole is made in the film 8, and S/D contacts 11, 12 are connected with a gate G side of an active region layer 3a and the opposite side. The gate G and the S/D contacts 11, 12 are arranged interposing the active region layer 3a between them, so that capacitance between the gate/contact becomes almost zero. As the result, the gate parasitic capacitance decreases about 10%. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a capacitance between a gate and a contact is substantially zero and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor device such as an SOIFET, a source / drain, a body, and the like are formed in a top Si layer of an SOI substrate, and a gate is provided above the body via an insulating film. A gate parasitic capacitance exists between the gate and the source / drain and between the gate and the contact due to its structure. This capacity reduces the operating speed of the semiconductor device and increases power consumption (CV ² ). Therefore, in recent semiconductor devices, an SOI semiconductor device formed on an SOI substrate, which can reduce the parasitic capacitance of a conventional semiconductor device and improve the capability, has become increasingly important. .
[0003]
[Problems to be solved by the invention]
On the other hand, with the miniaturization of semiconductor devices, the ratio of the local wiring in the LSI circuit to the gate-contact capacitance has been increasing. Further, since the gate height and the like are gently downscaled, the ratio of the gate-contact capacitance to the entire parasitic capacitance is increasing. Therefore, there is a problem that the merit of using SOI having a small parasitic capacitance is faded.
[0004]
The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of reducing the gate-contact capacitance to substantially zero and a method of manufacturing the same.
[0005]
[Means for Solving the Problems]
A semiconductor device according to the present invention is characterized in that, in a MOS SOI semiconductor device in which a contact is arranged above a semiconductor layer, a gate is arranged only below the semiconductor layer. Since the gate and the contact are provided on the opposite side of the semiconductor layer (active region), the capacitance between the gate and the contact becomes substantially zero.
[0006]
As a method for manufacturing this semiconductor device, an SOI substrate in which an insulating layer and a semiconductor layer are stacked on a semiconductor substrate is used, and an ordinary SOI transistor manufacturing process is performed from element isolation region formation to an interlayer insulating film deposition step. After performing ion implantation for separating the semiconductor substrate by an ion implantation separation method, and bonding the interlayer insulating film side of the element to another semiconductor substrate, the semiconductor substrate of the SOI substrate is separated and removed, and on the insulating layer which appears. , An interlayer insulating film is added, and the contact is connected from the back surface of the SOI transistor.
[0007]
Alternatively, using a semiconductor substrate, a normal bulk transistor manufacturing process is performed from the element isolation region formation to the interlayer insulating film deposition step, and then ion implantation is performed to peel off the semiconductor substrate below the element isolation region lower surface position. After bonding the interlayer insulating film side to another semiconductor substrate, the semiconductor substrate below the element isolation region lower surface position is peeled off and removed, an interlayer insulating film is formed, and the contact is connected from the back surface of the SOI transistor. To manufacture. In this case, by controlling the thickness of the element isolation region formed in the semiconductor substrate, the thickness of the semiconductor layer serving as the active region can be controlled.
[0008]
When the body contact is provided, the body region is expanded in a plane, and the body contact is connected to the side opposite to the gate of the semiconductor layer. In this case, the operation of the semiconductor device can be stabilized by applying a voltage to the body.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example 1)
First Embodiment An inverter according to a first embodiment of the present invention and a method for manufacturing the inverter will be described with reference to FIG. First, as in the case of manufacturing a conventional SOIFET, an SOI substrate in which a buried oxide film (BOX) 2 having a thickness of 100 nm and a Si layer (SOI layer) 3 having a thickness of 50 nm are laminated on a substrate A1 is used. An element isolation region (SiO ₂ ) 4 is formed in the Si layer 3 by a trench method or the like, and then a p-type (or n-type) active impurity for forming a body 5 in the element region 3 a surrounded by the element isolation region 4. To form a gate G having a thickness of 150 nm made of a Si film on the body 5 with a gate oxide film 6 having a thickness of 3 nm interposed therebetween. The gate G is provided with a drawn-out end in the length direction (perpendicular to the paper surface). An n-type (p-type) active impurity is ion-implanted to form a gate contact and then a source / drain diffusion layer (S / D), and an active impurity is also ion-implanted into the gate G. Then, silicide is formed on the upper surface of the source / drain diffusion layer (S / D) and the gate G. Thereafter, an interlayer insulating film (SiO ₂ ) 7 having a thickness of 500 nm is formed, and the upper surface is flattened by CMP (chemical mechanical). (Polishing) (FIG. 1A).
[0010]
Next, H ⁺ or the like is ion-implanted from the upper side of the wafer in order to separate the substrate A1 by an ion-implantation separation method. This ion implantation is performed so that the ion range Rp is located at a depth of, for example, 0.2 μm on the substrate A1 (FIG. 1B). This ion implantation was performed under the condition of H ⁺ 80 keV (Rp = 840 nm) 5 × 10 ¹⁶ / cm ² .
[0011]
After this ion implantation, the wafer is turned upside down and the lower surface of the interlayer insulating film 7 (the upper surface before turning over the wafer) is bonded to the upper surface of another Si substrate B using a substrate bonding technique. Thereafter, a heat treatment at 600 to 800 ° C. is performed to peel off and remove the substrate A1 at the position of the ion range Rp (FIG. 1C). Next, in order to remove the substrate A1a remaining on the surface of the BOX2, trimming is performed using the BOX2 as a stopper. As a result, Si of the substrate A1 is not present in the field portion, and BOX2 appears on the upper surface.
[0012]
Next, an interlayer insulating film 8 (SiO ₂ ) including the thickness of the BOX 2 is deposited on the BOX 2 so as to have a thickness of 800 nm, and a hole is formed in the interlayer insulating film 8 to form a source / drain (S / D). The contacts 11 and 12 are connected (FIG. 1D). Similarly, a hole is made in the interlayer insulating film 8 and a contact is also connected to the leading end of the gate G (not shown).
[0013]
In the inverter formed as described above, since the gate G is disposed on the lower surface side of the active region 3a opposite to the contacts 11 and 12 on the upper surface side of the active region 3a, the capacitance between the gate and the contact is substantially zero. It becomes. Therefore, the gate parasitic capacitance was reduced by about 10% as compared with the conventional inverter.
(Example 2)
Second Embodiment A SOI inverter used as a starting substrate and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIG. Referring to FIG. 2A, first, similarly to the case of manufacturing a conventional bulk type semiconductor device, an element isolation region (SiO ₂ ) 4 is formed on a Si substrate A2 as a starting substrate by a trench method or the like. . At this time, the thickness of the element region 3a surrounded by the element isolation region 4 is controlled by the trench depth T (FIG. 2B). In this embodiment, the thickness of the element region 3a is set to 50 nm.
[0014]
Next, ions of p-type (or n-type) active impurities for forming the body 5 are formed in the element region 3a, and a thickness of a Si film is formed on the body 5 via the gate oxide film 6 having a thickness of 3 nm. A 150 nm gate G is formed. The gate G is provided with a drawn-out end in the length direction (perpendicular to the paper surface). An n-type (p-type) active impurity is ion-implanted to form a gate contact and then a source / drain diffusion layer (S / D), and an active impurity is also ion-implanted into the gate G. Then, silicide is formed on the upper surface of the source / drain diffusion layer (S / D) and the gate G. Thereafter, an interlayer insulating film (SiO ₂ ) 7 having a thickness of 500 nm is formed, and the upper surface is flattened by CMP (chemical mechanical). Grind.
[0015]
Next, H ^{+ and the} like are ion-implanted from the upper side of the wafer in order to separate the substrate A2 below the element region 3a and the element isolation region 4 by an ion implantation separation method. This ion implantation is performed so that the ion range Rp is located at a position slightly below the trench depth T formed in the substrate A2, for example, at 0.2 μm (FIG. 2B).
[0016]
After the H ion implantation, the wafer is turned upside down and the lower surface of the interlayer insulating film 7 (the upper surface before the wafer is turned upside down) is bonded to the upper surface of another Si substrate B using a substrate bonding technique. Thereafter, a heat treatment at 600 to 800 ° C. is performed to peel off and remove the substrate A2 at the position of the ion range Rp (FIG. 2C). Then, in order to remove the substrate A2a remaining on the upper surfaces of the element region 3 and the element isolation region 4, the upper surface is flattened by trimming using the element isolation region 4 as a stopper. This eliminates the Si of the substrate A2 in the field portion.
[0017]
Next, an interlayer insulating film 8 is deposited to a thickness of 800 nm on the trimmed surface, and a hole is made in the interlayer insulating film 8 to connect contacts 11 and 12 to the source / drain (S / D) (FIG. 2 (d)). )). Similarly, a hole is made in the interlayer insulating film 8 and a contact is also connected to the leading end of the gate G (not shown).
[0018]
This inverter has the same configuration as that of the inverter of the first embodiment. Since the gate G is disposed on the opposite side of the contacts 11 and 12 across the active region 3a, the capacitance between the gate and the contact becomes substantially zero.
[0019]
In the first and second embodiments, the body 5 is in the floating state. However, the operation of the inverter can be stabilized by applying a voltage to the body 5 by attaching a contact to the body 5. When a contact is made to the body 5 to apply a voltage to the body 5, for example, a body 5 pad is exposed, or the body 5 region is widened by a large gate length, and a body contact is made in the same direction as the contacts 11 and 12. When a contact is provided, a process for obtaining an ohmic contact is required.
[0020]
In the inverters produced in Examples 1 and 2, the capacitance between the gate and the contact was calculated to be 0.55 fF as the wiring capacitance. The total parasitic capacitance of the conventional SIO type and Bulk type inverters equivalent to the first and second embodiments is 4.7 fF and 5.8 fF, respectively. Therefore, the effect of reducing the parasitic capacitance in the embodiment is as follows.
[0021]
SOI: 11.2%, Bulk: 9.5%.
(Example 3)
FIG. 3 shows an arrangement of a body contact and the like of a large-sized transistor provided with a body contact. This large-sized transistor is manufactured by the method of the first embodiment (or the second embodiment). In this case, a body extending portion for connecting the body contact 14 to the body formed in the active region 3a having a considerably large length is provided. A gate G having a gate extension Ga is formed on the lower surface side of the active region 3a in a shape corresponding to the body having this body extension. The gate G is provided with a lead-out end Gb having a shape connectable with a gate contact in the gate length direction. Holes are opened in the interlayer insulating film 8 (see FIGS. 1 and 2) formed on the active region 3a and the element isolation region 4 to connect to the source / drain, the gate and the body, thereby forming the source / drain contact 11/12 and the gate contact. 13, body contact 14 is connected from above.
[0022]
According to the third embodiment, as in the first and second embodiments, the gate G is disposed on the opposite side to the S / D contacts 11 and 12 with the active region 3a interposed therebetween. -The capacitance between the contacts is substantially zero. Further, by applying a voltage to the body contact 14, the operation of the transistor can be stabilized.
[0023]
【The invention's effect】
In the semiconductor device according to the present invention, since the gate and the source / drain contact are on opposite sides of the active region, the capacitance between the gate and the source / drain contact is substantially zero. Therefore, the gate parasitic capacitance is reduced, so that the operation speed of the semiconductor device is improved and the power consumption is significantly reduced.
[Brief description of the drawings]
FIG. 1 is a view illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is an explanatory view of a manufacturing process of a semiconductor device according to a second embodiment of the present invention. FIG. 3 is a plan view showing a main part of a semiconductor device according to a third embodiment of the present invention.
[Explanation of symbols]
A1: Si substrate of SOI substrate, A2: single crystal Si substrate,
B: Si substrate, G: Gate, S: Source (diffusion layer),
D: drain (diffusion layer) 2: buried oxide film (BOX)
3 SOI layer, Si layer 3a Element region, active region 4 Element isolation region 5 Gate oxide film 6 Body
7, 8 ... interlayer insulating film, 11 ... source contact,
12 ... drain contact, 13 ... gate contact,
14 ... body contact,

Claims (5)

In a MOS type SOI semiconductor device in which a contact is arranged above a semiconductor layer, a gate is arranged only below the semiconductor layer. 2. The semiconductor device according to claim 1, wherein the starting substrate is a semiconductor substrate, and the thickness of the semiconductor layer is controllable by controlling the thickness of the element isolation region formed on the starting semiconductor substrate. The semiconductor device according to claim 1, wherein the body contact is connected from above the semiconductor layer, and the body region is expanded in a plane. Using an SOI substrate in which an insulating layer and a semiconductor layer are stacked on a semiconductor substrate, performing from an element isolation region formation to an interlayer insulating film deposition step in a normal SOI transistor manufacturing process,
After that, ion implantation for separating the semiconductor substrate of the SOI substrate by an ion implantation separation method is performed,
After bonding the element's interlayer insulating film side to another semiconductor substrate, the semiconductor substrate of the SOI substrate is peeled and removed,
2. The method according to claim 1, wherein an interlayer insulating film is added on the exposed insulating layer, and a contact is connected from a back surface of the SOI transistor. Performing from the element isolation region formation to the interlayer insulating film deposition step in the normal bulk transistor manufacturing process using a semiconductor substrate,
After that, ion implantation is performed to peel the semiconductor substrate below the element isolation region lower surface position,
After bonding the element's interlayer insulating film side to another semiconductor substrate, the semiconductor substrate below the element isolation region lower surface position is peeled off and removed, an interlayer insulating film is formed, and contacts are connected from the back surface of the SOI transistor. 3. The method for manufacturing a semiconductor device according to claim 2, wherein:

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