JP2004072217A - Data reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a synchronous reproduction processing between a transmitter side and a receiver side without causing duplicate or missing sample points to the receiver side even when the transmitter side transmits no synchronous data and no synchronizing clock in packet data transmission. <P>SOLUTION: A low pass filter 22 smoothes a flag signal hf denoting whether or not an unread data amount in a buffer memory 15 exceeds a half the capacity of the memory 15 and gives the smoothed signal to an oscillator 16 for generating a read clock. Thus, the frequency of the read clock is changed with the unread data amount in the buffer memory 15 so as to keep the unread data amount nearly constant thereby coping with a very small frequency difference between the transmitter side and the receiver side. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is suitably implemented for data in which the reproduction timing of data cannot be arbitrarily determined on the reproduction device side, such as data with synchronization such as video and audio and data distributed to a plurality of reproduction devices, The present invention relates to an apparatus for reproducing received data into a video signal and an audio signal.
[0002]
[Prior art]
Conventionally, in order to simplify a transmission path, a device that receives and reproduces digital audio data transmitted from a transmitting side without a clock signal on a receiving side has been used. In such a configuration, when data is reproduced based on a sampling clock that is not synchronized with the received data, a time lag occurs between the data and the sampling clock because the periods of the data and the sampling clock do not completely match. . For this reason, when the sampling frequency of the receiving side is higher than that of the transmitting side, the same sample point is reproduced twice (duplicated) continuously as shown in FIG. When the sampling frequency on the receiving side is low, there is a problem that a reproduced waveform becomes discontinuous due to occurrence of a sample point (loss) which is not reproduced as shown in FIG. 6B.
[0003]
In order to solve such a problem, for example, IEC60958, which is a standard of a digital audio interface, transmits data after bi-phase modulation. As a result, the clock signal component synchronized with the data is superimposed on the data and transmitted. When the reception data is input to the PLL, a clock signal having the same cycle as the reception data can be obtained as the output. . Further, by generating a sampling clock synchronized with the clock and reproducing the data, a time lag of the sampling clock does not occur between the transmitting and receiving devices, and the duplication or omission of the sample points of the reproduced data as described above is prevented. Can be avoided.
[0004]
[Problems to be solved by the invention]
However, in the above-described method, when data is continuously transmitted, a clock synchronized with the received data can be generated and the audio data can be reproduced without any problem, but the data is compressed in the time axis direction. In the case of intermittent transmission as a packet, there is a period during which there is no data during reception, a clock for reproduction cannot be obtained, and such a method cannot be used. For this reason, in an apparatus that receives and reproduces packet data, the packet data is stored in a buffer memory such as a FIFO (First In First Out) and is stored in a fixed amount from the buffer memory using a clock generated independently on the receiving side. It is common practice to read out data from the oldest data at intervals and reproduce the data.
[0005]
FIG. 7 is a block diagram showing an electrical configuration of a typical conventional reproducing apparatus 1 for receiving and reproducing packet data. On the transmitting side, packetized data sampled and encoded at a fixed period is intermittently input from the communication path 2 to the receiving circuit 3, read out by the control circuit 4, and sequentially written into the buffer memory 5 of the FIFO. Rare and accumulate. On the other hand, data is continuously read from the buffer memory 5 at regular intervals by the clock from the oscillator 6, decoded into audio data by the decoder 7, converted to an analog signal in the D / A converter 8, The signal is output from the communication path 10 to an amplifier circuit (not shown) through the pass filter 9.
[0006]
The data read from the buffer memory 5 in this manner is processed in synchronization with the clock from the oscillator 6. That is, the sampling clock of the D / A converter 8 is a clock from the oscillator 6 or a clock generated inside the D / A converter 8 in synchronization with the clock, and the sampling clock on the transmission side is used. Is asynchronous with
[0007]
FIG. 8 is a graph showing an example of a time change between the input / output data of the buffer memory 5 and the unread data amount. 8A shows data written to the buffer memory 5, FIG. 8B shows data read from the buffer memory 5, and FIG. 8C shows the amount of unread data in the buffer memory 5. As described above, the data compressed in the time axis direction and packetized is sequentially and intermittently input to the buffer memory 5 as shown by reference numerals in1, in2, in3,. It is written. Also, from the buffer memory 5, as shown by reference numerals out 1, out 2, out 3,... In FIG. It is being done. Correspondingly, the unread data amount repeatedly increases and decreases as indicated by reference numeral α1 in FIG.
[0008]
Note that the packet data is not always sent from the transmitting side at regular intervals. Generally, the packet data is indicated by reference numerals in3, in7, in11,. May not be present. In this case, although the amount of unread data temporarily decreases largely, it gradually increases gradually, and the long-term average of the amount of unread data always becomes a constant value indicated by the reference numeral ref.
[0009]
Here, usually, in order to set the capacity margins before the buffer memory 5 overflows and underflows to the same extent, the data is read from the point in time when half of the data has been accumulated in the buffer memory 5 after the start of reception. Is started, and reproduction is performed. When the frequency of the sampling clock on the transmitting side and the frequency of the sampling clock on the receiving side are completely the same, the encoding cycle on the transmitting side is equal to the decoding cycle on the receiving side. The average speed of the data to be read is equal to the average speed of the data read from the buffer memory 5, and half the capacity of the buffer memory 5 becomes the convergence value of the unread data amount indicated by the reference numeral ref.
[0010]
However, in practice, as described above, the sampling clock on the receiving side is asynchronous with respect to the sampling clock on the transmitting side, so that the respective clock frequencies are slightly different or fluctuate with respect to the other. As a result, the average period of the encoding process on the transmitting side, that is, the average period of writing to the buffer memory 5, and the average period of the decoding process on the receiving side, that is, the average period of reading from the buffer memory 5 are different from each other. As shown by reference numerals α2 and α3, the data amount deviates from the value ref which is the half capacity with the passage of time, and eventually an overflow or an underflow occurs.
[0011]
In order to solve this problem, for example, in data transmission according to the IEEE 1394 standard, a node called a cycle master exists on the IEEE 1394 bus, timer information on this cycle master is transmitted in a packet and transmitted to other nodes on the bus. The timer is provided with a mechanism for adjusting the time of the timer between the nodes by copying approximately every basic cycle (125 μs). Both the transmitting side and the receiving side individually use the sampling clock based on their own timer. Generate As a result, there is no time lag of the sampling clock between the transmitting and receiving devices, and it is possible to avoid duplication or omission of the sample points on the receiving side.
[0012]
Here, the original function of the cycle master is to transmit a packet called a cycle start packet at the beginning of a basic cycle and to determine the transmission / reception timing of a band-guaranteed packet called an isochronous packet. A master is required when using the Isochronous packet. On the other hand, in the IEEE 1394 standard, when the transmission rate is low or the traffic of other packets is small, and there is no need to guarantee the bandwidth, the isochronous packet is not used, and only a packet called a basic asynchronous packet is used. The transfer can be performed by using. However, in this case, the processing of the isochronous packet and the processing of the cycle master become unnecessary, and the hardware can be simplified. On the other hand, since there is no means for synchronizing between transmission and reception, a time lag occurs, and the sampling point as described above occurs. Duplication or omission occurs.
[0013]
As another method for solving the overflow or underflow of the buffer memory 5, the data receiving side sends a command to the transmitting side to perform flow control and request a change in the speed of transmission data. A method of preventing the overflow and the underflow while reproducing the data with the generated clock is described in the technical document of 1394 TRADE ASSOCIATION "TA Document 199999015 AV / C Command Set for Rate Control of Isochronous Data Flow". In this method, no duplicate or missing sample points occur during playback, and the transmitting side adjusts the transmission data speed according to the receiving side, so it can be played back with an independent sampling clock on the receiving side, and clock jitter is extremely low. This is a very effective method.
[0014]
However, although this method can be applied to the reproduction of data stored on a recording medium such as a CD player, in the case of synchronous data such as real-time broadcast data, the transmitting side It is not applicable because it is impossible to adjust the data transmission rate of Further, in this method, a request is made from the receiving side to the transmitting side, and the transmitting node adjusts the transmission speed only to the receiving node that has received the request, so that there are a plurality of receiving nodes for one transmitting node. Not applicable in cases. Furthermore, the hardware for transmitting the data on the transmission side corresponds to such flow control, and complicated control for controlling the data reading speed from the CD on the transmission side as described above is required.
[0015]
An object of the present invention is to perform a reproduction process synchronized with a transmission side on a reception side without transmitting synchronization data or a synchronization clock from a transmission side even in data transmission by a packet, and to reproduce data without duplication or loss of sample points. An object of the present invention is to provide a data reproducing device capable of reproducing.
[0016]
[Means for Solving the Problems]
A data reproducing apparatus according to the present invention is a data reproducing apparatus for reproducing received data, sequentially accumulates data received from a receiving means, and sequentially reads data from an oldest data in response to a read clock. A buffer memory, an unread data amount calculating unit that calculates an unread data amount of the buffer memory, a smoothing unit that temporally smoothes an output of the unread data amount calculating unit, and a buffer memory based on an output from the smoothing unit. Clock frequency changing means for changing the frequency of the read clock; and reproducing means for reproducing data read from the buffer memory in synchronization with the read clock.
[0017]
According to the above configuration, when reproducing the received data, the received data is temporarily stored in the buffer memory, the unread data amount in the buffer memory is calculated by the unread data amount calculation means, and the clock frequency changing means is By changing the frequency of the read clock from the buffer memory to the reproducing means based on the output obtained by temporally smoothing the unread data amount, the accumulated data amount of the unread data in the buffer memory can be maintained substantially constant. And read out.
[0018]
Therefore, the transmission side and the reception side do not synchronize (cooperate) with a special clock signal, communication, or the like. By changing the frequency of the read clock as described above for data for which data reproduction timing cannot be determined arbitrarily, that is, for data that cannot absorb a time lag such as jitter due to accumulation in the buffer memory, The time lag can be absorbed.
[0019]
Further, the data reproducing apparatus of the present invention is a device for receiving and reproducing data transmitted by being time-axis-compressed into a packet. The data reproducing apparatus sequentially accumulates data received from a receiving unit and responds to a read clock. A buffer memory that sequentially reads data from the oldest data, an unread data amount calculating unit that calculates an unread data amount of the buffer memory, and a smoothing unit that temporally smoothes an output of the unread data amount calculating unit. Means for changing the frequency of the read clock based on the output from the smoothing means, and reproduction for performing a reproduction process of data read from the buffer memory in synchronization with the read clock. Means.
[0020]
According to the above configuration, in a device that receives and reproduces packet data transmitted from the transmission side at regular intervals via a communication path realized by an IEEE 1394 serial bus or USB, the received data is stored in the buffer memory. The packet data is temporarily stored and sequentially read out from the buffer memory sequentially from the oldest data, thereby extending the time axis of the packet data and converting the packet data into continuous data. Then, the amount of unread data in the buffer memory is calculated by the unread data amount calculating means, and the clock frequency changing means reads the clock from the buffer memory to the reproducing means based on the output obtained by temporally smoothing the unread data amount. By changing the frequency, the amount of unread data stored in the buffer memory is kept substantially constant and reading is performed.
[0021]
Therefore, the transmission side and the reception side do not synchronize (cooperate) with a special clock signal, communication, or the like. By changing the frequency of the read clock as described above for data for which the data reproduction timing cannot be determined arbitrarily, that is, for data that cannot absorb the time lag due to accumulation in the buffer memory, Can be absorbed.
[0022]
Still further, in the data reproducing apparatus according to the present invention, the clock signal source for generating the read clock includes a voltage-controlled oscillator, and the unread data amount calculation unit determines whether the unread data amount is equal to or greater than a predetermined value. And the clock frequency changing means switches and outputs the voltage to be increased and the voltage to be decreased based on the output of the 1-bit signal.
[0023]
According to the above configuration, the unread data amount calculation unit outputs a 1-bit signal indicating whether or not the unread data amount is equal to or greater than a predetermined value, and in response, the clock frequency changing unit changes the frequency. As described above, the reading speed can be maintained constant only by switching the voltage to be lowered, for example, the GND potential, or the voltage to be raised in frequency, for example, the Vcc potential, and outputting the same to the voltage-controlled oscillator.
[0024]
Therefore, it can be easily realized with a simple configuration at low cost.
[0025]
Further, in the data reproducing apparatus according to the present invention, the predetermined value is a half of the capacity of the buffer memory.
[0026]
According to the configuration described above, the overflow and the underflow due to the difference between the clock on the transmission side, that is, the write clock to the buffer memory and the read clock occur with equal probability, so that the voltage whose frequency should be raised and the voltage that should be dropped fall. By setting the amount of unread data, which is the threshold value for switching to the power voltage, to be half of the capacity of the buffer memory, such flows can be prevented with the highest probability.
[0027]
Still further, in the data reproducing apparatus according to the present invention, the clock frequency changing unit may be configured so that the unread data amount reaches a predetermined value from the time when the input of data to the buffer memory is started to the time when reading is started. It is characterized in that it outputs an intermediate value between the voltage to increase the frequency and the voltage to decrease.
[0028]
According to the above configuration, if the control voltage from the clock frequency changing means to the clock signal source composed of the voltage controlled oscillator is initially set to one of the voltage to decrease the frequency and the voltage to increase the frequency, the reading is performed. Although the control voltage to the voltage-controlled oscillator does not converge and the read speed changes even when the read operation starts, the voltage By setting it to an intermediate value, the clock is substantially stable at a specified frequency from the beginning of the reading, the control voltage is relatively stable, and the reading speed can be kept constant.
[0029]
In the data reproducing apparatus of the present invention, the clock signal source for generating the read clock includes a voltage-controlled oscillator, and the clock frequency changing unit outputs an analog voltage corresponding to output data of the unread data amount calculating unit. It is characterized by doing.
[0030]
According to the above configuration, the control voltage input to the voltage-controlled oscillator can be finely adjusted with an analog voltage in accordance with the output data of the unread data amount calculation means, and the clock frequency can be controlled with higher accuracy. can do.
[0031]
Still further, in the data reproducing apparatus according to the present invention, the voltage-controlled oscillator is set to a non-linear function in which a change in an output frequency with respect to a change in an input voltage is small near a center voltage and large at a peripheral voltage. It is characterized by.
[0032]
According to the above configuration, in a steady state where the input voltage converges near the center voltage, the output frequency can be stably maintained even if the input voltage slightly changes. When the voltage fluctuates significantly, the output frequency also changes greatly, and the input voltage can be efficiently returned to near the center voltage by feedback control.
[0033]
In the data reproducing apparatus of the present invention, the received data to be reproduced is video data and / or audio data, and is stored in the buffer memory except for components other than the video and / or audio components. Features.
[0034]
According to the above configuration, of the received data, the buffer memory is stored excluding components other than the video and / or audio components such as a header and an error correction code.
[0035]
Therefore, the consumption of the memory capacity of the buffer memory is suppressed, and the reading does not require a higher frequency clock to read such extra data, and the reading clock is set to the same frequency as the transmitting side. Can be.
[0036]
Still further, in the data reproducing apparatus of the present invention, the received data to be reproduced is 1-bit audio data.
[0037]
According to the above configuration, in the case of multi-bit data having different weights for each bit, if a transmission error occurs in data near the MSB, there is a possibility that a large distortion may occur in a reproduced sound, whereas a 1-bit data The weight of each bit is equal to each other, and there is little possibility that perceptible distortion will occur even if a transmission error occurs.
[0038]
Therefore, data transmission with a large SN can be performed by using 1-bit audio data.
[0039]
Further, in the data reproducing apparatus of the present invention, the received data from the receiving means is input, and an identification number indicating an order for each packet added to the packet data in advance is identified. In a case where the data becomes discontinuous, a data compensating means for writing predetermined specific data into the buffer memory instead of the lost packet is further provided.
[0040]
According to the above configuration, when the data compensating unit determines that the packet has been lost, the data compensating unit writes specific data in place of the received data to the buffer memory for the number of lost packets.
[0041]
Therefore, the present invention is suitable for data in which the reproduction timing of the data cannot be arbitrarily determined on the reproduction device side, such as the data with synchronization and the data distributed to a plurality of reproduction devices.
[0042]
Still further, in the data reproducing apparatus according to the present invention, the specific data is data such that a level of a reproduced signal is a constant value or a zero level.
[0043]
According to the above configuration, by making the data to be compensated be the above-described data, for example, in the case of an audio signal, it is possible to suppress audible noise.
[0044]
BEST MODE FOR CARRYING OUT THE INVENTION
One embodiment of the present invention will be described below with reference to FIGS.
[0045]
FIG. 1 is a block diagram showing an electrical configuration of a reproducing apparatus 11 according to one embodiment of the present invention for receiving and reproducing packet data. The playback device 11 is a playback device for digital audio data. Although FIG. 1 shows one channel, the playback device 11 is a device in which a speaker, a playback device, and an amplifier are integrated (the D / A converter in FIG. 1). 18 and the like), these devices are provided in parallel (the decoder 17 in FIG. 1 is shared, and the D / A converter 18 and subsequent channels are provided in multiple channels). In this case, the configuration shown in FIG. 1 is connected in parallel. Therefore, it is not possible to arbitrarily determine the reproduction timing for each reproduction apparatus 11, and it is necessary to perform the reproduction in synchronization between the channels. It is.
[0046]
On the transmitting side, the packetized data sampled and encoded at a fixed period is intermittently input to the receiving circuit 13 from the communication path 12 implemented by an IEEE 1394 serial bus or USB, and is read out by the control circuit 14. The data is sequentially written and stored in the buffer memory 15. On the other hand, data is continuously read from the buffer memory 15 at regular intervals by the clock from the oscillator 16, decoded into audio data by the decoder 17, converted into an analog signal in the D / A converter 18, The signal is output from the communication path 20 to an amplification circuit (not shown) through the pass filter 19.
[0047]
The buffer memory 15 is a memory of the FIFO. The buffer memory 15 sequentially stores input data, asynchronously with the writing, sequentially reads the oldest data, and sequentially stores new data in the read area. Is rewritten. The decoder 17 decodes the read data of one word into audio data of one sample.
[0048]
The data read from the buffer memory 15 in this manner is processed in synchronization with the clock from the oscillator 16. That is, the sampling clock of the D / A converter 18 is a clock from the oscillator 16 or a clock generated inside the D / A converter 18 in synchronization with the clock. And are asynchronous.
[0049]
It should be noted that, in the present invention, the oscillator 16 for generating the read clock comprises a variable frequency oscillator, and the oscillation frequency is changed according to the amount of unread data in the buffer memory 15. Specifically, the buffer memory 15 has a function of outputting a 1-bit flag signal (generally called a half flag signal) hf indicating whether or not the amount of unread data in the buffer memory 15 has exceeded half of the capacity. Then, the flag signal hf is input to the low-pass filter 22 via the switch 21, smoothed, and then input to the oscillator 16.
[0050]
The oscillator 16 is composed of a voltage controlled oscillator (VCO), and the higher the input voltage, the higher the oscillation frequency. On the other hand, the flag signal hf becomes “1” when the amount of unread data in the buffer memory 15 is more than half, for example, a high-level voltage such as Vcc, and when it is not more than half. "0", for example, a low level voltage such as GND. Therefore, when the amount of unread data exceeds half, the oscillation frequency of the oscillator 16 increases and the data reading speed increases, and when the amount of unread data does not exceed half, the oscillation of the oscillator 16 increases. As the frequency decreases, the data reading speed decreases, and thus the closed-loop control is performed such that the unread data amount is always half the capacity of the buffer memory 15.
[0051]
Further, the flag signal hf is also input to the control circuit 14. In response to the flag signal hf, the control circuit 14 changes the switch signal sw to “0” in the initial state and “1” after the timing when the flag signal hf first becomes “1”. Output to The switch 21 receives the flag signal hf and a predetermined voltage Vh. When the switching signal sw is "0", the switch 21 outputs the voltage Vh to the low-pass filter 22, and outputs "1". At some point, the flag signal hf is output to the low-pass filter 22.
[0052]
The voltage Vh is selected as an intermediate value between two voltages of the flag signal hf, for example, Vcc / 2. Therefore, the oscillator 16 receives the constant voltage Vh until reading of data from the buffer memory 15 is started, oscillates at a predetermined frequency corresponding to the voltage Vh, and starts reading data from the buffer memory 15. Then, the frequency smoothly changes from the frequency corresponding to the voltage Vh to the flag signal hf, that is, the frequency corresponding to the amount of unread data, and oscillation is performed.
[0053]
The switching signal sw is also input to one input of the AND gate 23. The clock from the oscillator 16 is input to the other input of the AND gate 23, and the output is output to the buffer memory 15, the decoder 17, the D / A converter 18, and the like. Therefore, the switching signal sw acts as a clock enable signal, and when the switching signal sw is “0”, that is, until the unread data amount reaches half the capacity of the buffer memory 15, the clock output is inhibited. When the value becomes "1", that is, when the amount of unread data exceeds half of the capacity of the buffer memory 15, the output of the clock is permitted, that is, the reading of data from the buffer memory 15 is permitted.
[0054]
FIG. 2 is a graph showing an example of a time change between the input / output data of the buffer memory 15 and the amount of unread data in the playback device 11 configured as described above. FIG. 2 corresponds to FIG. 8 described above. FIG. 2A shows data written to the buffer memory 15, FIG. 2B shows data read from the buffer memory 15, and FIG. ) Indicates the amount of unread data in the buffer memory 15. FIG. 2D shows the flag signal hf, and FIG. 2E shows input / output to / from the low-pass filter 22.
[0055]
First, in an initial state or an idle state where data is not being received, the switching signal sw from the control circuit 14 is set to “0”. As a result, the switch 21 outputs the constant voltage Vh to the low-pass filter 22. The voltage Vh is set to a level that is の of the amplitude change width of the flag signal hf, and the DC component passes through the low-pass filter 22, so that the oscillator 16 is supplied with the constant voltage Vh. Here, the oscillator 16 is designed to oscillate at the same frequency as the desired sampling clock frequency when the voltage Vh is input. This clock is blocked by the AND gate 23 and is not output, and the inside of the buffer memory 15 is empty.
[0056]
When the reception of data from another node via the communication path 12 is started, the received packet is input to the reception circuit 13 and the reception circuit 13 notifies the control circuit 14 that the data has been received. First, the header in the packet is read from the receiving circuit 13 by the control circuit 14. For example, in the communication method based on IEEE1394, the header stores the number of data included in the packet, and the control circuit 14 writes only the audio data in the packet from the reception circuit 13 to the buffer memory 15 by the number of data. In the case of a communication system in which a packet does not include a header or the like and the entire packet is composed of only data, the control circuit 14 may write data from the beginning to the end of the packet in the buffer memory 15. The above operation is repeated for each packet. As described above, the data compressed and packetized in the time axis direction is sequentially input to the buffer memory 15 as shown by reference numerals IN1, IN2, IN3,... In FIG. It will be inserted.
[0057]
Then, at the time TH, when the data is stored in the buffer memory 15 by half, the flag signal hf output from the buffer memory 15 becomes “1” as shown in FIG. Keeps the switching signal sw at "1" from this point until a series of data reception is completed. As a result, during reproduction, the switch 21 supplies the flag signal hf to the oscillator 16 via the low-pass filter 22, and the AND gate 23 permits the output of the clock, and the clock from the oscillator 16 continues to be output. As a result, the read clock is input to the buffer memory 15 from the time TH, and as shown by reference numerals OUT1, OUT2, OUT3,... In FIG. And expanded in the time axis direction. The read data is decoded by the decoder 17, converted into an analog signal by the D / A converter 18, and output.
[0058]
Here, at the time TH, the input voltage of the oscillator 16 immediately after the switch 21 is switched to the flag signal hf side does not immediately change due to the effect of the low-pass filter 22, and therefore the clock cycle does not change immediately. When reading of data from the buffer memory 15 is started in response to this clock as described above, the amount of unread data repeatedly increases and decreases as indicated by the reference symbol β in FIG. 2C. As a result, the flag signal hf changes as shown in FIG. 2D, and the input to the low-pass filter 22 via the switch 21 also corresponds to the flag signal hf as shown by reference numeral γ1 in FIG. This signal is smoothed by the low-pass filter 22 and is input to the oscillator 16 as a waveform having almost no time change as indicated by reference numeral γ2, and a clock having a stable frequency is output from the oscillator 16. Is output.
[0059]
Here, when there is no configuration for supplying the voltage Vh to the low-pass filter 22 until the reading from the buffer memory 15 is started, the output of the low-pass filter 22 is referred to as γ3 in FIG. As shown by, it takes time to reach the voltage Vh and the clock becomes unstable during that time. On the other hand, by supplying the constant voltage Vh as described above, before and after the start of the reading, As the output of the low-pass filter 22, a waveform with almost no voltage change that makes the amount of unread data constant is obtained, and the clock frequency can be stabilized.
[0060]
With the above configuration, conventionally, when the frequency of the sampling clock on the transmitting side is slightly higher than that of the sampling clock on the receiving side, the unread data as indicated by reference numeral α2 in FIG. While the amount increases with time and overflow occurs, in the reproducing apparatus 11 of the present invention, the ratio of the flag signal hf to “1” increases due to the increase in the amount of unread data, and the read clock increases. Since the frequency slightly increases, such a problem does not occur as shown by reference numeral β in FIG. 2C, and the amount of unread data can always be kept substantially constant.
[0061]
Similarly, conventionally, when the frequency of the sampling clock on the transmitting side is slightly lower than that of the sampling clock on the receiving side, the amount of unread data decreases with time as indicated by reference numeral α3 in FIG. 8C. In the reproducing apparatus 11 of the present invention, the ratio of the flag signal hf to "0" increases due to the decrease in the unread data amount, and the frequency of the read clock slightly decreases. Therefore, as shown by reference numeral β in FIG. 2C, such a problem does not occur, and the amount of unread data can always be kept substantially constant.
[0062]
In this way, the unread data amount of the buffer memory 15 is fed back to the oscillator 16 by the flag signal hf, and the clock cycle is controlled to be the same as the encoding cycle on the transmission side, that is, the sampling cycle. Since the average value is maintained at a constant value, no overflow or underflow of the buffer memory 15 occurs, and no duplication or omission of sample points occurs during reproduction. Therefore, when receiving and reproducing packet data transmitted from the transmission side at regular intervals, the transmission side and the reception side do not synchronize (cooperate) with a special clock signal or communication, and have synchronization. For data such as data or data distributed to a plurality of playback devices, for which the playback device cannot determine the playback timing of the data arbitrarily, that is, data that cannot absorb a time lag due to accumulation in the buffer memory 15. On the other hand, the time lag can be absorbed by changing the frequency of the read clock as described above.
[0063]
Here, the cause of the fluctuation of the clock frequency is due to the disorder of the writing cycle to the buffer memory 15, but as shown by reference numerals IN3, IN7, IN11,... In FIG. Since the average period of the data in the packet over a long period of time coincides with the encoding period of the transmitting side and is always constant, the long-term average of the period of writing to the buffer memory 15 is also constant. The fluctuation of the clock can be avoided by the effect of the low-pass filter 22 that performs the following.
[0064]
Further, in the reproducing apparatus 11 of the present invention, the oscillator 16 is constituted by a voltage controlled oscillator, and the flag signal hf from the buffer memory 15 is smoothed by the low-pass filter 22 and supplied to the oscillator 16. hf switches the voltage at which the oscillation frequency of the oscillator 16 is to be increased and the voltage at which the oscillation frequency is to be decreased, and outputs the same at the initial stage of reading. Since the voltage Vh is input, the input voltage of the oscillator 16 is relatively stable from the beginning of reading, and the reading speed can be kept constant.
[0065]
Further, as shown in FIG. 3, the oscillator 16 has an input / output characteristic set to a non-linear function in which a change in output frequency with respect to a change in input voltage is small near a center voltage and large at a peripheral voltage. ing. As a result, as described above, during normal reproduction, even if the input voltage of the oscillator 16 which is in a state of equilibrium with the constant voltage Vh which is the center voltage of the flag signal hf fluctuates somewhat, the output frequency can be stably maintained. When the input voltage fluctuates greatly, the output frequency also greatly fluctuates, and the voltage obtained by smoothing the flag signal hf by the low-pass filter 22 by feedback control is efficiently returned to the vicinity of the constant voltage Vh. Can be done.
[0066]
Another embodiment of the present invention will be described below with reference to FIGS.
[0067]
FIG. 4 is a block diagram showing an electrical configuration of a reproducing apparatus 31 according to another embodiment of the present invention. The playback device 31 is similar to the playback device 11 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that in the reproducing apparatus 31, the signal for performing the feedback control is not a one-bit signal such as the flag signal hf but a signal obtained by converting a multi-bit digital signal into an analog value. is there. Further, the reproduction processing portion is to perform reproduction processing of 1-bit audio data obtained by binarizing digital audio data.
[0068]
Specifically, the counter 32 and the buffer memory 15 are first initialized by the control circuit 38, and thereafter, a write clock to the buffer memory 15 from the control circuit 38 and a read clock described later are input to the counter 32, The difference value obtained by increasing or decreasing the numerical value by each clock, that is, the count value of the unread data amount of the buffer memory 15 is converted into an analog value by the D / A converter 33. The analog value is input to the clock oscillator 34 via the switch 21 and the low-pass filter 22.
[0069]
FIG. 5 is a block diagram showing a configuration example of the D / A converter 33. The D / A converter 33 is a D / A converter realized with a simple configuration combining resistors, and shows an example of 4-bit input. Digital data of the count value of the unread data amount from the counter 32 is input in parallel from above in FIG. 5, and an analog value is output from below. When the number of input bits is large, it is only necessary to increase the resistance in the horizontal direction in FIG.
[0070]
The oscillator 34 includes a voltage-controlled oscillator as described above, and outputs a clock having an oscillation frequency corresponding to the sampling frequency of the 1-bit audio data. This clock is output to a decoder 35 and a 1-bit audio data D / A converter 36, and after being divided by a frequency divider 37, is used as a read clock for the buffer memory 15.
[0071]
In the reproducing device 31 configured as described above, when data reading is started, the low-pass filter 22 includes the flag γ1 shown in FIG. 2D and FIG. In place of the signal hf, an analog value of the unread data amount indicated by reference numeral β in FIG. 2C is input, and the same frequency control as that of the reproducing apparatus 11 is performed by feedback. This makes it possible to control the clock frequency with higher accuracy, though the configuration is more complicated than that of the reproducing apparatus 11.
[0072]
When binary 1-bit audio data is used as digital audio data, one bit in one word of data read from the buffer memory 15 corresponds to one sample. Therefore, assuming that the number of bits in one word is n, the sampling process is performed n times while data is read from the buffer memory 15 once. Therefore, the sampling clock is supplied to the buffer memory 15 by n. The frequency-divided clock is generated by the frequency divider 37 and input.
[0073]
Here, the oscillator 34 is designed to oscillate at the same frequency as the desired sampling clock frequency for 1-bit audio reproduction when the constant voltage Vh is input. In the case of 1-bit audio, only parallel / serial conversion processing for converting one word data into one bit is performed inside the decoder 35, and only processing using a low-pass filter is performed inside the D / A converter 36. It can be converted to an analog signal.
[0074]
By transmitting 1-bit audio data in this way, with multi-bit data having different weights for each bit, if a transmission error occurs in data near the MSB, there is a possibility that large distortion will occur in reproduced sound. Thus, the 1-bit audio data has the same weight for each bit, has little possibility of causing perceptible distortion even if a transmission error occurs, and can perform data transmission with a large SN.
[0075]
Furthermore, packets may not be received correctly and may be lost due to an error during transmission. In such a case, the amount of transmission data differs from the amount of reception data, the average level of the signal input to the low-pass filter 22 changes, and the sampling frequency is temporarily disturbed. Although this disturbance is eventually recovered by the above-described feedback control, the reproducing apparatus 31 takes measures to prevent such disturbance, which will be described below. In the following description, it is assumed that the amount of data included in each packet is a fixed amount K and the amount of data in the lost packet is also K.
[0076]
First, a transmitting side (not shown) transmits a serial number capable of identifying a packet in a header portion. Upon receiving the packet, the control circuit 38 confirms this number in the header for each packet. If the number of the packet received this time is not consecutive with the number of the packet received last time, the control circuit 38 determines that the packet between them has been lost due to a transmission error, and determines from the number of the packet received this time The number of the lost packets is calculated by subtracting the number of the received packet and further subtracting 1 from the result. Then, the reproduction data amount of the number of lost packets × K is written to the buffer memory 15 as dummy data.
[0077]
As a result, even if a packet is lost due to an error during transmission, the same amount of data as the amount of data in the transmitted packet is written to the buffer memory 15, and the average value of the unread data amount in the buffer memory 15 is reduced. It is possible to prevent the sampling frequency from being disturbed without any change.
[0078]
When the dummy data is read out from the buffer memory 15 and reproduced as audio data, it becomes audible noise. Therefore, when the dummy data is output from the D / A converter 36, the amplitude becomes zero level. Alternatively, it is desirable to maintain a constant value. If the audio data is 1-bit audio data as described above, this can be realized by writing data in which the bit string of the reproduction data alternates between 1 and 0 alternately. In this case, the average value is at the 0 level, so that the reproduction level can be maintained at the 0 level, and the audible noise can be suppressed as much as possible.
[0079]
Although all of the above embodiments have been described with reference to audio data, it is apparent that the present invention can be similarly applied to video data and the like that are periodically reproduced. Further, the present invention can be used not only for packet data but also for data transmitted continuously to remove jitter.
[0080]
【The invention's effect】
As described above, when reproducing the received data, the data reproducing apparatus of the present invention temporarily accumulates the received data in the buffer memory and calculates the unread data amount in the buffer memory by the unread data amount calculating means. The clock frequency changing means changes the frequency of the read clock from the buffer memory to the reproducing means based on the output obtained by smoothing the unread data amount, so that the accumulated data amount of the unread data in the buffer memory becomes substantially constant. Maintain and read.
[0081]
Therefore, the transmission side and the reception side do not synchronize (cooperate) with a special clock signal, communication, or the like. By changing the frequency of the read clock as described above for data for which the data reproduction timing cannot be arbitrarily determined on the side, that is, for data that cannot absorb a time lag such as jitter due to accumulation in the buffer memory. , The time lag can be absorbed.
[0082]
Further, the data reproducing device of the present invention, as described above, in a device that receives and reproduces packet data transmitted at regular intervals from the transmitting side, temporarily stores received data in a buffer memory, By sequentially reading the oldest data from the buffer memory sequentially, the time axis of the packet data is expanded and converted to continuous data. Then, the unread data amount in the buffer memory is calculated by the unread data amount calculation means, and the clock frequency changing means calculates the frequency of the read clock from the buffer memory to the reproduction means based on the output obtained by smoothing the unread data amount. By changing it, reading is performed while the amount of unread data stored in the buffer memory is kept substantially constant.
[0083]
Therefore, the transmission side and the reception side do not synchronize (cooperate) with a special clock signal, communication, or the like. By changing the frequency of the read clock as described above for the data for which the reproduction timing of the data cannot be arbitrarily determined on the side, that is, the data for which the time lag cannot be absorbed by the accumulation in the buffer memory, The displacement can be absorbed.
[0084]
Still further, as described above, the data reproducing apparatus of the present invention uses a voltage-controlled oscillator as the clock signal source for generating the read clock, and the unread data amount calculation means determines whether the unread data amount is equal to or greater than a predetermined value. The clock frequency changing means outputs a 1-bit signal indicating whether the frequency is low or not, and switches the voltage to decrease the frequency, for example, the GND potential, or the voltage to increase the frequency, for example, the Vcc potential, and By outputting to the voltage controlled oscillator, the reading speed is kept constant as described above.
[0085]
Therefore, it can be easily realized with a simple configuration at low cost.
[0086]
Further, as described above, the data reproducing apparatus of the present invention sets the predetermined value to half the capacity of the buffer memory.
[0087]
Therefore, overflow and underflow due to the difference between the clock on the transmission side, that is, the write clock to the buffer memory and the read clock can be prevented with the highest probability.
[0088]
Still further, in the data reproducing apparatus of the present invention, as described above, the clock frequency changing unit may be configured to perform the processing from the time when the input of the data to the buffer memory is started until the amount of unread data reaches a predetermined value and the reading is started. During this period, an intermediate value between the voltage to increase the frequency and the voltage to decrease the frequency is output.
[0089]
Therefore, the clock is substantially stable at the prescribed frequency from the time when data input to the buffer memory is started before the reading is started, and the control voltage is relatively stable at the time when reading is started, and the reading speed is kept constant. Can be maintained.
[0090]
Further, in the data reproducing apparatus of the present invention, the clock signal source for generating the read clock is a voltage-controlled oscillator, and the clock frequency changing unit outputs an analog voltage corresponding to output data of the unread data amount calculating unit. .
[0091]
Therefore, the control voltage input to the voltage-controlled oscillator can be finely adjusted by the analog voltage in accordance with the amount of unread data, and the clock frequency can be controlled with higher accuracy.
[0092]
Further, as described above, the data reproducing apparatus of the present invention converts the voltage-controlled oscillator into a nonlinear function in which the change in the output frequency with respect to the change in the input voltage is small near the center voltage and large at the peripheral voltage. Set.
[0093]
Therefore, in a steady state in which the input voltage converges near the center voltage, the output frequency can be stably maintained even if the input voltage slightly changes. In this case, the output frequency also changes greatly, and the input voltage can be efficiently returned to the vicinity of the center voltage by feedback control.
[0094]
Further, as described above, the data reproducing apparatus of the present invention converts the received data to be reproduced into video data and / or audio data, and stores the video and / or audio data such as a header and an error correction code in the buffer memory. Alternatively, the information is stored excluding components other than the voice component.
[0095]
Therefore, the consumption of the memory capacity of the buffer memory can be suppressed, and the read clock can be set to the same frequency as the transmission side.
[0096]
Furthermore, as described above, the data reproducing apparatus of the present invention has the same possibility that the received data to be reproduced has the same weight for each bit and generates a perceptible distortion even if a transmission error occurs. It is 1-bit audio data.
[0097]
Therefore, data transmission with a large SN can be performed.
[0098]
Further, in the data reproducing apparatus according to the present invention, as described above, the data compensating means identifies the identification number indicating the order of each packet, which is previously added to the received packet data, and identifies the identification number in the received packet sequence. Is discontinuous, predetermined specific data is written in the buffer memory in place of the lost packet.
[0099]
Therefore, the present invention is suitable for data in which the reproduction timing of data cannot be arbitrarily determined on the reproduction device side, such as the data with synchronization and the data distributed to a plurality of reproduction devices.
[0100]
Furthermore, as described above, the data reproducing apparatus of the present invention sets the specific data to data at which the level of the reproduction signal becomes a constant value or data at which the level becomes zero.
[0101]
Therefore, for example, in the case of an audio signal, it is possible to suppress noise in the sense of hearing.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an electrical configuration of a reproducing apparatus according to an embodiment of the present invention that receives and reproduces packet data.
FIG. 2 is a graph showing an example of a temporal change between input / output data of a buffer memory and an unread data amount in the reproducing apparatus shown in FIG. 1;
FIG. 3 is a graph showing a change in an output frequency with respect to a change in an input voltage of an oscillator.
FIG. 4 is a block diagram showing an electrical configuration of a reproducing apparatus according to another embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration example of a D / A converter in the playback device shown in FIG.
FIG. 6 is a diagram showing a reproduced waveform when a sample point is missing.
FIG. 7 is a block diagram showing the electrical configuration of a typical prior art playback device.
8 is a graph showing an example of a time change between input / output data of a buffer memory and an unread data amount in the reproducing apparatus shown in FIG. 7;
[Explanation of symbols]
11,31 playback device
12, 19 Communication channel
13. Receiving circuit (receiving means)
14 Control circuit
15 Buffer memory (means for calculating unread data, means for changing clock frequency)
16, 34 oscillator (clock signal source, voltage controlled oscillator)
17, 35 decoder (reproduction means)
18,36 D / A converter
21 Switch (clock frequency changing means)
22 Low-pass filter (smoothing means)
23 AND gate
32 counter (unread data amount calculating means, clock frequency changing means)
33 D / A converter (clock frequency changing means)
37 divider
38 control circuit (data compensation means)

Claims (11)

In a device for reproducing received data,
A buffer memory for sequentially accumulating data received from the receiving means, and sequentially reading the oldest data sequentially in response to a read clock;
Unread data amount calculation means for calculating the unread data amount of the buffer memory,
Smoothing means for temporally smoothing the output of the unread data amount calculating means,
A clock frequency changing unit that changes a frequency of the read clock based on an output from the smoothing unit;
A data reproducing device for reproducing data read from the buffer memory in synchronization with the read clock. In a device that receives and reproduces data that is transmitted after being compressed on the time axis into packets,
A buffer memory for sequentially accumulating data received from the receiving means, and sequentially reading the oldest data sequentially in response to a read clock;
Unread data amount calculation means for calculating the unread data amount of the buffer memory,
Smoothing means for temporally smoothing the output of the unread data amount calculating means,
A clock frequency changing unit that changes a frequency of the read clock based on an output from the smoothing unit;
A data reproducing device for reproducing data read from the buffer memory in synchronization with the read clock. The clock signal source for generating the read clock comprises a voltage-controlled oscillator,
The unread data amount calculating means outputs a 1-bit signal indicating whether the unread data amount is equal to or greater than a predetermined value, and the clock frequency changing means outputs a frequency based on the output of the 1-bit signal. 3. The data reproducing apparatus according to claim 1, wherein a voltage to be raised and a voltage to be dropped are switched and outputted. 4. The data reproducing apparatus according to claim 3, wherein the predetermined value is a half of a capacity of the buffer memory. The clock frequency changing means includes a voltage for increasing the frequency and a voltage for decreasing the frequency until the amount of unread data reaches a predetermined value from the start of input of data to the buffer memory and the reading is started. 5. The data reproducing apparatus according to claim 3, wherein an intermediate value of the data is output. The clock signal source for generating the read clock comprises a voltage-controlled oscillator,
3. The data reproducing apparatus according to claim 1, wherein the clock frequency changing unit outputs an analog voltage corresponding to output data of the unread data amount calculating unit. 7. The voltage-controlled oscillator according to claim 3, wherein a change in output frequency with respect to a change in input voltage is set to a non-linear function that is small near a center voltage and large at a peripheral voltage. A data reproducing apparatus according to any one of the claims. The reception data to be reproduced is video data and / or audio data, and is stored in the buffer memory except for components other than the video and / or audio components. Data playback device. 3. The data reproducing apparatus according to claim 1, wherein the received data to be reproduced is 1-bit audio data. Received data from the receiving means is input, and an identification number indicating the order of each packet, which is pre-attached to the packet data, is identified.If the identification number becomes discontinuous in the received packet sequence, 3. The data reproducing apparatus according to claim 2, further comprising a data compensator for writing predetermined specific data in place of the packet into the buffer memory. 11. The data reproducing apparatus according to claim 10, wherein the specific data is data such that a level of a reproduction signal is a constant value or data having a zero level.

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