JP2004069886A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device with high reliability and with high efficiency by suppressing variation of a voltage-transmittance curve without changing a condition and a system for driving in practical use to a large extent. <P>SOLUTION: In driving and displaying a liquid crystal element of which the average axis of the liquid crystal molecule takes on the first monostable state when no voltage is applied, and when a voltage with the first polarity is applied the average axis is tilted to one side of the monostabilized position with an angle corresponding to the magnitude of the applied voltage, and when a voltage with the second polarity, reverse to the first polarity, is applied the average axis is tilted to the other side of the monostabilized position, reverse to the side of voltage application with the first polarity, with an angle smaller than that based on the first polarity, the display panel is driven by making the voltage application with the first polarity and that with the second polarity, reverse to the first polarity, be asymmetrical to each other. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal device used for a light valve used for a flat panel display, a projection display, and the like.
[0002]
[Prior art]
Conventionally, as typical liquid crystal modes of a nematic liquid crystal display element widely used as a display element using an active element such as a TFT (Thin Film Transistor), for example, M. Schadt and W. Helchrich ( The Twisted Nematic mode shown in Applied Physics Letters Vol.
[0003]
On the other hand, recently, a liquid crystal display using an in-plane switching (In-Plane Switching) mode using a lateral electric field and a vertical alignment (Vertical Alignment) mode has been announced, and the visual field which has been a disadvantage of the conventional liquid crystal display has been announced. The angular characteristics have been improved. As described above, there are several modes as liquid crystal modes for use in a TFT display element using such a nematic liquid crystal. In any of these modes, the response speed of the liquid crystal is several tens of milliseconds or more. Slow, further improvement in response speed is required.
[0004]
In order to improve the response speed of such a conventional nematic liquid crystal element, recently, several liquid crystal modes using a liquid crystal exhibiting a chiral smectic phase have been proposed. For example, "short-pitch type ferroelectric liquid crystal", "polymer stable ferroelectric liquid crystal", "threshold-less antiferroelectric liquid crystal" and the like have been proposed. It is also reported that high-speed response of sub-millisecond or less can be realized.
[0005]
On the other hand, the present applicant has invented and proposed an element described in Japanese Patent Application No. 10-177145 (hereinafter referred to as “prior application 1”). In the present invention, for example, a phase-series material showing an isotropic liquid phase (ISO.)-Cholesteric phase (Ch) -chiral smectic C phase or an isotropic liquid phase (ISO.)-Chiral smectic C phase from a high temperature side. And monostable at a position inside the edge of the virtual cone.
[0006]
Then, for example, at the time of Ch-SmC * phase transition or isotropic phase-SmC * phase transition, a positive or negative DC voltage is applied between a pair of substrates to make the layer direction uniform in one direction. Thus, a high-speed response and gradation control can be performed, and a high-brightness liquid crystal element having excellent moving image quality can be realized with high mass productivity. Since the element of the prior application can reduce the spontaneous polarization value as compared with the above-described various smectic liquid crystal modes, the element has good matching with an active element such as a TFT.
[0007]
Similarly, the present applicant has invented and proposed an element (hereinafter referred to as “prior application 2”) described in JP-A-2000-01076. In the present invention, for example, a phase-series material showing an isotropic liquid phase (ISO.)-Cholesteric phase (Ch) -chiral smectic C phase or an isotropic liquid phase (ISO.)-Chiral smectic C phase from a high temperature side. And monostable at the position of the virtual cone edge.
Then, for example, at the time of Ch-SmC * phase transition or isotropic phase-SmC * phase transition, a positive or negative DC voltage is applied between a pair of substrates to make the layer direction uniform in one direction. Thus, a high-speed response and gradation control can be performed, and a high-brightness liquid crystal element excellent in moving image quality can be realized with high mass productivity.
[0008]
Further, the element of the prior application 2 can realize a stable halftone display with small hysteresis and can reduce the spontaneous polarization value as compared with other various smectic liquid crystal modes described above. Is a good element.
[0009]
Further, the present applicant has invented and proposed an element described in Japanese Patent Application No. 11-84639 (hereinafter referred to as "prior application 3"). In the present invention, as the alignment control method of the prior application 1 or 2, an element in which a stripe-like alignment state is formed by appropriately adjusting the alignment control force, thereby achieving a high contrast can be realized.
[0010]
As described above, a chiral smectic liquid crystal, in particular, a liquid crystal display device using the liquid crystal devices of the prior applications 1 to 3, in the sense that the problem relating to the response speed that a TFT liquid crystal display using a nematic liquid crystal has conventionally can be solved. The realization of is expected.
[0011]
[Problems to be solved by the invention]
As described above, the prior application of the smectic liquid crystal element having gradation display capability in next-generation displays such as high-speed response performance is expected.
[0012]
However, with respect to the voltage-transmittance characteristic of the liquid crystal element of the prior application, it has been found that the voltage-transmittance curve A may be driven continuously to cause a phenomenon that the characteristic gradually changes. This characteristic change itself also exists in the conventional SSFLC, and has been studied in various fields from the viewpoint of (1) due to the uneven distribution of impurity ions, and (2) due to the change in orientation.
[0013]
On the other hand, at present, almost no studies have been made on changes in the characteristics of ferroelectric liquid crystal modes other than SSFLC, particularly TFT-driven ferroelectric liquid crystal modes.
[0014]
Therefore, the inventor of the present invention has conducted intensive studies on the characteristic change due to driving of the monostable ferroelectric liquid crystal mode which is the element of the prior application. It has been clarified that the voltage-transmittance characteristic changes due to the occurrence of the phenomenon. Therefore, in order to suppress the display burn-in phenomenon caused by the characteristic change in the element of the prior application, it is considered that the panel is considered to be generated by the asymmetric driving of the liquid crystal element, the asymmetric configuration of the liquid crystal display panel, the asymmetry by the driving of the liquid crystal display panel, and the like. It is necessary to cancel the DC component generated and accumulated inside.
[0015]
The present invention has been made in view of the above problems, and a purpose thereof is to suppress a change in a voltage-transmittance curve without largely changing driving conditions and a driving system in actual use, and to achieve high reliability, and Another object of the present invention is to provide a highly efficient liquid crystal display device.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a chiral smectic liquid crystal, a pair of electrodes for applying a voltage to the liquid crystal, and a pair of electrodes that sandwich and oppose the liquid crystal, and a uniaxial alignment treatment for aligning the liquid crystal is performed. A liquid crystal device comprising a pair of substrates and a polarizer on at least one of the substrates, wherein a phase transition series of the chiral smectic liquid crystal is isotropic liquid phase (ISO.)-Cholesteric from a high temperature side. Phase (Ch) -chiral smectic C phase or isotropic liquid phase (ISO.)-Chiral smectic C phase, wherein at least one of the substrates used for the liquid crystal element is an active element connected to an electrode corresponding to each pixel. The display panel has a first state in which the average molecular axis of the liquid crystal is monostable when no voltage is applied, and the liquid crystal displays the liquid crystal when a voltage of the first polarity is applied. Is tilted to one side from the mono-stabilized position at an angle corresponding to the magnitude of the applied voltage, and when a voltage of a second polarity having a polarity opposite to the first polarity is applied, the A liquid crystal element that tilts at a small angle with respect to the first polarity to an average molecular axis of the liquid crystal from the mono-stabilized position to a side opposite to when a voltage of the first polarity is applied; When driving and displaying the element, the element is driven with the voltage application of the first polarity and the voltage application voltage of the second polarity having a polarity opposite to the first polarity being asymmetric.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0018]
<Embodiment 1>
In the liquid crystal display device of the present invention, the non-uniformity of the pixel potential generated in each pixel by performing the asymmetric driving described above is realized by making the signal input voltage asymmetrical, thereby realizing the driving without the non-uniformity of the pixel potential, and performing display burn-in. The problem can be solved.
[0019]
Hereinafter, an embodiment of the present invention will be described.
[0020]
FIG. 2 schematically shows a part of a configuration diagram of an example of a liquid crystal element used in the present embodiment.
In this configuration, a TFT (thin film transistor) is used as an active element, and a ferroelectric liquid crystal having VT characteristics as shown in FIG. 3 (hereinafter referred to as “one-sided V-shaped liquid crystal”) is used as a liquid crystal modulation element. It is. In FIG. 2, 2 indicates an information signal line (source line), 3 indicates a scanning signal line (gate line), 4 indicates a TFT, and 5 indicates a pixel.
[0021]
In the configuration of FIG. 2, an information signal voltage (source voltage) corresponding to display data is applied from the information signal line drive circuit 6 to the source electrode of the TFT 4 via the information signal line 2. The scanning signal voltage (gate voltage) corresponding to the scanning timing is applied to the gate electrode of the TFT 4 via the scanning signal line 3.
[0022]
The one-sided V-shaped liquid crystal preferably used for the configuration is a ferroelectric liquid crystal mode without a threshold, and as shown in FIG. 3, the transmittance continuously changes with a change in applied voltage, and has a clear threshold. Absent. Therefore, the transmittance can be continuously changed by controlling the voltage applied to the liquid crystal.
[0023]
FIG. 1 shows a color liquid crystal display device according to the present invention, in which a reset waveform having an offset applied thereto is generated from an input color image signal and is displayed on a liquid crystal display panel, thereby achieving a highly reliable burn-in phenomenon (V). FIG. 4 is a block diagram showing a display up to a display without (−t shift).
[0024]
The input component video signal is supplied with an R signal from an input terminal 22, a G signal from an input terminal 23, a B signal from an input terminal 24, and A / D converters 31, 32, and 33. Each performs digital conversion processing.
[0025]
Each of the RGB digital signals output from the A / D converter is subjected to digital conversion processing in each of the γ correction circuits 34, 35, and 36.
[0026]
The RGB digital signals output from the gamma correction circuits 34, 35, 36 are supplied to an offset data generation circuit 41.
[0027]
As described above, in the present embodiment, since one-sided V-shaped liquid crystal is used, the display cannot be performed on one pole, and the drive is normally performed as one frame of the negative field opposite to the positive field. You. That is, it is necessary to drive at twice the period of the normal driving. In the present embodiment, each digital signal input from each input terminal 25-28 of the offset data generation circuit 41 passes through the memory 55 and follows the R signal (positive electrode) waveform input from the output terminal 26, respectively. Then, an R (negative electrode) signal whose gradation level has been corrected based on the offset data shown in FIG. 4 of the offset data generation circuit 41 is output.
[0028]
That is, when the gradation level of the input R signal is 255, data of the gradation level 255 is sent in the positive field which is a write (display) field in the present embodiment, but in the single-sided V-shaped mode. In the negative field serving as the reset field, the reset data as the gradation level 215 is sent to the display 44 at double speed based on the value of the offset data table.
[0029]
Similarly, the G (green) and B (blue) data input to the offset data generation circuit 41 at the same time also correct the reset fields, respectively, and the image data doubled from the output terminals 27 and 28 is output. It is supplied to the display 44.
[0030]
The synchronizing signal F-Sync generated based on the synchronizing signal V-Sync supplied from the input terminal 25 is synchronously separated and input to the liquid crystal display 44 and the light source unit 45, respectively.
[0031]
In the liquid crystal display 44, the input double speed digital signal is converted into an analog signal by a driver IC of the liquid crystal display, and an image is displayed based on the timing of the synchronization signal F-Sync. In other words, each R, G, B (positive) feed and each R, G, B (negative) feed are sequentially displayed within one frame.
[0032]
The light source unit 45 is turned on based on the input synchronization signal F-Sync, and the display 44 performs color display.
[0033]
FIG. 7 is a diagram showing the DC component application amount at the input level of an information signal of a system in which the voltage-transmittance characteristic of the liquid crystal display panel is stable when one-sided V-shaped liquid crystal is used and asymmetric driving is performed.
[0034]
In the driving state in the illustrated embodiment, three conditions of environmental temperature of 10 degrees, 30 degrees, and 50 degrees are set, and a maximum of ± 5 V is applied to a DC component in an information signal input stage. A specific image (fixed pattern such as a black-and-white chart) was changed every 5 V by changing only the voltage level of the reset-side field and continuously displayed for about 5 hours to perform an image sticking durability test. As a result, as shown in FIG. 7, it was clarified that there was a condition in which no change in the voltage-transmittance characteristic was observed under the driving conditions to which a certain DC component was applied under each temperature condition.
[0035]
FIG. 5 is a diagram showing an offset voltage level generated due to asymmetric information signals generated in the present embodiment.
[0036]
A voltage containing an asymmetric DC component as shown in FIG. 5 is output from the information signal line driver 6 shown in FIG. 2 and applied to the source electrode of the TFT. Note that the offset level was determined based on the experimental results shown in FIG.
[0037]
In the asymmetric driving state shown in FIG. 5, a specific image (fixed pattern such as a black-and-white chart) was continuously displayed for about 5 hours, and a burn-in durability test was performed. As a result, the display burn-in phenomenon was not observed at all. That is, due to the asymmetric drive as an external input, no DC component is generated inside the panel, and the shift of the voltage-transmittance characteristic due to the generation of the DC component is completely eliminated, and a stable state can be maintained. It is considered that the reliability against image sticking was greatly improved.
[0038]
<Embodiment 2>
FIG. 6 schematically shows a part of a configuration diagram of an example of a liquid crystal element used in the present embodiment. Also in this configuration, a TFT (thin film transistor) shown in FIG. 2 is used as an active element, and a single-sided V-shaped liquid crystal having VT characteristics as shown in FIG. 3 is used as a liquid crystal modulation element.
[0039]
FIG. 6 shows a color liquid crystal display device according to the present invention, in which the reset data input to the liquid crystal display is modulated according to the input color image signal in accordance with the ambient temperature of the liquid crystal display, and the voltage input to the source electrode of the TFT. FIG. 5 is a block diagram showing a process of driving with offset applied to a display with high reliability and no burn-in phenomenon (Vt shift).
[0040]
For the input component video signal, an R signal is input from an input terminal 52, a G signal is input from an input terminal 53, a B signal is input from an input terminal 54, and the A / D converters 61, 62, and 63 respectively. Perform digital conversion processing.
[0041]
Each of the RGB digital signals output from the A / D converter is subjected to a digital conversion process in each of the γ correction circuits 64, 65, and 66.
[0042]
Each of the RGB digital signals output from the γ correction circuits 64, 65, and 66 is supplied to an offset data generation circuit 71.
[0043]
Also in this embodiment, since one-sided V-shaped liquid crystal is used, it is necessary to drive at twice the cycle as in the first embodiment. Each digital signal input from each input terminal 25-28 of the offset data generating circuit 41 passes through the memory 55, and then the input R signal (positive electrode) is output from the output terminal 26 first. Subsequently, according to the panel temperature information from the offset data generation circuit 71 that has obtained the panel temperature information from the panel temperature sensor 72, the offset data generation circuit 71 shown in FIG. 4 (rst 10 degrees), (rst 30 degrees), and (rst 50 degrees) , And an R (negative electrode) signal whose gradation level has been corrected based on the selected offset table is output.
[0044]
In other words, an optimum offset table is selected according to the response ratio of the rise and fall of the liquid crystal element, which occurs according to the panel temperature. When the table of FIG. Similarly to the case 1, when the gradation level of the input R signal is 255, data of the gradation level 255 is sent in the positive field which is a write (display) field, but the reset field in the one-sided V-shaped mode is used. In the negative field, the reset data as the gradation level 215 is transmitted to the display 44 at double speed based on the value of the offset data table.
[0045]
Further, when a table having a low panel temperature (rst 10 degrees) is selected, and the gradation level of the input R signal is 255, the gradation level in the positive field as a writing (display) field is determined. 255 is transmitted. In the negative field which is a reset field in the one-sided V-shaped mode, reset data as the gradation level 196 is transmitted to the display 44 at a double speed based on the value of the offset data table. Become.
[0046]
Similarly, when the panel temperature is high, the offset data table shown in FIG. 4 (rst 50 degrees) is selected, and when the gradation level of the input R signal is 255, it becomes a write (display) field. In the positive field, data of the gradation level 255 is sent. In the negative field, which is a reset field in the one-sided V-shaped mode, the reset data as the gradation level 215 is twice as fast based on the value of the offset data table. It will be sent to the display 44.
[0047]
Further, similarly, the G (green) and B (blue) data input to the offset data generation circuit 41 at the same time also use the same offset data table, apply a correction to the reset field, and output terminals 57, Image data that is twice as fast as 58 is supplied to the display 74.
[0048]
The synchronizing signal F-Sync generated based on the synchronizing signal V-Sync supplied from the input terminal 59 is synchronously separated and input to the liquid crystal display 74 and the light source unit 75, respectively.
[0049]
In the liquid crystal display 74, the input double-speed digital signal is converted into an analog signal by a driver IC of the liquid crystal display, and an image is displayed based on the timing of the synchronization signal F-Sync. In other words, each R, G, B (positive) feed and each R, G, B (negative) feed are sequentially displayed within one frame.
[0050]
The light source unit 75 is turned on based on the input synchronization signal F-Sync, and the display 74 performs color display.
[0051]
In the driving state in the above-described embodiment, a specific image (fixed pattern such as a black-and-white chart) is continuously displayed for about 5 hours under the three conditions of the environmental temperature of 10 degrees, 30 degrees, and 50 degrees to perform a seizure durability test. Was. As a result, the display burn-in phenomenon was not observed at all under any conditions. Therefore, it is possible to compensate for the temperature characteristics of the liquid crystal element by performing asymmetric driving by changing the level according to the use environment, and no DC component is generated inside the panel, and the voltage-transmittance characteristic is not improved. It is considered that the shift completely disappeared and the reliability against burn-in was greatly improved in an environment temperature at which the liquid crystal element could be driven.
[0052]
Further, in the present embodiment, three patterns of offset data tables are prepared, but it is desirable that the number of data tables is adjusted and used according to the temperature characteristic performance of the liquid crystal display element.
[0053]
In addition, in the first and second embodiments, most of the asymmetric drive data processing is performed outside the panel and further performed in the state of 256 digital signals, which is the stage of image data. There is no problem even if it is performed, and more precise control can be performed by processing as a higher bit, for example, a 10-bit digital signal.
[0054]
Further, in the present embodiment, three patterns of offset data tables are prepared, but it is desirable that the number of data tables is adjusted and used according to the temperature characteristic performance of the liquid crystal display element.
[0055]
In addition, in the first and second embodiments, most of the asymmetric drive data processing is performed outside the panel and further performed in the state of 256 digital signals, which is the stage of image data. There is no problem even if it is performed, and more precise control can be performed by processing as a higher bit, for example, a 10-bit digital signal.
[0056]
<Embodiment 3>
In the present embodiment, a description will be given of a form in which the display is realized with high efficiency and high reliability by modulating the selection time of the write field and the reset field, and modulating the reset voltage.
[0057]
Also in the present embodiment, similarly to the first embodiment, in the color liquid crystal display device in FIG. 1, a reset waveform with an offset applied thereto is generated from an input color image signal and displayed on the liquid crystal display panel. 5 is a block diagram showing a process leading to a display with high reliability and no burn-in phenomenon (Vt shift).
[0058]
The input component video signal is supplied with an R signal from an input terminal 22, a G signal from an input terminal 23, a B signal from an input terminal 24, and A / D converters 31, 32, and 33. Each performs digital conversion processing.
[0059]
Each of the RGB digital signals output from the A / D converter is subjected to digital conversion processing in each of the γ correction circuits 34, 35, and 36.
[0060]
The RGB digital signals output from the gamma correction circuits 34, 35, 36 are supplied to an offset data generation circuit 41.
[0061]
As described above, in the present embodiment, since one-sided V-shaped liquid crystal is used, display can be performed only on one pole. Therefore, the driving is performed as one frame including the normal positive field and the opposite negative field. That is, it is necessary to drive at twice the frame period of the normal driving. Further, in the present embodiment, the time division ratio of the write field: reset field is set to 6: 4.
[0062]
FIG. 8 is a diagram schematically showing vertical scanning of a write field and a reset field in the present embodiment.
[0063]
As shown in FIG. 8, the temporal constraint of one vertical scanning time is that the reset writing side where the one vertical scanning time is short,
Reset field-vertical scanning time = 1 / field frequency * 4/10
It will be decided by.
[0064]
Furthermore,
One horizontal scanning time (1H time) = reset field one vertical scanning time / vertical resolution
Can be determined by
[0065]
Therefore, one vertical scan of the write field is also made equal to one vertical scan time of the reset field, and a blanking period is provided after the vertical scan of the write field. Data processing can be performed in the vertical scanning time.
[0066]
Next, in the present embodiment, each digital signal input from each input terminal 25-28 of the offset data generation circuit 41 passes through the memory 55, and the R signal (positive electrode) input from the output terminal 26, respectively. Following the waveform, an R (negative electrode) signal whose gradation level has been corrected based on the offset data shown in FIG. 4 of the offset data generation circuit 41 and the voltage drop data caused by spontaneous polarization inversion is output.
[0067]
In the present embodiment, the dynamic range of the information signal is determined so that the time integral of the input voltage in one field becomes equal based on the time ratio of each subfield of the write field and the reset field. When the source potential of the reset field is 0 V to 5 V and the gradation of 0 to 255 is expressed, the source potential of the reset field is
Write field time: reset field time = 6: 4
From 0V to -7.5V.
[0068]
Therefore, when the gradation level of the input R signal is 255, data of the gradation level 255 is sent in the positive field which is a write (display) field in the present embodiment, but in the single-sided V-shaped mode. In the negative field serving as the reset field, reset data as the gradation level 216 is set to 2. based on the value of the offset data table and the voltage drop data caused by the Ps inversion. It will be sent to the display 44 at 5 × speed.
[0069]
Further, similarly, the G (green) and B (blue) data input to the offset data generation circuit 41 at the same time also correct the reset field, respectively. The image data at 5 × speed is supplied to the display 44.
[0070]
The synchronizing signal F-Sync generated based on the synchronizing signal V-Sync supplied from the input terminal 25 is synchronously separated and input to the liquid crystal display 44 and the light source unit 45, respectively.
[0071]
In the liquid crystal display 44, the input 2.. The quintuple-speed digital signal is converted into an analog signal by the driver IC of the liquid crystal display, and an image is displayed based on the timing of the synchronization signal F-Sync. That is, the image is sequentially displayed in the positive field and the negative field in one frame.
[0072]
The light source unit 45 is turned on based on the input synchronization signal F-Sync, and the display 44 performs color display.
[0073]
In the driving sequence of FIG. 8 described above, a specific image (fixed pattern such as a black and white chart) is continuously displayed for about 5 hours in an asymmetric driving state in consideration of FIGS. went. As a result, the display burn-in phenomenon was not observed at all. In other words, even when the selection time ratio between the write field and the reset field is changed, no DC component is generated inside the panel by the asymmetric drive as the optimal external input, and the voltage due to the DC component is generated. -It is considered that the shift of the transmittance characteristic completely disappeared, the stable state could be maintained, and a display with high reliability against burn-in was realized.
[0074]
Further, by setting the selection time ratio between the writing field and the reset field to 6: 4, the maximum transmitted light amount was successfully increased to 1.2 times. To obtain the same amount of transmitted light as that of a conventional liquid crystal display device in which the selection time ratio between the write field and the reset field is 5: 5, power saving of the signal line drive voltage of the write field is performed from 5 V to 3.3 V. And efficient driving was realized.
[0075]
In the present embodiment, when performing asymmetric driving, it is assumed that the time integration of the execution voltage within one field period does not change even if the selection time ratio between the writing field and the reset field is changed, and the asymmetric driving is performed by the modulation of the reset voltage. Drive was performed. However, in a system in which the charge amount of the DC component is small during the symmetric drive shown in FIGS. 5 and 7, or when the charge amount of the DC component is substantially constant without being related to the drive voltage, the write field and the write field are determined based on this. It is also possible to adjust the selection time ratio of the reset field and asymmetrical the time integration of the execution voltage within one field period to cancel the internal DC component.
[0076]
In the first to third embodiments, most of the asymmetric drive data processing is performed outside the panel and further performed in the state of 256 digital signals, which is the stage of image data. There is no problem, and more precise control can be performed by processing as a higher bit, for example, a 10-bit digital signal.
[0077]
In the present embodiment, the offset data generation is digitally processed. However, it is also possible to perform analog processing, and there is no problem in performing collective correction by a reference voltage generation circuit that performs γ correction processing of liquid crystal. However, it is necessary to use them properly depending on the specifications and cost of the product to be aimed at.
[0078]
【The invention's effect】
As apparent from the above description, according to the present invention, the drive voltage of the write field and the reset field and each selection time ratio are modulated to make the time integral value of the voltage as an external input asymmetrical and generated inside the panel. Since the DC component is canceled, it is possible to achieve an effect that high-efficiency and highly reliable driving without burn-in of one-sided V-shaped liquid crystal can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a schematic plan view illustrating a configuration of a display panel according to one embodiment of the present invention.
FIG. 3 is a diagram showing voltage-transmittance characteristics of a liquid crystal display element according to one embodiment of the present invention.
FIG. 4 is a diagram showing input-output characteristics of information signals on a write drive side and a reset drive side in the display device according to the embodiment of the present invention.
FIG. 5 is a diagram showing a DC component applied to the inside of a panel when asymmetrical driving according to the present invention is performed using one-sided V-shaped liquid crystal.
FIG. 6 is a schematic diagram showing a configuration of a display panel which is one mode of another embodiment of the present invention.
FIG. 7 is a diagram showing a DC component application amount at an input level of an information signal of a system in which a voltage-transmittance characteristic of a liquid crystal display panel is stable when one-sided V-shaped liquid crystal is used and asymmetric driving is performed.
FIG. 8 is a diagram showing an example of one vertical scanning time when a subfield asymmetric time division drive according to the present invention is performed using one-sided V-shaped liquid crystal.
FIG. 9 is a diagram illustrating a drop amount of a drain potential due to spontaneous polarization reversal when one-sided V-shaped liquid crystal is used and driven by a TFT array substrate.
[Explanation of symbols]
1 Display panel
2 Source electrode line
3 Gate electrode line
4 TFT
5 Display pixels
6 Source line driver
7 Gate line driver
31-33, 61-63 A / D converter
41, 71 offset data generation circuit
44,74 color liquid crystal display
45,75 light source unit
55,73 memory
72 Temperature sensor

Claims (15)

A chiral smectic liquid crystal, a pair of electrodes that apply a voltage to the liquid crystal, and a pair of substrates that face each other while sandwiching the liquid crystal and that have been subjected to a uniaxial alignment process for aligning the liquid crystal; A liquid crystal element comprising a polarizing plate on a substrate,
The phase transition series of the chiral smectic liquid crystal is an isotropic liquid phase (ISO.)-Cholesteric phase (Ch) -chiral smectic C phase or an isotropic liquid phase (ISO.)-Chiral smectic C phase from a high temperature side. So,
At least one of the substrates used for the liquid crystal element has an active element connected to an electrode corresponding to each pixel,
When no voltage is applied, the display panel shows a first state in which the average molecular axis of the liquid crystal is monostable, and when a voltage of the first polarity is applied, the average molecular axis of the liquid crystal is large in magnitude of the applied voltage. The tilt is tilted to one side from the monostable position at an angle corresponding to the angle, and when a voltage of a second polarity having a polarity opposite to the first polarity is applied, the average molecular axis of the liquid crystal becomes the monostable. A liquid crystal element that tilts at a small angle with respect to the first polarity on the side opposite to when a voltage of the first polarity is applied from the converted position,
The liquid crystal device is characterized in that, when driving and displaying the liquid crystal element, the liquid crystal element is driven with the voltage application of the first polarity and the voltage application voltage of the second polarity opposite to the first polarity being asymmetric. Display device. 2. The asymmetrical voltage drive according to claim 1, wherein a DC component generation direction and a level of the asymmetric drive for generating a DC component are generated and applied to cancel a DC component generated inside the liquid crystal panel in the symmetric drive. Liquid crystal display. In the asymmetric driving method, the method of generating a DC component includes adjusting an applied voltage from a position where the average molecular axis of the liquid crystal is tilted at a small angle with respect to the first polarity from the position where the monostable state is applied to the second polarity. 3. The liquid crystal display device according to claim 1, wherein the modulation is performed. In the asymmetric driving method, the method of generating a DC component includes selecting a first polarity and a second polarity in which the average molecular axis of the liquid crystal tilts at a small angle with respect to the first polarity from the stabilized position. 3. The liquid crystal display device according to claim 1, wherein time is adjusted and modulated. In the asymmetric driving method, the method of generating a DC component includes selecting a first polarity and a second polarity in which the average molecular axis of the liquid crystal tilts at a small angle with respect to the first polarity from the stabilized position. 3. The liquid crystal display device according to claim 1, wherein a time is adjusted and modulated uniformly, and a voltage applied to the second polarity is adjusted and modulated. 4. The liquid crystal according to claim 1, wherein a DC component applied by the applied asymmetric drive voltage increases in proportion to an information signal level input from outside the liquid crystal panel with a certain threshold value. Display device. The DC component applied by the asymmetric drive voltage is changed to a display gradation level to compensate for a non-linear DC component generated in the liquid crystal panel when an information signal is output to display all gradations during symmetric drive. The liquid crystal display device according to claim 1, wherein the liquid crystal display device applies a non-linear correction according to the correction. The first polarity selection time and the second polarity selection time change the selection time ratio between the first polarity selection subframe (field) and the second polarity selection subframe (field) within one frame, The liquid crystal display device according to claim 4, wherein modulation is performed. The dynamic range of the information signal voltage of the second polarity depends on the selection time ratio between the first polarity selection time and the second polarity selection time in one frame, and the dynamic range of the first polarity and the second polarity selection time in one field period. 6. The liquid crystal display device according to claim 4, wherein time integration values applied to the two polarities are equal. 10. The liquid crystal display device according to claim 4, wherein the voltage control corrects a voltage drop due to spontaneous polarization reversal of the display liquid crystal. In the voltage control method, the time integral value of the execution voltage input to the information signal line including the voltage drop due to the spontaneous polarization reversal of the first polarity and the voltage drop due to the spontaneous polarization reversal of the second polarity becomes equal. The liquid crystal display device according to any one of claims 4, 5, 9, and 10, wherein 10. A voltage drop control method based on spontaneous polarization reversal, comprising a voltage drop compensation table having at least a plurality of compensation points, and performing different control according to an information line input voltage. 11. The liquid crystal display device according to any one of items 10 to 10. 8. The liquid crystal display device according to claim 1, wherein the DC component applied by the asymmetric drive voltage can be controlled differently according to the environmental temperature of the liquid crystal display panel. 14. The liquid crystal display device according to claim 13, wherein the asymmetric drive voltage control method according to the use environment temperature has a plurality of asymmetric drive compensation tables, and selects and compensates the table according to the environment temperature. In the asymmetric voltage control method, the γ correction and the asymmetric drive voltage compensation are performed in advance so that the γ correction circuit (reference voltage correction circuit) mounted to compensate for the voltage-transmittance characteristic of the liquid crystal display element collectively. 15. The liquid crystal display device according to claim 6, further comprising a compensation table set to output the set value, and controlling the asymmetric drive voltage.

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