JP2004063551A - Semiconductor element surface protecting film and semiconductor element unit - Google Patents

Semiconductor element surface protecting film and semiconductor element unit Download PDF

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Publication number
JP2004063551A
JP2004063551A JP2002216391A JP2002216391A JP2004063551A JP 2004063551 A JP2004063551 A JP 2004063551A JP 2002216391 A JP2002216391 A JP 2002216391A JP 2002216391 A JP2002216391 A JP 2002216391A JP 2004063551 A JP2004063551 A JP 2004063551A
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Prior art keywords
film
semiconductor element
semiconductor
protecting
resin
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Inventor
Hiroshi Kirihara
桐原　博
Yoichi Hosokawa
細川　羊一
Michio Uruno
宇留野　道生
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor element surface protecting film and a semiconductor element unit excellent in protection property of a semiconductor element surface and invisibility by means of laser markings. <P>SOLUTION: There is provided a film 4 used for the semiconductor element 3 whose circuit surface is arranged toward a side of semiconductor interconnection substrate 1 and further used for protecting a face side opposed to the circuit surface of the semiconductor element 3. A coloring agent different in color from that of the opaque film 4 is contained in the opaque film4. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、例えば、回路面が半導体配線基板側に向けて配置されるフェイスダウン構造の半導体装置に適用され、半導体素子の表面を保護するための半導体素子表面保護用フィルム及び本半導体素子表面保護用フィルムを使用した半導体素子ユニットに関する。
【０００２】
【従来の技術】
従来から、電子機器の小型化・軽量化が進められており、これに伴い基板への高密度実装が要求され、電子機器に搭載する半導体パッケージの小型化・軽量化が進められている。
【０００３】
半導体パッケージは、時代の変遷とともに各種変化しており、従来、ＬＯＣ（Ｌｅａｄ　Ｏｎ　Ｃｈｉｐ）やＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）等と呼ばれるパッケージがあり、例えば、１６Ｍ以降のＤＲＡＭでは、ＬＯＣのパッケージが使用されている。
【０００４】
通常、パッケージには、製品を識別するためにロットナンバーやメーカー名などの識別情報を印字しており、製品がどのように作製されたかが判別できるようになっている。そして、ＬＯＣやＱＦＰ等のパッケージの場合には、パッケージ外面に形成された封止材に、製品を判別するための識別情報を直接レーザーマーキングしていた。
【０００５】
レーザーマーキングに使用されるレーザーとしては、炭酸ガスレーザーとＹＡＧレーザーとがあり、封止材にレーザーマーキングをする際には、主に、ＹＡＧレーザーが使用されている。ＹＡＧレーザーを使用して封止材にレーザーマーキングする方法の原理について、以下、図１０（ａ）〜図１０（ｃ）を用いて簡単に説明する。
【０００６】
図１０（ａ）は、レーザーマーキングを行う被処理材である封止材２０の断面を示す図であり、本図に示すように、樹脂２１中にはシリカフィラー２２及び顔料（カーボン）２３が均一に分散されている。
【０００７】
封止材２０の表面側からＹＡＧレーザー２４を照射すると、図１０（ｂ）に示すように、レーザーを照射した部位に存在するカーボンの粒２３ａ，２３ｂ，２３ｃが、レーザーの波長に応じて選択的に熱せられる。
【０００８】
すると、図１０（ｃ）に示すように、カーボン粒２３ａ，２３ｂ，２３ｃがその周囲の樹脂２１とともに蒸発し、樹脂２１中にシリカフィラー２２のみが残る。カーボンが蒸発した後の色が白色であるため、レーザー照射位置が、白くマーキングされているように見える。このようにして封止材上にレーザーマーキングが行われる。
【０００９】
近年、半導体パッケージの小型化・軽量化がより一層進められており、上述したＬＯＣやＱＦＰ等のパッケージよりもさらに小型化・軽量化したＣＳＰ（ＣｈｉｐＳｉｚｅ　Ｐａｃｋａｇｅ）やμＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）等のパッケージの開発が行われている。このようなパッケージでは、半導体素子と基板とを接続する配線を半導体素子の中央部に配置してその部分のみを封止しているため、従来における半導体素子の全体を封止材により封止した形状と比べ、より一層パッケージの小型化・軽量化を図ることができる。
【００１０】
【発明が解決しようとする課題】
しかしながら、上述したパッケージでは、小型化・軽量化を図ることができるが、半導体素子がフェイスダウン型となっており、つまり、半導体素子の回路面が半導体配線基板側に向けられ、パッケージの上部に半導体素子の裏面が露出している形状であるため、パッケージを製造し、あるいは、パッケージを搬送する時に、半導体素子の端部が欠けてしまう等の問題を有していた。
【００１１】
また、特に、ＣＳＰなどのパッケージの中には、封止材により封止していない形状のものもあるため、半導体素子に直接レーザーマーキングするか、あるいは、半導体素子に直接印刷することにより、製品を判別するための識別情報を印字していた。
【００１２】
しかし、半導体素子に直接レーザーマーキングをした場合には、半導体素子と識別情報との明確なコントラストが出ないため、半導体素子とマーキングとの識別力が低く、視認性が悪いという問題を有していた。
【００１３】
また、半導体素子に直接印刷することにより識別情報のマーキングをした場合には、半導体素子上に識別情報を明確に表示できるため、半導体素子と識別情報との識別性が高いという利点を有する。しかし、印刷によると工程数が多いため、識別情報を印字するための作業時間が大幅に増大してしまうという問題を有していた。
【００１４】
さらに、封止材により封止しない形状のＣＳＰ等のパッケージにあっては、保護膜を形成する方法や、あるいは、保護フィルムを貼り付ける等の方法を用いて半導体素子の表面を保護している。このような保護膜または保護フィルムとしては、例えば、透明または半透明の膜またはフィルムが使用されている。この理由は、半導体に用いられる材料はイオン性不純物の析出を嫌うため不純物の混入はできるだけ避けているというのが現状であり、また、材料中にイオン補足剤を導入してイオン性不純物の析出を防止しており、顔料及び染料といった不純物の混入をしないことが前提となっているためである。このため、透明あるいは半透明の膜またはフィルムに直接レーザーを照射して製品を判別する識別情報を表示した場合であってもレーザーマーキングの視認性は劣っていた。
【００１５】
本発明は、上述した問題を解決するためになされたものであり、半導体素子表面の保護特性およびレーザーマーキングによる視認性が優れた半導体素子表面保護用フィルム及び半導体素子ユニットを得ることを目的とする。
【００１６】
【課題を解決するための手段】
上記目的を解決すべく種々研究し、回路面と対向する面側の半導体素子の表面にフィルムを被覆して半導体素子の表面を保護すると共に、不透明なフィルム中にフィルムの色とは異なる着色剤を添加して、フィルムに識別情報を表示する際、レーザーを照射して着色剤を揮発させて、レーザー照射によるマーキング部と非マーキング部との色の差を明確とすることにより、レーザーマーキングの視認性が優れた半導体素子表面保護用フィルム及びこの半導体素子表面保護用フィルムを使用した半導体素子ユニットを得たものである。
【００１７】
すなわち、本発明は、回路面が半導体配線基板側に向けて配置される半導体素子に使用され、かつ、当該半導体素子の回路面と対向する面側を保護するためのフィルムであって、不透明なフィルム中に当該フィルムとは色が異なる着色剤が含有されていることを特徴とする。
【００１８】
また、上記発明において、フィルムに着色剤が含有されており、当該着色剤の含有量が、フィルムに対して０．１〜１０質量％であることを特徴とする。
【００１９】
さらに、上記発明において、フィルムに白色のフィラーが含有されており、当該白色のフィラーの含有量が、１〜７０質量％であることを特徴とする。
【００２０】
また、上記発明において、着色剤は、カーボンフィラーであることを特徴とする。
【００２１】
上記発明において、フィルムの２５℃における弾性率が、２０〜２０００ＭＰａであることを特徴とする。
【００２２】
また、フィルムの厚さが、２５〜２００μｍであることを特徴とする。
【００２３】
本発明の半導体素子ユニットは、回路面が半導体配線基板側に向けて配置される半導体素子と、当該半導体素子の回路面と対向する面側に形成され、不透明なフィルム中に当該フィルムとは色が異なる着色剤が含有された半導体素子表面保護用フィルムと、を備えることを特徴とする。
【００２４】
また、上記半導体素子ユニットの半導体素子表面保護用フィルムが、上記記載の半導体素子表面保護用フィルムであることを特徴とする。
【００２５】
【発明の実施の形態】
以下、本発明の実施形態について図１〜図９、表１及び表２を用いて説明する。
【００２６】
図１は、本発明の半導体表面保護用フィルムを適用した半導体装置の一部の断面を示す図である。図１に示すように、半導体配線基板１上に樹脂等の接着剤から成る接着剤層２を介して半導体素子３が搭載されており、半導体素子３の回路面は半導体配線基板１側に向けて配置されるとともに、半導体素子３の回路面と対向する面側には半導体素子表面保護用フィルム４が被覆形成されている。半導体配線基板１及び接着剤層２の中央部には、半導体配線基板１の配線の一部と半導体素子のボンディングパッドとを各端部とする接続部材５がボンディングされており、ボンディング部位の周囲は封止材６により封止されている。また、半導体配線基板１の裏面には配線７を介して外部接続端子８が接続されている。
【００２７】
上記構成の半導体装置に適用される本発明の半導体素子ユニットＡは、図２の断面図に示すように、半導体素子３の表面上に半導体素子表面保護用フィルムが被覆形成される。この半導体素子表面保護用フィルム４は、通常、図３の断面図に示すように３層構造のフィルムを有しており、半導体素子表面保護用フィルム４の両面に、ベースフィルム９および保護フィルム１０が各々形成されている。なお、保護フィルム１０は半導体素子表面保護用フィルム４の種類に応じて形成され、保護フィルム１０が必ず形成されるものではない。
【００２８】
本発明の半導体素子表面保護用フィルム４に使用する樹脂としては、半導体素子３がリフロー温度にさらされたときに剥離することがない半導体素子３との接着力を有していれば特に成分に制限はなく、例えば、ポリイミド樹脂、ポリアミド樹脂、ポリエーテルスルホン樹脂、ポリアミドイミド樹脂等の熱可塑性樹脂、エポキシ樹脂、ビスマレイミド樹脂、シアネート樹脂、フェノール樹脂、ポリウレタン樹脂等の熱硬化性樹脂またはそれらを含有する接着剤及びその混合物を使用することができる。また、ベースフィルム９としては耐熱フィルムを使用することができ、ベースフィルム９の表面は、例えば、シリコーン等で離型処理することが好ましい。
【００２９】
また、半導体素子表面保護用フィルム４に使用する樹脂に含まれる着色剤としては、例えば、カーボンブラック、黒鉛、チタンカーボン、二酸化マンガン、フタロシアニン系等の顔料及び染料を用いることができる。半導体素子表面保護用フィルム４に含有する着色剤の含有量は、０．１〜１０質量％が好ましく、より好ましくは０．５〜２．０質量％である。着色剤の含有量が０．１質量％以下になると、フィルムに色が付かずレーザーマーキング後の視認性が悪くなり、逆に、着色剤の含有量が１０質量％以上になると、イオン性不純物の増加、フィルム延性の低下または半導体素子との接着強度の低下等の問題が発生してしまうからである。
【００３０】
また、レーザーマーキングに使用されるレーザーは、ＹＡＧレーザーであることが多いため、着色剤としてＹＡＧレーザーにより揮発し易いカーボンブラックを使用することが好ましい。
【００３１】
さらに、半導体素子表面保護用フィルム４に使用する樹脂に含まれる白色フィラーとしては、例えば、結晶性シリカ、非晶性シリカ、酸化アルミニウム、炭酸カルシウム、炭酸マグネシウム、窒化アルミニウム、窒化ホウ素等が挙げられる。また、白色フィラーの含有量は１〜７０質量％とすることが好ましく、特に、５〜５０質量％とすることが好ましい。白色フィラーの含有量が１質量％以下になると、レーザーマーキングにより着色剤が揮発した後に、半導体素子表面保護用フィルム４の色が白くならず、レーザーマーキングした後の視認性が悪くなり、逆に、白色フィラーの含有量が７０質量％以上になると、半導体素子表面保護用フィルム４がもろくなり成形性が低下し、シリコンウエハとの接着強度の低下等の問題が発生するためである。
【００３２】
また、半導体素子表面保護用フィルム４の樹脂中の着色剤と白色フィラーとの割合は、適宜調整することができる。例えば、マーキングのかすれが生じた場合には、着色剤の含有量を増加させると良く、コントラストが不足している場合には、白色フィラーの含有量を増加させると良い。また、すすが出やすい場合には、着色剤の含有量を低下させてレーザーマーキングを行うことができる。
【００３３】
上記３層構造のフィルムは、例えば、耐熱性フィルムから成るベースフィルム９上に接着フィルムの形成する材料のワニスを塗布した後、加熱乾燥し、その後、溶剤を除去して形成される。このときの加熱乾燥条件は、使用するフィルムの成分やワニスの溶媒等によって異なるが、一般的には７０〜２００℃の温度により３〜３０分間加熱するものである。
【００３４】
また、このような接着フィルムを使用して半導体素子３上に半導体素子表面保護用フィルムを形成する場合には、半導体素子に負荷を与えず、作業性に優れる点で、半導体素子３への接着可能な温度が１８０℃以下であることが好ましく、１４０℃以下であることがより好ましい。
【００３５】
さらに、本発明の半導体素子表面保護用フィルム４の厚さは、２５〜２００μｍであることが好ましく、特に、５０〜１００μｍであることがより好ましい。半導体素子表面保護用フィルム４の厚さが２５μｍ以下になると半導体素子３の欠けの原因となる衝撃を吸収しきれないため、半導体素子３を保護する保護フィルムとしての特性が低下し、逆に、半導体素子表面保護用フィルムの厚さが２００μｍ以上になると、パッケージ全体の厚さが増えてパッケージ設計の障害になるからである。
【００３６】
本発明の半導体素子表面保護用フィルム４は、２５℃での弾性率が２０〜２０００ＭＰａであることが好ましく、５０〜１０００ＭＰａであることがより好ましい。弾性率が２０ＭＰａ以下になると半導体素子表面保護用フィルム４にタック性が残り、搬送中にフィルム同士が貼り付く、またはフィルムに埃が貼り付くなどして作業性の低下、不純物の増加に繋がるからである。逆に、弾性率が２０００ＭＰａ以上になると、半導体素子表面保護用フィルム４を成形し、貼り付けた後に半導体素子３にそりが発生し、パッケージの信頼性の悪化、作業性の低下等の問題が発生するからである。
【００３７】
上記３層構造のフィルムに含まれる半導体素子表面保護用フィルム４を使用して、半導体装置を製造する手順について図４〜図９を用いて説明する。
【００３８】
まず、３層構造から成るフィルムの保護フィルム１０を剥離し、図４に示すように、ベースフィルム９の付いた半導体素子表面保護用フィルム４を半導体素子３であるシリコンウエハ上にヒートプレス、ラミネーター等で圧着して半導体表面保護用フィルム４を形成する。その後、ベースフィルム９を剥離する。ここで、半導体素子表面保護用フィルム４が熱硬化性樹脂の場合は必要に応じてフィルムの硬化を行う。その後、図５に示すようにウエハをダイシンングした後、図６に示すように接着剤から成る接着剤層１１を介してＴＡＢ１２を貼り付ける。さらに、図７に示すようにワイヤボンディング及び半田ボール付けをする。その後、図８に示すように、半導体素子表面保護用フィルム４側からＹＡＧレーザーを照射し、製品を判別するための識別情報を表示した後、図９に示すように、実装基板１５上に設置して半導体装置が形成される。
【００３９】
また、半導体表面保護用フィルム４を形成する方法は、上述したフィルムラミネートやヒートプレス等による方法に限定されるものではなく、半導体表面保護用フィルム４の原材料を溶剤に溶解したワニスをウエハの上にスピンコーター、バーコーター等によって塗布し、加熱乾燥し、溶剤を除去して、直接シリコンウエア上に製膜することができる。なお、この時のスピンコート条件及び加熱乾燥条件は使用するフィルム成分、ワニスの溶媒によって異なるが、一般に７０〜２００℃、３〜３０分である。なお、スピンコーターによりウエハ上に半導体表面保護用フィルム４を製膜する場合には、前述した樹脂中で接着性を有していない樹脂でも半導体素子３がリフロー温度にさらされたときに剥離することがない半導体素子３との接着力を有していれば使用することができる。
【００４０】
上述したように、ＹＡＧレーザーの照射により識別情報をマーキングしているが、本発明は、着色剤を含有させて着色した半導体素子表面保護用フィルム４を使用したため、レーザーマーキングを行った後の視認性が良好である。また、フィルムの視認性は、画像処理装置を用いてマーキング部と非マーキング部の正反射光強度を２５６段階に数値化し、その数値の差を比較することにより、視認性の評価を行った。また、良好な視認性を得るためには反射光強度の差が４０以上必要であり、６０以上であれば特に好ましい。
【００４１】
以下、例１〜例８を用いて、さらに具体的に説明する。
【００４２】
例１
エポキシ樹脂としてビスフェノールＡ型エポキシ樹脂（エポキシ当量１７５、東都化成株式会社製のＹＤ−８１２５を使用）６０重量部、フェノールノボラック型のエポキシ樹脂（東都化成株式会社製のＹＤＣＮ−７０３を使用）５重量部、硬化剤としてビスフェノールＡノボラック樹脂（大日本インキ製のＬＦ−２８８２を使用）３５重量部、白色フィラーとしてシリコンフィラー（株式会社アドマテックス製のアドマファインＳＯ−Ｃ２を使用）３０重量部、着色剤としてカーボンブラックを含有した樹脂系加工顔料（御国色素のＣＦブラックＨＧＢＫ−０２）を３５重量部、溶剤としてシクロヘキサノン３０重量部をビーズミルにより混合したワニスに、エポキシ基含有アクリル系共重合体としてエポキシ基含有アクリルゴム（分子量１００万、帝国化学産業株式会社製のＨＴＲ−８６０Ｐ−３）２３０重量部、硬化促進剤として１−シアノエチル−２−フェニルイミダゾール（キュアゾール２ＰＺ−ＣＮを使用）０．５重量部からなる成分に溶剤としてシクロヘキサノンを１７００重量部加えて攪拌混合し、半導体素子表面保護用ワニスを得た。（これをワニスＡとする）
得られたワニスＡを離型剤付きのベースフィルム（帝人製ピューレックスＡ３１）上に５０μｍ厚みで塗工し、ベースフィルム付き接着フィルムを得た。この接着フィルムをシリコンウエハの裏面に１２０℃でラミネートし、シリコンウエハ上に形成された半導体素子表面保護用フィルムを得た。
【００４３】
例２
本例では、例１に示したワニスを乾燥後の厚さが４５〜５５μｍになるようにシリコンウエハの裏面にスピンコートによって製膜した後、１４０℃で５分乾燥してシリコンウエハ上に半導体素子表面保護用フィルムを形成した。
【００４４】
例３
エポキシ樹脂としてビスフェノールＡ型エポキシ樹脂（エポキシ当量１７５、東都化成株式会社製のＹＤ−８１２５を使用）５０重量部、フェノールノボラック型のエポキシ樹脂（東都化成株式会社製のＹＤＣＮ−７０３を使用）１５重量部、硬化剤としてビスフェノールＡノボラック樹脂（大日本インキ製のＬＦ−２８８２を使用）２０重量部、フェノキシ樹脂としてビスフェノール型フェノキシ樹脂（東都化成株式会社製のＹＰ−５０を使用）１５重量部、着色剤としてカーボンブラックを含有した樹脂系加工顔料（御国色素のＣＦブラックＨＧＢＫ−０２）を３５重量部、溶剤としてシクロヘキサノン３０重量部をビーズミルにより混合したワニスに、エポキシ基含有アクリル系共重合体としてエポキシ基含有アクリルゴム（分子量１００万、帝国化学産業株式会社製のＨＴＲ−８６０Ｐ−３）２３０重量部、硬化促進剤として１−シアノエチル−２−フェニルイミダゾール（キュアゾール２ＰＺ−ＣＮを使用）０．５重量部からなる成分に溶剤としてシクロヘキサノンを１７００重量部加えて攪拌混合し、半導体素子表面保護用ワニスを得た。（これをワニスＢとする）
このフィルムは樹脂自体が乳白色であるため、シリコンフィラーを含有させなかった。その他は、例１と同様の方法を用いて半導体素子表面保護用フィルムを形成した。
【００４５】
例４
例１に示すワニス組成のうちシリコンフィラーの含有量を８０質量％としてワニスを作製し、その他は例１と同じ手順を用いて、シリコンウエハ上に半導体素子表面保護用フィルムを形成した。
【００４６】
例５
例１に示すワニス組成のうち樹脂系加工顔料の含有量を２０質量％としてワニスを作製し、その他は例１と同じ手順を用いて、シリコンウエハ上に半導体素子表面保護用フィルムを形成した。
【００４７】
例６
例１と同様にしてシリコンウエハ上に半導体素子表面保護用フィルムを形成したものであるが、フィルムの厚さを１５μｍとした。
【００４８】
例７
本例では、例１に示すワニス組成のうちシリコンフィラーを含有しなかった。その他は例１と同じ手順を用いてシリコンウエハ上に半導体素子表面保護用フィルムを形成した。
【００４９】
例８
本例では、例１に示すワニスの組成のうち樹脂系加工顔料の含有量を０．０５質量％としてワニスを作製し、その他は例１と同じ手順を用いてシリコンウエハ上に半導体素子表面保護用フィルムを形成した。
【００５０】
上記例１〜例８で使用した各フィルムの配合及び特性を示す。
【００５１】
【表１】

Figure 2004063551
【００５２】
得られた各半導体素子表面保護用フィルムを硬化した後、出力５．０Ｊ／パルスのＹＡＧレーザーによりレーザーマーキングを行って視認性を確認した。なお、視認性の評価は、レーザーマーキング後のフィルム表面をスキャナによって画像取り込みを行い、画像処理ソフト（Ａｄｏｂｅ社製ＰＨＯＴＯＳＨＯＰ）によってマーキング部分及びその周りの非マーキング部分の２階調化を行う。この操作により、画像は明度によって白黒の２５６段階に分けられる。次に、マーキング部分が白く、非マーキング部分が黒く表示される「２階調化する境界のしきい値」と、マーキング部分も黒く表示されマーキング／非マーキング部分の境界が無くなる「２階調化する境界のしきい値」の値を求め、その差が４０以上である場合に視認性が良好であるとし（○）、その差が３０以上４０未満である場合に視認性がほぼ良好であるとし（△）、その差が３０未満である場合に視認性が不良である（×）として評価を行った。評価結果を表２に示す。
【００５３】
また、上述した例１〜例８の各組成材料及び製造方法を用いて、フィルム試験片を各々作製した。なお、各フィルム試験片のサイズは、３ｍｍ×２０ｍｍとし、各フィルム試験片について、試験条件を昇温速度２℃／分、測定温度２０〜２００℃として弾性率を測定した。測定結果を表２に示す。
【００５４】
【表２】
Figure 2004063551
【００５５】
表２に示すように、例１〜例３は視認性に優れ、チップ保護膜としての特性にも優れるものであった。例４〜例６は、それぞれフィルム成形性、素子との接着性、チップ保護性において例１及び例３より劣るものの、レーザーマーキングの視認性には優れるものであった。例７では、白色のフィラーを含有しなかったため、元の接着剤の色が透明に近く、レーザーマーキングを行って表面付近の着色剤が揮発しても下層に存在する着色剤の色がフィルム表面から見えてしまい、レーザーマーキングを行った場合であっても、結果として色の違いが生じず、視認性が低下していた。また、例８では、着色剤の含有量が少ないため、マーキング部分とそれ以外の部分のコントラストは上記例に比べると劣り、着色剤を含有させないよりは視認性は向上したが、充分ではなかった。
【００５６】
これに対し例１はフィルムに着色剤と白色のシリコンフィラーを含有することによりレーザーマーキング後に良好な視認性を得られた。また、例２は、フィルムを単体で形成してからシリコンウエハに貼り付ける方法によっても、レーザーマーキング後に良好な視認性を持つフィルムを得られることが判明した。また、例３では、ベースとなる樹脂が不透明な乳白色であることから、白色フィラーを含有しない場合であっても、視認性が良好であった。
【００５７】
本実施形態によれば、フィルムを着色することによりレーザーマーキングの視認性を良好とすることができ、容易に識別情報を製品に表示することが可能であり、かつ、半導体素子の表面の保護特性が優れているため、パッケージの製造時あるいはパッケージの搬送時に、半導体素子端部の欠けを防止することができる。
【００５８】
【発明の効果】
以上説明したように、本発明の半導体素子表面保護用フィルムによれば、優れた半導体素子表面の保護特性およびレーザーマーキングによる視認性を得ることができ、その結果、製造コストを削減することができると共に高品質の製品を提供することができる。
【図面の簡単な説明】
【図１】本実施形態における、半導体素子表面保護用フィルムを適用した半導体装置の一部を示す断面図。
【図２】半導体素子ユニットの構成を示す断面図。
【図３】本発明の半導体用フィルムを備えた３層構造のフィルムを示す断面図。
【図４】半導体装置の製造工程の一部を示し、半導体素子表面保護用フィルムをシリコンチップ上に形成する際の工程を示す図。
【図５】半導体装置の製造工程の一部を示し、ウエハをダイシングする工程を示す図。
【図６】半導体装置の製造工程の一部を示し、ＴＡＢを貼り付ける工程を示す図。
【図７】半導体装置の製造工程の一部を示し、ワイヤボンディング及び半田ボール付けをする工程を示す図。
【図８】半導体装置の製造工程の一部を示し、レーザー照射により識別情報を表示する工程を示す図。
【図９】半導体装置の製造工程の一部を示し、実装基板上に実装する工程を示す図。
【図１０】ＹＡＧレーザーを使用して封止材にレーザーマーキングする方法の原理について説明する図であり、（ａ）〜（ｃ）は、封止材の断面を示す図。
【符号の説明】
１　半導体配線基板
２　接着剤層
３　半導体素子
４　半導体素子表面保護用フィルム
５　接続部材
６　封止材
７　配線
８　外部接続端子
９　ベースフィルム
１０　保護フィルム
１１　接着剤層
１２　ＴＡＢ
１３　ワイヤボンディング
１４　半田ボール
１５　実装基板
Ａ　半導体素子ユニット[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is applied to, for example, a semiconductor device of a face-down structure in which a circuit surface is arranged toward a semiconductor wiring substrate side, a semiconductor element surface protection film for protecting the surface of a semiconductor element, and the semiconductor element surface protection. The present invention relates to a semiconductor element unit using a film for use.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, miniaturization and weight reduction of electronic devices have been promoted, and accordingly, high-density mounting on substrates has been demanded, and miniaturization and weight reduction of semiconductor packages mounted on electronic devices has been promoted.
[0003]
Semiconductor packages have variously changed with the times, and there are conventionally packages called LOC (Lead On Chip) and QFP (Quad Flat Package). For example, LOC packages are used in DRAMs of 16M or later. ing.
[0004]
Usually, identification information such as a lot number and a manufacturer name is printed on the package to identify the product, so that it is possible to determine how the product was manufactured. In the case of a package such as LOC and QFP, laser sealing is directly performed on the sealing material formed on the outer surface of the package with identification information for identifying a product.
[0005]
Lasers used for laser marking include carbon dioxide gas lasers and YAG lasers. When performing laser marking on a sealing material, YAG lasers are mainly used. The principle of the method of laser marking a sealing material using a YAG laser will be briefly described below with reference to FIGS. 10 (a) to 10 (c).
[0006]
FIG. 10A is a diagram showing a cross section of a sealing material 20 which is a material to be subjected to laser marking. As shown in FIG. 10A, a silica filler 22 and a pigment (carbon) 23 are contained in a resin 21. It is evenly distributed.
[0007]
When the YAG laser 24 is irradiated from the surface side of the sealing material 20, as shown in FIG. 10 (b), carbon particles 23a, 23b, 23c present at the laser-irradiated portion are selected according to the wavelength of the laser. It is heated.
[0008]
Then, as shown in FIG. 10C, the carbon particles 23a, 23b and 23c evaporate together with the surrounding resin 21 and only the silica filler 22 remains in the resin 21. Since the color after the carbon has evaporated is white, the laser irradiation position appears to be marked white. In this way, laser marking is performed on the sealing material.
[0009]
In recent years, the size and weight of semiconductor packages have been further reduced, and packages such as CSP (ChipSize Package) and μBGA (Ball Grid Array) have been further downsized and reduced in weight than packages such as LOC and QFP. Is being developed. In such a package, the wiring connecting the semiconductor element and the substrate is arranged at the center of the semiconductor element and only that part is sealed. Therefore, the entire conventional semiconductor element is sealed with a sealing material. As compared with the shape, the size and weight of the package can be further reduced.
[0010]
[Problems to be solved by the invention]
However, in the above-mentioned package, although the size and weight can be reduced, the semiconductor element is a face-down type, that is, the circuit surface of the semiconductor element is directed to the semiconductor wiring board side, and the Since the back surface of the semiconductor element has an exposed shape, there is a problem that the end of the semiconductor element is chipped when a package is manufactured or the package is transported.
[0011]
Also, in particular, some packages, such as CSP, are not sealed with a sealing material. Therefore, products can be manufactured by direct laser marking on semiconductor elements or printing directly on semiconductor elements. The identification information for discriminating was printed.
[0012]
However, when laser marking is performed directly on a semiconductor element, there is no clear contrast between the semiconductor element and the identification information, so that the discriminating power between the semiconductor element and the marking is low and visibility is poor. Was.
[0013]
In addition, when the identification information is marked by directly printing on the semiconductor element, the identification information can be clearly displayed on the semiconductor element, so that there is an advantage that the identification property between the semiconductor element and the identification information is high. However, according to the printing, the number of steps is large, so that there is a problem that the work time for printing the identification information is significantly increased.
[0014]
Further, in the case of a package such as a CSP that is not sealed with a sealing material, the surface of the semiconductor element is protected by a method of forming a protective film or a method of attaching a protective film. . As such a protective film or protective film, for example, a transparent or translucent film or film is used. The reason for this is that the materials used for semiconductors avoid the deposition of ionic impurities as much as possible, so that the contamination of impurities is avoided as much as possible. This is because it is assumed that impurities such as pigments and dyes are not mixed. For this reason, even when a transparent or translucent film or film is directly irradiated with a laser to display identification information for identifying a product, the visibility of the laser marking is poor.
[0015]
The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a semiconductor element surface protection film and a semiconductor element unit having excellent protection characteristics of a semiconductor element surface and excellent visibility by laser marking. .
[0016]
[Means for Solving the Problems]
In order to solve the above-mentioned object, various studies have been carried out, and a film is coated on the surface of the semiconductor element on the side opposite to the circuit surface to protect the surface of the semiconductor element, and a colorant different from the color of the film in the opaque film. In addition, when displaying identification information on the film, by irradiating the laser to volatilize the colorant and clarifying the color difference between the marked part and the non-marked part by laser irradiation, the laser marking A semiconductor element surface protection film having excellent visibility and a semiconductor element unit using the semiconductor element surface protection film are obtained.
[0017]
That is, the present invention is a film used for a semiconductor element having a circuit surface arranged toward a semiconductor wiring substrate side, and a film for protecting a surface side of the semiconductor element facing the circuit surface, which is opaque. It is characterized in that the film contains a colorant different in color from the film.
[0018]
Further, in the above invention, a colorant is contained in the film, and the content of the colorant is 0.1 to 10% by mass with respect to the film.
[0019]
Further, in the above invention, a white filler is contained in the film, and the content of the white filler is 1 to 70% by mass.
[0020]
Further, in the above invention, the colorant is a carbon filler.
[0021]
In the above invention, the elastic modulus at 25 ° C. of the film is from 20 to 2000 MPa.
[0022]
Further, the thickness of the film is 25 to 200 μm.
[0023]
The semiconductor element unit according to the present invention includes a semiconductor element having a circuit surface arranged toward the semiconductor wiring board and a surface formed on the surface of the semiconductor element facing the circuit surface. And a film for protecting the surface of a semiconductor element containing a colorant different from the above.
[0024]
The semiconductor element surface protection film of the semiconductor element unit is the semiconductor element surface protection film described above.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 9 and Tables 1 and 2.
[0026]
FIG. 1 is a diagram showing a cross section of a part of a semiconductor device to which a film for protecting a semiconductor surface of the present invention is applied. As shown in FIG. 1, a semiconductor element 3 is mounted on a semiconductor wiring board 1 via an adhesive layer 2 made of an adhesive such as a resin, and a circuit surface of the semiconductor element 3 faces the semiconductor wiring board 1 side. The surface of the semiconductor element 3 facing the circuit surface is coated with a semiconductor element surface protection film 4. At the center of the semiconductor wiring substrate 1 and the adhesive layer 2, a connection member 5 having a part of a wiring of the semiconductor wiring substrate 1 and a bonding pad of a semiconductor element at each end is bonded. Are sealed by a sealing material 6. An external connection terminal 8 is connected to the back surface of the semiconductor wiring substrate 1 via a wiring 7.
[0027]
In the semiconductor element unit A of the present invention applied to the semiconductor device having the above configuration, as shown in the sectional view of FIG. 2, a semiconductor element surface protecting film is formed on the surface of the semiconductor element 3 by coating. The semiconductor element surface protection film 4 usually has a three-layer film as shown in the sectional view of FIG. 3, and a base film 9 and a protection film 10 are provided on both sides of the semiconductor element surface protection film 4. Are respectively formed. The protective film 10 is formed according to the type of the semiconductor element surface protecting film 4, and the protective film 10 is not always formed.
[0028]
The resin used for the semiconductor element surface protection film 4 of the present invention is particularly a component as long as the semiconductor element 3 has an adhesive force with the semiconductor element 3 which does not peel off when exposed to a reflow temperature. There is no limitation, for example, a thermoplastic resin such as a polyimide resin, a polyamide resin, a polyether sulfone resin, a polyamide imide resin, an epoxy resin, a bismaleimide resin, a cyanate resin, a phenol resin, and a thermosetting resin such as a polyurethane resin. Adhesives and mixtures thereof can be used. Further, a heat-resistant film can be used as the base film 9, and the surface of the base film 9 is preferably subjected to a release treatment with, for example, silicone or the like.
[0029]
As the colorant contained in the resin used for the semiconductor element surface protection film 4, for example, pigments and dyes such as carbon black, graphite, titanium carbon, manganese dioxide, and phthalocyanine can be used. The content of the colorant contained in the semiconductor element surface protection film 4 is preferably from 0.1 to 10% by mass, and more preferably from 0.5 to 2.0% by mass. When the content of the colorant is 0.1% by mass or less, the film is not colored and visibility after laser marking is deteriorated. Conversely, when the content of the colorant is 10% by mass or more, ionic impurities This causes problems such as an increase in the film thickness, a decrease in the ductility of the film, and a decrease in the adhesive strength to the semiconductor element.
[0030]
Further, since a laser used for laser marking is often a YAG laser, it is preferable to use carbon black which is easily volatilized by the YAG laser as a coloring agent.
[0031]
Further, examples of the white filler contained in the resin used for the semiconductor element surface protection film 4 include crystalline silica, amorphous silica, aluminum oxide, calcium carbonate, magnesium carbonate, aluminum nitride, and boron nitride. . Further, the content of the white filler is preferably 1 to 70% by mass, and particularly preferably 5 to 50% by mass. When the content of the white filler is 1% by mass or less, the color of the semiconductor element surface protection film 4 does not become white after the colorant is volatilized by laser marking, and the visibility after the laser marking is deteriorated. If the content of the white filler is 70% by mass or more, the surface protection film 4 of the semiconductor element becomes brittle, the moldability is reduced, and problems such as a decrease in the adhesive strength to the silicon wafer occur.
[0032]
Further, the ratio between the colorant and the white filler in the resin of the semiconductor element surface protection film 4 can be appropriately adjusted. For example, when the marking is blurred, the content of the colorant may be increased, and when the contrast is insufficient, the content of the white filler may be increased. When soot is easily produced, laser marking can be performed by reducing the content of the coloring agent.
[0033]
The film having the three-layer structure is formed by, for example, applying a varnish of a material forming an adhesive film on a base film 9 made of a heat-resistant film, heating and drying, and then removing a solvent. The heating and drying conditions at this time vary depending on the components of the film to be used, the solvent of the varnish, and the like, but generally heating is performed at a temperature of 70 to 200 ° C. for 3 to 30 minutes.
[0034]
Further, when a film for protecting the surface of a semiconductor element is formed on the semiconductor element 3 using such an adhesive film, a load is not applied to the semiconductor element and the workability is excellent. Preferably, the possible temperature is 180 ° C. or lower, more preferably 140 ° C. or lower.
[0035]
Further, the thickness of the semiconductor element surface protecting film 4 of the present invention is preferably 25 to 200 μm, and more preferably 50 to 100 μm. If the thickness of the semiconductor element surface protection film 4 is 25 μm or less, the impact as a cause of chipping of the semiconductor element 3 cannot be completely absorbed, so that the characteristic as a protective film for protecting the semiconductor element 3 is deteriorated. This is because if the thickness of the semiconductor element surface protection film is 200 μm or more, the thickness of the entire package increases, which hinders the package design.
[0036]
The film 4 for semiconductor element surface protection of the present invention has an elastic modulus at 25 ° C. of preferably 20 to 2000 MPa, more preferably 50 to 1000 MPa. If the elastic modulus is 20 MPa or less, the tackiness remains on the semiconductor element surface protection film 4, and the films adhere to each other during transportation, or dust adheres to the film, leading to a decrease in workability and an increase in impurities. It is. On the other hand, when the elastic modulus is 2000 MPa or more, the semiconductor element surface warp occurs after the semiconductor element surface protection film 4 is formed and attached, which causes problems such as deterioration of package reliability and workability. Because it occurs.
[0037]
A procedure for manufacturing a semiconductor device using the semiconductor element surface protection film 4 included in the three-layer film will be described with reference to FIGS.
[0038]
First, the protective film 10 having a three-layer structure is peeled off, and as shown in FIG. 4, the semiconductor element surface protecting film 4 with the base film 9 is heat-pressed on a silicon wafer as the semiconductor element 3 by a laminator. The film 4 for semiconductor surface protection is formed by pressure bonding. Thereafter, the base film 9 is peeled off. Here, when the semiconductor element surface protection film 4 is a thermosetting resin, the film is cured as necessary. Then, after dicing the wafer as shown in FIG. 5, a TAB 12 is attached via an adhesive layer 11 made of an adhesive as shown in FIG. Further, as shown in FIG. 7, wire bonding and solder ball bonding are performed. Thereafter, as shown in FIG. 8, a YAG laser is irradiated from the side of the semiconductor element surface protection film 4 to display identification information for discriminating a product, and then, as shown in FIG. Thus, a semiconductor device is formed.
[0039]
Further, the method of forming the film 4 for semiconductor surface protection is not limited to the above-described method using film lamination or heat pressing, and a varnish obtained by dissolving the raw material of the film 4 for semiconductor surface protection in a solvent is placed on the wafer. Can be applied by a spin coater, a bar coater or the like, dried by heating, and the solvent is removed to form a film directly on siliconware. The spin coating conditions and the heating and drying conditions at this time vary depending on the film components used and the solvent of the varnish, but are generally 70 to 200 ° C. for 3 to 30 minutes. When the semiconductor surface protecting film 4 is formed on a wafer by a spin coater, even the resin having no adhesiveness among the aforementioned resins is peeled off when the semiconductor element 3 is exposed to a reflow temperature. It can be used as long as it has an adhesive force to the semiconductor element 3 which does not have any.
[0040]
As described above, the identification information is marked by irradiation with the YAG laser. However, in the present invention, since the semiconductor element surface protection film 4 which is colored by containing a coloring agent is used, the visual recognition after laser marking is performed. The properties are good. The visibility of the film was evaluated by quantifying the regular reflection light intensity of the marked portion and the non-marked portion into 256 levels using an image processing apparatus, and comparing the difference in the numerical values. Further, in order to obtain good visibility, the difference in reflected light intensity is required to be 40 or more, and particularly preferably 60 or more.
[0041]
Hereinafter, a more specific description will be given using Examples 1 to 8.
[0042]
Example 1
60 parts by weight of a bisphenol A type epoxy resin (epoxy equivalent: 175, YD-8125 manufactured by Toto Kasei Co., Ltd.) and 5 parts by weight of a phenol novolak type epoxy resin (YDCN-703 manufactured by Toto Kasei Co., Ltd.) Part, 35 parts by weight of bisphenol A novolak resin (using LF-2882 manufactured by Dainippon Ink) as a curing agent, 30 parts by weight of silicon filler (using Admafine SO-C2 manufactured by Admatechs) as a white filler, coloring A varnish prepared by mixing 35 parts by weight of a resin-based pigment containing carbon black as an agent (CF black HGBK-02, a land color pigment) and 30 parts by weight of cyclohexanone as a solvent with a bead mill, and epoxy as an epoxy group-containing acrylic copolymer Group-containing acrylic rubber (molecular weight 100,000 parts by weight of HTR-860P-3 manufactured by Teikoku Chemical Industry Co., Ltd., and 0.5 parts by weight of 1-cyanoethyl-2-phenylimidazole (using Curezol 2PZ-CN) as a curing accelerator and a solvent And 1700 parts by weight of cyclohexanone were added and mixed by stirring to obtain a varnish for protecting the surface of the semiconductor element. (This is varnish A)
The obtained varnish A was applied on a base film with a release agent (Purex A31 manufactured by Teijin) in a thickness of 50 μm to obtain an adhesive film with a base film. This adhesive film was laminated on the back surface of the silicon wafer at 120 ° C. to obtain a film for protecting the surface of the semiconductor element formed on the silicon wafer.
[0043]
Example 2
In this example, the varnish shown in Example 1 was formed on the back surface of the silicon wafer by spin coating so that the thickness after drying was 45 to 55 μm, and then dried at 140 ° C. for 5 minutes to form a semiconductor on the silicon wafer. An element surface protection film was formed.
[0044]
Example 3
50 parts by weight of a bisphenol A type epoxy resin (epoxy equivalent: 175, YD-8125 manufactured by Toto Kasei Co., Ltd.) and 15 parts by weight of a phenol novolak type epoxy resin (YDCN-703 manufactured by Toto Kasei Co., Ltd.) Parts, 20 parts by weight of bisphenol A novolak resin (using LF-2882 manufactured by Dainippon Ink) as a curing agent, 15 parts by weight of bisphenol-type phenoxy resin (using YP-50 manufactured by Toto Kasei Co., Ltd.) as a phenoxy resin, coloring A varnish prepared by mixing 35 parts by weight of a resin-based pigment containing carbon black as an agent (CF black HGBK-02, a land color pigment) and 30 parts by weight of cyclohexanone as a solvent with a bead mill, and epoxy as an epoxy group-containing acrylic copolymer Group-containing acrylic rubber (molecular weight 1 230,000 parts by weight of HTR-860P-3 manufactured by Teikoku Chemical Industry Co., Ltd., 0.5 part by weight of 1-cyanoethyl-2-phenylimidazole (using Curezol 2PZ-CN) as a curing accelerator, and a solvent And 1700 parts by weight of cyclohexanone were added and mixed by stirring to obtain a varnish for protecting the surface of the semiconductor element. (This is varnish B)
This film did not contain a silicon filler because the resin itself was milky white. Otherwise, the same method as in Example 1 was used to form a semiconductor element surface protecting film.
[0045]
Example 4
A varnish was prepared by setting the content of the silicon filler to 80% by mass in the varnish composition shown in Example 1, and a film for protecting a semiconductor element surface was formed on a silicon wafer by using the same procedure as in Example 1 except for the above.
[0046]
Example 5
A varnish was prepared with the content of the resin-based processed pigment being 20% by mass in the varnish composition shown in Example 1, and a film for protecting the surface of a semiconductor element was formed on a silicon wafer by using the same procedure as in Example 1 except for the above.
[0047]
Example 6
A semiconductor element surface protection film was formed on a silicon wafer in the same manner as in Example 1, except that the thickness of the film was 15 μm.
[0048]
Example 7
In this example, the varnish composition shown in Example 1 did not contain a silicon filler. Otherwise, the same procedure as in Example 1 was used to form a semiconductor element surface protection film on a silicon wafer.
[0049]
Example 8
In this example, a varnish was prepared by setting the content of the resin-based processed pigment in the composition of the varnish shown in Example 1 to 0.05% by mass, and otherwise the same procedure as in Example 1 was used to protect the surface of the semiconductor element on the silicon wafer. Film was formed.
[0050]
The composition and characteristics of each film used in Examples 1 to 8 are shown.
[0051]
[Table 1]
Figure 2004063551
[0052]
After curing each of the obtained semiconductor element surface protective films, laser marking was performed with a YAG laser having an output of 5.0 J / pulse to confirm the visibility. The visibility is evaluated by taking an image of the film surface after laser marking with a scanner, and performing two gradations of the marking portion and the non-marking portion around the marking portion using image processing software (PHOTOSHOP manufactured by Adobe). By this operation, the image is divided into 256 levels of black and white according to the brightness. Next, the "threshold of the boundary for two-gradation" in which the marking part is displayed in white and the non-marking part is displayed in black, and the "two-gradation" in which the marking part is also displayed in black and the boundary of the marking / non-marking part disappears The threshold value of the boundary to be performed is determined, and if the difference is 40 or more, the visibility is good (（). If the difference is 30 or more and less than 40, the visibility is almost good. (Δ), and when the difference was less than 30, the visibility was evaluated as poor (×). Table 2 shows the evaluation results.
[0053]
Further, using the respective composition materials and the production methods of Examples 1 to 8 described above, film test pieces were produced. The size of each film test piece was 3 mm x 20 mm, and the elasticity of each film test piece was measured at a test rate of 2 ° C / min and a measurement temperature of 20 to 200 ° C. Table 2 shows the measurement results.
[0054]
[Table 2]
Figure 2004063551
[0055]
As shown in Table 2, Examples 1 to 3 were excellent in visibility and also excellent in characteristics as a chip protective film. Examples 4 to 6 were inferior to Examples 1 and 3 in film formability, adhesion to the element, and chip protection, respectively, but were excellent in laser marking visibility. In Example 7, since the white filler was not contained, the color of the original adhesive was nearly transparent, and even if the colorant near the surface was volatilized by performing laser marking, the color of the colorant present in the lower layer was changed to the surface of the film. , And even when laser marking was performed, no color difference occurred as a result, and visibility was reduced. In Example 8, since the content of the coloring agent was small, the contrast between the marking portion and the other portions was inferior to that of the above example, and the visibility was improved as compared with the case where the coloring agent was not contained, but was not sufficient. .
[0056]
In contrast, in Example 1, good visibility was obtained after laser marking by containing a colorant and a white silicon filler in the film. In addition, in Example 2, it was found that a film having good visibility after laser marking could be obtained also by a method of forming a film alone and attaching the film to a silicon wafer. Further, in Example 3, since the base resin was opaque milky white, the visibility was good even when no white filler was contained.
[0057]
According to the present embodiment, the visibility of the laser marking can be improved by coloring the film, the identification information can be easily displayed on the product, and the protection property of the surface of the semiconductor element can be obtained. This makes it possible to prevent chipping of the end of the semiconductor element at the time of manufacturing the package or transporting the package.
[0058]
【The invention's effect】
As described above, according to the semiconductor element surface protection film of the present invention, excellent protection properties of the semiconductor element surface and visibility by laser marking can be obtained, and as a result, manufacturing cost can be reduced. And provide high quality products.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a part of a semiconductor device to which a semiconductor element surface protection film is applied according to an embodiment.
FIG. 2 is a cross-sectional view illustrating a configuration of a semiconductor element unit.
FIG. 3 is a cross-sectional view showing a three-layer film including the semiconductor film of the present invention.
FIG. 4 is a view showing a part of a manufacturing process of the semiconductor device and showing a process when a semiconductor element surface protection film is formed on a silicon chip.
FIG. 5 is a view illustrating a part of the manufacturing process of the semiconductor device and illustrating a process of dicing a wafer.
FIG. 6 is a diagram illustrating a part of the manufacturing process of the semiconductor device and illustrating a process of attaching a TAB.
FIG. 7 is a diagram illustrating a part of the manufacturing process of the semiconductor device and illustrating a process of performing wire bonding and solder ball bonding.
FIG. 8 is a diagram illustrating a part of the manufacturing process of the semiconductor device and illustrating a process of displaying identification information by laser irradiation.
FIG. 9 is a diagram illustrating a part of the manufacturing process of the semiconductor device and illustrating a process of mounting the semiconductor device on a mounting board.
FIGS. 10A to 10C are views for explaining the principle of a method of laser marking a sealing material using a YAG laser, and FIGS. 10A to 10C are views showing cross sections of the sealing material.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor wiring board 2 Adhesive layer 3 Semiconductor element 4 Semiconductor element surface protection film 5 Connecting member 6 Sealing material 7 Wiring 8 External connection terminal 9 Base film 10 Protective film 11 Adhesive layer 12 TAB
13 Wire Bonding 14 Solder Ball 15 Mounting Board A Semiconductor Element Unit

Claims (8)

回路面が半導体配線基板側に向けて配置される半導体素子に使用され、かつ、当該半導体素子の回路面と対向する面側を保護するためのフィルムであって、不透明なフィルム中に当該フィルムとは色が異なる着色剤が含有されていることを特徴とする半導体素子表面保護用フィルム。A film used for a semiconductor element whose circuit surface is arranged toward the semiconductor wiring board side, and a film for protecting the surface side of the semiconductor element opposite to the circuit surface, wherein the film is included in an opaque film. Is a film for protecting the surface of a semiconductor element, which comprises a coloring agent having a different color. 前記着色剤の含有量が、フィルムに対して０．１〜１０質量％であることを特徴とする請求項１記載の半導体素子表面保護用フィルム。2. The film for protecting a semiconductor element surface according to claim 1, wherein the content of the coloring agent is 0.1 to 10% by mass based on the film. 前記フィルムに白色のフィラーが含有されており、当該白色のフィラーの含有量が、１〜７０質量％であることを特徴とする請求項１または２記載の半導体素子表面保護用フィルム。The film for protecting a semiconductor element surface according to claim 1, wherein the film contains a white filler, and the content of the white filler is 1 to 70% by mass. 前記着色剤は、カーボンフィラーであることを特徴とする請求項１または２記載の半導体素子表面保護用フィルム。3. The film according to claim 1, wherein the colorant is a carbon filler. 前記フィルムの２５℃における弾性率が、２０〜２０００ＭＰａであることを特徴とする請求項１から４までのいずれかに記載の半導体素子表面保護用フィルム。The film for protecting a surface of a semiconductor device according to any one of claims 1 to 4, wherein the film has an elastic modulus at 25 ° C of 20 to 2000 MPa. 前記フィルムの厚さが、２５〜２００μｍであることを特徴とする請求項１から５までのいずれかに記載の半導体素子表面保護用フィルム。The film for protecting a semiconductor element surface according to any one of claims 1 to 5, wherein the film has a thickness of 25 to 200 µm. 回路面が半導体配線基板側に向けて配置される半導体素子と、当該半導体素子の回路面と対向する面側に形成され、不透明なフィルム中に当該フィルムとは色が異なる着色剤が含有された半導体素子表面保護用フィルムと、を備えることを特徴とする半導体素子ユニット。A semiconductor element whose circuit surface is arranged toward the semiconductor wiring substrate side, and a colorant having a color different from that of the film is contained in an opaque film formed on a surface side opposite to the circuit surface of the semiconductor element. A semiconductor element surface protection film. 前記半導体素子表面保護用フィルムが、請求項２から６までのいずれかに記載の半導体素子表面保護用フィルムであることを特徴とする半導体素子ユニット。A semiconductor element unit, wherein the semiconductor element surface protection film is the semiconductor element surface protection film according to any one of claims 2 to 6.
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