JP2004047566A - Field effect transistor, its manufacturing method, and image display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor which can be manufactured simply and inexpensively, obtain a large on/off ratio by attaining improvement of on-current and reduction of off-current at the same time, and to provide its manufacturing method and image display. <P>SOLUTION: The field effect transistor is composed of at least a semiconductor layer 106, a first gate electrode 108 formed via a first insulating film 107 on the side of one surface of the semiconductor layer 106, and source-drain electrodes 104 and 105. The semiconductor layer 106 is located between the source-drain electrodes 104 and 105, and has a region in thinner film thickness than that of the other region in at least a partial region facing the first gate electrode 108. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field effect transistor (FET), a method for manufacturing the same, and an image display device, and more particularly, to a semiconductor layer using an organic material which has a large on / off ratio and is advantageously used as a switching element. The present invention relates to a field effect transistor, a method for manufacturing the same, and an image display device using the field effect transistor.
[0002]
Problems to be solved by the prior art and the invention
In recent years, thin film transistors have been widely put to practical use in various devices including liquid crystal display elements, and their application as display devices is expected.
Generally, there are two types of driving methods for liquid crystal display elements. One is a simple matrix system in which strip-shaped transparent electrode rows are arranged so as to be orthogonal to each other, and are used for a binary display such as a word processor. The other is an active matrix system in which a transistor is used for each pixel and a switch is turned on and off for each pixel, and is used for a color or monochrome liquid crystal display device. A type (FET) transistor is used.
[0003]
This transistor is usually formed by laminating an inorganic semiconductor layer made of Si, Ge, Ga, As, In, P, or the like on a substrate at a high process temperature by a vacuum deposition apparatus and patterning the layer. For example, an a-Si semiconductor layer which has already been put into practical use is formed at a high temperature of 350 ° C. by a plasma CVD device, and a semiconductor layer made of low-temperature polysilicon, which has recently been receiving attention, is formed at a higher temperature. For this reason, there are few choices of materials used for the substrate, and a glass substrate has been mainly used for a transparent substrate.
However, recently, the range of use of displays has rapidly expanded, and applications as portable information terminals are expected. Above all, demand for flexible displays has been increasing.
[0004]
Therefore, in order to exhibit such flexibility, a TFT made of an organic semiconductor is proposed in place of a TFT made of an inorganic semiconductor in Japanese Patent Application Laid-Open No. 1-259323. That is, since the organic TFT can reduce the process temperature as compared with the process temperature of the conventional silicon semiconductor, the selection range of the substrate can be widened, and the organic TFT is flexible or curved using a plastic substrate. Since an organic thin film transistor can be formed and an inexpensive substrate can be used, production cost can be reduced.
[0005]
In general, conductive polymers such as polythiophene and polythienylenevinylene used as organic semiconductors are π-conjugated polymers, and have a flexibility not found in inorganic materials such as silicon and gallium arsenide. Have. In addition, a π-conjugated polymer can synthesize an organic semiconductor soluble in an organic solvent by introducing a substituent, and can form a thin film by a simple method such as a spin coating method or a dipping method (immersion method). For this reason, rectifying elements and field effect transistors using a π-conjugated polymer have been experimentally manufactured, and certain characteristics have been obtained.
[0006]
In these conventional π-conjugated polymer field effect transistors, that is, organic field effect transistors, an organic semiconductor layer 902 is laminated on a substrate 901 as shown in FIG. A source electrode 903 and a drain electrode 904 are formed, and a staggered structure in which a gate electrode 906 is formed over the organic semiconductor layer 902, the source electrode 903, and the drain electrode 904 via a gate insulating film 905.
It has been studied to apply such an organic TFT to a pixel driving element of an active matrix type liquid crystal display. In this case, a high ON / OFF ratio, that is, a low OFF current is required for improving the contrast and increasing the response speed. In order to reduce the off-state current, it is necessary that the conductivity of the semiconductor layer at the time of off-state be low. As for the on-state current, the value of the field-effect mobility described below is important.
[0007]
Generally, in a field-effect transistor, when a sufficient voltage is applied between the source and the drain, a current I _D Is known to be expressed by the following equation (only ON current is considered).
I _D = (W / 2L) μ _FE C _OX (V _G -Vth) ² (I)
(In the formula (I), W: channel width, L: channel length, μ _FE : Field effect mobility, C _OX : Capacitance per unit area of gate insulating film, V _G : Gate voltage, Vth: threshold)
[0008]
Here, the field effect mobility (μ _FE ) Is obtained from the relationship between the on-state current and the gate voltage of the field-effect transistor, and represents the effective carrier mobility of the current flowing through the semiconductor layer during the on-state.
As can be seen from the equation (I), in order to obtain a large on-state current in the field-effect transistor, the field-effect mobility (μ _FE ) Must be large.
Therefore, various attempts have been made to improve the on-current and the on / off ratio of the organic field effect transistor.
[0009]
For example, in Japanese Patent Application Laid-Open No. H5-110069, a π-conjugated polymer is used as a semiconductor layer of a field-effect transistor, and 1 × 10 ^-1 cm ² / V · s, which is a considerably high field-effect mobility.
However, in this transistor, the off-state current increases as the on-state current increases, and as a result, it does not lead to an improvement in the on / off ratio.
In Applied Physics Letter, Vol. 62, p. 1794, 1993, an organic field-effect transistor using a π-conjugated polymer, which realizes a five-digit on / off ratio by reducing an off current. Has been proposed.
However, the field effect mobility of this transistor is 2 × 10 ^-4 cm ² / V · s, and does not increase the on-current.
[0010]
On the other hand, as a technique for increasing the on-current, a technique is known in which the upper and lower sides of the inorganic semiconductor layer are sandwiched between two gate electrodes to increase the conduction channel formed near the interface between the semiconductor layer and the insulating layer (for example, JP-A-53-246874).
In this field-effect transistor, as shown in FIG. 12, a first gate electrode 1002 is disposed on a substrate 1001, and a semiconductor layer 1005 serving as a channel layer is disposed thereon via a first gate insulating film 1003. A source electrode 1006 and a drain electrode 1004 connected to the semiconductor layer 1005 are arranged on the side. Further, a second gate electrode 1008 is provided over the semiconductor layer 1005 with a second gate insulating film 1007 interposed therebetween.
[0011]
However, although a transistor having such a structure can obtain a sufficient ON current, it cannot reduce the OFF current and cannot improve the ON / OFF ratio. Furthermore, as a technique for increasing the ON current and increasing the ON / OFF ratio, two types of organic semiconductor layers having different carrier densities are stacked on the gate electrode, and two organic layers are formed according to the voltage applied from the gate electrode. There is a method in which the electric conductivity between a source and a drain is changed by moving a carrier between them (JP-A-5-48094).
[0012]
However, this transistor has a problem that the manufacturing process is very complicated because two types of semiconductor layers are formed.
As described above, it is difficult to manufacture the field-effect transistor used for the organic semiconductor layer simply and easily, and to simultaneously improve the on-current and reduce the off-current.
The present invention has been made in view of the above problems, and can be manufactured simply and easily, and at the same time, achieves a large on / off ratio at a low cost by realizing both improvement of the on-current and reduction of the off-current. An object of the present invention is to provide a field-effect transistor that can be obtained, a method for manufacturing the same, and an image display device.
[0013]
[Means for Solving the Problems]
According to the present invention, the semiconductor layer includes at least a semiconductor layer, a first gate electrode formed on one surface side of the semiconductor layer via a first insulating film, and a source / drain electrode. There is provided a field-effect transistor including a region formed between a source / drain electrode and at least a part facing a first gate electrode with a smaller thickness than other regions.
Further, according to the present invention, a first gate electrode having a convex portion is formed on a substrate, and the first insulating film is formed so as to cover at least a part of the first gate electrode on which the convex portion is not arranged. Forming a semiconductor layer via a first insulating film on a first gate electrode between the source / drain electrodes and between the source / drain electrodes and on which the protrusions are arranged, via a field effect. A method of manufacturing a type transistor is provided.
Further, according to the present invention, there is provided an image display device in which at least one field effect transistor is used as a switching element of a display element per pixel.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
The field effect transistor of the present invention includes at least a semiconductor layer, a first insulating film, a first gate electrode, and a source / drain electrode.
This transistor is usually formed on a substrate. The substrate is not particularly limited, and examples thereof include glass; plastic substrates such as polyimide, PET, PEN, and PES; elemental semiconductors such as silicon and germanium; and substrates composed of compound semiconductors such as GaAs, InGaAs, and ZnSe. . Among them, a transistor having a small dimensional change in a transistor manufacturing process is preferable, and a plastic substrate is more preferable in consideration of a purpose of reducing substrate cost and a purpose of giving flexibility to a completed device.
[0015]
The semiconductor layer is a layer for forming a channel region of the transistor, and can be formed using, for example, an organic semiconductor in addition to the element semiconductor or the compound semiconductor. Above all, a-Si or an organic semiconductor that can be applied is preferable because it can be formed by a simple process. The organic semiconductor is not particularly limited. Examples thereof include acene-based materials such as pentacene, tetracene, anthracene, and pyrene; polyacene-based materials such as polyacene and polyphenanthrene; and aromatic conjugates such as polyphenylene, polynaphthalene, and polyanthracene. Polymer; Heterocyclic conjugated polymers such as polypyrrole, polythiophene, polyisothianaphthene, polyisonaphthothiophene, polyfuran, polyselenophene, polytellurophen and the like, alone or in combination. Note that the semiconductor layer may be formed as a single layer with the above-described materials or as a stacked structure of two or more layers with different or the same materials.
[0016]
The semiconductor layer has a region formed between the source / drain electrodes and at least part of the region facing the first gate electrode described later with a smaller thickness than other regions. The semiconductor layer is suitably formed to have a thickness of about 100 to 300 nm, and the thin film region is formed to be about 20 to 80% thinner than a normal thickness. For example, the thin film region suitably has a thickness of about 50 to 150 nm. The size of the thin film region can be appropriately adjusted depending on the size of the gate electrode, the driving voltage, and the like. For example, it is appropriate that the area is about 50 to 100% of the entire area of the gate electrode. The shape of the thin film region is not particularly limited, and may include various shapes such as a notch, a slit, a groove, and a recess. Further, only one or a plurality of thin film regions may be provided. Further, when a thin film region is formed by a cutout or the like on the surface of the semiconductor layer, it may be formed on only one surface or may be formed on both surfaces. When a plurality of cutouts are formed in the semiconductor layer, all of the cutouts need not have the same shape. For example, the semiconductor layer can have a shape as shown in FIGS.
[0017]
As a method of forming a semiconductor layer having a thin film region, as described later, a gate electrode having a convex portion is formed in advance, and a flat semiconductor layer is formed thereon, thereby forming a thin film region on the convex portion. Can be formed. As a method for forming a flat semiconductor layer, a method in which a semiconductor material is dissolved in an appropriate solvent and applied or printed, a semiconductor layer is formed by a sputtering method, an evaporation method, a CVD method, or the like, and the surface is etched or etched. A polishing method such as CMP may be used. Alternatively, the semiconductor layer can be formed by forming a uniform thickness by the above-described method and then partially removing the semiconductor layer by etching or the like.
[0018]
The first insulating film generally functions as a gate insulating film, but does not necessarily have to have such a function, and may have a function as an interlayer insulating film or a protective film. As the first insulating film, those having a high dielectric constant and a low conductivity are preferable, for example, silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, aluminum oxide, titanium oxide, polyethylene, polyimide, acrylic resin, and the like. A single layer or a laminated film of a derivative having photosensitivity and the like can be given. These films can be formed by coating, printing, or dissolving in an appropriate solvent, in addition to a CVD method, a sputtering method, an evaporation method, a sol-gel method, and an anodizing method. The thickness of the first insulating film is, for example, about 100 to 500 nm.
[0019]
The first gate electrode may be formed of any material as long as it is formed of a conductive film. For example, high melting point metals such as platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony, lead, tantalum, indium, aluminum, zinc, magnesium, zinc, magnesium or alloys thereof, titanium, tantalum, and tungsten Or their alloys, SnO ₂ , InO ₂ , ZnO, transparent conductive materials such as ITO, etc., inorganic and organic semiconductors whose conductivity is improved by doping or the like, for example, silicon single crystal, polysilicon, amorphous silicon, germanium, graphite, polyacetylene, polyparaphenylene, polythiophene, polypyrrole , Polyaniline, polythienylenevinylene, polyparaphenylenevinylene, and the like. These can be formed by various methods such as a sputtering method, an evaporation method, and an EB method. The thickness of the first gate electrode is not particularly limited, and may be, for example, about 50 to 300 nm. Note that the shape of the gate electrode is not particularly limited, but the first gate electrode is usually formed so as to face the thin film region of the semiconductor layer, that is, below or above the semiconductor layer. It may be formed so that the film thickness is partially different, or may be formed in a shape having undulations in the film thickness direction corresponding to the thin film region of the semiconductor layer.
[0020]
Usually, the source electrode and the drain electrode are formed separately from each other on both sides of the gate electrode in plan view in contact with the semiconductor layer. These electrodes can be formed of the same material as that exemplified as the gate electrode. Among them, those having low electric resistance at the contact surface with the semiconductor layer are appropriate, and those having a low barrier at the Schottky junction and those capable of ohmic contact with the semiconductor layer are preferable. In the field-effect transistor of the present invention, a second gate electrode may be further formed on a side of the semiconductor layer opposite to a side on which the first gate electrode is formed, with a second insulating film interposed therebetween.
[0021]
In this case, the second insulating film can be formed using the same material as the first insulating film. In particular, it is preferable that the first insulating film is formed of a material different from that of the first insulating film. Further, it is preferable that one of the first insulating film and the second insulating film is formed of an organic material, particularly, a photosensitive organic material. When it is formed of an organic substance, its thickness is suitably about 1500 to 3500 nm.
[0022]
The second gate electrode can be formed using the same material as the first gate electrode. Similarly to the first gate electrode, the second gate electrode may be formed in a shape corresponding to the thin film region of the semiconductor layer. The second gate electrode need not necessarily be formed in the same shape and the same projected area as the first gate electrode. That is, the second gate electrode may be formed larger or smaller than the second gate electrode, but has the same projected area. Preferably, it is formed. In addition, the second gate electrode may be formed on the same side as being separated from and in parallel with the first gate electrode. However, when the first gate electrode is arranged above or below the semiconductor layer, It is preferably disposed below or above the semiconductor layer, and more preferably disposed so as to substantially face the first gate electrode. In this case, the switching characteristics of the transistor can be more effectively controlled by the electric field of the first gate electrode and the electric field of the second gate electrode. Note that the second gate electrode is formed by a field-effect mobility (μ) of a material forming the semiconductor layer. _FE Is not particularly necessary when the value is large, but it is effective when the on-current is particularly increased.
[0023]
Note that the on-current can be further improved by adding three or more gate electrodes, that is, by adding as many as the restrictions permit. In this case, a plurality of gate electrodes are separated and parallel to the first gate electrode on the same side as the first gate electrode of the semiconductor layer, or separated and parallel to the second gate electrode on the same side as the second gate electrode. A plurality may be formed.
[0024]
As described above, in the case where the first gate electrode is formed to face the thin film region with respect to the semiconductor layer having the thin film region, off-state current can be reduced. In the case where the semiconductor layer is formed so as to be sandwiched between the first gate electrode and the second gate electrode, not only the off-state current can be reduced but also the on-state current can be increased. As a result, the on / off ratio can be improved.
[0025]
That is, when a voltage is applied between the source and the drain and a voltage is applied to the gate electrode, an on-current flows between the source and the drain because a conductive channel is formed near an interface between the semiconductor layer and the insulating film. it is conceivable that. On the other hand, even if a conduction channel is not formed near the interface, if a voltage is applied between the source and the drain, a region (bulk) other than near the semiconductor layer / insulating film interface is formed unless the semiconductor layer is a perfect insulator. A small amount of current flows between the source and drain via This is the cause of the off-state current.When doping is performed on the entire semiconductor layer to improve the carrier mobility and increase the conductivity of the entire semiconductor layer, the on-state current also increases, but the off-state current flowing through the bulk also increases. To increase. Therefore, if the carrier mobility is increased only for the current flowing near the interface with the insulating film without increasing the carrier mobility of the current flowing through the bulk of the semiconductor layer, the on-current is hardly increased without increasing the off-current. The current can be increased. For this reason, a structure in which the region (bulk) other than the vicinity of the interface between the semiconductor layer and the insulating film, which is a cause of the off current, is reduced, that is, a structure in which a part of the bulk is narrowed reduces the off current. Can be done. In addition, by increasing the number of conduction channels formed near the interface between the semiconductor layer and the insulating film, the on-current can be improved and the off-current can be reduced.
[0026]
In the method of manufacturing a field-effect transistor according to the present invention, first, a first gate electrode having a projection is formed on a substrate. A gate electrode having a convex portion is formed by, for example, forming a flat film with a conductive material, etching only part of the surface using a mask, forming a flat film with a conductive material, and further forming a conductive film thereon. And patterning only the upper conductive film.
Next, a source / drain electrode is formed via a first insulating film so as to cover at least a part of the first gate electrode on which the protrusion is not provided. That is, source / drain electrodes are formed over a region other than a region where a semiconductor layer is to be formed later via the first insulating film. The source / drain electrodes can be formed by depositing a conductive material and etching with a mask having a desired shape.
[0027]
After that, a semiconductor layer is formed via a first insulating film between the source / drain electrodes and on the first gate electrode on which the protrusions are arranged. Here, it is appropriate that the first insulating film is formed at the same time as the previous step. In addition, the semiconductor layer may be formed by forming a semiconductor layer in an entire region including a region above the first gate electrode where the projection is provided, and etching the semiconductor layer using a mask having a desired shape, or a desired mask. May be used to form a semiconductor layer only on the first gate electrode on which the protrusions are arranged, or without using a mask, a semiconductor material solution dissolved in an appropriate solvent may be formed on the first gate electrode. It may be formed by coating (for example, spin coating) or printing only on one gate electrode.
[0028]
After the above method, a second gate electrode may be further formed on the semiconductor layer and the source / drain electrode via a second insulating film. In this case, the second insulating film is formed of a material different from the first insulating film, preferably, an organic material, and more preferably, a photosensitive organic material. Further, the second gate electrode formed thereon can be formed by the known method as described above.
[0029]
In the present invention, when the field-effect transistor is formed together with other elements on the same substrate, at least one first electrode is formed on the substrate on which one or more electrodes are formed. An insulating film and a second insulating film are formed simultaneously with the above, a contact hole is formed in the second insulating film, and the first insulating film or the first insulating film and the electrode are formed using the second insulating film as a mask. It may be etched. This is effective when the first insulating film and the second insulating film are formed of different materials. The formation of the electrode, the formation of the contact hole, and the etching of the first insulating film and / or the electrode can be performed by a method known in the art and under known conditions.
[0030]
The field-effect transistor of the present invention can be formed as a thin-film transistor, a three-dimensional transistor such as a cylinder, and an integrated circuit, a logic circuit, a transmissive liquid crystal display device with or without a backlight, It can be used for various systems such as displays such as organic light emitting devices. In particular, it is useful as at least one switching element of a display element (for example, an electric field driving type, a current driving type switching element, etc.) for one pixel of a display device.
Hereinafter, embodiments of a field-effect transistor, a method for manufacturing the same, and an image display device according to the present invention will be described with reference to the drawings.
[0031]
Example 1
As shown in FIG. 1, the field-effect transistor of the present invention has a configuration in which a semiconductor layer 106 is formed on a substrate 101, and an upper gate electrode 108 is formed thereon via an upper gate insulating film 107. You.
In the semiconductor layer 106, a source electrode 104 and a drain electrode 105 are arranged so as to be located on both sides of the upper gate electrode 108, and a channel region is formed between the source electrode 104 and the drain electrode 105 in a region facing the upper gate electrode 108. .
[0032]
The semiconductor layer 106 has a region where the film thickness is small in a part directly below the upper gate electrode 108. That is, it has a structure in which the channel region is narrowed in part of the channel length 109.
Note that the upper gate insulating film 107 also functions as a channel protection layer.
Since the semiconductor layer 106 has the region 203 in which the channel region is narrowed in a part of the region opposing the upper gate electrode 108, the off-state current can be reduced and the on / off ratio can be improved. Can be done.
[0033]
Example 2
In the field-effect transistor of the present invention, as shown in FIG. 2A, a lower gate electrode 102 is disposed on a substrate 101, and a semiconductor layer 106 is formed thereon via a lower gate insulating film 103. Further, an upper gate electrode 108 is formed thereon with an upper gate insulating film 107 interposed therebetween.
In the semiconductor layer 106, a source electrode 104 and a drain electrode 105 are disposed so as to be located on both sides of the upper and lower gate electrodes 102 and 108, and a channel is provided between the source electrode 104 and the drain electrode 105 in a region facing the upper and lower gate electrodes 102 and 108. An area is formed.
[0034]
The semiconductor layer 106 has a region where the film thickness is small in a part directly below the upper gate electrode 108. That is, it has a structure in which the channel region is narrowed in part of the channel length 109.
In this transistor, as shown in FIG. 2B, by applying a voltage to the lower gate electrode 102, a conduction channel 201, which is a path of an on-current, is formed in a region of the semiconductor layer 106 opposed to the lower gate electrode 102. It is controlled by that voltage. In addition, by applying a voltage to the upper gate electrode 108, a conduction channel 202 is formed in a region of the semiconductor layer 106 opposite to the upper gate electrode 108, and is controlled by the voltage.
[0035]
As described above, when the semiconductor layer 106 includes the region 203 in which the channel region is narrowed in a part of the region facing the upper gate electrode 108, the off-state current can be reduced.
In particular, in a field-effect transistor in which an on-state current cannot be increased by using an organic material for the semiconductor layer, the conduction channels 201 and 202 are increased by using the same signal source for the lower gate electrode 102 and the upper gate electrode 108. This makes it possible to improve the on-current.
That is, the ON current can be increased while suppressing the increase in the OFF current, and as a result, the ON / OFF ratio can be improved.
[0036]
Example 3
As shown in FIG. 3, the transistor of this embodiment has an example in which a cutout portion of a semiconductor layer 407 is arranged on a lower surface.
In this transistor, as illustrated in FIG. 4, the semiconductor layer 407 can be formed using an organic material by an evaporation method.
First, as shown in FIG. 4A, a transparent glass substrate 401 having a thickness of 0.7 mm is prepared as a substrate, and a Ti / Al / TiN film is formed thereon with a thickness of 30/200/150 nm by a sputtering method. Formed by Next, using a first photomask (not shown), the obtained film is patterned into a desired shape by photolithography and a dry etching technique mainly using chlorine gas to form a lower gate electrode 402. I do. Subsequently, Al is formed with a thickness of 300 nm on the lower gate electrode 402 by a sputtering method, and is formed on the lower gate electrode 402 by photolithography and wet etching using a second photomask (not shown). Then, a convex portion 403 is formed. The wet etching at this time was performed using a mixture of sulfuric acid, nitric acid, acetic acid, and water as an etching solution under the processing conditions of 40 ° C. for 150 seconds, and washing with water at 70 liters / minute for 45 seconds. Under these conditions, the amount of side etching shift of Al of the lower gate electrode 402 was 0.8 μm on one side, and it was confirmed that the lower gate electrode 402 was in a sufficiently usable state.
[0037]
Next, as shown in FIG. 4B, a 400-nm-thick silicon nitride film is formed as a lower gate insulating film 404 on the lower gate electrode 402 having the convex portion 403 by a plasma CVD method at a low temperature. The substrate temperature at this time was 200 ° C.
Subsequently, Ti / Al / Ti are formed to a thickness of 30/150/50 nm, respectively, by a sputtering method, and a third photomask (not shown) is used by photolithography and dry etching techniques. A source electrode 405 and a drain electrode 406 are formed.
[0038]
Next, as shown in FIG. 4C, using a shadow mask 501 made of stainless steel and having a thickness of 0.7 mm, 20 mg of pentacene purified by sublimation in a dark place was used as an organic substance in an amount of 2 to 4 ×. 10 ^-6 Under a pressure of Torr, a semiconductor layer 407 having a planarized surface is formed from a tungsten boat for a sublimation metal, which is 5 cm away from the deposition substrate, by mask vapor deposition performed by resistance heating. The semiconductor layer 407 has a thickness of 300 nm in the thickest region and a thickness of 80 nm in the thinnest region.
[0039]
Note that at this time, if a shadow mask having an opening only in a portion where the semiconductor layer is to be formed is used, the surface of the obtained semiconductor layer 409 is not flattened as shown in FIG. Therefore, as shown in FIG. 5, a shadow mask 501 having an opening 503 at a portion where a semiconductor layer is to be formed and having a slit 504 formed in the opening 503 is used, as shown in FIG. Thus, the semiconductor layer 407 is planarized. The shadow mask 501 can planarize the semiconductor layer 407 by appropriately changing the width, the number of the slits 504 and the gap 502 between the slits according to the shape of the semiconductor layer 407 to be obtained.
[0040]
Next, as shown in FIG. 4D, a 1-μm-thick film was formed by spin-coating a polyvinylphenol resin as the upper gate insulating film 408 also serving as a channel protective layer. Note that the film formation was performed in a dark place under a nitrogen atmosphere in order to prevent oxidation of the semiconductor layer 407.
After that, in order to input a signal to the lower gate electrode 402 having the convex portion 403 and input / output a signal to / from the source electrode 405 and the drain electrode 406, the lower gate insulating film 404 and / or the upper gate insulating film 408 existing thereover. Was removed using a fourth photomask (not shown).
[0041]
Finally, as shown in FIG. 3, a Ti / Al / Ti film is formed on the upper gate insulating film 408 in a thickness of 30/150/50 nm by sputtering, and a fifth photomask (not shown). 3), an upper gate electrode 409 was formed using a dry etching technique mainly using chlorine gas. For the upper gate electrode 409, a pattern having the same shape as that of the first photomask was used. Further, the lower gate electrode 402 and the upper gate electrode 409 are designed so that the same signal can be input.
The thin film transistor thus formed has three digits of off current at the same channel width (W) and channel length (L) as compared with a conventional double-gate thin film transistor as shown in FIG. Since the ON current did not decrease, the ON / OFF ratio can be improved by three digits.
[0042]
Example 4
As shown in FIG. 6, the transistor of this embodiment has an example in which a cutout portion of a semiconductor layer 407 is arranged on a lower surface.
In this transistor, as shown in FIG. 7, the semiconductor layer 407 can be formed by spin coating with an organic material.
First, a lower gate electrode 402 having a convex portion 403 on a substrate 401, a lower gate insulating film 404, a source electrode 405, and a drain electrode are formed in the same manner as in FIGS. 406 is formed.
[0043]
Next, as shown in FIG. 7A, pentacene purified by sublimation in a dark place was used as an organic semiconductor material on the obtained substrate 401, and this was added to 1,2,4-trichlorobenzene at a concentration of 40 wt%. The dissolved solution is applied by a spin coating method, and the residual solvent is evaporated on a hot plate under vacuum to form a semiconductor layer 601 having a thickness of 300 nm in the thickest region and a thickness of 70 nm in the thinnest region. Form.
Next, as shown in FIG. 7B, a 1.5 μm-thick resist pattern 602 is formed on the semiconductor layer 601 using a fourth photomask (not shown) by photolithography. .
[0044]
Subsequently, as shown in FIG. 7C, using the resist pattern 602 as a mask, wet etching is performed with a 1: 1 mixed solution of 1,2,4-trichlorobenzene and benzene to form a semiconductor layer 601. Is etched. At this time, the side etching shift amount is 2.5 μm on one side. After that, the resist pattern 602 is removed with a resist stripper. At this time, since the interface state between the resist pattern 602 and the semiconductor layer 601 affects the characteristics of the transistor, the process from the photolithography step to the etching step is performed in a short time so that the semiconductor layer 601 is not affected as much as possible. The resist pattern 602 is not left.
[0045]
Next, as shown in FIG. 7D, an upper gate insulating film 408 also serving as a channel protective layer was formed as in Example 3, and an upper gate electrode 604 was formed as in Example 3.
The thin film transistor thus formed has two digits of off-current at the same channel width (W) and channel length (L) as compared with a conventional double-gate thin film transistor as shown in FIG. Since the ON current did not decrease, the ON / OFF ratio can be improved by two digits.
[0046]
Example 5
In this embodiment, an example is shown in which a field-effect transistor is formed as a driving transistor of an active matrix liquid crystal display device.
In the liquid crystal display device, as shown in FIGS. 8A to 8C, a plurality of gate signal lines 706 connected to a gate terminal 701 are arranged in parallel with each other, and a CS terminal 703 is connected between the gate signal lines 706. A plurality of CS signal lines 705 are arranged in parallel with each other. A plurality of source lines 707 connected to the source terminal 702 are arranged in parallel with each other so as to cross the gate signal line 706. At the intersection of the gate signal line 706 and the source line 707, a field-effect transistor 704 similar to the field-effect transistor described in Embodiment 3 is arranged, and is surrounded by the gate signal line 706 and the source line 707. The pixel electrode 810 connected to this field-effect transistor is disposed in the region to be connected.
[0047]
The pixel electrode 810 is connected to the drain electrode 806 of the field-effect transistor 704 through the contact hole 811. The lower gate electrode 802 and the upper gate electrode 809 are connected to the gate signal line 706, and the source electrode 805 is connected to the source line 707. Each is connected.
Such a liquid crystal display device can be manufactured by the following method.
[0048]
First, as shown in FIGS. 9A to 9F, a lower portion having a convex portion 803 on a substrate 801 by the same method as in FIGS. 4A and 4B in the third embodiment. A gate electrode 802, a lower gate insulating film 804, a source electrode 805, and a drain electrode 806 are formed. Note that a gate signal line 706, a gate terminal 701, a CS signal line 705, and a CS terminal 703 are formed over the substrate 801 at the same time as the formation of the lower gate electrode 802. Further, a source terminal 702 and a source line 707 are formed at the same time as the source electrode 805 and the drain electrode 806.
[0049]
Next, as shown in FIG. 9G, an acrylic positive photosensitive resin film capable of forming a pattern by light irradiation is spin-coated on the obtained substrate 801 and is exposed with a fourth photomask. Then, patterning is performed by developing to form an upper gate insulating film 808 also serving as a channel protective layer. In this example, TMAH diluted to 10% with water was used as a developer for patterning. Thereafter, a contact hole 811 is formed in the upper gate insulating film 808 on the drain electrode 806, and contact holes are also formed on the gate terminal 701, the source terminal 702, and the CS terminal 703 as shown in FIG. I do.
Subsequently, in order to crosslink the photosensitive resin film of the upper gate insulating film 808, a heat treatment was performed in a baking furnace at 85 ° C. for 200 seconds to a thickness of 2 μm.
[0050]
Next, as shown in FIG. 9I, in order to remove the lower gate insulating film 804 on the gate terminal 701, the source terminal 702, and the CS terminal 703, the patterned upper gate insulating film 808 is used as a mask pattern. Dry etching was performed. The conditions of the dry etching are as follows: a power of 2.4 kW, a pressure of 300 mTorr, and an etching gas of CF in a RIE (reactive ion etching) mode so as not to damage the semiconductor layer 807 due to an organic substance. ₄ Ion (330 sccm), O ₂ (170 sccm), the GAP distance was set to 130 mm, and the temperature was set to 60 ° C.
[0051]
Finally, as shown in FIGS. 8B and 9I, an ITO film is formed and patterned to form an upper gate electrode 809 and a pixel electrode 810, and a gate terminal 701 and a source terminal 702. Further, a gate signal line 706, a source line 707, and a CS signal line 705 connected to the CS terminal 703 can be formed.
Also in this example, the upper gate electrode 809 was patterned into the same shape as the lower gate electrode 802.
[0052]
An alignment film was formed on the substrate 801 on which the field-effect transistor 704 formed by the above method was formed and on the opposite substrate. Then, plastic beads having a size of 3 μm were sprinkled on both substrates, the two substrates were bonded with a thermosetting resin, a liquid crystal was injected into a gap between the substrates, and sealed with a UV curable resin, thereby producing a liquid crystal display device. . In addition, as a counter substrate, an ITO film having a thickness of 100 nm was formed as a transparent electrode by a sputtering method on a 0.7 mm thick transparent glass substrate. Further, the electrode connection to the common electrode was performed using carbon paste, and only black and white display was performed. A square pixel may be divided into three pixels, and a full-color display may be performed using a counter substrate separated by red, blue, and green colors.
[0053]
Although a transmissive liquid crystal display device is manufactured in this embodiment, the present invention can be applied to a reflective liquid crystal display device. In that case, by using a reflective material such as aluminum instead of the transparent electrode used for the pixel electrode, the drain electrode 806 can be patterned and used so as to also serve as the pixel electrode without processing the contact hole 811. it can. This is advantageous in that the manufacturing process can be simplified and the gate insulating film can be formed on the flexible plastic substrate at a reduced film formation temperature.
[0054]
A liquid crystal display device using a field-effect transistor manufactured in this manner has a smaller off-state current than a conventional liquid crystal display device using a field-effect transistor as shown in FIG. 11 or FIG. Can be reduced, and as a result, the on / off ratio can be improved, so that a liquid crystal display device with high aperture ratio and contrast, excellent in gradation display, and high-speed response can be obtained.
In addition, since the manufacturing process is simpler than that of a conventional field-effect transistor, a high-performance field-effect transistor with high yield can be provided.
[0055]
【The invention's effect】
According to the invention, the semiconductor layer has a region formed with a smaller thickness than other regions in at least a part of the region between the source / drain electrodes and facing the first gate electrode. The off-state current can be reduced by reducing a region (bulk) other than the vicinity of the interface between the semiconductor layer and the insulating film, which is a cause of the current. Thus, a high-performance and high-quality field-effect transistor with an improved on / off ratio can be obtained.
Further, when the semiconductor device further includes the second insulating film and the second gate electrode, the number of conduction channels formed in the vicinity of the interface between the semiconductor layer and the insulating film can be increased. The current can be reduced, and the on / off ratio can be further improved.
[0056]
Further, since the semiconductor layer is formed of an organic material, it is possible to provide a field-effect transistor having flexibility and bendability.
Moreover, according to the method for manufacturing a field-effect transistor of the present invention, a high-performance and high-quality transistor can be realized by a simple manufacturing process, so that the manufacturing cost can be reduced and an inexpensive transistor is provided. It becomes possible.
In addition, by applying such a transistor to an image display device, it is possible to obtain a display device with improved on / off ratio, high aperture ratio and high contrast, excellent gray scale display, and high-speed response. .
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a main part showing an embodiment of a field-effect transistor of the present invention.
FIG. 2 is a schematic cross-sectional view of a main part showing another embodiment of the field-effect transistor of the present invention.
FIG. 3 is a schematic cross-sectional view of a main part showing still another embodiment of the field-effect transistor of the present invention.
FIG. 4 is a schematic cross-sectional process drawing of a main part for describing a method of manufacturing the field-effect transistor in FIG.
FIG. 5 is a plan view of a shadow mask used in the method for manufacturing a field-effect transistor of the present invention.
FIG. 6 is a schematic sectional view of a main part showing still another embodiment of the field-effect transistor of the present invention.
FIG. 7 is a schematic cross-sectional process diagram of a main part for describing a method of manufacturing the field-effect transistor of FIG.
FIG. 8 is a schematic plan view and a cross-sectional view of a main part of an image display device using the field-effect transistor of the present invention.
FIG. 9 is a schematic cross-sectional process drawing of a main part for describing the method of manufacturing the image display device in FIG. 8;
FIG. 10 is a schematic cross-sectional view of a main part for describing the shape of a semiconductor layer of the field-effect transistor of the present invention.
FIG. 11 is a schematic sectional view showing an element structure of a conventional field-effect transistor.
FIG. 12 is a schematic sectional view showing the element structure of another conventional field-effect transistor.
[Explanation of symbols]
101, 401, 801 substrate
102, 402, 802 Lower gate electrode
103, 404, 804 Lower gate insulating film
104, 405, 805 Source electrode
105, 406, 806 Drain electrode
106, 407, 409, 601, 807 Semiconductor layer
107, 408, 808 Upper gate insulating film
108, 409, 604, 809 Upper gate electrode
109 channel length
201, 202 conduction channel
203 Channel area narrowed area
403, 803 convex part
409, 604, 809 Upper gate electrode
501 shadow mask
502 gap
503 opening
504 slit
602 resist pattern
701 Gate terminal
702 source terminal
703 CS terminal
704 Field-effect transistor
705 CS signal line
706 gate signal line
707 source line
810 pixel electrode
811 Contact hole

Claims (12)

At least a semiconductor layer, a first gate electrode formed on one surface side of the semiconductor layer via a first insulating film, and a source / drain electrode;
The field effect type wherein the semiconductor layer has a region formed between the source / drain electrodes and facing the first gate electrode in a thickness smaller than other regions in at least a part of the region. Transistor. 2. The transistor according to claim 1, wherein the semiconductor layer has a notch on a surface facing the first gate electrode, so that the semiconductor layer has a region formed with a smaller thickness than other regions. 3. 3. The transistor according to claim 1, wherein the semiconductor layer is formed of an organic material. 2. The transistor according to claim 1, further comprising a second gate electrode formed on a side of the semiconductor layer opposite to a side on which the first gate electrode is formed, with a second insulating film interposed therebetween. The transistor according to claim 4, wherein the first insulating film and the second insulating film are formed of different materials. The transistor according to claim 4, wherein at least the first insulating film or the second insulating film is made of an organic material. The transistor according to claim 4, wherein at least the first insulating film or the second insulating film is made of a photosensitive material. Forming a first gate electrode having a protrusion on a substrate, forming source / drain electrodes via a first insulating film so as to cover at least a part of the first gate electrode on which the protrusion is not arranged; And forming a semiconductor layer via a first insulating film between the source / drain electrodes and on the first gate electrode on which the protrusions are arranged. 9. The method according to claim 8, further comprising forming a second gate electrode on the semiconductor layer and the source / drain electrodes via a second insulating film. The method according to claim 9, comprising forming the first or second insulating film by a spin coating method. Further, one or more electrodes are formed on the substrate, at least a first insulating film and a second insulating film are formed on the electrodes, a contact hole is formed in the second insulating film, and the second insulating film is masked. The method according to claim 9, wherein the first insulating film or the first insulating film and the electrode are etched by using the first insulating film. An image display device comprising at least one field effect transistor according to any one of claims 1 to 7 used as a switching element of a display element for one pixel.

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