JP2004022716A - Semiconductor element - Google Patents

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JP2004022716A
JP2004022716A JP2002173991A JP2002173991A JP2004022716A JP 2004022716 A JP2004022716 A JP 2004022716A JP 2002173991 A JP2002173991 A JP 2002173991A JP 2002173991 A JP2002173991 A JP 2002173991A JP 2004022716 A JP2004022716 A JP 2004022716A
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layer
parallel
region
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semiconductor device
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JP3925319B2 (en
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Takahiro Sato
佐藤　高広
Susumu Iwamoto
岩本　進
Tatsuji Nagaoka
永岡　達司
Yasuhiko Onishi
大西　泰彦
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element such as a MOSFET provided with parallel pn layers wherein an n-type region and a p-type region are alternately arranged as a drift layer that prevents concentration of current in a reverse recovery process of a built-in diode so as to enhance the reverse recovery breakdown. <P>SOLUTION: An n<SP>+</SP>buffer layer 11 with a impurity concentration higher than that of the parallel pn layers 20 is provided between an n<SP>++</SP>drain layer 12 and the parallel pn layers 20, 23. Alternatively, the parallel pn layers 23, arranged at a pitch smaller than that of the parallel pn layers 20 of an active region 50 are provided to a region at the outside of the active region 50, or a lifetime control region 24 with a reduced carrier lifetime is provided to the parallel pn layers 23 of breakdown voltage structural part 60. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明はオン状態では電流を流すとともに、オフ状態では空乏化する並列ｐｎ層からなる構造を備える半導体素子に関し、特にＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）等のソース、ドレイン間に等価的に内蔵されたダイオードを有する半導体素子に関する。
【０００２】
【従来の技術】
一般的にＭＯＳＦＥＴのソース、ドレイン間に等価的にダイオードが内蔵されており、そのダイオードの一方の例えばアノード電極は、一方の主表面のうち電流制御が行われる活性部にしか形成されないにもかかわらず、他方のカソード電極は活性部と耐圧構造部との主表面全体に形成されるため、内蔵ダイオードに順バイアスが印加された場合、耐圧構造部にも蓄積キャリアが存在する。
【０００３】
ダイオードの順方向バイアス状態から逆方向バイアス状態に遷移する過程において、逆回復過程を通る。これは内蔵ダイオードが順方向バイアス状態の時にドリフト領域中にキャリアが蓄積するため、逆バイアスにしても蓄積されたキャリアが消滅するまで短時間ではあるが、逆方向に電流が流れる現象である。
この逆回復過程において逆回復破壊が起きることがある。逆回復破壊は一般的に活性部と耐圧構造部との境界部分で発生し、破壊の原因は前記境界部分で発生する電界集中と電流集中による熱的破壊である。
【０００４】
電界集中は、アノード領域の終端部分に形成される円筒状態或いは球面状態のｐｎ接合が原因となっており、電流集中は、耐圧構造部に存在するキャリアが逆回復時にアノード電極に向かって流れることが原因である。
【０００５】
【発明が解決しようとする課題】
ＭＯＳＦＥＴの内蔵ダイオードの逆回復過程の問題は、ｎ型領域とｐ型領域とを交互に配置した並列ｐｎ層をもつ半導体素子で重大である。特に、特開２００１−２９８１９０号公報に開示されたような耐圧構造部にもｎ型領域とｐ型領域とを交互に配置した並列ｐｎ層をもつ半導体素子では、非常に大きな問題となる。
【０００６】
以下でｎまたはｐを冠した層や領域はそれぞれ電子、正孔を多数キャリアとする層や領域を意味している。また＋　は比較的高不純物濃度の、−　は比較的低不純物濃度の領域を意味している。
図１３は、ｎドリフト領域１およびｐ仕切り領域２からなる並列ｐｎ層２０を備えるＭＯＳＦＥＴの電流制御が行われる活性部５０と耐圧を維持する耐圧構造部６０とを示す部分断面図である。耐圧構造部６０にもｎドリフト領域２１およびｐ仕切り領域２２からなる並列ｐｎ層２３が形成されている。耐圧構造部６０のｎドリフト領域２１にはドリフト電流は殆ど流れないが、活性部５０の並列ｐｎ層２０との比較上仮にこのように呼ぶことにする。左端がチップの端である。但し図の煩雑化を避けるため、並列ｐｎ層２０、２３のｎドリフト領域およびｐ仕切り領域の数は減らしてある。
【０００７】
活性部５０では、低抵抗のｎ＋＋ドレイン層１２の上にｎドリフト領域１およびｐ仕切り領域２とを交互に配置した並列ｐ層２０があり、そのｐ仕切り領域２の上にｐウェル領域３が形成され、そのｐウェル領域３の表面層に選択的にｎ＋　ソース領域６とｐ＋　コンタクト領域５とが形成されている。ｎドリフト領域１およびｐ仕切り領域２とは、例えば共に縦型層状であり、紙面に垂直方向に伸びている。
【０００８】
ｎドリフト領域１の上には不純物濃度の高いｎ表面ドリフト領域４が形成されている。ｎ表面ドリフト領域４とｎ＋　ソース領域６とに挟まれたｐウェル領域３の表面上にはゲート絶縁膜７を介してゲート電極層８が設けられている。ｎ＋　ソース領域６とｐ＋　コンタクト領域５との表面に共通に接触してソース電極１０が設けられ、ｎ＋＋ドレイン層１２の裏面に接してドレイン電極１３が設けられている。９はゲート電極層８とソース電極１０とを絶縁する絶縁膜である。
【０００９】
耐圧構造部６０においてもｎ＋＋ドレイン層１２の上にｎドリフト領域２１およびｐ仕切り領域２２とを交互に配置した並列ｐｎ構造部２３があり、その上にフィールド絶縁膜１５が形成されている。ソース電極１０がフィールド絶縁膜１５上に延ばされて、フィールドプレート構造をなしている。チップの端にはｎチャネルストッパ領域１４が形成されその表面に周縁電極１６が設けられている。ソース電極１０は内蔵ダイオードのアノード電極となり、ドレイン電極１３はカソード電極となる。
【００１０】
例えば６００ＶクラスのＭＯＳＦＥＴの場合、各部の基準的な寸法および不純物濃度は次のような値を取る。ｎ＋＋ドレイン層１２の不純物濃度１×１０１８ｃｍ−３、厚さ５μｍ、活性部５０のｎドリフト領域１およびｐ仕切り領域２の不純物濃度２．５７×１０１５ｃｍ−３、厚さ４２μｍ、幅８μｍ、耐圧構造部６０の並列ｐｎ層２３の不純物濃度５×１０１４ｃｍ−３である。
【００１１】
活性部５０と耐圧構造部６０の並列ｐｎ層２０、２３では、耐圧構造部６０の方が不純物濃度を低くして空乏層が広がり易くしているが、ほぼ同じでも良い。ｎドリフト領域１　、２１およびｐ仕切り領域２、２２の領域幅は等しく、そのピッチは等しい（Ｐ１）。
図１３のような従来のＭＯＳＦＥＴ構造の場合、活性部５０の並列ｐｎ構造部２０では５０Ｖ程度の逆バイアスで完全に空乏化し、内蔵ダイオードの順バイアス時に蓄積されたキャリアは、逆回復過程にある時、ソース電極（アノード電極）１０から瞬時に掃き出される。
【００１２】
一方、耐圧構造部６０でのキャリアの掃き出しは逆電圧の増加とともに徐々に行われ、キャリアの掃き出しによる逆回復電流は、耐圧構造部６０の並列ｐｎ層２３のｐ仕切り領域２２をソース電極１０側に流れ、電極が無いためさらに並列ｐｎ層２３の表面を流れる。そしてソース電極（アノード電極）１０が接触している部分（Ｅ部）に電流が集中し破壊する。
【００１３】
図１４（ａ）、（ｂ）はそれぞれこの時の逆回復時のキャリア電流密度とキャリア密度とのシミュレーション結果を、密度が高い程濃く示した濃淡図である。逆回復電流が最大の時点での密度を示している。
図１４より、耐圧構造部６０にキャリアが多く残り、ソース電極１０接触部（Ｅ部）付近に１×１０４　Ａ／ｃｍ２　程度の電流が集中することがわかる。尚、図の１ｅ４　Ａ／ｃｍ２　は、１×１０４　Ａ／ｃｍを意味している。
【００１４】
同様の問題は、ゲートパッドの近傍でも起きる。図１５は従来のＭＯＳＦＥＴのゲートパッド１８近傍の部分断面図である。
ゲートパッド１８直下の並列ｐｎ層２７にもダイオードが内蔵されており、この内蔵ダイオードから逆回復過程で掃き出されるキャリアは行き場がなくなり、ゲートパッド１８直下の両側に形成されたｐウェル領域３に集中し、ときには破壊を招く。
【００１５】
このような問題に鑑み本発明の目的は、並列ｐｎ構造を備えるＭＯＳＦＥＴ等において内蔵ダイオードからの電流集中を防ぎ、逆回復耐量を向上させた半導体素子を提供することにある。
【００１６】
【課題を解決するための手段】
上記課題解決のため本発明の半導体素子は、第一と第二の主面と、第一と第二の主面にそれぞれ設けられた第一と第二の電極と、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層とを有し、並列ｐｎ層の第一の主面側の表面層に高濃度の第二導電型領域を含む活性領域が選択的に形成され、その高濃度の第二導電型領域に第二の電極が接している半導体素子において、前記第一導電型低抵抗層と並列ｐｎ層との間に、第一導電型バッファ層を有し、その第一導電型バッファ層は、少なくとも前記活性領域の一部を含む外側にわたり形成されているものとする。
【００１７】
そのようにすれば、内蔵ダイオードの順バイアス時に第一導電型バッファ層に蓄積されたキャリアが、電界分布により活性部の並列ｐｎ層の第二導電型仕切り領域に供給される。並列ｐｎ層の第二導電型仕切り領域にはキャリアが存在するため、耐圧構造部からのキャリア吐き出しによる逆回復電流は並列ｐｎ層と第二導電型ウェル領域の接合付近に集中することなく、第一導電型バッファ層、および活性部並列ｐｎ層の第二導電型仕切り領域を通して流れる。このため、ＭＯＳＦＥＴ等に内蔵されるダイオードの逆回復過程におけるアノード電極付近での電流集中を緩和し、破壊耐量を向上することができる。
【００１８】
従って、第一導電型バッファ層は、前記第一導電型低抵抗層よりも高抵抗層であり、並列ｐｎ層に比べ低抵抗層であることがよい。
また、並列ｐｎ層がキャリアライフタイムが異なる少なくとも二つの領域からなるものとする。望ましくは、素子活性部の外側にライフタイムの短い領域を配置するものとする。
【００１９】
ライフタイムが、少なくとも二種類以上になるように制御された領域を有することにより、耐圧構造部を含むライフタイムの短い領域でのキャリア蓄積量が減少し、耐圧構造部からのキャリア吐き出しによる逆回復電流を低減することができる。このため、ＭＯＳＦＥＴ等に内蔵される内蔵ダイオードの逆回復過程におけるアノード電極付近での電流集中を緩和し、破壊耐量を向上することができる。
【００２０】
望ましくは、活性領域の外側の並列ｐｎ層のキャリアライフタイムが、活性領域の並列ｐｎ層のキャリアライフタイムより短く制御されていることが大事である。
更に活性領域を含む領域に第一のピッチで配置した並列ｐｎ層の第一の部分と、活性領域の外側の領域に第一のピッチと同じ、若しくは小さい第二のピッチで配置した並列ｐｎ層の第二の部分とを有していることがよい。
【００２１】
小さいピッチの部分は、空乏層が広がり易いので蓄積キャリアが分散され電流集中が起きにくくなる。
並列ｐｎ層の第二の部分の外側に第一導電型のチャネルストッパ領域を配置すれば、表面の反転を防止するチャネルストッパとなる。
けでなく、
並列ｐｎ層の第二の部分の表面が絶縁膜で覆われているものとする。
【００２２】
並列ｐｎ層の第二の部分は、いわゆる耐圧構造部の部分なので、厚い絶縁膜出覆われていることが多い。
第一導電型のチャネルストッパ領域が、並列ｐｎ層の下方に形成されている第一導電型低抵抗層と連続させることにより、チップの側面もすべてドレイン電極１３と同電位にすることができるので、これにより素子の絶縁耐圧は安定化し、品質も向上する。
【００２３】
【発明の実施の形態】
以下に本発明の実施の形態を説明する。
〔実施例１〕
図３は本発明にかかる実施例１の超接合ＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。但し図の煩雑化を避けるため、並列ｐｎ構造２０、２３は減らしてある。以後も同様である。
【００２４】
図３において、図１３と同じ機能をもつ部分には同じ記号を付している。図１３と重複するが説明する。
１１は低抵抗のｎ＋　バッファ層、１２は低抵抗のｎ＋＋ドレイン層、１は第一導電型ドリフト領域、２は第二導電型仕切り領域とからなる並列ｐｎ層２０である。表面層にはｐ仕切り領域２に連続してｐウェル領域３が形成されている。ｐウェル領域３の内部にｐ＋　コンタクト領域５及びｎ＋　ソース領域６が形成されている。ｎ＋　ソース領域６とｎドリフト領域１とに挟まれたｐウェル領域３の表面上にはゲート絶縁膜７を介して多結晶シリコンのゲート電極層８が、またｎ＋　ソース領域６とｐ＋　コンタクト領域５の表面に共通に接触するソース電極１０が設けられている。ｎ＋＋ドレイン層１２の裏面にはドレイン電極１３が設けられている。１５は表面保護及び安定化のための酸化膜であり、例えば、熱酸化膜と燐シリカガラス（ＰＳＧ）からなる。ソース電極１０は図３のように層間絶縁膜９を介してゲート電極層８の上に延長されることが多い。図示しない部分でゲート電極層８上に金属膜のゲート電極が設けられる。
【００２５】
耐圧構造部６０の並列ｐｎ層２３のピッチは、活性部５０のものと同じピッチで形成されている。
ＭＯＳＦＥＴに内蔵されたダイオードの場合、ＭＯＳＦＥＴのソース電極１０がアノード電極に、ドレイン電極１３がカソード電極となる。またＭＯＳＦＥＴのゲート電極はアノード電極に接続することが多い。
【００２６】
ｎドリフト領域１　とｐ仕切り領域２との平面的な形状は、例えばともにストライプ状とする。ｎドリフト領域１とｐ仕切り領域２との平面的な形状は、他に一方が格子状や網状であり、他方がその中に挟まれた形状でもよい。
本実施例１での耐圧構造は、通常行われるフィールドプレート構造を備えているが、勿論ガードリング構造でもよい。
【００２７】
図３において、耐圧構造部６０の並列ｐｎ層２３に隣接して低抵抗のｎチャネルストッパ領域１４が配置されており、ｎチャネルストッパ領域１４はまた、ｎ＋　バッファ層１１を介してｎ＋＋ドレイン層１２とつながっている。そして、半導体チップ側面全てがこのｎチャネルストッパ領域１４で覆われており、その表面に接触して周縁電極１６が設けられている。
【００２８】
このｎチャネルストッパ領域１４は、表面の反転を防止するチャネルストッパとなるだけでなく、チップの側面もすべてドレイン電極１３と同電位にすることができるので、これにより素子の絶縁耐圧は安定化し、品質も向上する。
但し、ｎチャネルストッパ領域１４が必ずチップの側面でなければならないわけではなく、ｎチャネルストッパ領域１４をはさんで反対側の半導体領域に別の半導体素子や半導体領域を形成することもできる。
【００２９】
本実施例ではｎ＋＋ドレイン層１２上にｎ＋　バッファ層１１を形成することでＭＯＳＦＥＴの内蔵ダイオードの逆回復耐量を向上させることが可能となった。これは次のように説明できる。
内蔵ダイオードに順バイアスが印加されると活性部５０および耐圧構造部６０にはキャリアが蓄積する。逆回復過程に入ると蓄積していたキャリアが内蔵ダイオードへの逆バイアス印加により掃き出される。
【００３０】
このとき活性部は５０Ｖ程度の逆バイアスで完全に空乏化してしまうが、ｎ＋　バッファ層１１があることで順バイアス時にｎ＋　バッファ層１１に蓄積されたキャリアが電界分布により、活性部５０と耐圧構造部６０境界近傍の活性部５０の並列ｐｎ層２０のｐ型仕切り領域２に分散される。
このため、耐圧構造部６０からのキャリア掃き出しによる逆回復電流は、活性部５０の並列ｐｎ層２０の端のｐ仕切り領域２付近に集中することなく、ｎ＋　バッファ層１１から活性部並列ｐｎ層２０のｐ仕切り領域２に分散されて流れる。従ってｐウェル領域３の接合付近での電流集中が抑えられ、逆回復耐量が向上する。
【００３１】
なお、例えば６００ＶクラスのＭＯＳＦＥＴの場合、各部の基準的な寸法および不純物濃度は次のような値を取る。ｎ＋＋ドレイン層１２の不純物濃度１×１０１８ｃｍ−３、厚さ５μｍ、ｎ＋　バッファ層１１の不純物濃度４×１０１５ｃｍ−３、厚さ３０μｍ、ｎドリフト領域１およびｐ仕切り領域２の不純物濃度２．５７×１０１５ｃｍ−３、厚さ４２μｍ、幅８μｍ、耐圧構造部６０の並列ｐｎ層２３の不純物濃度５×１０１４ｃｍ−３である。
【００３２】
ｎ＋　バッファ層１１の不純物濃度は、ｎ＋＋ドレイン層１２のそれより低く、並列ｐｎ層のそれより高い。なお、ｎ＋　バッファ層１１は、例えばエピタキシャル成長法により形成できる。
図４は本実施例１のＭＯＳＦＥＴのゲートパッド近傍の部分断面図である。
本実施例では、ゲートパッド１８の下方にもｎ＋　バッファ層１１が設けられている。これにより、内蔵ダイオードの逆回復過程において掃き出されたキャリアがｎ＋　バッファ層１１を通じて分散されるため、ゲートパッド１８直下の両側に形成されたｐウェル領域３への逆回復電流集中を緩和し、逆回復耐量を向上できる。
【００３３】
本実施例では、ゲートパッド１８直下にｐウェル領域３を設けていないが、ｐウェル領域３を設けてもよい。また、ゲートパッド１８直下の並列ｐｎ層は、活性部の並列ｐｎ層のピッチよりも狭くしたり、正味の不純物濃度を低くなるようにしても良い。
〔実施例２〕
図１は本発明にかかる実施例２のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００３４】
図３の第一の実施例との違いは、耐圧構造部６０の一部の並列ｐｎ層２３のピッチ（Ｐ２）が活性部５０のそれ（Ｐ１）より小さいピッチで形成されている点である。具体的にはＰ２をＰ１の１／２とした。この部分は製造時にマスクの寸法を変えるだけで、他のｐｎ層部分と全く同様にして形成できる。
小さいピッチの部分は、フィールド絶縁膜１５上にソース電極１０が延びている付近までとした。耐圧構造部６０ではピッチが狭いので空乏層が広がり易いので蓄積キャリアが分散され電流集中が起きにくくなる。
【００３５】
この場合も実施例１と同様にｎ＋　バッファ層１１の不純物濃度は、ｎ＋＋ドレイン層１２のそれより低く、並列ｐｎ層のそれより高い。そしてｎ＋　バッファ層１１の存在により、内蔵ダイオードの蓄積キャリアの吐き出しによる電流が活性部５０の並列ｐｎ層２３のｐ仕切り領域２に分散され、電流集中が緩和される。
図２（ａ）、（ｂ）はそれぞれこの時の逆回復時のキャリア電流密度とキャリア密度とのシミュレーション結果を、密度が高い程濃く示した濃淡図でる。
【００３６】
図２より、ｎ＋　バッファ層１１の存在により内蔵ダイオードの蓄積キャリアが分散されていることおよび、キャリアの掃き出しによる電流が活性部５０の並列ｐｎ層２０のｐ型仕切り領域２に分散され、アノード電極１０の接触部（Ｅ部）付近への電流集中は、１×１０Ａ／ｃｍ２　程度であり、電流集中が緩和されていることがわかる。
【００３７】
実際に試作した素子は、従来のＭＯＳＦＥＴの８倍以上の耐量を示した。
〔実施例３〕
図５は本発明にかかる実施例３のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
図１の実施例２との違いは、耐圧構造部６０の並列ｐｎ層２３のピッチ（Ｐ２）が活性部５０のｐウェル領域３まで全部、活性部５０のそれ（Ｐ１）より小さいピッチで形成されている点である。
【００３８】
これにより、ｐウェル領域３の端付近で空乏層が広がり易いので蓄積キャリアが分散され電流集中が起きにくくなる。
この場合も実施例２と同様の効果が得られる。
〔実施例４〕
図６は本発明にかかる実施例４のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００３９】
図５の実施例３との違いは、耐圧構造部６０の表面側のみに活性部５０のそれ（Ｐ１）より小さいピッチ（Ｐ２）の並列ｐｎ層２３が形成されている点である。耐圧構造部６０ではピッチが狭いので空乏層が広がり易いので蓄積キャリアが分散され電流集中が起きにくくなる。
この場合も実施例３と同様の効果が得られる。
〔実施例５〕
図７は本発明にかかる実施例５のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００４０】
耐圧横造部６０の並列ｐｎ層２３の接合が波うっている場合である。例えば、ｐ型不純物の埋め込み拡散とエピタキシャル成長、熱処理を繰り返すなど、並列ｐｎ層２３の製造方法によってはｐｎ層２３の接合がこのようになることがある。
この場合も、実施例１と同様の効果が得られる。
〔実施例６〕
図８は本発明にかかる実施例６のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００４１】
耐圧構造部６０の並列ｐｎ層２３のｐ仕切り領域２２が深さ方向に連続していない場合である。耐圧構造部６０の並列ｐｎ層２３のｎドリフト領域２１、ｐ仕切り領域２２については、一定電圧で空乏化するという条件の下にさまざまな不純物濃度、形状の組み合わせを取りうるので、このようなケースも考えられる。
〔実施例７〕
図９は本発明にかかる実施例７のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００４２】
実施例３との違いはｎ＋　バッファ層１１がない点である。このためこれまでの例のようなｎ＋　バッファ層１１を通じての内蔵ダイオードの逆回復電流の分散は起きない。
しかし、本実施例では、耐圧構造部６０の並列ｐｎ層２３のピッチ（Ｐ２）が活性部５０の並列ｐｎ層２０のピッチ（Ｐ１）より狭いため、耐圧構造部６０での並列ｐｎ層２３は活性部５０の並列ｐｎ層２０に対し正味の不純物濃度が低いことになる。
【００４３】
このため、活性部５０と耐圧構造部６０との境界部の並列ｐｎ層の電界が緩和され、電流集中の緩和により逆回復耐量が向上する。
図１０（ａ）、（ｂ）はそれぞれこの時の逆回復時のキャリア電流密度とキャリア密度とのシミュレーション結果を、密度が高い程濃く示した濃淡図でる。
図１０より、内蔵ダイオードの蓄積キャリアは広い範囲に分散されていることおよび、キャリアの掃き出しによるアノード電極付近（Ｅ部）への電流集中が緩和されていることがわかる。電流集中は、２×１０Ａ／ｃｍ２　程度であったので、電流集中が緩和されていることがわかる。
【００４４】
実際に試作した素子は、従来のＭＯＳＦＥＴの５倍以上の耐量を示した。
〔実施例８〕
図１１は本発明にかかる実施例８のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
この実施例８のＭＯＳＦＥＴでは、耐圧構造部６０の並列ｐｎ層２３内に、ライフタイムが短く制御されたライフタイム調整領域２４が設けられている点が特徴であり、ハッチングで示されている。
【００４５】
このライフタイムが短い調整領域２４は、耐圧構造部６０の並列ｐｎ層２３と活性部５０の最外周部のｐウェル領域３との接合領域及び、活性部５０の最外周部のｐウェル領域３とアノード電極１０とが接する領域を含む領域に、形成されている。
内蔵ダイオードの逆回復電流が集中するのは、図１４に示したように、活性部５０の最外周部のｐウェル領域３と隣接する耐圧構造部６０の並列ｐｎ層２３のｐ仕切り領域２２であった。
【００４６】
従って、この領域をライフタイムの短い領域とすれば、逆回復時に耐圧構造部から吐き出されるキャリアは、そのライフタイムの短い領域中で再結合し、電流集中が緩和され逆回復耐量が向上する。
このようなライフタイムの短い領域は、電子線照射、ヘリウムイオン照射やプロトン照射のような粒子線を利用した結晶欠陥導入法を用いることで、容易に形成できる。本実施例ではｎ＋＋ドレイン層１２側から、電子線を加速電圧４．８ＭｅＶ、約１６０キログレイ（ｋｇｒｙ）照射した。条件により１００〜５００ｋｇｒｙの範囲で調節すると良い。
【００４７】
すなわち、ヘリウムイオンやプロトンの阻止能力のある材料（例えば、アルミニウム金属、厚いレジスト膜）を用いて、ライフタイムを短くしたい部分に窓が開けられた構造のマスクを作製する。そして、このマスク上部に対して垂直な方向から粒子線を照射する。
本実施例のように並列ｐｎ層の深さ全体にライフタイムの短い領域を形成する場合は、照射探さを並列ｐｎ層の厚さよりも深い部分にして、ヘリウムイオンあるいはプロトンを通過させても良いし、照射深さを変えて数回に分けて照射を分けて行うことにより結晶欠陥を導入しても良い。
【００４８】
実際に試作した素子は、従来のＭＯＳＦＥＴの８倍以上の逆回復耐量を示した。
なお、このようなライフタイムを短く制御した領域２４は、活性領域５０を含まず耐圧構造部６０のみであるため、順電圧（オン電圧）の上昇はない。
〔実施例９〕
図１２は本発明にかかる実施例９のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００４９】
実施例８では耐圧構造部６０の一部にライフタイムの短い領域２４を形成したが、図１２のように耐圧構造部６０全体にわたってライフタイムの短い領域２４にしてもよい。
また以上の実施例の方法を組み合わせることにより、複合効果が得られ、逆回復耐量を向上できることはもちろんである。
【００５０】
なお、本実施例はＭＯＳＦＥＴの内蔵ダイオードで記載されているが、フリーホィールダイオード、ショットキーダイオード等でも同様な効果が得られる。
【００５１】
【発明の効果】
以上説明したように本発明によれば、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層と、並列ｐｎ層の第一の主面側の表面層に第二導電型領域を含む活性領域が選択的に形成され、その第二導電型領域に第二の電極が接している半導体素子において、第一導電型低抵抗層と並列ｐｎ層との間に、第一導電型バッファ層を設け、或いは、活性領域の外側の領域にピッチの異なる並列ｐｎ層の第二の部分を設け、若しくは、活性領域の外側の並列ｐｎ層のキャリアライフタイムを、活性領域の並列ｐｎ層のキャリアライフタイムより短くする等の手段で、ＭＯＳＦＥＴ等に内蔵されるダイオードの逆回復過程におけるアノード電極付近での電流集中を緩和し、破壊耐量を向上することができる。
【００５２】
いずれも従来の技術の応用で実行可能であり、かつ破壊耐量が６倍以上と効果も大きいことが実証された非常に有効な発明である。
【図面の簡単な説明】
【図１】本発明実施例２のＭＯＳＦＥＴの模式的部分断面図
【図２】（ａ）、（ｂ）は実施例２のＭＯＳＦＥＴにおける内蔵ダイオードの逆回復過程におけるキャリア電流密度、キャリア密度のシミュレーション結果を濃淡で表した図
【図３】本発明実施例１のＭＯＳＦＥＴの模式的部分断面図
【図４】実施例１のＭＯＳＦＥＴのゲートパッド部の部分断面図
【図５】本発明実施例３のＭＯＳＦＥＴの模式的部分断面図
【図６】本発明実施例４のＭＯＳＦＥＴの模式的部分断面図
【図７】本発明実施例５のＭＯＳＦＥＴの模式的部分断面図
【図８】本発明実施例６のＭＯＳＦＥＴの模式的部分断面図
【図９】本発明実施例７のＭＯＳＦＥＴの模式的部分断面図
【図１０】（ａ）、（ｂ）は実施例７のＭＯＳＦＥＴにおける内蔵ダイオードの逆回復過程におけるキャリア電流密度、キャリア密度のシミュレーション結果を濃淡で表した図
【図１１】本発明実施例８のＭＯＳＦＥＴの模式的部分断面図
【図１２】本発明実施例９のＭＯＳＦＥＴの模式的部分断面図
【図１３】従来のＭＯＳＦＥＴのＭＯＳＦＥＴの部分断面図
【図１４】（ａ）、（ｂ）は従来のＭＯＳＦＥＴにおける内蔵ダイオードの逆回復過程におけるキャリア電流密度、キャリア密度のシミュレーション結果を濃淡で表した図
【図１５】従来のＭＯＳＦＥＴのゲートパッド部部分断面図
【符号の説明】
１　ｎドリフト領域
２　ｐ仕切り領域
３　ｐウェル領域
４　表面ｎドリフト領域
５　ｐ＋　コンタクト領域
６　　ｎ＋　ソース領域
７　ゲート絶縁膜
８　ゲート電極層
９　層間絶縁膜
１０　ソース電極、内蔵ダイオードのアノード電極
１１　ｎ＋　バッファ層
１２　ｎ＋＋ドレイン層
１３　ドレイン電極、内蔵ダイオードのカソード電極
１４　ｎチャネルストッパ領域
１５　フィールド絶縁膜
１６　周縁電極
１７　絶縁膜
１８　ゲートパッド
２０　並列ｐｎ層（活性部）
２１　ｎドリフト領域
２２　ｐ仕切り領域
２３　並列ｐｎ層（耐圧構造部）
２４　ライフタイム制御領域
５０　活性部
６０　耐圧構造部[0001]
TECHNICAL FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure composed of a parallel pn layer that causes a current to flow in an on state and depletes in an off state, and particularly, is equivalently built in between a source and a drain of a MOSFET (insulated gate field effect transistor) or the like. And a semiconductor device having the diode.
[0002]
[Prior art]
Generally, a diode is equivalently provided between the source and the drain of the MOSFET, and one of the diodes, for example, an anode electrode is formed only on an active portion of one main surface where current control is performed. However, since the other cathode electrode is formed on the entire main surface of the active portion and the breakdown voltage structure portion, when a forward bias is applied to the built-in diode, accumulated carriers also exist in the breakdown voltage structure portion.
[0003]
In the process of transitioning the diode from the forward bias state to the reverse bias state, the diode goes through a reverse recovery process. This is a phenomenon in which a current flows in the reverse direction for a short time until the accumulated carriers disappear even if the reverse bias is applied because carriers are accumulated in the drift region when the built-in diode is in the forward bias state.
During this reverse recovery process, reverse recovery destruction may occur. Reverse recovery breakdown generally occurs at the boundary between the active portion and the breakdown voltage structure, and the cause of the breakdown is thermal breakdown due to electric field concentration and current concentration occurring at the boundary.
[0004]
The electric field concentration is caused by a cylindrical or spherical pn junction formed at the end of the anode region, and the current concentration is caused by carriers existing in the breakdown voltage structure flowing toward the anode electrode during reverse recovery. Is the cause.
[0005]
[Problems to be solved by the invention]
The problem of the reverse recovery process of the built-in diode of the MOSFET is serious in a semiconductor device having a parallel pn layer in which n-type regions and p-type regions are alternately arranged. In particular, in a semiconductor device having a parallel pn layer in which an n-type region and a p-type region are alternately arranged in a breakdown voltage structure portion as disclosed in Japanese Patent Application Laid-Open No. 2001-298190, a very serious problem occurs.
[0006]
Hereinafter, a layer or a region bearing n or p means a layer or a region having electrons and holes as majority carriers, respectively. Also + Has a relatively high impurity concentration, − Means a region having a relatively low impurity concentration.
FIG. 13 is a partial cross-sectional view showing an active portion 50 for controlling the current of a MOSFET including a parallel pn layer 20 including an n drift region 1 and a p partition region 2, and a breakdown voltage structure 60 for maintaining a breakdown voltage. The parallel pn layer 23 including the n drift region 21 and the p partition region 22 is also formed in the breakdown voltage structure 60. Although little drift current flows in the n drift region 21 of the breakdown voltage structure 60, the drift current is tentatively referred to as such in comparison with the parallel pn layer 20 of the active portion 50. The left edge is the edge of the chip. However, the number of n drift regions and p partition regions of the parallel pn layers 20 and 23 is reduced in order to avoid complication of the drawing.
[0007]
In the active section 50, the low-resistance n ++ On the drain layer 12, there is a parallel p layer 20 in which n drift regions 1 and p partition regions 2 are alternately arranged. On the p partition region 2, a p well region 3 is formed. Selective n for surface layer + Source region 6 and p + A contact region 5 is formed. The n-drift region 1 and the p-partition region 2 are, for example, both in the form of a vertical layer and extend in the direction perpendicular to the plane of the drawing.
[0008]
Above n drift region 1, n surface drift region 4 having a high impurity concentration is formed. n surface drift region 4 and n + A gate electrode layer 8 is provided on the surface of p well region 3 sandwiched between source region 6 with gate insulating film 7 interposed therebetween. n + Source region 6 and p + A source electrode 10 is provided in common contact with the surface of contact region 5, and n ++ A drain electrode 13 is provided in contact with the back surface of the drain layer 12. Reference numeral 9 denotes an insulating film that insulates the gate electrode layer 8 from the source electrode 10.
[0009]
Also in the pressure-resistant structure 60 ++ On the drain layer 12, there is a parallel pn structure portion 23 in which n drift regions 21 and p partition regions 22 are alternately arranged, and a field insulating film 15 is formed thereon. Source electrode 10 is extended on field insulating film 15 to form a field plate structure. An n-channel stopper region 14 is formed at the end of the chip, and a peripheral electrode 16 is provided on the surface thereof. The source electrode 10 becomes the anode electrode of the built-in diode, and the drain electrode 13 becomes the cathode electrode.
[0010]
For example, in the case of a MOSFET of the 600 V class, the standard size and impurity concentration of each part take the following values. n ++ The impurity concentration of the drain layer 12 is 1 × 10 18 cm -3 , A thickness of 5 μm, and an impurity concentration of 2.57 × 10 5 in the n drift region 1 and the p partition region 2 of the active portion 50. Fifteen cm -3 , A thickness of 42 μm, a width of 8 μm, and an impurity concentration of 5 × 10 14 cm -3 It is.
[0011]
In the parallel pn layers 20 and 23 of the active portion 50 and the withstand voltage structure 60, the withstand voltage structure 60 has a lower impurity concentration to make the depletion layer easier to spread, but may be almost the same. The n drift regions 1 and 21 and the p partition regions 2 and 22 have the same region width and the same pitch (P1).
In the case of the conventional MOSFET structure as shown in FIG. 13, the parallel pn structure portion 20 of the active portion 50 is completely depleted by a reverse bias of about 50 V, and the carriers accumulated during the forward bias of the built-in diode are in a reverse recovery process. At this time, it is instantaneously swept from the source electrode (anode electrode) 10.
[0012]
On the other hand, the sweeping out of the carriers in the breakdown voltage structure 60 is gradually performed with an increase in the reverse voltage, and the reverse recovery current caused by the sweeping out of the carriers causes the p partition region 22 of the parallel pn layer 23 of the breakdown voltage structure 60 to be closer to the source electrode 10. And flows further on the surface of the parallel pn layer 23 because there is no electrode. Then, current concentrates on a portion (E portion) where the source electrode (anode electrode) 10 is in contact with the source electrode (anode electrode), and is broken.
[0013]
FIGS. 14 (a) and 14 (b) are gray scale diagrams each showing a simulation result of the carrier current density and the carrier density at the time of the reverse recovery at this time, where the higher the density, the higher the density. The density at the time when the reverse recovery current is maximum is shown.
As shown in FIG. 14, a large amount of carriers remain in the breakdown voltage structure 60, and 1 × 10 4 A / cm 2 It can be seen that about the current concentrates. In addition, 1e4 A / cm in the figure 2 Is 1 × 10 4 A / cm.
[0014]
A similar problem occurs near the gate pad. FIG. 15 is a partial sectional view showing the vicinity of a gate pad 18 of a conventional MOSFET.
A diode is also built in the parallel pn layer 27 immediately below the gate pad 18. Carriers swept out of the built-in diode in the reverse recovery process have nowhere to go, and are in the p-well regions 3 formed on both sides immediately below the gate pad 18. Focus and sometimes destruction.
[0015]
In view of such a problem, an object of the present invention is to provide a semiconductor device in a MOSFET or the like having a parallel pn structure, in which current concentration from a built-in diode is prevented and reverse withstand capability is improved.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the semiconductor element of the present invention has first and second main surfaces, first and second electrodes provided on the first and second main surfaces, respectively, and first and second electrodes. A first conductivity type low resistance layer in contact with the first electrode between the main surfaces, and a parallel pn layer in which first conductivity type drift regions and second conductivity type partition regions are alternately arranged; In a semiconductor element in which an active region including a high-concentration second conductivity type region is selectively formed in the surface layer on the first main surface side and the second electrode is in contact with the high-concentration second conductivity type region Having a first conductivity type buffer layer between the first conductivity type low resistance layer and the parallel pn layer, wherein the first conductivity type buffer layer is formed over an outside including at least a part of the active region. It is assumed that
[0017]
In this case, carriers accumulated in the first conductivity type buffer layer at the time of forward bias of the built-in diode are supplied to the second conductivity type partition region of the parallel pn layer of the active part by electric field distribution. Since carriers are present in the second conductivity type partition region of the parallel pn layer, the reverse recovery current due to carrier discharge from the breakdown voltage structure is not concentrated near the junction between the parallel pn layer and the second conductivity type well region. It flows through the one conductivity type buffer layer and the second conductivity type partition region of the active portion parallel pn layer. For this reason, current concentration near the anode electrode in the reverse recovery process of the diode built in the MOSFET or the like can be reduced, and the breakdown strength can be improved.
[0018]
Therefore, the first conductivity type buffer layer is preferably a higher resistance layer than the first conductivity type low resistance layer, and a lower resistance layer than the parallel pn layer.
It is assumed that the parallel pn layer includes at least two regions having different carrier lifetimes. Desirably, an area with a short lifetime is arranged outside the element active portion.
[0019]
By having regions where the lifetime is controlled to be at least two types or more, the amount of accumulated carriers in the region with a short lifetime including the breakdown voltage structure is reduced, and the reverse recovery is caused by the discharge of carriers from the breakdown voltage structure. The current can be reduced. For this reason, current concentration near the anode electrode in the reverse recovery process of the built-in diode built in the MOSFET or the like can be reduced, and the breakdown strength can be improved.
[0020]
Desirably, it is important that the carrier lifetime of the parallel pn layer outside the active region is controlled to be shorter than the carrier lifetime of the parallel pn layer in the active region.
Furthermore, a first portion of the parallel pn layer arranged at a first pitch in a region including the active region, and a parallel pn layer arranged at a second pitch equal to or smaller than the first pitch in a region outside the active region And the second part of the above.
[0021]
Since the depletion layer easily spreads in the small pitch portion, the accumulated carriers are dispersed, and current concentration hardly occurs.
If a channel stopper region of the first conductivity type is arranged outside the second portion of the parallel pn layer, it becomes a channel stopper for preventing surface inversion.
Not just
It is assumed that the surface of the second portion of the parallel pn layer is covered with an insulating film.
[0022]
Since the second part of the parallel pn layer is a part of a so-called breakdown voltage structure, it is often covered with a thick insulating film.
Since the channel stopper region of the first conductivity type is continuous with the low resistance layer of the first conductivity type formed below the parallel pn layer, all the side surfaces of the chip can have the same potential as the drain electrode 13. This stabilizes the withstand voltage of the element and improves the quality.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[Example 1]
FIG. 3 is a partial cross-sectional view of the super-junction MOSFET according to the first embodiment of the present invention. However, the parallel pn structures 20 and 23 are reduced to avoid complication of the drawing. The same applies to the following.
[0024]
In FIG. 3, parts having the same functions as those in FIG. The description is the same as in FIG.
11 is a low resistance n + The buffer layer 12 has a low resistance n ++ The drain layer 1 is a parallel pn layer 20 composed of a first conductivity type drift region and a second conductivity type partition region. In the surface layer, a p-well region 3 is formed continuously from the p-partition region 2. p inside the p well region 3 + Contact region 5 and n + A source region 6 is formed. n + On the surface of p well region 3 sandwiched between source region 6 and n drift region 1, a gate electrode layer 8 of polycrystalline silicon + Source region 6 and p + A source electrode 10 that is in common contact with the surface of the contact region 5 is provided. n ++ On the back surface of the drain layer 12, a drain electrode 13 is provided. Reference numeral 15 denotes an oxide film for protecting and stabilizing the surface, and is composed of, for example, a thermal oxide film and phosphor silica glass (PSG). The source electrode 10 is often extended over the gate electrode layer 8 via the interlayer insulating film 9 as shown in FIG. A gate electrode of a metal film is provided on the gate electrode layer 8 in a portion not shown.
[0025]
The pitch of the parallel pn layers 23 of the breakdown voltage structure section 60 is formed at the same pitch as that of the active section 50.
In the case of a diode built in a MOSFET, the source electrode 10 of the MOSFET serves as an anode electrode and the drain electrode 13 serves as a cathode electrode. The gate electrode of the MOSFET is often connected to the anode electrode.
[0026]
The planar shapes of the n drift region 1 and the p partition region 2 are, for example, both stripes. The planar shape of the n drift region 1 and the p partition region 2 may be a lattice shape or a mesh shape, and the other may be a shape sandwiched between them.
The withstand voltage structure in the first embodiment has a field plate structure which is usually performed, but may of course have a guard ring structure.
[0027]
In FIG. 3, a low-resistance n-channel stopper region 14 is arranged adjacent to the parallel pn layer 23 of the breakdown voltage structure 60, and the n-channel stopper region 14 + N via the buffer layer 11 ++ It is connected to the drain layer 12. The entire side surface of the semiconductor chip is covered with the n-channel stopper region 14, and a peripheral electrode 16 is provided in contact with the surface.
[0028]
The n-channel stopper region 14 not only functions as a channel stopper for preventing inversion of the surface but also allows all side surfaces of the chip to have the same potential as the drain electrode 13, thereby stabilizing the withstand voltage of the element, Quality also improves.
However, the n-channel stopper region 14 does not necessarily have to be a side surface of the chip, and another semiconductor element or another semiconductor region can be formed in the semiconductor region on the opposite side with the n-channel stopper region 14 interposed therebetween.
[0029]
In this embodiment, n ++ N on the drain layer 12 + The formation of the buffer layer 11 makes it possible to improve the reverse recovery resistance of the built-in diode of the MOSFET. This can be explained as follows.
When a forward bias is applied to the built-in diode, carriers are accumulated in the active portion 50 and the breakdown voltage structure portion 60. In the reverse recovery process, accumulated carriers are swept out by applying a reverse bias to the built-in diode.
[0030]
At this time, the active portion is completely depleted by a reverse bias of about 50 V. + Due to the presence of the buffer layer 11, n + The carriers accumulated in the buffer layer 11 are dispersed by the electric field distribution to the p-type partition region 2 of the parallel pn layer 20 of the active section 50 near the boundary between the active section 50 and the breakdown voltage structure section 60.
For this reason, the reverse recovery current due to the carrier sweeping out of the breakdown voltage structure portion 60 is not concentrated near the p partition region 2 at the end of the parallel pn layer 20 of the active portion 50, and is n + It flows from the buffer layer 11 to the p partition region 2 of the active portion parallel pn layer 20 in a distributed manner. Therefore, current concentration near the junction of the p-well region 3 is suppressed, and the reverse recovery withstand capability is improved.
[0031]
In the case of a MOSFET of, for example, a 600 V class, the standard size and impurity concentration of each part take the following values. n ++ The impurity concentration of the drain layer 12 is 1 × 10 18 cm -3 , Thickness 5 μm, n + 4 × 10 impurity concentration of buffer layer 11 Fifteen cm -3 , Thickness of 30 μm, impurity concentration of n drift region 1 and p partition region 2 of 2.57 × 10 Fifteen cm -3 , A thickness of 42 μm, a width of 8 μm, and an impurity concentration of 5 × 10 14 cm -3 It is.
[0032]
n + The impurity concentration of the buffer layer 11 is n ++ It is lower than that of the drain layer 12 and higher than that of the parallel pn layer. Note that n + The buffer layer 11 can be formed by, for example, an epitaxial growth method.
FIG. 4 is a partial cross-sectional view near the gate pad of the MOSFET of the first embodiment.
In the present embodiment, n is also provided below the gate pad 18. + A buffer layer 11 is provided. Thereby, the carriers swept out in the reverse recovery process of the built-in diode become n + Since the dispersion is dispersed through the buffer layer 11, the concentration of the reverse recovery current in the p-well region 3 formed on both sides immediately below the gate pad 18 can be reduced, and the reverse recovery tolerance can be improved.
[0033]
In this embodiment, the p-well region 3 is not provided immediately below the gate pad 18, but the p-well region 3 may be provided. Further, the pitch of the parallel pn layer immediately below the gate pad 18 may be smaller than the pitch of the parallel pn layer of the active portion, or the net impurity concentration may be lower.
[Example 2]
FIG. 1 is a partial cross-sectional view of a MOSFET according to a second embodiment of the present invention.
[0034]
The difference from the first embodiment shown in FIG. 3 is that the pitch (P2) of a part of the parallel pn layers 23 of the breakdown voltage structure section 60 is formed at a smaller pitch than that of the active section 50 (P1). . Specifically, P2 was set to 1/2 of P1. This portion can be formed in exactly the same manner as the other pn layer portions, only by changing the dimensions of the mask during manufacture.
The portion having the small pitch was set to the vicinity where the source electrode 10 extends on the field insulating film 15. In the breakdown voltage structure 60, since the pitch is narrow, the depletion layer easily spreads, so that the accumulated carriers are dispersed and current concentration hardly occurs.
[0035]
In this case, n is the same as in the first embodiment. + The impurity concentration of the buffer layer 11 is n ++ It is lower than that of the drain layer 12 and higher than that of the parallel pn layer. And n + Due to the presence of the buffer layer 11, the current generated by the discharge of the accumulated carriers of the built-in diode is dispersed in the p partition region 2 of the parallel pn layer 23 of the active portion 50, and the current concentration is reduced.
FIGS. 2A and 2B are gray scale diagrams each showing a simulation result of the carrier current density and the carrier density at the time of reverse recovery at this time, where the higher the density, the higher the density.
[0036]
From FIG. 2, n + The presence of the buffer layer 11 causes the accumulated carriers of the built-in diode to be dispersed, and the current due to the sweeping out of the carriers is dispersed to the p-type partition region 2 of the parallel pn layer 20 of the active portion 50, and the contact portion of the anode electrode 10 ( The current concentration in the vicinity of section E) is 1 × 10 A / cm 2 This indicates that the current concentration is reduced.
[0037]
The actually fabricated device exhibited a withstand capability of at least eight times that of the conventional MOSFET.
[Example 3]
FIG. 5 is a partial cross-sectional view of a MOSFET according to a third embodiment of the present invention.
The difference from the second embodiment shown in FIG. 1 is that the pitch (P2) of the parallel pn layers 23 of the breakdown voltage structure section 60 is formed at a pitch smaller than that of the active section 50 (P1) up to the p-well region 3 of the active section 50. That is the point.
[0038]
As a result, the depletion layer is likely to spread near the end of the p-well region 3, so that the accumulated carriers are dispersed, and current concentration hardly occurs.
In this case, the same effect as in the second embodiment can be obtained.
[Example 4]
FIG. 6 is a partial cross-sectional view of a MOSFET according to a fourth embodiment of the present invention.
[0039]
The difference from the third embodiment of FIG. 5 is that the parallel pn layers 23 having a pitch (P2) smaller than that of the active portion 50 (P1) are formed only on the surface side of the breakdown voltage structure portion 60. In the breakdown voltage structure 60, since the pitch is narrow, the depletion layer easily spreads, so that the accumulated carriers are dispersed and the current concentration hardly occurs.
In this case, the same effect as in the third embodiment can be obtained.
[Example 5]
FIG. 7 is a partial cross-sectional view of a MOSFET according to a fifth embodiment of the present invention.
[0040]
This is a case where the junction of the parallel pn layers 23 of the withstand voltage horizontal structure 60 is wavy. For example, the junction of the pn layer 23 may be formed depending on the method of manufacturing the parallel pn layer 23, such as repeating buried diffusion of p-type impurities, epitaxial growth, and heat treatment.
In this case, the same effect as in the first embodiment can be obtained.
[Example 6]
FIG. 8 is a partial cross-sectional view of a MOSFET according to a sixth embodiment of the present invention.
[0041]
This is a case where the p partition region 22 of the parallel pn layer 23 of the breakdown voltage structure section 60 is not continuous in the depth direction. In the n drift region 21 and the p partition region 22 of the parallel pn layer 23 of the breakdown voltage structure 60, various combinations of impurity concentrations and shapes can be taken under the condition that depletion is performed at a constant voltage. Is also conceivable.
[Example 7]
FIG. 9 is a partial cross-sectional view of a MOSFET according to a seventh embodiment of the present invention.
[0042]
The difference from the third embodiment is n + The point is that there is no buffer layer 11. For this reason, n + Dispersion of the reverse recovery current of the built-in diode through the buffer layer 11 does not occur.
However, in this embodiment, since the pitch (P2) of the parallel pn layers 23 of the breakdown voltage structure section 60 is narrower than the pitch (P1) of the parallel pn layers 20 of the active section 50, the parallel pn layer 23 of the breakdown voltage structure section 60 has The net impurity concentration is lower than that of the parallel pn layer 20 of the active portion 50.
[0043]
For this reason, the electric field of the parallel pn layer at the boundary between the active portion 50 and the breakdown voltage structure portion 60 is reduced, and the reverse recovery withstand is improved by reducing the current concentration.
FIGS. 10A and 10B are gray scale diagrams respectively showing the simulation results of the carrier current density and the carrier density at the time of the reverse recovery at this time, where the higher the density, the higher the density.
From FIG. 10, it can be seen that the accumulated carriers of the built-in diode are dispersed over a wide range, and that the current concentration near the anode electrode (E part) due to the sweeping out of the carriers is reduced. Current concentration is 2 × 10 A / cm 2 This indicates that the current concentration is reduced.
[0044]
The actually manufactured device exhibited a tolerance of five times or more that of the conventional MOSFET.
Example 8
FIG. 11 is a partial cross-sectional view of a MOSFET according to an eighth embodiment of the present invention.
The MOSFET of the eighth embodiment is characterized in that a lifetime adjustment region 24 whose lifetime is controlled to be short is provided in the parallel pn layer 23 of the breakdown voltage structure section 60, which is indicated by hatching.
[0045]
The adjustment region 24 having a short life time includes a junction region between the parallel pn layer 23 of the breakdown voltage structure portion 60 and the p-well region 3 at the outermost periphery of the active portion 50 and a p-well region 3 at the outermost periphery of the active portion 50. The anode electrode 10 is formed in a region including a region in contact with the anode electrode 10.
As shown in FIG. 14, the reverse recovery current of the built-in diode concentrates in the p partition region 22 of the parallel pn layer 23 of the withstand voltage structure 60 adjacent to the p well region 3 on the outermost periphery of the active portion 50. there were.
[0046]
Therefore, if this region is a region having a short life time, carriers discharged from the breakdown voltage structure during reverse recovery are recombined in the region having a short life time, current concentration is reduced, and the reverse recovery withstand capability is improved.
Such a region having a short lifetime can be easily formed by using a crystal defect introduction method using a particle beam such as electron beam irradiation, helium ion irradiation, or proton irradiation. In this embodiment, n ++ An electron beam was irradiated at an acceleration voltage of 4.8 MeV and about 160 kilogray (kgry) from the drain layer 12 side. It may be adjusted in the range of 100 to 500 kgry depending on conditions.
[0047]
That is, a mask having a structure in which a window is opened in a portion where the lifetime is desired to be shortened is manufactured using a material capable of blocking helium ions and protons (for example, aluminum metal and a thick resist film). Then, the upper part of the mask is irradiated with a particle beam from a direction perpendicular to the mask.
In the case where a region having a short lifetime is formed over the entire depth of the parallel pn layer as in this embodiment, the irradiation search may be set to a portion deeper than the thickness of the parallel pn layer to allow helium ions or protons to pass. Alternatively, a crystal defect may be introduced by changing the irradiation depth and performing irradiation several times separately.
[0048]
The actually fabricated device exhibited a reverse recovery withstand capability of at least eight times that of the conventional MOSFET.
Since the region 24 in which the lifetime is controlled to be short is only the breakdown voltage structure portion 60 without including the active region 50, the forward voltage (ON voltage) does not increase.
[Example 9]
FIG. 12 is a partial cross-sectional view of a MOSFET according to a ninth embodiment of the present invention.
[0049]
In the eighth embodiment, the region 24 with a short lifetime is formed in a part of the withstand voltage structure 60. However, as shown in FIG.
In addition, by combining the methods of the above embodiments, a combined effect can be obtained, and the reverse recovery resistance can be improved.
[0050]
Although the present embodiment is described with a built-in MOSFET diode, a similar effect can be obtained with a free wheel diode, a Schottky diode or the like.
[0051]
【The invention's effect】
As described above, according to the present invention, the first conductivity type low resistance layer in contact with the first electrode between the first and second main surfaces, the first conductivity type drift region and the second conductivity type partition region, And an active region including a second conductivity type region is selectively formed in a surface layer on the first main surface side of the parallel pn layer, and a second conductivity type region is formed in the second pn layer. In the semiconductor element with which the electrodes are in contact, a first conductivity type buffer layer is provided between the first conductivity type low resistance layer and the parallel pn layer, or a parallel pn layer having a different pitch is provided in a region outside the active region. By providing a second portion or making the carrier lifetime of the parallel pn layer outside the active region shorter than the carrier lifetime of the parallel pn layer outside the active region, the reverse of the diode built in the MOSFET or the like is performed. Current collection near the anode electrode during the recovery process Relaxed, it is possible to improve the breakdown resistance.
[0052]
All of these are very effective inventions that have been demonstrated to be feasible by application of the conventional technology, and to have a large breakdown strength of 6 times or more and a large effect.
[Brief description of the drawings]
FIG. 1 is a schematic partial cross-sectional view of a MOSFET according to a second embodiment of the present invention.
FIGS. 2 (a) and 2 (b) are graphs showing the results of simulation of carrier current density and carrier density in the reverse recovery process of a built-in diode in the MOSFET of Example 2 by shading;
FIG. 3 is a schematic partial cross-sectional view of the MOSFET according to the first embodiment of the present invention.
FIG. 4 is a partial cross-sectional view of a gate pad portion of the MOSFET according to the first embodiment.
FIG. 5 is a schematic partial sectional view of a MOSFET according to a third embodiment of the present invention.
FIG. 6 is a schematic partial sectional view of a MOSFET according to a fourth embodiment of the present invention.
FIG. 7 is a schematic partial sectional view of a MOSFET according to a fifth embodiment of the present invention.
FIG. 8 is a schematic partial sectional view of a MOSFET according to a sixth embodiment of the present invention.
FIG. 9 is a schematic partial sectional view of a MOSFET according to a seventh embodiment of the present invention.
FIGS. 10A and 10B are graphs showing the results of simulation of carrier current density and carrier density in the reverse recovery process of the built-in diode in the MOSFET of Example 7 by shading;
FIG. 11 is a schematic partial sectional view of a MOSFET according to an eighth embodiment of the present invention.
FIG. 12 is a schematic partial sectional view of a MOSFET according to a ninth embodiment of the present invention.
FIG. 13 is a partial cross-sectional view of a conventional MOSFET.
14 (a) and 14 (b) are graphs showing the results of simulation of carrier current density and carrier density in the process of reverse recovery of a built-in diode in a conventional MOSFET by shading
FIG. 15 is a partial cross-sectional view of a gate pad portion of a conventional MOSFET.
[Explanation of symbols]
1 n drift region
2p partition area
3 p-well region
4 Surface n drift region
5 p + Contact area
6 n + Source area
7 Gate insulating film
8 Gate electrode layer
9 Interlayer insulation film
10 Source electrode, anode electrode of built-in diode
11 n + Buffer layer
12 n ++ Drain layer
13 Drain electrode, cathode electrode of built-in diode
14 n-channel stopper region
15 Field insulation film
16 Peripheral electrode
17 Insulating film
18 Gate pad
20 Parallel pn layer (active part)
21 n drift region
22p partition area
23 Parallel pn layer (withstand voltage structure)
24 Lifetime control area
50 Active part
60 pressure resistant structure

Claims (10)

第一と第二の主面と、第一と第二の主面にそれぞれ設けられた第一と第二の電極と、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層とを有し、並列ｐｎ層の第一の主面側の表面層に第二導電型領域を含む活性領域が選択的に形成され、その第二導電型領域に第二の電極が接している半導体素子において、前記第一導電型低抵抗層と並列ｐｎ層との間に、第一導電型バッファ層を有し、前記第一導電型バッファ層は、少なくとも前記活性領域の一部を含む外側にわたり形成されていることを特徴とする半導体素子。First and second main surfaces, first and second electrodes provided on the first and second main surfaces, respectively, and a first electrode in contact with the first electrode between the first and second main surfaces. A conductive type low-resistance layer, and a parallel pn layer in which first conductive type drift regions and second conductive type partition regions are alternately arranged. An active region including a conductivity type region is selectively formed, and in a semiconductor element in which a second electrode is in contact with the second conductivity type region, between the first conductivity type low resistance layer and the parallel pn layer, A semiconductor device having a first conductivity type buffer layer, wherein the first conductivity type buffer layer is formed over an outside including at least a part of the active region. 前記第一導電型バッファ層は、前記第一導電型低抵抗層よりも高抵抗層であることを特徴とする請求項１に記載の半導体素子。The semiconductor device according to claim 1, wherein the first conductivity type buffer layer is a higher resistance layer than the first conductivity type low resistance layer. 前記第一導電型バッファ層は、並列ｐｎ層に比べ低抵抗層であることを特徴とする請求項２に記載の半導体素子。3. The semiconductor device according to claim 2, wherein the first conductivity type buffer layer is a lower resistance layer than a parallel pn layer. 半導体素子が絶縁ゲート型電界効果トランジスタであり、そのゲートパッドの下方に前記第一導電型バッファ層を有することを特徴とする請求項３に記載の半導体素子。4. The semiconductor device according to claim 3, wherein the semiconductor device is an insulated gate field effect transistor, and has the first conductivity type buffer layer below a gate pad. 第一と第二の主面と、第一と第二の主面にそれぞれ設けられた第一と第二の電極と、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層とを有し、並列ｐｎ層の第一の主面側の表面層に第二導電型領域を含む活性領域が選択的に形成され、その第二導電型領域に第二の電極が接している半導体素子において、並列ｐｎ層がキャリアライフタイムが異なる少なくとも二つの領域からなることを特徴とする半導体素子。First and second main surfaces, first and second electrodes provided on the first and second main surfaces, respectively, and a first electrode in contact with the first electrode between the first and second main surfaces. A conductive type low-resistance layer, and a parallel pn layer in which first conductive type drift regions and second conductive type partition regions are alternately arranged. In a semiconductor device in which an active region including a conductivity type region is selectively formed and a second electrode is in contact with the second conductivity type region, the parallel pn layer includes at least two regions having different carrier lifetimes. Characteristic semiconductor element. 活性領域の外側の並列ｐｎ層のキャリアライフタイムが、活性領域の並列ｐｎ層のキャリアライフタイムより短く制御されていることを特徴とする請求項５に記載の半導体素子。The semiconductor device according to claim 5, wherein the carrier lifetime of the parallel pn layer outside the active region is controlled to be shorter than the carrier lifetime of the parallel pn layer in the active region. 第一と第二の主面にそれぞれ設けられた第一と第二の電極と、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層とを有し、並列ｐｎ層の第一の主面側の表面層に高濃度の第二導電型領域を含む活性領域が選択的に形成されている半導体素子において、活性領域を含む領域に第一のピッチで配置した並列ｐｎ層の第一の部分と、活性領域の外側の領域に第一のピッチと同じ、若しくは異なる第二のピッチで配置した並列ｐｎ層の第二の部分とを有していることを特徴とする請求項１ないし６のいずれかに記載の半導体素子。First and second electrodes respectively provided on the first and second main surfaces, a first conductivity type low resistance layer in contact with the first electrode between the first and second main surfaces, Active region having parallel pn layers in which mold drift regions and second conductivity type partition regions are alternately arranged, and including a high-concentration second conductivity type region in a surface layer on the first principal surface side of the parallel pn layers In the semiconductor element where is selectively formed, the first portion of the parallel pn layer arranged at a first pitch in a region including the active region, and the same as the first pitch in a region outside the active region, or 7. The semiconductor device according to claim 1, further comprising a second portion of the parallel pn layer arranged at a different second pitch. 並列ｐｎ層の第二の部分の外側に第一導電型のチャネルストッパ領域を配置したことを特徴とする請求項７に記載の半導体素子。8. The semiconductor device according to claim 7, wherein a channel stopper region of the first conductivity type is arranged outside the second portion of the parallel pn layer. 並列ｐｎ層の第二の部分の表面が絶縁膜で覆われていることを特徴とする請求項８に記載の半導体素子。9. The semiconductor device according to claim 8, wherein the surface of the second portion of the parallel pn layer is covered with an insulating film. 第一導電型のチャネルストッパ領域が、並列ｐｎ層の下方に形成されている第一導電型低抵抗層と連続していることを特徴とする請求項９に記載の半導体素子。10. The semiconductor device according to claim 9, wherein the first conductivity type channel stopper region is continuous with the first conductivity type low resistance layer formed below the parallel pn layer.
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