JP2004005936A - Information-recording medium, recording device and recording device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize information reproduction which prevents unauthorized copying digital works recorded on an optical disk to other optical disks and which is stabilized. <P>SOLUTION: When main information is recorded as a recording mark, an edge position of the record mark is displaced very slightly in the track direction and sub-information is recorded, It is determined whether to displace the edge position of the recording mark in the phase lead direction or in the of phase lag direction, based on a frequency lower than one half of the reference frequency of the write clock for forming the recording mark and based on a frequency which is higher than the response frequency of a phase-locked loop (PLL) for generating a reproducing channel clock, when the main information is reproduced. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information recording medium, a recording apparatus for recording information on the information recording medium, and a reproducing apparatus for reproducing information from the information recording medium, and more particularly, to a technique for recording sub-information in main information.
[0002]
[Prior art]
An optical disk represented by a DVD (Digital Versatile / Video Disc) is widely used as a medium for recording large-capacity digital data such as AV (Audio Video) data and computer data. For example, high-quality moving images of two hours or more are recorded on a read-only optical disk and sold. In order to prevent such digital works from being illegally copied to another recording medium, a method called content encryption has been introduced (see Non-Patent Document 1).
[0003]
In this method, compressed digital content such as a movie is encrypted using a three-layer secret key (title key, disk key, master key) and recorded in a user information area accessible to a user. . Then, the most important master key among the secret keys is notified only to the authorized manufacturer, and the disk key and title key required for each DVD and each title are encrypted based on the master key. , In a control information area that cannot be accessed by the user. As a result, the user is restricted from accessing the private key required for decryption, and cannot perform illegal copying by file copying or the like. However, in such a technique, if the contents of the entire recording area including the control information area in which the secret key is recorded are illegally copied to another optical disk as it is, the encrypted content is reproduced by the authorized reproducing apparatus. It is decrypted and played.
[0004]
Therefore, normal main information is recorded by changing the length or interval of a pit or a recording mark formed on a track so that a reproduction signal that changes at a period that is an integral multiple of a predetermined basic period is obtained, On the other hand, a method of recording information such as an identification code for identifying an optical information recording medium by moving a position of a leading edge or a trailing edge of these pits or marks from a position determined by ordinary information by a small amount. Has been proposed (see Patent Document 1).
[0005]
This conventional example will be described with reference to FIG. FIG. 7 shows a conventional optical information recording device 501. As shown in FIG. 7, the optical information recording device 501 records digital information on the optical information recording medium 502 by modulating the recording light L applied to the optical information recording medium 502. The optical information recording device 501 includes a modulation circuit 504, a disc identification code generation circuit 505, a second modulation circuit 506, an optical modulator 507, a spindle servo 508, and a recording laser 509.
[0006]
The modulation circuit 504 generates a first modulation signal S2 by switching a signal level at a cycle that is an integral multiple of a predetermined basic cycle according to the first digital information D1 from the digital audio tape recorder 503.
[0007]
The second modulating circuit 506 responds to the second digital information SC1 (which is a disk identification code in the conventional example and is output from the disk identification code generation circuit 505) other than the first digital information D1. A double modulation signal SC is generated by modulating the timing of the level change of the modulation signal S2. The optical modulator 507 modulates the recording light L according to the double modulation signal SC.
[0008]
FIG. 8 shows the second modulation circuit 506, and FIG. 9 shows a timing chart of each element in the second modulation circuit 506. 8, the EFM signal S2 input to the second modulation circuit 506 is input to monostable multivibrators 510A and 510B, and the monostable multivibrators 510A and 510B detect the rising edge and the falling edge of the EFM signal S2, respectively. Then, a rising edge detection pulse MMS and a falling edge detection pulse MMR are output (see FIG. 9). The rising edge detection pulse MMS and a signal obtained by delaying the rising edge detection pulse MMS by the delay circuit 512A are input to the data selector 511A. The falling edge detection pulse MMR and a signal obtained by delaying the falling edge detection pulse MMR by the delay circuit 512B are input to the data selector 511B. The disk identification information SC1 is initialized by the frame clock FCK. The M-sequence code MS is generated based on the channel clock CK generated by the PLL 513. The control signal MS1 is generated by performing an exclusive OR operation on the initialized disc identification information SC1 and the M-sequence code MS. The control signal MS1 and the inverted control signal MS1 are input to the selection input terminals of the data selectors 511A and 511B.
[0009]
When the control signal MS1 indicates "H", the data selector 511A selects the rising edge detection pulse MMS delayed by the delay circuit 512A and outputs the same as the rising edge pulse SS. When the control signal MS1 indicates "L", the rising edge detection pulse MMS without delay is selected and output as the rising edge pulse SS. When the control signal MS1 indicates "L", the data selector 511B selects the falling edge detection pulse MMR delayed by the delay circuit 512B and outputs it as a falling edge pulse RR. When the control signal MS1 indicates "H", the falling edge detection pulse MMR without delay is selected and output as the falling edge pulse RR.
[0010]
The rising edge pulse SS and the falling edge pulse RR are reconfigured into an EFM signal by the set / reset flip-flop 514. As a result, the edge of the EFM signal is partially delayed. According to such a recording method, the disc identification information superimposed on the edge of the recording mark cannot be copied even if the contents of the entire recording area are illegally bit-copied to another optical disc as it is. For this reason, for example, when the disc identification information is detected during reproduction and the disc identification information cannot be reproduced, the reproduction operation can be stopped.
[Patent Document 1]
JP-A-11-126426
[Non-patent document 1]
Nikkei Electronics 1996, 11, 18 P13-14
[0011]
[Problems to be solved by the invention]
However, in such a conventional technique, when detecting the sub-information superimposed on the main information, bit shift may occur due to dust or scratches on the disc, and the bit shift may be added to the edge of the EFM signal during recording. In some cases, the correspondence between the delayed position and the control signal that determines the edge position to be delayed is shifted. At this time, the first digital information D1 has a problem that although the information can be correctly reproduced by the error correction processing, the sub-information cannot be correctly detected.
[0012]
In view of the above problems, the present invention prevents the recorded contents of an information recording medium on which a digital work is recorded from being illegally copied in its entirety, and has little effect on existing playback devices and the like. An object of the present invention is to provide an information recording medium capable of stably reproducing sub-information even when there is a scratch or dust, a recording device for recording information on the information recording medium, and a reproducing device for reproducing information from the information recording medium. And
[0013]
[Means for Solving the Problems]
An information recording medium for recording main information and sub-information of the present invention has a track, and the information recording medium has one of a pit indicating the main information and a recording mark indicating the main information. The main information is recorded by being formed on the information recording medium along a track direction, and the edge position of one of the pits and the recording marks is set on the information recording medium by a phase along the track direction. The sub-information is recorded by being displaced in one of the leading direction and the phase-lagging direction. Whether the edge position is displaced in the phase-leading direction or in the phase-lagging direction for recording the sub-information Is determined based on a predetermined frequency, and the predetermined frequency is determined by a recording clock for forming one of the pit and the recording mark. Than half of the quasi frequency substantially always lower, higher than the response frequency of the PLL for generating a reproduction clock for reproducing the main information, the object is achieved.
[0014]
The predetermined frequency is determined based on a result of a logical operation of the predetermined binary sequence and the sub information, and the frequency of the predetermined binary sequence is set to be less than の of a reference frequency of the recording clock. And may be higher than the response frequency of the PLL.
[0015]
The predetermined binary sequence is a pseudo-random number sequence including a plurality of elements, and the predetermined frequency is a further logic of a PE modulation signal whose logic is inverted at the center of each of the plurality of elements and a result of the logic operation. The frequency of the PE modulation signal is determined based on a result of the calculation, and may be lower than １ ／ of a reference frequency of the recording clock.
[0016]
A recording apparatus for recording main information and sub-information on an information recording medium having a track according to the present invention includes a recording signal generating unit that generates a recording signal indicating the main information synchronized with a recording clock, and an edge position of the recording signal. A phase modulation unit that generates a phase modulation recording signal indicating the main information and the sub information by modulating the phase modulation direction into one of a phase advance direction of the recording signal and a phase delay direction of the recording signal; Based on the recording signal, so that one edge position of the pit indicating the main information and the recording mark indicating the main information is displaced in one of a phase leading direction and a phase delay direction along the track direction. By forming one of the pits and the recording marks on the information recording medium along the track direction, the main information and the sub information are A recording unit for recording on the information recording medium, the phase modulation unit, whether to modulate the edge position of the recording signal in the phase leading direction of the recording signal or to modulate the phase delay direction of the recording signal, The predetermined frequency is determined based on a predetermined frequency, and the predetermined frequency is substantially always lower than の of a reference frequency of the recording clock, and the PLL for generating a reproduction clock for reproducing the main information is used. Higher than the response frequency, thereby achieving the above objective.
[0017]
A binary sequence generating unit that generates a predetermined binary sequence, a sub-information output unit that outputs the sub-information, performs a logical operation on the predetermined binary sequence and the sub-information, and outputs a result of the logical operation. A logic operation unit that generates a control signal indicating the predetermined frequency based on the recording signal. The phase modulation unit modulates an edge position of the recording signal in a phase leading direction of the recording signal or a phase of the recording signal. Whether to modulate in the delay direction is determined based on the predetermined frequency indicated by the control signal, and the frequency of the predetermined binary sequence is lower than の of a reference frequency of the recording clock, and It may be higher than the response frequency.
[0018]
The predetermined binary sequence is a pseudo-random number sequence including a plurality of elements, and the recording apparatus further includes a PE modulation signal generation unit that generates a PE modulation signal that is logically inverted at the center of each of the plurality of elements. , The logical operation unit performs a further logical operation of the PE modulation signal and the result of the logical operation, generates the control signal based on the result of the further logical operation, the frequency of the PE modulation signal, The frequency may be lower than 1/2 of the reference frequency of the recording clock and higher than the response frequency of the PLL.
[0019]
In a reproducing apparatus for reproducing main information and sub information recorded on an information recording medium according to the present invention, the information recording medium has a track, and the information recording medium has a pit indicating the main information and the main information. The main information is recorded by forming one of the recording marks indicating the information on the information recording medium along the track direction, and the information recording medium has one of the pit and the recording mark. The sub-information is recorded by displacing the edge position in one of a phase advance direction and a phase delay direction along the track direction, and the reproducing device performs one of the pit and the recording mark. And a PLL for generating a read signal synchronized with the read signal, a PLL for generating a read clock synchronized with the read signal, and a phase of the read signal. Comparing the phase of the reproduced clock, and if the phase of the read signal is ahead of the phase of the reproduced clock, generate a phase advance signal indicating that the phase of the read signal is advanced; A phase comparing section that generates a delayed signal indicating that the phase of the read signal is delayed when the phase of the signal is delayed from the phase of the reproduced clock; and the advanced signal based on a predetermined frequency. A sub-information detection unit that detects the sub-information based on the result of the integration, and a demodulation unit that detects the main information by demodulating the read signal, The predetermined frequency is substantially always lower than 基準 of a reference frequency of a recording clock for forming one of the pit and the recording mark, and a response frequency of the PLL. Remote high, the object can be achieved.
[0020]
The sub information detection unit may detect the value of the sub information by comparing the result of the integration with a predetermined positive threshold value and a predetermined negative threshold value.
[0021]
The sub-information detecting unit may detect the presence or absence of the sub-information by comparing the result of the integration with a predetermined positive threshold and a predetermined negative threshold.
[0022]
A pseudo-random number sequence generation unit that generates a pseudo-random number sequence including a plurality of elements; a PE modulation signal generation unit that generates a PE modulation signal that is logically inverted at the center of each of the plurality of elements; A logical operation unit that performs a logical operation on the PE modulation signal and generates a control signal indicating the predetermined frequency based on a result of the logical operation. The phase advance signal and the phase delay signal are integrated based on a predetermined frequency, and the frequency of the pseudo-random number sequence and the frequency of the PE modulation signal are lower than 基準 of the reference frequency of the recording clock. It may be higher than the response frequency of the PLL.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0024]
FIG. 1 shows an optical disc recording apparatus 100 according to an embodiment of the present invention. The optical disc recording apparatus 100 includes an error correction addition circuit 1, a modulation circuit 2, a phase modulation circuit 3, a recording channel 4, a recording head 5, a synchronization signal detection circuit 7, a timing generation circuit 8, a pseudo random number generation The circuit includes a circuit 9, a sub information output circuit 10, a logical operation circuit 11, and a PE (Phase Encoding) modulation circuit 12. The optical disk recording device 100 has an optical disk 6 mounted thereon as an information recording medium. The optical disc 6 has a track 320 (FIG. 5).
[0025]
The error correction addition circuit 1 calculates an error correction code of the main information 201 input from an external device or the like (not shown) and adds the error correction code to the main information 201. The modulation circuit 2 functions as a recording signal generation unit that generates a recording channel signal 202 indicating the main information 201 synchronized with the recording channel bit clock 206. The modulation circuit 2 modulates the main information 201 ′ to which the error correction code has been added, and generates a recording channel signal 202 obtained by subjecting the modulation code to NRZi conversion. The recording channel signal 202 indicates the main information 201.
[0026]
The phase modulation circuit 3 performs phase modulation on the recording channel signal 202 generated by the modulation circuit 2 based on a phase modulation control signal 212 described later. The phase modulation circuit 3 slightly advances or delays the phase of the rising edge and the falling edge of the input recording channel signal 202 according to the polarity of the phase modulation control signal 212. The phase modulation circuit 3 outputs a modulated recording channel signal 203 obtained by phase-modulating the recording channel signal 202. The modulated recording channel signal 203 indicates the main information 201 and the sub information 210.
[0027]
The recording channel 4 and the recording head 5 function as a recording unit that records the main information 201 and the sub information 210 on the optical disc 6. Based on the modulated recording channel signal 203, the recording channel 4 and the recording head 5 determine whether the edge position of the pit indicating the main information 201 or the recording mark indicating the main information 201 is in the phase advance direction and the phase delay direction along the track direction. By forming pits or recording marks on the optical disc 6 along the track direction so as to be displaced to one of the two, the main information 201 and the sub-information 210 are recorded on the optical disc 6. The recording channel 4 generates a control signal 204 for changing the recording power of the laser beam output to the optical disc 6 according to the polarity of the modulated recording channel signal 203 and outputs the control signal 204 to the recording head 5. The recording head 5 forms an optically readable modulated recording pit or a modulated recording mark on the optical disk 6 while changing the power of the laser beam based on the control signal 204 from the recording channel 4.
[0028]
The synchronization signal detection circuit 7 detects a synchronization signal 205 added to the main information 201 by the modulation circuit 2. The timing generation circuit 8 functions as a PE modulation reference signal generation unit. The timing generation circuit 8 receives a recording channel bit clock 206 synchronized with the recording channel signal 202 from an external device or the like (not shown), and generates a pseudo random number sequence (binary sequence generation unit) 9 generated by a pseudo random number generation circuit (binary sequence generation unit) 9. A random number generation clock 207 and a PE modulation reference signal 208 indicating the generation timing of the base sequence are generated and output.
[0029]
In this embodiment, the timing generation circuit 8 sets the “Low” section and the “High” section for every 16 recording channel bit clocks in the 32 recording channel bit clocks 206 based on the synchronization signal 205. And outputs a PE modulation reference signal 208 that switches between. The random number generation clock 207 is a signal obtained by inverting the PE modulation reference signal 208, and the pseudo random number generation circuit 9 updates the pseudo random number sequence 209 at each rising edge of the random number generation clock 207. The frequency of the pseudo-random number sequence 209 (ie, the frequency of the random number generation clock 207 serving as a reference for generating the pseudo-random number sequence 209) is lower than １ ／ of the reference frequency of the recording channel bit clock 206, and the main information 201 is reproduced. Is higher than the response frequency of the PLL (Phase-Locked Loop) 45 (FIG. 3) for generating the reproduction channel clock 304 (FIG. 5). As shown in FIG. 2, in this embodiment, one cycle of the reference frequency of the recording channel bit clock 206 is one clock. In the present embodiment, one cycle of at least one of the random number generation clock 207 and the PE modulation reference signal 208 is 32 clocks.
[0030]
The sub information output circuit 10 stores, as the sub information 210, for example, disc identification information, a secret key for encrypting and recording digital content on the optical disc 6, and the like. The sub information output circuit 10 outputs the sub information 210 one bit at a time according to the synchronization signal 205. In the present embodiment, the sub-information 210 is generated inside the optical disc recording apparatus 100. The sub-information 210 may be input from an external device (not shown). A mechanism for extracting 210 may be used.
[0031]
The logical operation circuit 11 and the PE modulation circuit 12 function as a logical operation unit. The logical operation circuit 11 performs an exclusive OR operation on the pseudo-random number sequence 209 output from the pseudo-random number generation circuit 9 and the sub information 210 output from the sub information output circuit 10. The PE modulation circuit 12 performs PE modulation on the exclusive OR output signal 211 output from the logical operation circuit 11 using the PE modulation reference signal 208. The exclusive OR output signal 211 indicates the result of the operation performed by the logical operation circuit 11. Specifically, the PE modulation circuit 12 performs an exclusive OR operation on the exclusive OR output signal 211 and the PE modulation reference signal 208. As a result, the PE modulation circuit 12 generates the phase modulation control signal 212 in which the polarity is inverted at the center of the exclusive OR output signal 211. The PE modulation circuit 12 outputs “01” when the exclusive OR output signal 211 indicates “1”, and outputs “10” when the exclusive OR output signal 211 indicates “0”.
[0032]
In the present embodiment, since the exclusive OR output signal 211 is a pseudo-random number sequence that is updated every 32 clocks of the recording channel bit clock 206, it is located at the center of the 1-bit pseudo-random number sequence (that is, the recording channel bit clock 206). Every 16 clocks of the clock 206), the polarity of the phase modulation control signal 212 is inverted.
[0033]
The phase modulation circuit 3 receives the phase modulation control signal 212. The phase modulation circuit 3 determines whether to modulate the edge position of the recording channel signal 202 in the phase leading direction of the recording channel signal 202 or in the phase delaying direction of the recording channel signal 202 based on the frequency of the phase modulation control signal 212. decide. The frequency of the phase modulation control signal 212 is substantially always lower than 基準 of the reference frequency of the recording channel bit clock 206, and is used to generate the reproduction channel clock 304 (FIG. 5) for reproducing the main information 201. Is higher than the response frequency of the PLL 45 (FIG. 3). The expression “substantially always low” means that an error such that a frequency equal to or more than の of the reference frequency is included in the phase modulation control signal 212 to the extent of noise is slightly tolerated. The phase modulation circuit 3 advances or delays the phase of each edge of the recording channel signal 202 in accordance with the polarity of the phase modulation control signal 212 at each edge point of the recording channel signal 202. Specifically, when the phase modulation control signal 212 indicates “1”, the phase of the edge of the recording channel signal 202 is advanced, and when the phase modulation control signal 212 indicates “0”, the edge of the recording channel signal 202 increases. Delay the phase. In this way, the laser emission of the recording head 5 is controlled by the modulated recording channel signal 203 having undergone the phase modulation via the recording channel 4, and a recording mark is formed on the optical disk 6.
[0034]
FIG. 2 shows a timing chart of each element of the optical disc recording apparatus 100 according to the present embodiment. With reference to FIG. 2, the operation of optical disc recording apparatus 100 of the present embodiment will be further described. The main information 201 'to which the error correction code is added by the error correction addition circuit 1 is subjected to modulation processing in the modulation circuit 2 and a synchronization signal is added. The modulated main information 201 ′ is subjected to NRZi conversion, and then output to the phase modulation circuit 3 as a recording channel signal 202.
[0035]
The synchronization signal detection circuit 7 detects and outputs the synchronization signal 205 added in the modulation circuit 2. The timing generation circuit 8 generates a PE modulation reference signal 208 and a random number generation clock 207 which is an inverted signal of the PE modulation reference signal 208 from a recording channel bit clock 206 synchronized with the recording channel signal 202 with reference to the synchronization signal 205. Generate. That is, as shown in FIG. 2, the PE modulation reference signal 208 is generated such that "0" and "1" alternate with every 16 clocks of the recording channel bit clock 206 based on the synchronization signal 205. Generated in circuit 8. Further, the random number generation clock 207 is a signal obtained by inverting the PE modulation reference signal 208, and the pseudo random number generation circuit 9 generates a pseudo-random number at every rising edge of the random number generation clock 207 (that is, at the falling edge of the PE modulation reference signal 208). The random number sequence 209 is updated.
[0036]
The pseudo-random number sequence 209 includes a plurality of elements. In the embodiment of the present invention, one of a plurality of elements included in the pseudo-random number sequence 209 has a value of “0” or “1” included in a certain section (a section of 32 clocks in FIG. 2). Is a set of pseudo-random numbers. The PE modulation reference signal 208 is logically inverted at the center of each of a plurality of elements included in the pseudo-random number sequence 209. The frequency of the PE modulation reference signal 208 is lower than 1/2 of the reference frequency of the recording channel bit clock 206, and the PLL 45 (FIG. 3) for generating the reproduction channel clock 304 (FIG. 5) for reproducing the main information 201. ) Higher than the response frequency.
[0037]
The synchronization signal 205 is input to the pseudorandom number generation circuit 9 and the sub information output circuit 10. In the pseudo random number generation circuit 9, the operation of the pseudo random number generation circuit 10 is initialized in response to the timing indicated by the synchronization signal 205, and the pseudo random number sequence 209 is generated in time series at the timing indicated by the random number generation clock 207. . In response to the synchronization signal 205, the sub-information output circuit 10 outputs the sub-information 210 such as the disc identification information and the secret key stored in the sub-information output circuit 10 bit by bit.
[0038]
The exclusive OR circuit 11 calculates an exclusive OR of the pseudo-random number sequence 209 and the sub information 210 and inputs an exclusive OR output signal 211 to the PE modulation circuit 12. The PE modulation circuit 12 calculates an exclusive OR of the exclusive OR output signal 211 and the PE modulation reference signal 208, and generates a phase modulation control signal 212 based on the calculation result. In the present embodiment, when the polarity of the exclusive OR output signal 211 is “0”, the phase modulation control signal 212 indicates “0” during the first 16 clocks of the 32 clocks, and the second 16 "1" is shown during the clock. When the polarity of the exclusive OR output signal 211 is “1”, the phase modulation control signal 212 indicates “1” during the first 16 clocks, and indicates “0” during the second 16 clocks. .
[0039]
The phase modulation control signal 212 output from the PE modulation circuit 12 is input to the phase modulation circuit 3. The phase modulation circuit 3 advances the phase of the edge position of the recording channel signal 202 when the phase modulation control signal 212 indicates “1”, and shifts the edge position of the recording channel signal 202 when the phase modulation control signal 212 indicates “0”. Performs phase modulation to delay the phase of the position.
[0040]
The modulated recording channel signal 203 on which the phase modulation has been performed is input to the recording channel 4, and the recording channel 4 generates a control signal 204 for changing the recording power of the laser beam according to the modulated recording channel signal 203. And outputs it to the recording head 5. The recording head 5 forms an optically readable modulated recording mark (or a modulated recording pit) on the optical disk 6 while raising or lowering the power of the laser beam based on the control signal 204 output from the recording channel 4. I do.
[0041]
As described above, the sub-information encrypted by the pseudo-random number sequence can be superimposed on the edge of the recording mark of the main information and recorded on the information recording medium.
[0042]
Here, the cycle of the phase modulation performed by the phase modulation circuit 3, that is, the cycle of switching between the first state in which the phase of the edge position is advanced and the second state in which the phase of the edge position is delayed will be described. The first state in which the phase of the edge position is advanced or the second state in which the phase of the edge position is delayed is included in the response frequency band of the PLL that generates the reproduction channel clock during reproduction (that is, the first state). When the frequency, which is the reciprocal of the cycle for switching between the second state and the second state, becomes equal to or lower than the response frequency of the PLL, the PLL follows the phase-modulated edge position, and corrects the sub information recorded by the phase modulation. It cannot be detected. The response frequency of the PLL is the reciprocal of the cycle at which the PLL updates the reproduction channel clock.
[0043]
The predetermined frequency indicated by phase modulation control signal 212 of the present embodiment is higher than the response frequency of PLL 45. For this reason, the period for switching the direction in which the edge position of the pit or the recording mark is displaced for recording the sub-information is shorter than the period for the PLL 45 to update the reproduction channel clock 304, so that the PLL is shifted to the phase-modulated edge position. Do not follow.
[0044]
In the conventional example, the frequency at which the first state and the second state are switched is set sufficiently higher than the response frequency of the PLL so that the switching between the first state and the second state is performed in channel clock units. I have to. In this case, if a bit shift occurs during reproduction due to scratches, dust, fingerprints, etc. on the optical disk (for example, a synchronization signal detected during reproduction is shifted by one clock from a synchronization signal used during recording), Since the polarities of the phase modulation control signal and the phase modulation control signal at the time of reproduction are reversed, accurate phase difference detection cannot be performed.
[0045]
Therefore, it is necessary to determine the time during which the first state or the second state continues, based on the response frequency of the PLL and the allowable width of the bit shift. At this time, as the first state and the second state become longer, the adverse effect due to the bit shift decreases, but the length of the pseudo-random number sequence for superimposing 1-bit sub-information becomes shorter. In this case, the number of cases where there is a correlation between the correct pseudo-random number sequence and the incorrect pseudo-random number sequence increases.
[0046]
Next, an optical disc reproducing apparatus 300 for reproducing the main information 201 and the sub information 210 from the optical disc 6 on which the main information 201 and the sub information 210 are recorded by using the above-described optical disc recording apparatus 100 will be described. FIG. 3 shows an optical disc reproducing apparatus 300 according to the embodiment of the present invention. The optical disk reproducing device 300 has a function of reproducing the main information 201 and the sub information 210 from the optical disk 6 at the same time. The optical disc reproducing apparatus 300 not only reproduces the main information 201 based on the modulated recording mark formed on the optical disc 6 but also reproduces the sub information buried in the jitter of the modulated recording mark detected when reproducing the main information 201. Has the function of detecting
[0047]
The optical disc reproducing apparatus 300 includes a reproducing head 31, a reproducing channel 32, a demodulating circuit 33, a clock extracting circuit 34, a timing generating circuit 35, a synchronous detecting circuit 36, a synchronous signal detecting circuit 37, a pseudo random number generating circuit 38, a PE modulation circuit 39, and an error correction circuit 40. The clock extraction circuit 34 includes a PLL 45 and a phase comparison circuit 46. The optical disk reproducing device 300 has an optical disk 6 mounted thereon as an information recording medium.
[0048]
The reproducing head 31 condenses and irradiates a modulated recording mark 301 (FIG. 5) formed on the rotating optical disk 6 with a light beam, and receives the reflected light with a photodiode. The reproducing head 31 generates an analog read signal 302 indicating the edge position of the modulated recording mark 301 by amplifying the output signal of the photodiode that has received the reflected light, and outputs the analog read signal 302 to the reproducing channel 32. The reproducing head 31 functions as a reading unit that reads one of the pits and the recording marks. The reproduction channel 32 converts the analog read signal 302 into a digital read signal 303 by equalizing or shaping the waveform, and outputs the digital read signal 303 to the clock extraction circuit 34 and the demodulation circuit 33.
[0049]
The PLL 45 included in the clock extraction circuit 34 generates a reproduction channel clock 304 synchronized with the recording channel bit clock 206 (FIG. 2) based on the digital read signal 303, and outputs the reproduction channel clock 304 to the timing generation circuit 35. At the same time, the phase comparison circuit 46 included in the clock extraction circuit 34 detects a phase error of the digital read signal 303 with reference to the reproduction channel clock 304.
[0050]
The phase comparison circuit 46 compares the phase of the digital read signal 303 with the phase of the reproduced clock. If the phase of the digital read signal 303 is ahead of the phase of the reproduced channel clock 304, the phase of the digital read signal 303 is changed. A leading error signal 305 indicating that the vehicle is leading is generated. When the phase of the digital read signal 303 is behind the phase of the reproduction channel clock 304, the phase comparison circuit 46 generates a delay error signal 306 indicating that the phase of the digital read signal 303 is behind. The phase comparison circuit 46 outputs the phase error signal 305 and the phase error signal 306 to the synchronous detection circuit 36 described later.
[0051]
The demodulation circuit 33 detects the main information 201 by demodulating the digital read signal 303 with reference to the synchronization signal detected by the synchronization signal detection circuit 37. The error correction circuit 40 performs error correction on the detected main information 201, and outputs the main information 201.
[0052]
The synchronization signal detection circuit 37 detects a synchronization pattern included in the digital read signal 303, generates a synchronization signal 307, and outputs it to the demodulation circuit 33, the timing generation circuit 35, and the pseudo-random number generation circuit 38.
[0053]
The timing generation circuit 35 has the same function as the timing generation circuit 8 (FIG. 1) of the optical disc recording device 100, and generates a PE modulation reference signal 308 and a random number generation clock 309 based on the synchronization signal 307.
[0054]
The pseudo-random number generation circuit 38 has the same function as the pseudo-random number generation circuit 9 (FIG. 1) of the optical disc recording device 100, and presets an initial value in response to the timing indicated by the synchronization signal 307. The pseudo random number sequence 310 is generated in response to the timing indicated by the output random number generation clock.
[0055]
The PE modulation reference signal 208 is logically inverted at the center of each of a plurality of elements included in the pseudorandom number sequence 310. The frequency of the pseudo-random number sequence 310 (that is, the frequency of the random number generation clock 309 serving as a reference for generating the pseudo-random number sequence 310) and the frequency of the PE modulation reference signal 308 are lower than の of the reference frequency of the recording channel bit clock 206. Is higher than the response frequency of the PLL 45 for generating the reproduction channel clock 304 for reproducing the main information 201.
[0056]
The PE modulation circuit 39 has the same function as the PE modulation circuit 12 (FIG. 1) of the optical disc recording device 100, and outputs a signal from the pseudo random number generation circuit 38 based on the PE modulation reference signal 308 output from the timing generation circuit 35. The output pseudo-random number sequence 310 is subjected to PE modulation to generate a phase modulation detection control signal 311 and output to the synchronous detection circuit 36. The frequency of the phase modulation detection control signal 311 is substantially always lower than 基準 of the reference frequency of the recording channel bit clock 206, and the response of the PLL 45 for generating the reproduction channel clock 304 for reproducing the main information 201. Higher than the frequency.
[0057]
The synchronous detection circuit 36 detects the sub information 210 from the phase error signal 305 and the phase error signal 306 output from the clock extraction circuit 34 and the phase modulation detection control signal 311 output from the PE modulation circuit 39.
[0058]
FIG. 4 shows the synchronous detection circuit 36. The synchronous detection circuit 36 includes a selector 41, an integrator 42, a sub information determination circuit 43, and a sub information update timing generator 44. The selector circuit 41 includes two 2-input 1-output switches 47 and 48. When the phase modulation detection control signal 311 indicates “1”, the selector circuit 41 converts the leading error signal 305 and the lagging error signal 306 into the positive input terminal (+) and the negative input terminal (−) of the integration circuit 42, respectively. Let through. When the phase modulation detection control signal 311 indicates “0”, the selector circuit 41 uses the negative input terminal (−) and the positive input terminal (+) of the integration circuit 42 for each of the phase error signal 305 and the phase error signal 306. Let through.
[0059]
The integration circuit 42 is a differential input analog integrator, and adds the signal input to the positive input terminal (+) and subtracts the signal input to the negative input terminal (-). The sub information update timing generation circuit 44 outputs an update signal 312 to the integration circuit 42 according to the synchronization signal 307. Upon receiving the update signal 312, the integration circuit 42 clears the value held by the analog integrator. As a result, during the period in which the phase modulation detection control signal 311 indicates “1”, the integration circuit 42 sequentially adds the leading error signal 305 and subtracts and accumulates the lag error signal 306. Further, during a period in which the phase modulation detection control signal 311 indicates “0”, the phase error signal 305 is subtracted, and the phase error signal 306 is added and accumulated. Integration circuit 42 outputs a voltage corresponding to integration value 313 (FIG. 5) indicating the accumulated result.
[0060]
Therefore, a pulse appears only in the phase error detection signal 305 in the section where the phase modulation detection control signal 311 indicates “1”, and only in the phase error detection signal 306 in the section where the phase modulation detection control signal 311 indicates “0”. When a positive correlation such that a pulse appears continues, the integral value 313 monotonically increases in the positive direction, and conversely, only in the section where the phase modulation detection control signal 311 indicates “1”, the pulse is applied only to the delay error signal 306. Appears, and in a section where the phase modulation detection control signal 311 indicates “0”, if a negative correlation in which a pulse appears only in the phase error signal 305 continues, the integration value 313 monotonously decreases in the negative direction. .
[0061]
If there is no positive or negative correlation (that is, if the pulse of the phase error signal 305 and the phase error signal 306 appears randomly without depending on the phase modulation detection control signal 311), the phase error is Since the appearance frequencies of the signal 305 and the delay error signal 306 are substantially equal, the output voltage of the integration circuit 42 has a value close to zero level.
[0062]
The sub information determination circuit 43 includes a comparator or the like (not shown), and the voltage value of the analog signal 314 indicating the integrated value 313 output from the integration circuit 42 is set to a predetermined positive threshold voltage and a predetermined negative threshold voltage. It is determined which of the three voltage sections divided by the threshold voltage belongs. When the voltage value of the analog signal 314 is larger than the positive threshold value when the update signal 312 output from the sub information update timing generation circuit 44 is input, the sub information determination circuit 43 outputs “1”. And the detection flag 315 indicating the value of “1”. The detection flag 315 indicating a value of “1” indicates that the sub information 210 has been detected. When the voltage value of the analog signal 314 is smaller than the negative threshold value when the update signal 312 output from the sub information update timing generation circuit 44 is input, the sub information determination circuit 43 outputs “0”. And the detection flag 315 indicating the value of “1”.
[0063]
When the voltage value of the analog signal 314 is between the positive threshold value and the negative threshold value, the detection flag 315 indicating “0” is output. The detection flag 315 indicating a value of “0” indicates that the sub information 210 has not been detected.
[0064]
The sub information update timing generation circuit 44 generates an update signal 312 indicating the update timing of the sub information detection operation based on the synchronization signal 307. When the update signal 312 is output, the integration circuit 42 clears the integration value 313, and the sub information determination unit 43 clears the value of the sub information 210 and the determination result of the presence or absence of the sub information 210.
[0065]
Next, FIG. 5 shows a timing chart of each element of the optical disc reproducing apparatus 300 of the present embodiment. With reference to FIG. 5, the reproducing operation of optical disk reproducing device 300 of the present embodiment will be further described.
[0066]
The PLL 45 generates a reproduction channel clock 304 based on the digital read signal 303. The phase of the rising edge of the generated reproduction channel clock 304 is synchronized with the rising edge and the falling edge of the digital read signal 303. The synchronization signal detection circuit 37 samples the digital read signal 303 at the falling edge of the reproduction channel clock 304 and compares the digital read signal 303 with a specific synchronization pattern to determine whether the digital read signal 303 matches a specific synchronization pattern. The synchronization pattern in the signal 303 is detected. When a synchronization pattern that matches the specific synchronization pattern is detected, the synchronization signal detection circuit 37 outputs a synchronization signal 307 indicating the specific synchronization pattern.
[0067]
Upon receiving the synchronization signal 307, the timing generation circuit 35 outputs a PE modulation reference signal 308 obtained by dividing the reproduction channel clock 304 by 16 and a random number generation clock 309. The pseudo random number generation circuit 38 initializes the pseudo random number sequence 310 according to the timing indicated by the synchronization signal 307. The pseudorandom number generation circuit 38 outputs a pseudorandom number sequence 310 updated at the time of the falling edge of the PE modulation reference signal 308. The PE modulation circuit 39 generates a phase modulation detection control signal 311 according to the result of the exclusive OR operation of the pseudo-random number sequence 310 and the PE modulation reference signal 308. The PE modulation circuit 39 determines whether the value of the phase modulation detection control signal 311 is “1” or “0” in accordance with the result of the exclusive OR operation every 16 channel clocks out of the 32 channel clocks. .
[0068]
The phase comparator 46 detects a phase difference between the rising edge of the reproduction channel clock 304 and the rising and falling edges of the digital read signal 303. When the edge of the digital read signal 303 is ahead of the rising edge of the reproduction channel clock 304, the phase comparison circuit 46 outputs a phase error signal 305, and the phase of the digital read signal 303 is higher than the rising edge of the reproduction channel clock 304. If the edge is delayed, a delay error signal 306 is output.
[0069]
When the phase modulation detection control signal 311 indicates “1”, the synchronous detection circuit 36 adds the leading error signal 305 and subtracts the lag error signal 306. When the phase modulation detection control signal 311 indicates “0”, the synchronous detection circuit 36 adds the delayed error signal 306 and subtracts the advanced error signal 305.
[0070]
The synchronous detection circuit 36 repeats such addition processing and subtraction processing, and when integration of a predetermined number of bytes is completed, the voltage value of the analog signal 314 indicating the integration value 313 becomes lower than the positive threshold value. If it is larger, “1” is detected as the value of the sub information 210, and the sub information 210 indicating the value of “1” and the detection flag 315 indicating the value of “1” are output. When the voltage value of the analog signal 314 is smaller than the negative threshold value, “0” is detected as the value of the sub information 210, and the sub information 210 indicating the value of “0” and the value of “1” are indicated. The detection flag 315 is output. If the voltage value of the analog signal 314 falls between the positive threshold value and the negative threshold value, it is determined that the sub information 210 is not correctly embedded in the main information 201, and the "0" A detection flag 315 indicating the value is output.
[0071]
Next, in the optical disc reproducing device 300, a case where the synchronization between the reproduction channel clock 304 generated by the PLL and the digital read signal 303 is shifted (that is, a bit shift occurs) due to a scratch, dust, fingerprint, or the like on the optical disc 6 ,explain.
[0072]
In general, when detecting a synchronization pattern, not only when a read reproduction signal and a predetermined synchronization pattern match exactly, but also when a synchronization pattern substantially close to the predetermined synchronization pattern is detected, In some cases, a synchronization pattern that is close to the synchronization pattern is detected as a synchronization signal. For example, in the case of a DVD, main information is divided into units called frames by a plurality of bytes, and a plurality of types of synchronization patterns are recorded at the beginning of each frame according to each frame position. However, a common pattern (for example, 14T + 4T. In 14T + 4T, 14 clocks of "L" or "H" signals for 14 clocks, followed by "H" or "L" for 4 clocks) continues for a plurality of types of synchronization patterns. This common pattern is detected, and the common pattern is detected as a synchronization signal. At this time, when a pattern close to a predetermined pattern such as 14T + 3T, 13T + 3T, or 15T + 4T is detected as well as a pattern of 14T + 4T, it is detected as a close pattern synchronization signal.
[0073]
Alternatively, other than the deviation of the synchronization pattern, there is a case where the synchronization between the digital read signal and the reproduction channel clock is deviated and a bit pattern different from the bit pattern at the time of the recording operation is detected. In such a case, the reproduced digital read signal cannot be demodulated and correct main information cannot be obtained. Therefore, by performing erasure correction in the error correction processing, correct main information can be reproduced even when all of a plurality of frames are incorrect.
[0074]
However, the phase modulation control signal in the optical disk recording device indicates that the detection timing of the synchronization signal is out of synchronization with the synchronization pattern recorded on the disk, or that the synchronization between the reproduction channel clock and the digital read signal is out of synchronization. A deviation occurs between the timing and the timing indicated by the phase modulation detection control signal in the optical disk reproducing device, and the correlation between the phase modulation detection control signal and the leading and lagging error signals becomes incorrect.
[0075]
The bit shift will be described in more detail with reference to FIG. FIG. 6 shows a digital read signal 303 ′ in which a part of the bit pattern of the digital read signal 303 is garbled due to a scratch, dust, fingerprint, or the like on the disk 6, and as a result, no bit shift occurs. In this case, the detection of the synchronization pattern is shifted by three clocks.
[0076]
During a recording operation, a recording channel signal 202 (FIG. 2) is output according to a recording channel bit clock 206, and a synchronization signal 205 indicating a synchronization pattern is always output at the same position with respect to the recording channel signal 202 (that is, the recording channel signal 202). No bit shift occurs).
[0077]
As described with reference to FIG. 2, the PE modulation reference signal 208 and the pseudo-random number sequence 209 are generated based on the synchronization signal 205. A phase modulation control signal 212 is generated from an exclusive OR output signal 211 indicating the result of the exclusive OR of the pseudorandom number sequence 209 and the sub information 210 and the PE modulation reference signal 208. Based on the phase modulation control signal 212, the sub information 210 is superimposed and recorded on the main information 201 by advancing or delaying the phase of the edge of the recording mark.
[0078]
When the optical disc reproducing apparatus 300 reproduces the main information 201 and the sub-information 210 from the optical disc 6 on which the main information 201 and the sub-information 210 are recorded in this way, the synchronization signal 307 shifted from the synchronization signal 307 by three clocks. 'Is obtained. The phase error signal 305, the phase error signal 306, the PE modulation reference signal 308, the pseudo-random number sequence 310, and the phase modulation detection control signal 311 are each shifted by three clocks with respect to the synchronization signal 307 '. , A delay error signal 306 ′, a PE modulation reference signal 308 ′, a pseudo-random number sequence 310 ′, and a phase modulation detection control signal 311 ′. Compared with the phase modulation control signal 212 used during the recording operation, the phase modulation detection control signal 311 ′ used during the reproducing operation is delayed by three clocks. Among the edge positions of the digital readout signal 303 'shown in FIG. 6, the polarity of the phase modulation control signal 212 and the polarity of the phase modulation detection control signal 311' match at the edge positions marked with a circle. In a section where these polarities coincide, the correlation between the phase error detection signal 305 'and the phase modulation detection control signal 311' can be correctly detected. However, since the polarity of the phase modulation control signal 212 and the polarity of the phase modulation detection control signal 311 ′ are different at the edge positions marked with “x”, the correlation cannot be correctly detected.
[0079]
In a 1-bit pseudo-random number sequence section (32 clock lengths), a section in which the polarity of the phase modulation control signal 212 matches the polarity of the phase modulation detection control signal 311 ′ is a section of 26 clocks, and the phase modulation control signal 212 Is not coincident with the polarity of the phase modulation detection control signal 311 'is a section of 6 clocks. In the three-clock section of the non-matching section, correct correlation can be obtained with a probability of 1/2. Therefore, the probability of obtaining a correct correlation in 32 clock intervals is 27.5 / 32.
[0080]
Further, when the phase modulation occurs randomly, the probability that correct correlation is obtained in all clock sections is 、, and the probability that correct correlation is not obtained is １ ／. In this case, since the probability of obtaining a correct correlation in a 32 clock section is （(= 16/32), correct sub-information 210 can be obtained even if the synchronization signal detection is shifted by 3 clocks. .
[0081]
However, in the conventional example, if the detection of the synchronization signal is shifted by three clocks, the random number sequence at the time of recording and the random number sequence at the time of reproduction are completely different, and correct correlation cannot be obtained.
[0082]
In the present embodiment, the predetermined frequency serving as a reference for determining the displacement direction of the edge position of the pit or the recording mark is lower than 1/2 of the reference frequency of the recording bit channel clock 206. That is, the minimum one cycle indicated by each of the phase modulation control signal 212 and the phase modulation detection control signal 311 is longer than two clocks.
[0083]
Here, a case where the phase modulation control signal 212 and the phase modulation detection control signal 311 are shifted from each other by one clock will be described. Assuming that the minimum one cycle indicated by each of the phase modulation control signal 212 and the phase modulation detection control signal 311 is two clocks, the probability that a correct correlation can be obtained is 1/2 when one cycle is two clocks. It becomes. In the present embodiment, since the minimum one cycle indicated by each of the phase modulation control signal 212 and the phase modulation detection control signal 311 is longer than two clocks, the probability of obtaining a correct correlation is higher than 1/2. Correct sub-information 210 can be obtained. Therefore, in the present embodiment, correct sub-information 210 can always be obtained even if the phase modulation control signal 212 and the phase modulation detection control signal 311 are shifted by one clock.
[0084]
As described above, in the optical disk recording device and the optical disk reproducing device according to the embodiment of the present invention, the generation period of the pseudo-random number sequence for encrypting the sub-information is lengthened. Therefore, even if a bit shift occurs between the pseudo-random number sequence used by the optical disk recording device and the pseudo-random number sequence used by the optical disk reproducing device due to scratches, dust, fingerprints, etc. on the optical disk, the phase modulation detection control is performed. Since the probability that the correlation between the signal and the phase error signal and the phase error signal can be correctly detected can be made higher than 1/2, the sub information can be correctly detected.
[0085]
As described above, the embodiments of the optical disc related to the jitter modulation of the present invention, the optical disc recording apparatus and the optical disc reproducing apparatus using the optical disc have been described, but the present invention is of course not limited to the above embodiments. Further, the present invention can also be realized in a recording method and a reproducing method that include, as steps, operations of characteristic components included in the optical disk recording device and the optical disk reproducing device of the present invention.
[0086]
【The invention's effect】
According to the present invention, in order to record sub-information, whether one of the edge positions of the pit and the recording mark is displaced in the phase advance direction or in the phase delay direction is determined based on a predetermined frequency. ing. This predetermined frequency is substantially always lower than 1/2 of the reference frequency of the recording clock for forming one of the pit and the recording mark, and is used for generating a reproduction clock for reproducing the main information. It is higher than the response frequency of the PLL. As a result, even if a bit shift occurs in the synchronous operation at the time of reproduction due to a scratch, dust, fingerprint, or the like on the information recording medium, the value of the phase modulation control signal that determines the phase displacement direction at the time of recording and Since the difference from the value of the phase modulation detection control signal for detecting the phase displacement direction can be reduced, the sub information can be correctly detected.
[Brief description of the drawings]
FIG. 1 is a diagram showing an optical disk recording device according to an embodiment of the present invention.
FIG. 2 is an operation timing chart of each element of the optical disc recording apparatus according to the embodiment of the present invention;
FIG. 3 is a diagram showing an optical disc reproducing apparatus according to the embodiment of the present invention;
FIG. 4 is a diagram showing a synchronous detection circuit of the optical disc reproducing apparatus according to the embodiment of the present invention;
FIG. 5 is an operation timing chart of the optical disc reproducing apparatus according to the embodiment of the present invention;
FIG. 6 is a timing chart when a bit shift occurs in the optical disc reproducing apparatus according to the embodiment of the present invention;
FIG. 7 is a diagram showing a conventional optical disk recording device.
FIG. 8 is a diagram showing a second modulation circuit in a conventional optical disk recording device.
FIG. 9 is an operation timing chart of a conventional optical disc recording apparatus.
[Explanation of symbols]
1 Error correction additional circuit
2 Modulation circuit
3 Phase modulation circuit
4 Recording channel
5 Recording head
6 optical disk
7, 37 Synchronous signal detection circuit
8, 35 Timing generation circuit
9,38 Pseudo random number generation circuit
10 Sub-information output circuit
11 Exclusive OR operation circuit
12, 39 PE modulation circuit
31 Playhead
32 playback channels
33 Demodulation circuit
34 Clock Extraction Circuit
36 Synchronous detection circuit
41 Selector
42 Integrator
43 Sub-information judgment circuit
44 Sub-information update timing generation circuit

Claims (10)

An information recording medium for recording main information and sub-information,
The information recording medium has a track,
The main information is recorded on the information recording medium by forming one of a pit indicating the main information and a recording mark indicating the main information on the information recording medium along a track direction,
The sub-information is recorded on the information recording medium by displacing one edge position of the pit and the recording mark in one of a phase advance direction and a phase delay direction along the track direction. ,
Whether the edge position is displaced in the phase lead direction or displaced in the phase lag direction to record the sub-information is determined based on a predetermined frequency,
The predetermined frequency is substantially always lower than 1/2 of a reference frequency of a recording clock for forming one of the pit and the recording mark, and generates a reproduction clock for reproducing the main information. An information recording medium having a higher response frequency than a PLL. The predetermined frequency is determined based on a result of a logical operation of a predetermined binary sequence and the sub information,
2. The information recording medium according to claim 1, wherein a frequency of the predetermined binary sequence is lower than a half of a reference frequency of the recording clock and higher than a response frequency of the PLL. The predetermined binary sequence is a pseudo-random sequence including a plurality of elements,
The predetermined frequency is determined based on a result of a further logical operation of the PE modulation signal that is logically inverted at the center of each of the plurality of elements and a result of the logical operation,
3. The information recording medium according to claim 2, wherein a frequency of the PE modulation signal is lower than 1/2 of a reference frequency of the recording clock and higher than a response frequency of the PLL. A recording device for recording main information and sub-information on an information recording medium having a track,
A recording signal generation unit that generates a recording signal indicating the main information synchronized with a recording clock,
Phase modulation for modulating an edge position of the recording signal in one of a phase leading direction of the recording signal and a phase delaying direction of the recording signal to generate a phase modulated recording signal indicating the main information and the sub information. Department and
Based on the phase modulation recording signal, one edge position of the pit indicating the main information and the recording mark indicating the main information is displaced in one of a phase advance direction and a phase delay direction along a track direction. As described above, by forming one of the pits and the recording marks on the information recording medium along the track direction, a recording unit that records the main information and the sub information on the information recording medium. Prepare,
The phase modulating unit determines whether to modulate the edge position of the recording signal in the phase leading direction of the recording signal or to modulate the recording signal in the phase lagging direction based on a predetermined frequency,
The recording device, wherein the predetermined frequency is substantially always lower than 1/2 of a reference frequency of the recording clock, and higher than a response frequency of a PLL for generating a reproduction clock for reproducing the main information. A binary sequence generation unit that generates a predetermined binary sequence,
A sub-information output unit that outputs the sub-information,
A logical operation unit that performs a logical operation on the predetermined binary sequence and the sub information, and generates a control signal indicating the predetermined frequency based on a result of the logical operation,
The phase modulation unit determines whether to modulate the edge position of the recording signal in a phase leading direction of the recording signal or in a phase lagging direction of the recording signal based on the predetermined frequency indicated by the control signal. And
5. The recording apparatus according to claim 4, wherein the frequency of the predetermined binary sequence is lower than 1/2 of a reference frequency of the recording clock and higher than a response frequency of the PLL. The predetermined binary sequence is a pseudo-random sequence including a plurality of elements,
The recording apparatus further includes a PE modulation signal generation unit that generates a PE modulation signal that is logically inverted at the center of each of the plurality of elements,
The logical operation unit performs a further logical operation of the PE modulation signal and the result of the logical operation, generates the control signal based on the result of the further logical operation,
6. The recording apparatus according to claim 5, wherein a frequency of the PE modulation signal is lower than a half of a reference frequency of the recording clock and higher than a response frequency of the PLL. A reproducing apparatus for reproducing main information and sub information recorded on an information recording medium,
The information recording medium has a track,
The main information is recorded on the information recording medium by forming one of a pit indicating the main information and a recording mark indicating the main information on the information recording medium along a track direction,
The sub-information is recorded on the information recording medium by displacing one edge position of the pit and the recording mark in one of a phase advance direction and a phase delay direction along the track direction. And
The playback device,
A reading unit that reads one of the pit and the recording mark and generates a read signal;
A PLL for generating a reproduction clock synchronized with the read signal;
A phase advance signal indicating that the phase of the read signal is advanced when the phase of the read signal is advanced from the phase of the reproduced clock by comparing the phase of the read signal with the phase of the reproduced clock. A phase comparison unit that generates a delayed signal indicating that the phase of the read signal is delayed when the phase of the read signal is delayed from the phase of the reproduced clock;
A sub-information detecting unit that integrates the leading signal and the lag signal based on a predetermined frequency and detects the sub-information based on the result of the integration.
A demodulator that detects the main information by demodulating the read signal,
The reproducing apparatus, wherein the predetermined frequency is substantially always lower than 1/2 of a reference frequency of a recording clock for forming one of the pit and the recording mark, and higher than a response frequency of the PLL. The reproduction according to claim 7, wherein the sub-information detection unit detects the value of the sub-information by comparing the result of the integration with a predetermined positive threshold value and a predetermined negative threshold value. apparatus. 8. The reproduction according to claim 7, wherein the sub-information detection unit detects the presence or absence of the sub-information by comparing the result of the integration with a predetermined positive threshold value and a predetermined negative threshold value. apparatus. A pseudo-random number sequence generation unit that generates a pseudo-random number sequence including a plurality of elements,
A PE modulation signal generation unit that generates a PE modulation signal that is logically inverted at the center of each of the plurality of elements;
A logic operation unit that performs a logical operation on the pseudo-random number sequence and the PE modulation signal, and generates a control signal indicating the predetermined frequency based on a result of the logical operation,
The sub-information detection unit integrates the leading signal and the lag signal based on the predetermined frequency indicated by the control signal,
8. The reproducing apparatus according to claim 7, wherein a frequency of the pseudo-random number sequence and a frequency of the PE modulation signal are lower than a half of a reference frequency of the recording clock and higher than a response frequency of the PLL.

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