JP2003527029A - Enhanced turbo product code - Google Patents

Abstract

(57) [Summary] The hyper-encoding module encodes a block having a plurality of sub-blocks. Each sub-block contains a plurality of systematic block codewords. Parity sub-blocks are added to the block. The parity sub-block is rotated by a predetermined number of bits. Each successive sub-block of the n-dimensional block is rotated by an appropriate number of bits and subjected to a bitwise exclusive OR operation. An encoding method and apparatus include a hyper-encoding module for receiving a data block. The rows of the block are output immediately and are encoded by the first module according to the first encoding scheme. The columns are encoded by a second module according to a second encoding scheme. A second set of encoded data is generated, updated iteratively, and output by the output module. The hyper-encoding module encodes and outputs the information bits on the hyper diagonal as described above.

Description

Detailed Description of the Invention

[0001]

[Related application]

This patent application was filed on March 14, 2000 under US Patent Law 35 U.S.C. 119 (e), and the title of the invention is "enhanced turbo product code". Claim priority under No. 189,345. The provisional patent application No. 60 / 189,345 filed on Mar. 14, 2000 and whose title is "Enhanced Turbo Product Code" is incorporated into the present application by reference.

[0002]

BACKGROUND OF THE INVENTION

The present invention relates generally to enhanced turbo product codes (eTPCs), and more particularly to a method for encoding hyper product codes by diagonal encoding, and apparatus therefor.

The product code is a concatenation of two or more block codes. For example, the block codes are C1 and C2, each of which has a parameter (n1,
k1, d1) and (n2, k2, d2). n is a codeword
), K is the number of information bits, and d is the minimum Hamming distance. The product code P = C1 × C2 is k1 × k2 in an array of k1 rows and k2 columns.
It is obtained by arranging the information bits. Next, k1 rows are coded using code C1 and n2 columns are coded using code C2. Therefore, the product code is (n1 × n2, k1 × k2, d1 × d2). In this configuration, the matrix P
Are all C1 codewords and all columns of matrix P are C2 codewords. The product code is two-dimensional or multidimensional. However, as the dimension of the product code increases, the larger code Euclidean distance (d
min) is easier to obtain, but at the expense of a significantly larger block size.

Turbo Product Codes (TPCs) are a class of codes that provide performance closer to the Shannon limit than traditional concatenated codes. TPCs are iterative soft-decision decoding of product codes. TPCs are a class of codes with wide flexibility in performance, complexity, and code rate. Due to this flexibility, TPCs are used in a wide variety of applications.

The enhanced turbo product code is a code constructed based on TPCs. The base code is of arbitrary dimension and includes a parity code and / or an extended Hamming constituent code. A code is a "hyperproduct code" when all axes of the code include a constitutive code of parity only. Enhanced turbo product codes (eTPCs) include an N-dimensional product of an extended Hamming code and a simple parity code obtained by an additional parity operation performed along a “hyper diagonal”. Product code is 1 or 2
It has the above dimensions. The enhanced turbo product code can be executed with reduced complexity and can be iteratively decoded using a soft in soft out (SISO) algorithm.

To transition from the underlying TPC to eTPC, the bits in the base code are shuffled or interleaved according to a predetermined pattern. Parity is then computed over the newly shuffled array. For parity, one additional bit row is added to the 2-DTPC, or one additional plane is 3-DTP.
Calculated to be added to C. This generalizes to higher dimensions. This is because the parity bit of the n-1 dimensional structure is added to the code. Here, n is the dimension of the base code.

In addition to improved bit error rate performance, eTPCs also have utility with respect to flexibility. System designers have typically required various block sizes and coding rates when developing systems that use error correction. eTPC
Being able to use the full set of s (including turbo product codes, enhanced turbo product codes, and any combination thereof) allows a great deal of flexibility in choosing the correct code for a given system. .

The code rate and best error rate (BER) performance of TPCs depends on the number of systematic building block code codewords and axes of the product code. The set of eTPCs shown below includes codes in two or more dimensions, and the base code for each axis may include extended Hamming codes and / or parity codes, or other equivalent. The table below shows a set of configurations for 2-D and 3-DeTPC codes.

[0009]

[Table 1]

In the above table, “H” represents an axis of the extended Hamming code, “P” is an axis of only parity, and “+” is an enhanced turbo product code including an additional hyper-diagonal axis. Represent For example, the HP + code includes an extended Hamming code on the X axis and a parity only code on the Y axis and an additional hyper-diagonal axis. The minimum distance of the code containing the hyper-diagonal axis depends on the length of the code axis and must be found by computer analysis. The table shows the approximate minimum distances for these codes in the right column. From the above table, it can be seen that the minimum distance of the code increases as more axes of the code are coded. In addition, the code's minimum distance increases when a hyper-diagonal axis is added to the code. Also, if the coding rate decreases when encoding the code, the performance of the encoder increases.

A diagonal parity bit, or hyper-diagonal, is obtained by adding bits on the diagonal along a block using the following equation:

[0012]

[Equation 1]

B _ij is the (i, j) th product code bit. The diagonal parity bits are generated by "rotating" the i-th row of the original product code to the right by i + 1 bits and then adding each column to get the diagonal parity bits. Similarly, the diagonal parity bits are also diagonally rotated by "rotating" the i-th row of the original product code to the left by i-1 bits and then adding each column to obtain the diagonal parity bits. Get a bit.

By adding diagonal parity bits, the minimum Euclidean distance dmin of the code is increased. Diagonal axes are often referred to as hyper-axes, even when used with Hamming codes in various axes. The increased minimum distance results in a lower error floor for the code. In addition, the addition of hyper-axes can improve the performance of the code before the bound is reached.

Prior art encoding methods place data in a kx x ky (kx, ky) bit array. FIG. 1 schematically shows an encoding method according to the present invention. The X axis of the code is encoded by the X axis encoder (10) that encodes each row,
As a result, the data block has ky rows (1 row consisting of nx bits).
nx, ky). This data block is input to the Y-axis encoder (11) that encodes each column by adding data to the Y-axis, resulting in the output of (nx, ny) blocks. The final step involves a hyper-axis encoder (12) that adds diagonal parity bits to the code. In turn, a parity-only encoding is added to every column of the block. As a result, one row is added to the block and (nx, ny + 1) blocks are output.

The prior art encoding method has several disadvantages. Certain fully encoded 2-D blocks have codes (nx, ny) in their storage means and are required by the encoder to hold both the data array and the error correction code (ECC) bits. It In addition, the encoder has a latency of one block. Latency is defined as the time during which the first bit of a data block is input to the encoder and the last bit of the same block is output from the encoder. Prior art encoders have high latency. This is because the encoder cannot output the data array until both row and column encoding have been completed. To complete this encoding process, the encoder must receive the entire data array. Therefore, the first data bit of a block is not output until the last data bit of the same block is input and the latency of one entire block occurs. Many types of communication systems cannot handle long latencies. This is because the quality of service is suppressed in the system. For example, 1/2 on the telephone line
Second delay is not desirable. Because, due to the delay, until transmission and reception end
This is because communication is prohibited.

What is needed is an eTP with a hyper-diagonal parity array added
It is an efficient hardware implementation for iteratively encoding for Cs and its implementation method. Here, the eTPC includes a systematic block code codeword such as an extended Hamming code and a parity code like other codes. Using eTPCs with iterative diagonal encoding and decoding is beneficial because such eTPCs have lower error bounds on the order of 3 to 5 than current turbo product codes.

Also, what is needed is to store all blocks in the storage means,
An encoder that can encode "flying" data. Such an encoder has a very low latency. This is because the encoder does not store data bits, only error correction bits. The data bits are transmitted immediately on the channel, making the latency close to zero. In addition, such encoders require less storage. This is because the encoder does not store the data array itself.

[0019]

[Outline of the Invention]

The present invention is a method of encoding an n-dimensional data block. The block includes a plurality of systematic block code codewords whereby the method comprises performing a parity operation along a hyper-diagonal within the block to generate a parity result for the parity operation. The method also includes adding the parity result to the block data.

The present invention is a method for encoding an n-dimensional data block having a plurality of (n-1) -dimensional sub-blocks. Each sub-block includes multiple systematic block code codewords. The parity sub-block is added to the data block. The parity sub-block has a plurality of parity bits and the method of the invention comprises the step of making the parity sub-block equal to the first sub-block rotated by a predetermined number of bits. The method also includes a step of calculating a bitwise exclusive OR of each of the series of sub-blocks parallel to the first sub-block in the n-dimensional block with the parallel sub-block and the parity sub-block. . Here, the parity sub-block is rotated by an appropriate number of bits.

The present invention is a method of encoding an n-dimensional data block received from an input source. A block contains multiple information bits. The method of the present invention comprises the steps of receiving a row of blocks and immediately outputting the row. The method of the present invention includes the step of encoding information bits, the first set of encoded data being generated according to a first encoding scheme. The method of the present invention includes the step of outputting a first set of encoded data. The method of the present invention uses the second encoding scheme (s
The second set of encoded data is generated and iteratively updated according to the information bits in the rows. The method of the invention comprises hyper-diagonally encoding the information bits in a block according to a parity encoding scheme, wherein the hyperset of encoded data is the information bits in rows and columns, and of the encoded data. It is generated according to the first and second sets. The method of the invention comprises outputting an updated second set of encoded data after all the information bits and all of the subsequent first set of encoded data have been output. The method of the present invention includes the step of outputting the encoded hyperset.

The present invention is an encoder that encodes a data block having a plurality of information bits. The encoder outputs the information bit immediately after receiving the information bit. The encoder comprises a first encoder module that encodes information bits in the rows of the block, the first encoder module producing a set of encoded row bits. The encoder comprises a second encoder module encoding the information bits in the columns of the block, the second encoder module producing a set of column bits encoded according to the information bits in each row. Second
The encoder updates the encoded column bits for each row encoded by the first encoder. The encoder comprises a hyper-encoder module that hyper-diagonally encodes all information bits and all encoded bits on the diagonal along the block. The hyper encoder produces a set of parity results, each parity result corresponding to a diagonal of the encoded bits.

The present invention is an encoder that encodes a data block into an encoded data block. A data block has multiple information bits arranged in multiple rows and columns. The encoder of the invention comprises means for receiving a block of data, the received information bits being immediately output by the output means. The encoder comprises first means for encoding each row according to a first encoding scheme,
The first means generates a row encoding result for each row encoded according to the first encoding scheme. The encoder of the present invention comprises second means for encoding each column according to a second encoding scheme, the second means generating a column encoding result for each column encoded by the second encoding scheme. The column encoding result is iteratively updated for each row encoded by the first means. The encoder comprises means for hyper-diagonally encoding along the encoded data block, the means for hyper-diagonal encoding producing a hyper-parity result for each corresponding diagonal in the encoded data block.

The present invention is an encoder that encodes a data block within an encoded data block, the data block having a plurality of information bits. The encoder outputs the information bits as soon as it receives the information bits, and the encoder comprises a first encoder module for encoding the information bits in the block row, the first encoder producing a set of encoded row bits. The encoder comprises a second encoder module encoding the information bits in the columns of the block, the second encoder module producing a set of column bits encoded according to the information bits in each row. The second encoder updates the encoded column bits for each row encoded by the first encoder.

Other features and advantages of the present invention will become apparent after reading the detailed description of the preferred embodiments presented below.

[0026]

Detailed Description of the Preferred Embodiments

In the following example, a method for encoding an enhanced turbo product code (eTPC) using hyper-diagonal encoding is shown. The figure below is the lettering showing the order of parity calculation, which is the basis of the 2-
A code having only D parity is shown. Each character in the block represents one bit. In particular, the parity block seen in the figure has parameters (5,4) x (6,
4). Therefore, the data in a block consists of 4 rows and 4 columns of data, where each row and column is 4 bits. Since the block is an eTPC block, error correction bits such as extending Hamming codes or parity codes are added to each row and each column to make the block 5 rows and 5 columns. further,
Hyperparity rows or arrays are added to the eTPC as part of the block or separately. Encoded eTPC block is 4x in addition to ECC bits
It contains 4 blocks of information bits and the hyper parity array contains the results of the hyper-diagonal calculation for all of the eTPC blocks.

[0027]

[Outer 1]

All the above bits with the same letters (A to E) are used in the calculation of the additional parity bits placed in the hyperparity row. For example, all bits labeled A have even parity, all bits labeled B have even parity, and so on. 3D hyper-diagonal parity bit is 3
-Add by processing across all three axes of the D array. The same can be done with any number of dimensions. In the figure above, the encoder performs a parity calculation along a diagonally string of bits in a data block,
Performs hyper-diagonal by "rotating" the parity row. For example, the encoder performs the parity calculation by diagonally traversing the string of bits A and placing the parity row one column to the right. Then the encoder
Parity calculation is performed by traversing the string of bits B diagonally, placing the parity row one column to the right. This continues until the encoder has performed parity calculations on all strings. Then, the encoder rotates the parity row to the right by one column, and the parity row becomes as shown in the above figure. Other hyper-encoding methods may be used. For the 2-D code above, the hyper-diagonal parity result can also be calculated by moving down, to the left instead of down, to the right. Further, multiple rows of additional parity can be added to the code.

The encoder can encode higher dimensional codes by adding one array to the code. For example, (16,11) x (16,11) x (16,11) becomes (
It is encoded into a (16,11) x (16,11) x (17,11) code. As shown in FIG. 2, the encoding is performed in two steps except that an additional encoder is added between the “encode Y axis” module (21) and the “encode hyperaxis” module (22). The mechanism is similar to that of D. The module (23) labeled "Encode Z-axis" performs Z-axis encoding. Therefore, the block is output as (nx, ny, nz + 1).

The encoder of the present invention uses a new technique to limit the storage space required for the encoding process and reduce the latency of the encoder. A simplified block diagram of the present invention is shown in FIG. Instead of putting the data in a bit array of kx x kx, the encoder (100) of the present invention allows each bit of data in a two-dimensional block to be x_.
The encoder 40, the y_encoder 41, and the hyper_encoder 42 are input, and the encoded data is output and transmitted. The x_encoder (40) includes n1-k1 bits in the storage means, and the code on the X axis is (n1, k1). The y_encoder (41) includes (n2-k2) x k1 bits in the storage means, and the hyper_encoder (42) includes n1 bits in the storage means.

The encoding of the data of the two-dimensional block proceeds as follows. The data in the first row of the block is input to each encoder one or more bits at a time and immediately transmitted on the channel. The x_encoder (40) encodes the first row when data is input. The y_encoder (41) encodes k1 parallel codes. Each of the parallel codes corresponds to a column (k) of the array. Finally, the hyper encoder (42) encodes n1 parallel parity codes. Each of the parallel parity codes corresponds to a hyper-diagonal with an array

Once all the k1 data bits of the first row have been input, the x_encoder (40) is based on an encoding scheme such as adding an extended Hamming code, a parity code, or any equivalent to that row. Encodes the row. x_encoder (40)
After the first row has encoded the first row, it is ready to output the ECC bits of the first row or the set of encoded data. The multiplexer (43) is the y_encoder (41)
And the output of the first row of ECC bits to the multiplexer (44), the input data stream is stopped. Due to the stop of the data stream, the y_encoder during this time
(41) becomes idle. When the ECC bit of the first row on the x-axis is output, x_
All bits in the memory of the encoder (40) are zero, and the x_encoder (40)
Memory is cleared and the next row of data is input to the x_encoder (40). Then, when a series of data rows are input to the encoder (100), the y_encoder (41)
Encodes each column according to its encoding scheme and updates it repeatedly. Similarly, when data is input to the encoder (100), the hyper_encoder (42) updates with its encoding scheme by encoding each hyper-diagonal parity bit.

This process is repeated until k2 columns are output from the encoder (100).
When k2 columns have been output, the y_encoder (41) finishes encoding all remaining column bits by performing a parity calculation in row order on the entire set of encoded column bits. At this point, the y_encoder (41) is ready to output all the y-axis ECC data. The multiplexer (44) is switched so that the x_encoder (40) continues to encode new codewords and hyper_
While the encoder (42) continuously encodes and updates the data from the y-axis ECC data, the y-axis ECC data is output from the encoder (100). N2 of input data
Number of rows are encoded and output from the encoder (100), then the y-axis ECC
The data is exhausted. At this time, the memory of y_encoder (41) is
Cleared by zeroing all bits of the y_encoder (41) memory.
Further, the hyper_encoder (42) completes hyper-diagonal encoding of all blocks. Then, after the multiplexer (45) is switched, an additional row of parity bits from the hyper_encoder (42) is output.

For a three-dimensional block of data having (n, k, d) bits, a z_encoder (not shown) with a corresponding multiplexer is used to encode the d-plane of the data. The z_encoder encodes each surface according to its own encoding scheme when the first and series of rows are each input to the encoder (100),
Update repeatedly. The z_encoder is an x_encoder (40) and a y_encoder (4
The encoded ECC data generated in 1) is used to encode in-plane bits. Although FIG. 3 shows that a row is entered first, columns and hyper-diagonals are encoded by the row, this is not necessary in the method of the present invention. For example, the columns may be encoded first while the rows are updated, and so on.

FIG. 4 is a diagram of the encoder of the present invention. The encoder (100) comprises four modules. These are the input module (102) and the data path module (10
4), a control module (105), and an output module (106). Input module (1
02) receives input data by ready / accept handshake. The data is encoded in the datapath module and output module
It is output through the ready / accept handshake through (108). The control module (106) contains configuration settings, state machine and control signals for the encoder used in the encoding. The output module (108) receives the encoded data from the data path module (104) and the control module (106) and outputs the encoded code.

The input module receives input data at a rate of DATA_RATE bits. Here, DATA_RATE is a value indicating the number of encoded data bits processed per clock cycle. The DATA_RATE value cannot reach the minimum number of bits encoded on the x-axis of the block. The input module (102) receives the input data and provides the required number of bits for the row being encoded. The number of data bits required depends on the encoding process and may reach a value equal to DATA_RATE bits. The input module (102) receives the last_block_bits and last_block_row signals from the control module (106) which informs the input module (102) when the last bit is received by the input module (102).

The control module (106) comprises control logic that enables the input, data path, and output modules to communicate with other modules to encode the data. As shown in detail in FIG. 7, the control module (106
) Is register_control means (300), input_data_control means (302), block_control means (304), output_data_control means (306), x_encode_control means (308)
, Y_encode_control means (310), z_encode_control means (312), and hyper_control means (314). The register_control means (300) records all input module control signals. The input_data_control means (302) generates control signals used to receive input data from the input module (102). The block_control means (304) generates a control signal that specifies the block state. output_
The data_control means (306) generates control signals used to output the data from the output data module (108). The x_encoding_control means (308) uses x
_ Generates a control signal used for x-axis encoding performed by the encoder (110). Similarly, the y_encode_control means and the z_encode_control means generate control signals used for the y-axis and z-axis encoding performed by the y_encoder (112) and the z_encoder (114), respectively. Furthermore, the hyper_control signal is
Used for hyper-encoding performed by Hyper-Encoder 116. The output module 106 receives data on the DATA_RATE bits per clock and sends output data on the DATA_RATE bits per clock.
The data includes first_bit_flag and last_bit_flag, which indicate the positions of the first and last bits of the block.

The state machine (316) operates in idle mode until reset_n_pulse is applied. Given a reset_n_pulse, the state machine (316) becomes active and does not return to idle until the next reset_n_pulse is available. When data is input, either x_encoded bit, y_encoded bit, z_encoded bit, or hyperbit is output.

The data path module (104) shown in FIG. 5 performs an encoding function, as shown in detail in FIG. The datapath module 104 encodes the 3D block data in the x, y, and z dimensions and adds hyperbits if the datapath is possible. This is x_encoder (110), y_encoder (112), z_encoder
(114) and four different encoders consisting of a hyper encoder (116). In the case of two-dimensional block data, the data path module (104) uses x_
Only the encoder 110, y_encoder 112 and hyper_encoder 116 are used. Each encoder examines the data stream and outputs an independent encoded data stream to the path. If the load_in_reg signal is active, the data is stored in the in_reg register by the idata_in signal. The data is then sent to all encoders. The data is also sent to the output multiplexer (120) as data_out. The output multiplexer (120) either passes the data or selects the data to pass to the out_reg register from one or all encoders. If the load_out_reg signal is active, the data is stored in the out_reg register. Each encoder can optionally communicate with an external memory via a RAM bus structure.

The x_encoder (110), y_encoder (112), and z_encoder (114) modules are provided by the Hamming code generation logic, and further the encoder adds a systematic codeword to all data bits of the data block. To work with other logic that allows In the embodiment, the x_encoder (110
) Stores the Hamming calculation result and the parity calculation result in an internal register such as a column encoding storage array. If DATA_RATE is greater than 1, then DAT
Hamming calculation of A_RATE bit is performed in parallel. y_encoder (112
) Stores the Hamming calculation result in an external memory such as an external RAM or a column encode storage array when DATA_RATE equals 1. However, DAT
If A_RATE is greater than 1, the data is stored in the external memory as DATA_RATE wide group. In this case, the number of addresses is 1 / DATA_RA
TE, and the number of bits per address is DATA_RATE times. The z_encoder (114) operates similarly to the y_encoder (112) and stores the error correction bits in the surface encode storage array.

The hyper_encoder module 116 adds an additional row or column to the 2-D block or an additional hyperbit plane to the 3-D block. Hyperbits are calculated by performing even parity processing along the diagonal axis of the block. The resulting parity bits are stored in external memory such as a parity array. All RAM addresses, data, and control signals are output to the RAM bus and sent to external memory. The y_encoder is using the least significant bits, the z_encoder is using the middle bits and the hyper_encoder is using the most significant bits, if any.

The o_first signal asserts the first bit of the block output. o_l
The ast signal asserts the last bit of the block output. DATA_RATE
If is greater than 1, both signals may be asserted at the same time. Which bit in the bus is the first and last bit is determined by the user.

The Hyper_Encoder (116) computes parity bits across the diagonal for the input block. FIG. 6 shows a hyper encoder (1
Details of 16) are shown below. The hyper_encoder (116) has an input pipe stage (202),
It includes a hypercore (200) and an output pipe stage (204). Input pipe stage
(202) stores all the data used by other modules in the Hyper Encoder (116). Data enters the hyper encoder through the input pipe stage by a ready / accept handshake, indicated by enc_rdy and enc_acpt, respectively. Similarly, the output pipe stage (204) has hyper_rdy and hyper_ac
The hyper-encoded data is output by the ready / accept handshake indicated by pt.

The hyper_core (200) has a hyper register or hyper array that can store a complete row. The Hyper_Core (200) contains a control module that causes all RAM reads and writes. For 2-D enhanced turbo product codes, the register can hold a complete row. Therefore, the data is transferred between the immediately preceding row register and the hyper register. For 3-D blocks, the complete hyperplane is stored in the hyperencoder. Therefore, RAM is used to hold the hyperplane parity bits. Thus, as data is sent to the output pipestage (204), rows are stored in hyperregisters.
When the end of the row is reached, the row is written to RAM. The input data is manipulated by placing the previous row and performing an exclusive-OR operation on the input data, as discussed below. Then, this data is written in the RAM. The previous row is set to 0 during the entire first surface. The previous row is updated depending on which row is in the plane. If the row is the last row in the plane, it is RA
Receives the current data written to M. However, if the row is another row in the plane, it receives and writes the contents of the current RAM address. There are exceptions. For example, during the first surface, the previous row is set to 0. Also, the second
On the surface, the area in the shortr is set to zero. In these cases, the previous row is obviously zeroed to prevent the previous RAM contents from corrupting the hyper-operation.

The hyper_encoder (116) calculates parity along the hyper diagonal of the eTPC block. Hyper Diagonal traversal
Vary depending on the type of eTPC code. If the eTPC code is 2-D, then there is one hyper parity bit row that is either added to the block as part of the block or is present separately. However, more than one row of hyper parity bits may be added to the block. In 3-D block codes, the full plane of hyperparity is added to the block by the encoder (100).

Data is input from the upper left corner of the block. In the first row, the data is loaded into the output hyperregister. At the end of the row, the data is XORed with the previous row register and stored in the previous row register. After the last eTPC block's DATA_RATE collection is sent to the output, the data is sent to the previous row register. The result is then sent from the previous row register to the output pipestage.

A word is written to RAM if it is entirely in the hyper_reg register.
Then, the address is incremented. The address is reset to 0 when the last row of the surface is written. During the first side only data is written,
All reads are ignored. During the surface that follows, the data is read from RAM, placed in the previous row register, and the data in the hyperregister is written to the same address. The address is reset to 0 when the last word of the last row of the last facet has been sent to the output pipeline. The word in the hyperregister is output immediately. The address is incremented when the last word of the hyperregister is output to the output pipeline. At the end of each line of hyperbit output, the address is incremented. When the address reaches the y size, the output ends.

Although the encoder (100) is described as encoding 2 and 3 dimensional codes, the encoder (100) may encode higher dimensional data and is not limited to the above dimensions. It should be noted. If the data being input to the encoder (100) is higher than 3 in size, then the encoder (100) will encode sub-blocks of data such as rows, columns, etc. using the methods described above.

The encoder (100) also supports code shortening. For example, the number of x, y, and z rows that are reduced is specified by the input data for shortx (), shorty (), and shoutz (). The shoutb input data can be used to reduce the block size by the extra bits of data. With these input data, the encoder (100) can encode a block size of any length. Bit shortening removes the first bit of x rows. The shortened bits are not output in the data stream.

Since the bits are shortened by various amounts, the data inputs are not arranged in blocks. Therefore shortb and shortr are used to align bits within a block. In particular, shortb represents the "bit shortening amount" signal, which determines the number of bits in a row subtracted from a 2-D block. For 2-D Enhanced Turbo Product code, shortr must be set to 0. In addition, the shortr indicates the "line shortening amount", and defines the number of bits of the first surface to be shortened. In the 3-D block,
The value of shortr defines the number of lines shortened from the first side.

The block of FIG. 10 a is sh in the 2-D enhanced turbo product code.
FIG. 6 is a diagram showing the use of oprtb. A "-" in a bit indicates a shortened bit in a row and is absolutely 0. In FIG. 10a, a "-" is placed in each shortened row, row 1, at addresses 0-4. The input data does not start in the upper left corner of the face, but instead after the last "-". This affects the encoding process as it changes the location where the data is initially stored. However, since the parity row is initialized to 0 in the first step of hyperencoding, the initial position of the data does not change the result or output of the hyperparity check.

FIG. 10 b shows shortb and 3-b in 3-D enhanced turbo product code.
Indicates the use of shortr. Similar to the 2-D Enhanced Turbo Product code with shortb, a "-" symbol is placed in the shortened row, which symbol indicates an absolute 0. Again, the input data is placed after the last "-" sign that changes the position where the data is first recorded. However, as in the case of 2-D blocks, the initial position of the data does not change the result or output of the hyper parity check. This is because the hyper parity plane has been initialized to 0.

There are two counters, hyper_index and addr, which control the calculation of hyperbits. hyper_index is used to create the input vector, addr is R
This is the AM address. Shortr and shortb are processed by preloading the counter. In shortb, the hyper_index register is used. The very first row of the incoming eTPC is shortened by shortb bits. If the first word of the incoming codeword, enc_start, is sent with the data,
The hyper_index register is loaded with shortb + 1. hyper_reg register is D
ATA_RATE Receive bits are all zeroed except where they are located. From this point, when bits are input, they are loaded into hyper_reg.
In the lines that follow, all loading begins when hyper_index is set to zero.

In shortr, the addr register is used. At the start, the address of the first word written is shortr. RAM is filled from shortr. At the end of the plane, the address wraps around to 0. At this point, 0 to s
Addresses up to hort-1 do not hold data. All reads between the second side are forced to zero. Addresses are only generated for 3-D code, not for 2-D code.

Having described the structure of the encoder (100) according to the present invention, the operational aspects of the encoder (100) will now be described. 8a-8c show several eTPC blocks of different sizes. In a 2-D block, the block comprises the bits along the diagonal and the parity is calculated for that diagonal. The blocks shown in Figures 8a-8c include extended Hamming codes added to the information bits. In FIG. 8a, after hyper-encoding, the 7x7 block is 8x7eT.
It is a PC block. In FIG. 8b, after hyper-encoding, the 15x5 block becomes a 16x5e TPC block. In FIG. 8c, after hyper-encoding, the 4x8 block becomes a 4x9e TPC block. In each figure,
The number of each bit of the block represents the address number of the bit. In addition, in each figure, the hyperbits are represented by the symbol "h", followed by the address number of each byte along which the parity is calculated. In each figure, each address in a row of blocks is located to the right in the next row (along the y-axis). Data is input to the block row by row from the left corner of each block. The data is shown in Figure 8.
It is entered correctly, as shown in a-8c.

Data is entered line by line, starting with the first line. The data is encoded by the x_encoder (110), y_encoder (112), and z_encoder (114) and includes extended Hamming code bits. After the last row is input to the array, the placement means act on a series of arrays, such as rows or columns. In order to calculate the hyper parity bits of the eTPC block according to the present invention, the following steps are preferably performed. 1. Set the parity row of the block to zero (0).
That is, 0s are arranged in all bits of the parity row. 2. "Rotate" parity row,
That is, only the 1-bit address is arranged to the right. This step may be performed on rows or columns. 3. Perform an exclusive OR operation on the parity row and the input bit. 4. Store the result in the parity row. The process is repeated from step 2 until the result of the XOR operation of the parity row and the last row is placed in the parity row. When the result for the last row is placed in the parity row, the parity row is preferably rotated one revolution to the right and the result is output.

However, these steps need not be performed in this way. Other combinations of the above steps according to the invention for encoding the data will give the same result. Also, it should be noted that while the parity row is placed one to the right, the parity row may be placed in any other direction. Furthermore, the parity row is not necessarily rotated by one after each input row is subjected to an exclusive OR operation. That is, the parity row may be moved by two or more bit addresses.

FIG. 9 is a diagram of a 3-D enhanced turbo product code. As in the previous figure for the 2-D Enhanced Turbo Product code, the block number is the bit address and the number prefixed with "h" is hyper-diagonal. Two
Unlike the -D enhanced turbo product code, the parity bits of a 3-D block are added to the block either as a face, either as a face or as a separate face. The first surface is shown as the leftmost block. Similarly, the second surface is the second from the left and the third surface is shown to the right of the second surface. Further, the parity plane is shown at the far right. There is a positional relationship between the rows of the block, as in the example of a 2-D enhanced turbo product code. In the 3-D Enhanced Turbo Product code, the bit is 1.
Moved down one row or column, right, as the parity check progresses down the z axis. That is, each row of each surface is moved down one row or column right to the next row for the previous surface. For each subsequent face, the last row (of the previous face) is raised to the first row of the following face and moved one bit or column to the right.

The process of determining the hyper parity bit of the 3-D code will be described below. Data is entered line by line, starting with the first line. The data is x_encoder (110
), Y_encoder (112), and z_encoder (114) and includes extended Hamming code bits. After the last row is entered in the surface, the placement means act on a series of surfaces, such as rows or columns. In order to calculate the hyper parity bits of the eTPC block according to the present invention, the following steps are preferably performed. 1. Zero the hyper side of the block. 2. Each row in the next plane is "rotated", that is, placed one bit address to the right. This step may be performed on rows or columns. 3. The exclusive OR operation is performed on the hyper side and the input bit. 4. Store the result in the hyper side. 5. 2 until the parity check is done to the last face
The steps 4 to 4 are repeated. 6. Rotate or move each row of the hyper surface by 1 bit address. 7. Output the face.

However, these steps need not be performed in this way. Other combinations of the above steps according to the invention for encoding the data will give the same result. Also, it should be noted that while the parity row is placed one to the right, the parity row may be placed in any other direction. Furthermore, the parity row is not necessarily rotated by one after each input row is subjected to an exclusive OR operation. That is, the parity row may be moved by two or more bit addresses.

To aid in understanding the structural principles and objectives of the present invention, the present invention has been described in terms of specific embodiments including details. Such descriptions in the specification, which show examples and details, are not intended to limit the scope of the appended claims. It will be apparent to those of ordinary skill in the art that modifications can be made to the embodiments of the present invention selected for illustration without departing from the spirit and purpose of the invention.

[Brief description of drawings]

FIG. 1 is a block diagram of a method for encoding a two-dimensional code according to the present invention.

FIG. 2 is a block diagram of a method for encoding a three-dimensional code according to the present invention.

[Figure 3] FIG. 3 is a block diagram of a two-dimensional code encoder according to the present invention.

[Figure 4] FIG. 4 is a top-level diagram of an encoder module according to the present invention.

[Figure 5] FIG. 5 is a detailed diagram of a datapath module according to the present invention.

[Figure 6] FIG. 6 is a detailed diagram of a hyper encoder according to the present invention.

[Figure 7] FIG. 7 is a detailed diagram of a control module according to the present invention.

8a, 8b, 8c show a two-dimensional enhanced turbo product code according to the present invention.

[Figure 9] FIG. 9 shows a three-dimensional enhanced turbo product code according to the present invention.

FIG. 10a shows a two-dimensional enhanced turbo product code with shortened bits according to the present invention. FIG. 10b shows a three-dimensional enhanced turbo product code with shortened bits according to the present invention. 0

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE, TR), OA (BF , BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, G M, KE, LS, MW, MZ, SD, SL, SZ, TZ , UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, B Z, CA, CH, CN, CR, CU, CZ, DE, DK , DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, J P, KE, KG, KP, KR, KZ, LC, LK, LR , LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, R O, RU, SD, SE, SG, SI, SK, SL, TJ , TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW (72) Inventor Linstrom, Bradley Willia             Mu             United States 94306 California,             Palo Alto, Cherry Es-W             605 (72) Inventor Rad, Peter Shawn             United States 99163 Washington, P             Le Mans, Barry Road N 1805 (72) Inventor Danielson, Alan Robert             United States 83843 Moss, Idaho             Kou, Stephanie Lane 997 F-term (reference) 5B001 AA02 AA05 AA13 AE04 AE07                 5J065 AA01 AA03 AB01 AC01 AD02                       AD05 AE06 AF02 AG06 AG09                       AH01 AH08 AH21

Claims (40)

[Claims] 1. An n containing a plurality of systematic block code codewords.
A method of encoding a dimensional data block, comprising: a. Performing a parity calculation along the hyper-tiagonal of the data block and generating a parity result of the parity calculation; b. Adding a parity result to the data block. 2. The method of claim 1, further comprising storing the parity result in a parity array, the parity array being added to the data block as a separate array. 3. The method of claim 2 further comprising the step of rotating the parity array to substantially align the parity results stored in the parity array with the hyper-diagonals along which the parity result was calculated. Method. 4. The method of claim 2, further comprising the step of initializing the parity array and setting the parity bits to zero before the step of performing parity calculation along the hyper-diagonal is performed. 5. The method of claim 1, further comprising the step of outputting encoded block data when the parity results are substantially aligned in hyper-diagonal. 6. The method according to claim 1, wherein the data block is three-dimensional. 7. The method of claim 6, wherein the parity result of the parity calculation is stored in a parity plane, which parity plane is added to the block data as a separate plane. 8. A method for encoding an n-dimensional data block having a plurality of (n-1) -dimensional sub-blocks, each sub-block including a plurality of systematic block code codewords and a plurality of parity bits. A parity sub-block having has been added to the data block, and a. Equalizing a parity sub-block with a first sub-block rotated by a predetermined number of bits; b. for each of a series of sub-blocks parallel to the first sub-block in the n-dimensional block, performing a bitwise exclusive-OR operation on the parallel sub-block and the parity sub-block, the parity sub-block comprising: The method of rotating by an appropriate number of bits. 9. The method further comprises the step of initializing the parity sub-block such that each parity bit is zero, the step of initializing being performed before the parity sub-block is equal to the first side. The method according to 8. 10. The method of claim 8, further comprising outputting the encoded data block. 11. A method of encoding an n-dimensional data block that includes a plurality of information bits and is received from an input source, comprising: a. Receiving a row of blocks and outputting the row immediately; b. Encoding information bits in a row and producing a first set of encoded data according to a first encoding scheme; c. Outputting a first set of encoded data, d. Encoding information bits in a column according to a second encoding scheme to generate a second set of encoded data, the second set being iteratively updated according to the information bits in the rows; e. Encoding information bits on a hyper-diagonal according to a parity encoding scheme and producing a hyperset of encoded data in accordance with the information bits in rows and columns and the first and second sets of encoded data. And f. Outputting all the information bits and the updated second set of encoded data after all the first set of encoded data has been output, g. Outputting a hyperset of encoded data. 12. The method further comprising encoding a second set of encoded data row by row according to a first encoding scheme such that all received information bits are encoded. The method described in. 13. The method further comprising encoding a second set of encoded data row by row according to a second encoding scheme such that all received information bits are encoded. The method described in. 14. The method of claim 11, wherein the data block is three-dimensional and includes encoded bit planes, the planes being orthogonal to rows and columns. 15. Further comprising: a. Encoding the in-plane information bits according to a third encoding scheme to generate a third set of encoded data, the third set being iteratively updated according to the in-row information bits; b. ． 15. The method of claim 14, comprising outputting a third set of encoded data after all the second set of encoded data has been output. 16. The method of claim 14, wherein the hyper parity array is a hyper parity plane. 17. The method of claim 11, wherein the first set of encoded data is stored in a row encode storage array, the row encode storage array including a plurality of row array bits. 18. The method further comprises resetting the row-encoding storage array such that all row arrays are zero, the resetting step being performed after the first set of encoded data is output. The method according to claim 17. 19. The method of claim 11, wherein the second set of encoded data is stored in a column encode storage array. 20. The method of claim 11, wherein the hyperset of encoded data is stored in a hyperparity array, the hyperparity array including a plurality of parity array bits. 21. The step of encoding on hyper-diagonal further comprises:
a. Updating the hyper parity array by iteratively encoding the parity array of information bits and the first and second sets of encoded data for each row; b. 21. Rotating the hyper parity array by a predetermined number of bits. 22. The method comprises the step of initializing the hyper parity array such that all parity array bits are set to zero, the step of initializing being performed before any information bits are encoded. Item 21. The method according to Item 20. 23. A datapath module encoding a data block having a plurality of systematic block code codewords, each codeword including a plurality of information bits and a plurality of error correction bits, the datapath module comprising a piper. An encoder that encodes a string of block code codewords on a diagonal and performs a parity calculation on the string to produce a parity result for each string. 24. The encoder of claim 23, wherein the parity result for each string is stored in a parity array. 25. The encoder of claim 23, further comprising an input module that receives the block of data. 26. The encoder of claim 23, further comprising an output module that outputs the encoded data block. 27. The datapath module further comprises: a. A first encoder module encoding multiple rows from the data block and adding error correction bits to the rows; b. 24. The encoder of claim 23, comprising a second encoder module that encodes multiple columns from a data block and adds error correction bits to the columns so that encoded data blocks are formed. 28. An encoder according to claim 27, further comprising an output multiplexer connected to all encoder modules and outputting encoded data blocks. 29. The encoder of claim 27, wherein the datapath module further comprises a third encoder module that encodes multiple planes from the data block and adds error correction bits to those planes. 30. Encoding a data block having a plurality of information bits,
An encoder that outputs an information bit immediately after receiving the information bit, comprising: a. A first encoder module that encodes information bits within a row of a block and produces a set of encoded row bits; b. A second encoder that encodes the information bits in the columns of the block, produces a set of column bits encoded according to the information bits in each row, and updates the encoded column bits for each row encoded by the first encoder module. A module, c. A hyper-encoder module that hyper-diagonally encodes all information bits and all encoded bits on the block's diagonal to produce a set of parity results, each parity result being a diagonal of the encoded bits. Compatible encoder. 31. The encoder of claim 30, wherein the hyperencoder rotates the parity array and each parity result is aligned with the corresponding diagonal. 32. A third encoding of information bits in the plane of the block.
An encoder module is provided, the third encoder module generating a set of encoded surface bits according to the information bits in each row and column, and encoding the encoded surface bits according to each set of encoded row and column bits. The encoder according to claim 30, which is updated. 33. The encoder of claim 30, wherein the first encoder module outputs a set of encoded row bits. 34. The encoder of claim 33, wherein the second encoder module outputs the set of encoded column bits after all the sets of encoded row bits have been output. 35. The encoder of claim 34, wherein the hyperencoder module outputs the set of parity results after all encoded row bits and all encoded column bits have been output. 36. An encoder for encoding block data having a plurality of information bits arranged in a plurality of rows and columns into encoded block data, comprising: a. Means for receiving a block of data, the received information bits being immediately output by the output means, b. First means for encoding each row according to a first encoding scheme and producing a row encoding result for each row encoded by the first encoding scheme; c. Encoding each column according to a second encoding scheme and producing a column encoding result for each column encoded by the second encoding scheme, the row encoding result being iteratively updated for each row encoded by the first means. Second means for d. Encoder for encoding the encoded block data on the hyper-diagonal and producing a hyper-parity result for each corresponding diagonal in the encoded data block. 37. An encoder that encodes a data block having a plurality of information bits into encoded block data, and outputs the information bits immediately after receiving the information bits, comprising: a. A first encoder module that encodes information bits within a row of a block and produces a set of encoded row bits; b. A second encoding encoded information bits in columns of the block, producing a set of encoded column bits according to the information bits in each row, updating the encoded column bits for each row encoded by the first encoder module; An encoder with an encoder module. 38. A hyper-encoder module is further provided for encoding the encoded block data on a hyper-diagonal to produce a set of parity results, each parity result corresponding to a respective encoded diagonal. The encoder according to claim 37. 39. The hyperencoder module adds the set of parity results to a data block encoded as a parity array.
The encoder described in. 40. A third encoding of information bits within a plane of the block.
An encoder module is provided, the third encoder module generating a set of surface bits encoded according to the information bits of each row and column, each row encoded by the first encoder module and each row encoded by the second encoder module. 38. The encoder of claim 37, which updates the encoded face bits for columns and.