JP2003347312A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device whereby its metal silicide having an enough thickness to reduce resistance can be formed while preventing a junction leak. <P>SOLUTION: The manufacturing method of the semiconductor device has a process for depositing a metal film 181 contributing to silicification to cover the whole surface of the upper portion of a gate electrode 13 and heavily doped regions 17 of is source/drain, and has a process for covering the metal film 181 with a cap metal film 191. Since the metal film 181 affects largely thicknesses of silicide layers formed thereafter in the heavily doped regions 17 of its source/drain, the metal film 181 is formed firstly to obtain an about 30% in the thickness of the total silicide layer in order not to provide a cause of the junction leak as spiking. Thereafter, a silicide layer 20 is formed through a first rapid thermal annealing process. After removing metals subjected to no reaction and before a secondary rapid thermal annealing process, the whole substrate-surface including the upper portion of the silicide layer 20 is covered again with a metal film contributing to the silicification of remaining 70% portion. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a finer semiconductor element, particularly a semiconductor device having a step of forming a silicide film.

[0002]

2. Description of the Related Art A salicide process of a MOSFET (MOS type field effect transistor) is generally used in recent semiconductor integrated circuits which are required to be finer and faster. In the salicide process, the source / drain diffusion layers of the MOSFET and the upper part of the polysilicon gate electrode are silicided in a self-aligning manner. The parasitic resistance of the element is reduced, and it is possible to cope with miniaturization and high-speed operation.

[0003] The salicide process is realized as follows. On both sides of the polysilicon gate electrode of the MOSFET, an LDD (Lightly Doped Drain) structure, that is, spacers (sidewalls) for forming source / drain extension regions are provided. Therefore, with the silicidation of the upper portion of the gate electrode, the spacer becomes an isolation region, and a high melting point metal thin film can be formed on the source / drain Si substrate in a self-aligned manner, and then a silicide can be formed and a low resistance silicide layer can be formed. Such a salicide process is a well-known technique as a MOSFET for lowering resistance and improving performance.

In the generation having a gate length of 0.18 μm, it is known that Co is used as a refractory metal used in the salicide process. In addition to Co, Ti, Ni, and the like are known as metals having a reputation for the salicide process.
It has been found that Co is superior in heat resistance to Ni and less affected by the fine wire effect during processing than Ti. It is considered that Co is preferable to form low-resistance silicide in a shallow impurity diffusion layer while preventing leakage.

[0005]

Problems to be Solved by the Invention FIGS. 5A and 5B
3A to 3C are cross-sectional views showing a conventional MOSFET manufacturing method in the order of steps. A cobalt salicide process is shown in which the source / drain regions and the top of the gate electrode are silicided using Co.

As shown in FIG. 5A, after forming an element isolation region (not shown) in a Si substrate 51 and forming a well and the like, a gate oxide film 52 and a polysilicon gate electrode 53 are formed on the substrate 51. A sidewall 54 such as a silicon oxide film or a silicon nitride film is formed on the side of the gate. The source / drain region 55 has an LDD structure, that is, a so-called low concentration extension region. That is,
A low concentration impurity is ion-implanted into the substrate 51 using the polysilicon gate electrode 53 as a mask, and a high concentration impurity is ion-implanted using the sidewalls 54 as a mask. In such a configuration,
For example, a Co film 56 is formed on the entire surface by a sputtering method. Further, a cap metal film 57 covering the Co film 56 is formed by a sputtering method. The cap metal film 57 is a Co film 56
Formed to prevent oxidation of TiN.
Adopt a membrane. Next, heat treatment for silicidation is performed on the Co film 56. This is the first rapid thermal anneal, which is performed at an annealing temperature selected from 400 to 600 ° C. for about 30 seconds. The silicide layer becomes CoSi having a relatively high resistance.

Next, as shown in FIG. 5B, after removing the cap metal film 57 and unreacted Co, heat treatment is performed again. This is the second rapid thermal anneal, 800-
The annealing is performed at a selected annealing temperature of 900 ° C. for about 30 seconds. As a result, the composition of CoSi changes to CoSi ₂ , and a stable low-resistance silicide layer 58 is formed. The side wall 54 suppresses silicidation on the side of the polysilicon gate electrode 53 and prevents a short circuit with the source / drain region 55.

The thickness of the Co film 56 affects the thickness of a silicide layer to be formed later in the source / drain region 55. Co + Si → CoSi (or CoSi
By the reaction of _x ), the final thickness of the silicide layer 58 becomes three times or more the thickness of the Co film 56 to be formed first. Incidentally, CoSi obtained by the first rapid thermal annealing treatment is about twice the thickness of the Co film 56 to be formed first, and CoSi ₂ obtained through the second rapid thermal annealing treatment is initially This is about 3.6 times the thickness of the Co film 56 to be formed.

In order to lower the resistance, the thickness of the silicide layer 58 is preferably larger. However, if the Co film 56 is formed thicker to reduce the resistance, the reaction in the depth direction of the silicon in the source / drain region 55 is further promoted. This causes junction leakage such as CoSi spiking.

The present invention has been made in view of the above circumstances, and provides a method of manufacturing a semiconductor device capable of forming a metal silicide having a sufficient thickness required for low resistance while preventing junction leakage. What you want to do.

[0011]

According to a method of manufacturing a semiconductor device according to the present invention, an insulating film spacer is arranged on a gate insulating film on a substrate and a gate side portion formed of a polysilicon layer, and a gate and a source / drain region are formed on the gate. A method of manufacturing a semiconductor device which is silicided in a self-aligned manner, wherein the metal film coated for the silicidation is formed by sputtering a plurality of times according to at least each heat treatment step. I do.

According to the method of manufacturing a semiconductor device according to the present invention, in the silicidation reaction in the first heat treatment step, the reaction in the depth direction of silicon in the source / drain regions is remarkably accelerated. Therefore, the metal film to be coated for silicidation is not formed in the entire thickness from the beginning, but is formed in a part of the thickness. After that, if the remaining portion is formed by sputtering in accordance with the heat treatment process, the metal silicide reacts with the already silicided substance, and the metal silicide becomes thicker while the progress of the reaction in the depth direction of silicon is suppressed.

In a method of manufacturing a semiconductor device according to a more preferred embodiment of the present invention, an insulating film spacer is arranged on a side of a gate insulating film on a substrate and a gate side composed of a polysilicon layer, and a gate insulating film is formed on a gate and source / drain regions. A method for manufacturing a semiconductor device that silicides in a self-aligned manner, comprising: sputter forming a metal film for silicidation on the entire surface of a substrate; and sputter forming a cap metal film on the metal film. A first heat treatment step of forming a silicide layer by performing a heat treatment in a state where the cap metal film is covered, a step of removing the cap metal film and an unreacted portion of the metal film, and including at least a portion on the silicide layer Forming the metal film for silicidation again on the entire surface of the substrate by sputtering, and further reducing the metal film and the silicide layer. A second heat-treatment step of the anti-silicide layer, characterized by comprising the a step of selectively removing portions of the metal film of the unreacted.

According to the method of manufacturing a semiconductor device according to the present invention, the source / drain region is formed in the depth direction of silicon by a metal film for silicidation in the first heat treatment step by an amount corresponding to its thickness. The reaction proceeds. Therefore,
The metal film to be coated for silicidation is not formed thick from the beginning, but is set to a certain percentage of the whole amount. Thereafter, the remaining portion is formed by sputtering before the second heat treatment step. Thereby, in the second heat treatment step, the metal film for silicidation formed again by sputtering reacts with the already silicided substance, and the metal silicide becomes thicker while the reaction progress in the depth direction of silicon is suppressed. Become.

In the method of manufacturing a semiconductor device according to the present invention, the thickness of the metal film formed before the second heat treatment step is the same as that of the metal film formed before the first heat treatment step. It is characterized by being equal to or greater than the thickness. The metal film may include Co, and the cap metal film may include TiN. Co is suitable for fine processing and lowering resistance, and TiN is rich in barrier properties against oxidation.

[0016]

1 to 4 are cross-sectional views showing a main part of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. As shown in FIG. 1, a gate oxide film 12 and a polysilicon layer are sequentially formed in an element region on a Si substrate 11 having a predetermined impurity concentration, and a gate electrode 13 is patterned. Thereafter, the gate electrode 13 is post-oxidized (thermally oxidized), and the region of the gate electrode 13 is used as a mask.
LDD (Lightly Doped Drain) structure Low-concentration source / drain region 1 for so-called extension region
4 is formed by impurity ion implantation.

Next, an insulating film, for example, a silicon oxide film is deposited so as to cover the gate electrode 13 by the CVD method, and anisotropic dry etching is performed to form a sidewall 15 of the silicon oxide film. Next, using the region of the gate electrode 13 and the side wall 15 as a mask, a high concentration region 16 of source / drain is formed by impurity ion implantation.

Next, a metal film 181 contributing to silicidation is deposited on the entire surface so as to cover the upper portion of the gate electrode 13 and the high concentration region 16 of the source / drain. The metal film 181 is, for example, Co, and is deposited using a sputtering method. That is, Ar (argon) gas is supplied in a vacuum chamber using Co as a target electrode to generate plasma,
This is achieved by exhibiting a Co sputtering phenomenon.

The thickness of the metal film (Co in this case) 181 greatly affects the thickness of a silicide layer to be formed later in the high-concentration source / drain regions 17. Therefore, in order not to cause a junction leak such as spiking, first, the target overall silicide layer thickness of 3
A metal film (Co) 181 having a thickness of about 30% is formed. For example, when the depth of the source / drain high-concentration region 17 is 200 nm, the thickness of the metal film (Co) 181 is suppressed to about 6 nm.

Next, an oxidation-resistant cap metal film 191 is coated on the metal film (Co) 181. Cap metal film 1
Reference numeral 91 denotes, for example, TiN, which is deposited using a sputtering method. That is, it is achieved by supplying N ₂ (nitrogen) gas in a vacuum chamber using Ti as a target electrode to generate plasma, thereby exhibiting a Ti sputtering phenomenon. The thickness of the cap metal film (here, TiN) 191 is set to 5 to 10 nm in order to prevent the Co surface from being oxidized until the heat process for forming a silicide layer is performed later.
It just needs to be thick.

Next, a heat treatment for promoting silicidation of the above structure, that is, a so-called first rapid thermal annealing step is performed.
This is a heat treatment (lamp annealing) for about 30 to 90 seconds at an annealing temperature (for example, about 500 ° C.) selected from 400 to 600 ° C. Thus, a silicide layer 20 is formed at least on the gate electrode 13 and the source / drain region 17 (shown in FIG. 2).

Next, as shown in FIG. 2, unreacted metal,
That is, the metal film (TiN) 19 and the metal film (Co) 18
Unnecessary film is removed. The silicide layer 20 is formed of a high-resistance CoSi film (including a Co ₂ Si film). The unnecessary film removing step is wet etching, and the wafer is, for example, a solution containing ammonia + hydrogen peroxide solution (R
It is immersed in SC-1) referred to as CA cleaning for a predetermined time. Thereafter, after cleaning and drying, the wafer is immersed in a solution containing, for example, hydrochloric acid + hydrogen peroxide solution (SC-2 in RCA cleaning) for a predetermined time. Thereafter, the wafer is cleaned and dried.

Next, as shown in FIG.
A metal film (Co) 182 for silicidation is formed again by sputtering on the entire surface of the substrate so as to include on the zero. In the previous step, the target overall silicide layer thickness was about 3
Since the metal film (Co) 181 to be divided is already formed, the metal film (C) having a thickness of about 70% and a thickness of about 14 nm is remaining.
o) Form 182.

Next, an oxidation-resistant cap metal film 192 is coated on the metal film (Co) 182. Cap metal film 1
Reference numeral 92 denotes, for example, TiN, which is deposited using a sputtering method. That is, it is achieved by supplying N ₂ (nitrogen) gas in a vacuum chamber using Ti as a target electrode to generate plasma, thereby exhibiting a Ti sputtering phenomenon. The thickness of the cap metal film (here, TiN) 192 is set to 5 to 10 nm in order to prevent the Co surface from being oxidized until the heat process for forming a silicide layer is performed later.
It just needs to be thick.

Thereafter, annealing is performed again (the second rapid thermal annealing step is performed). This is 800-900 ° C
Annealing temperature selected (for example, about 850 ° C.)
For about 30 seconds (lamp annealing). Thereby, the silicide layer 20 is stabilized, and the metal film (Co) 182 and CoSi
The reaction proceeds (or CoSi _x). As a result, the silicide layer (CoSi ₂ film) is formed thick while suppressing the progress of the reaction in the depth direction of silicon (22 in FIG. 4). For example, a silicide layer (CoSi ₂ film) 22 having a thickness of about 70 nm is realized while the depth of the source / drain high concentration region 17 is about 200 nm.

Next, as shown in FIG. 4, unnecessary films of the cap metal film (TiN) 192 and the unreacted metal film (Co) 18 are removed. This removal step is wet etching, and the wafer is immersed in a solution containing, for example, ammonia + hydrogen peroxide (SC-1 in RCA cleaning) for a predetermined time. Thereafter, after cleaning and drying, the wafer is subjected to a solution containing, for example, hydrochloric acid + hydrogen peroxide solution (SC in RCA cleaning).
-2) is immersed for a predetermined time. Thereafter, the wafer is cleaned and dried. Through the above-described steps, a silicide layer (CoSi ₂ film) 22 having a large film thickness in which the progress of the reaction in the depth direction of silicon is suppressed is formed.

According to the method of the above-described embodiment, the metal film (Co) contributing to silicidation is divided into two metal films (Co) 181 and 182 according to the first and second annealing steps. It is formed by sputtering. Source / drain region 17
In the first thermal annealing step, the Co film 181 is reacted in the depth direction of silicon by an amount corresponding to its thickness. Therefore, the Co film 181 is not formed to be thick from the beginning, but is set to a certain percentage of the total amount. Thereafter, the remaining film, that is, the Co film 182 is formed by sputtering before the second annealing step.

[0028] Accordingly, in the secondary annealing process, become a reaction between the Co film 182 was again sputtered already silicided CoSi (or CoSi _x), while reaction progress in the depth direction of the silicon is suppressed The silicide layer 22 becomes thicker. In the method of the above embodiment, the distribution of the Co films 181 and 182 is set to about 3: 7.
However, the present invention is not limited to this, and the same effect can be obtained even if the distribution is changed by half, about 5: 5, and a mode is obtained in which the silicide layer 22 becomes thicker while suppressing the progress of the reaction in the depth direction of silicon. Can be

[0029]

As described above, according to the present invention, attention was paid to the fact that in the first heat treatment step in the silicidation reaction, the reaction in the depth direction of silicon in the source / drain regions was remarkably accelerated. Therefore, the metal film to be coated for silicidation is not formed in the entire thickness from the beginning, but is formed in a small portion thereof. Thereafter, if the remaining portion is formed by sputtering in accordance with the next heat treatment step, a reaction occurs with the already silicided substance, and the metal silicide becomes thicker while the progress of the reaction in the depth direction of silicon is suppressed. As a result, it is possible to provide a method of manufacturing a semiconductor device capable of forming a metal silicide having a sufficient thickness required for low resistance while preventing junction leakage.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a main part of a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a second cross-sectional view following FIG. 1 showing a main portion of the method of manufacturing the semiconductor device according to the embodiment of the present invention in the order of steps.

FIG. 3 is a third cross-sectional view following FIG. 2 showing a main portion of the method of manufacturing the semiconductor device according to the embodiment of the present invention in the order of steps;

FIG. 4 is a fourth cross-sectional view following FIG. 3 showing a main portion of the method of manufacturing the semiconductor device according to the embodiment of the present invention in the order of steps;

FIGS. 5 (a) and 5 (b) show a conventional MOSFE, respectively.
It is sectional drawing which shows the manufacturing method of T in order of a process.

[Explanation of symbols]

11, 51 ... Si substrate 12, 52 ... gate oxide film 13, 53: gate electrode (polysilicon gate electrode) 14. Source / drain region (low concentration region) 16, 54… Sidewall 17, 55: Source / drain region (high concentration region) 181, 182: Metal film (Co) 191, 192, 57: Cap metal film (TiN) 20, 22, 58 ... silicide layer 56 Co film

Continuation of front page    F-term (reference) 4M104 AA01 BB01 BB20 CC01 CC05                       DD02 DD37 DD80 DD84 FF14                       GG09 HH16 HH20                 5F033 HH04 HH25 KK25 PP15 QQ70                       QQ73 XX00 XX10                 5F140 AA01 AA10 AA24 AA39 BA01                       BF04 BF11 BF18 BG08 BG12                       BG30 BG34 BG44 BG45 BG52                       BG53 BG56 BH15 BJ01 BJ08                       BJ20 BK02 BK13 BK29 BK34                       CF04

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, wherein an insulating film spacer is arranged on a side of a gate made of a polysilicon layer and a gate insulating film on a substrate, and a gate and source / drain regions are silicided in a self-aligned manner. The method of manufacturing a semiconductor device, wherein the metal film coated for silicidation is formed by sputtering a plurality of times at least for each heat treatment step. 2. A method of manufacturing a semiconductor device in which an insulating film spacer is disposed on a side of a gate made of a polysilicon layer and a gate insulating film on a substrate, and the gate and source / drain regions are silicided in a self-aligned manner. A step of sputter-forming a metal film for silicidation on the entire surface of the substrate; a step of sputter-forming a cap metal film on the metal film; and a heat treatment in a state where the cap metal film is covered, to form a silicide layer. A first heat treatment step of forming; a step of removing the cap metal film and the unreacted portion of the metal film; and re-forming the metal film for silicidation on the entire surface of the substrate so as to include at least the silicide layer. A step of forming by sputtering, a second heat treatment step of making the metal film and the silicide layer a silicide layer having a lower resistance, Method of manufacturing a semiconductor device is characterized in that comprising the step of selectively removing portions of the metal film. 3. The method according to claim 1, wherein a thickness of the metal film formed before the second heat treatment is equal to or larger than a thickness of the metal film formed before the first heat treatment. A method for manufacturing a semiconductor device according to claim 2. 4. The method according to claim 2, wherein the metal film includes Co, and the cap metal film includes TiN.