JP2003338742A - Drive circuit for current controlled device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit, for a current controlled semiconductor device, for suppressing through-current, when one transistor constituting a half bridge is turned on while the other transistor is turned on in the opposite direction. <P>SOLUTION: When a transistor T2 for driving a lower side arm, is turned on while a transistor T1 for driving an upper side arm, is turned on in the opposite direction, the carrier accumulated in the drive transistor T1 is pulled out, using a current in the direction flowing into the dot side of the secondary winding SU of a transformer T. Thereby, the time during which the driving transistor T1 is made to conduct forward current, while being in off state, is reduced. The current, in the direction flowing into the dot side of the secondary winding SU of the transformer T, is made to flow by turning on an N-type MOS transistor M21U, when the induced voltage V2U in the secondary winding SU becomes negative (= the time, when the signal detected by a pulse period sensing circuit 24U reaches H level). Then, the detected signal at the pulse period sensing circuit 24U passes through a waveform shaping circuit 25U, to remove the noise superposed on the detected signal. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current control type element driving circuit for supplying a driving current to an inductive load.

[0002]

2. Description of the Related Art A drive circuit for a current control type element that drives an inductive load is used, for example, in a half bridge circuit that drives an induction motor. FIG. 12 is a diagram showing an example of a half bridge circuit. In FIG. 12, a transistor T1 forming the upper arm and a transistor T2 forming the lower arm are current-controlled switching transistors (hereinafter referred to as driving transistors).
Is. The driving transistors T1 and T2 are turned on / off according to the current supplied from the driving circuit to the base terminal, and are connected between the emitter terminal of the driving transistor T1 and the collector terminal of the driving transistor T2. The sexual load L is driven.

The drive circuit for the upper arm comprises a pulse power supply, a control circuit 92U, N-type MOS transistors 93U and 94U, and a diode D1U. The pulse power supply includes a pulse generation circuit 91, a DC power supply Vs,
It is composed of diodes Ds1 and Ds2, switches SW1 and SW2, and a transformer T. A primary winding P and a secondary winding SU are wound around the transformer T.

In the circuit on the primary winding P side of the transformer T,
A switch SW1 for applying the voltage of the DC power supply Vs to the primary winding P in a positive direction (upward toward dots in the figure)
And SW2 are connected in series. Further, the diode Ds is arranged in a direction in which the current flowing through the primary winding P is circulated.
1 and Ds2 are connected in series. The pulse generation circuit 91 has a pulse-shaped control signal Vg91 to turn on / off a set of switches SW1 and SW2 at a predetermined cycle.
Is output.

In the circuit on the secondary winding SU side of the transformer T, N-type MOS transistors 93U and 94U are provided so that the polarities of the body diodes incorporated therein are opposite to each other.
Are connected in series. Body diode D93U
Are incorporated in the N-type MOS transistor 93U. The body diode D94U is an N-type MOS transistor 94.
Built into U. The control circuit 92U turns on one of the N-type MOS transistors 93U and 94U and turns off the other one of the control signals Vg93U and Vg94.
Output U. The diode D1U has an anode terminal connected to the emitter terminal of the driving transistor T1 and a cathode terminal connected to the base terminal of the driving transistor T1.

The drive circuit for the lower arm comprises a pulse power supply, a control circuit 92L, N-type MOS transistors 93L and 94L, and a diode D1L. The pulse power supply is shared with the above-mentioned upper arm pulse power supply,
The secondary winding SL is further wound around the transformer T. The secondary winding SU and the secondary winding SL have opposite polarities.

In the circuit on the secondary winding SL side of the transformer T, N-type MOS transistors 93L and 94L are provided so that the polarities of the body diodes incorporated therein are opposite to each other.
Are connected in series. Body diode D93L
Are incorporated in the N-type MOS transistor 93L. The body diode D94L is an N-type MOS transistor 94.
Built into L. The control circuit 92L turns on one of the N-type MOS transistors 93L and 94L and turns off the other one of the control signals Vg93L and Vg94.
Output L. The diode D1L has an anode terminal connected to the emitter terminal of the driving transistor T2 and a cathode terminal connected to the base terminal of the driving transistor T2.

In the above half bridge circuit, for example, the case where the driving transistor T2 is turned on will be described. As described above, the control signal Vg91 is repeatedly turned on / off in a predetermined cycle. When the control signal Vg91 becomes H level, the switches SW1 and SW2 are turned on. At this time, the current flowing through the primary winding P of the transformer T increases, and the voltage V2L induced in the secondary winding SL has a negative direction. When the control signal Vg91 becomes L level,
The switches SW1 and SW2 are turned off. At this time,
The current flowing in the primary winding P of the transformer T is circulated and reduced through the diodes Ds1 and Ds2, and the voltage V2L induced in the secondary winding SL has a positive direction.

The control circuit 92L sets the control signal Vg94L to H level.
When the control signal Vg93L is set to L level and the N-type MOS transistor 94L is turned on,
The OS transistor 93L is turned off. Secondary winding SL
A current half-wave rectified by the body diode D93L of the N-type MOS transistor 93L is supplied to the side circuit.
Driving transistor T2 via S transistor 94L
It flows into the base terminal of. As a result, the driving transistor T2 is turned on by injecting carriers into the transistor T2. When the driving transistor T2 is turned on, a current flows in the direction shown in the figure.

After that, the control circuit 92L controls the control signal Vg9.
4L to L level and control signal Vg93L to H
When set to the level, the N-type MOS transistor 94L is turned off and the N-type MOS transistor 93L is turned on. The circuit on the side of the secondary winding SL has an N-type MOS transistor 94.
The current half-wave rectified by the L body diode D94L flows to the opposite side of the dot of the secondary winding SL via the N-type MOS transistor 93L. As a result, the driving transistor T2 is turned off by removing the carrier from the base terminal.

When the driving transistor T2 is turned off, a back electromotive force is generated from the inductive load L, and the back electromotive force raises the potential at the VM point in the figure. When the potential at the VM point becomes higher than the potential of the base terminal of the driving transistor T1 + the forward ON voltage of the diode D1U, the diode D1U is forward biased and a current flows in the direction shown in the figure. This current injects carriers into the base terminal of the driving transistor T1, and the driving transistor T1 is turned on in the reverse direction. As a result, the circulating current due to the counter electromotive force flows in the direction shown in the figure.

[0012]

The driving transistor T1 which is turned on in the reverse direction has many carriers inside. Therefore, in this state, the driving transistor T2
Is turned on again, carriers are retained in the driving transistor T1 and the reverse recovery operation takes time. Therefore, the driving transistor T1 is in a state in which a forward current flowing from the collector terminal to the emitter terminal of the driving transistor T1 easily flows even though the driving transistor T1 is turned off by the control circuit 92U. As a result, a large through current flows through the driving transistor T1 and the driving transistor T2.

An object of the present invention is to turn on a through current flowing in a current control type transistor forming upper and lower arms, that is, while one of the current control type transistors is turned on in the opposite direction, the other current control type transistor is turned on. It is an object of the present invention to provide a drive circuit for a current control type element that suppresses a current that passes through both upper and lower current control type transistors in some cases.

[0014]

(1) The invention according to claim 1 is located on the upper arm side with respect to the inductive load.
Is connected in series with the first current control type transistor and the first current control type transistor, which supplies a drive current in the direction of, and causes a current due to the counter electromotive force generated from the inductive load to flow in the reverse direction. A second current-controlled transistor which is located on the lower arm side with respect to and supplies a drive current in a second direction different from the first direction and allows a current due to a back electromotive force generated from an inductive load to flow in a reverse direction. It is applied to a drive circuit for a current control type element that drives each of and.
And, it is interposed between the pulse current generating means for alternately generating the positive pulse current and the negative pulse current, and the pulse current generating means and the first current control type transistor,
The first switch means for supplying a positive pulsed current to the control terminal of the first current control type transistor, and the first current control type transistor is interposed between the pulse current generating means and the first current control type transistor. Second switch means for supplying a negative pulsed current to the control terminal of the control type transistor, and generation timing of the pulsed current generated in the first current control type transistor by the pulse current generation means are detected, and a detection signal is detected. A first timing detecting means for outputting
When turning on the current control type transistor of (1), the first switch means is instructed to supply a positive pulsed current according to the detection signal from the first timing detection means, and (2) the first current control type transistor is turned on. When turned off, the first timing control circuit for instructing the supply of the negative pulsed current to the second switch means in response to the detection signal from the first timing detection means, the pulse current generation means, and the second current control. A third switch means for supplying a positive pulsed current to the control terminal of the second current control type transistor, the pulse current generating means and the second current control type transistor. The second current control transistor is interposed between the fourth switch means for supplying a negative pulsed current to the control terminal of the second current control transistor and the pulse current generating means. Second for detecting the generation timing of the pulsed current generated to Njisuta, and outputs a detection signal
And (1) when the second current control type transistor is turned on, the third switch means is instructed to supply a positive pulsed current according to the detection signal from the second timing detection means, (2) A second timing control circuit for instructing the fourth switch means to supply a negative pulsed current in response to a detection signal from the second timing detection means when turning off the second current control type transistor. And a waveform shaping unit that removes noise of at least the detection signal of the first timing detection unit among the detection signals of the first timing detection unit and the detection signal of the second timing detection unit. To achieve. (2) The invention according to claim 2 is the drive circuit for a current control type element according to claim 1, wherein noise is generated by the third switch means being a positive pulse to the control terminal of the second current control type transistor. It is characterized in that it is generated when the supply of the constant current is started. (3) The invention according to claim 3 is the drive circuit for a current control type element according to claim 1 or 2, wherein, as for noise, the first current control type transistor causes a current due to a counter electromotive force to flow in a reverse direction. It is characterized by occurring in the state. (4) The invention according to claim 4 is the drive circuit for a current control type element according to any one of claims 1 to 3, wherein the waveform shaping means changes the signal level of the input signal ( 1) Outputs the detected signal level after the change when the predetermined time has passed since the last signal level change, and (2) Signal level before the change when the predetermined time has not passed since the last signal level change Is output continuously. (5) The invention according to claim 5 is the drive circuit for a current control type element according to any one of claims 1 to 3, wherein the waveform shaping means has a PLL circuit, and the input signal is the P signal.
The reference frequency signal of the LL circuit is used, and the output signal is the P
The comparison frequency signal of the LL circuit is used. (6) The invention according to claim 6 is the drive circuit for a current control type element according to any one of claims 1 to 3, characterized in that the waveform shaping means is constituted by a low-pass filter circuit. To do.

[0015]

According to the current control type element driving circuit of the present invention, it is possible to suppress the through current flowing through the current control type transistors forming the upper and lower arms.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a drive circuit of a current control type element according to a first embodiment of the present invention. In FIG. 1, the driving transistor T1 connected to the top and bottom
And T2 form a half bridge.
T1 and T2 supply a drive current to an inductive load L such as a motor. For example, the collector terminal of the driving transistor T1 is connected to the DC power supply VP, and the emitter terminal of the driving transistor T2 is grounded. The emitter terminal of the driving transistor T1 and the driving transistor T2
An inductive load L is connected to the collector terminal of the.

The driving transistor T1 forming the upper arm is turned on / off according to the pulse current I2U supplied from the driving circuit to the base terminal. The driving transistor T2 forming the lower arm is turned on / off according to the pulse current I2L supplied from the driving circuit to the base terminal. The driving transistors T1 and T2 are driven in a complementary manner.

The drive circuit for the upper arm includes a pulse power source,
Timing control circuit 26U, N-type MOS transistors M21U, M22U and M23U, and waveform shaping circuit 2
5U and a pulse period sense circuit 24U. The lower arm drive circuit includes a pulse power supply, a timing control circuit 26L, and an N-type MOS transistor M21.
L, M22L and M23L, and a pulse period sense circuit 24L. The drive timing of each of the upper arm drive circuit and the lower arm drive circuit is controlled by the drive controller 30.

The pulse power supply is commonly used by the upper and lower arms. The pulse power supply is a DC power supply Vs and a diode Ds.
1 and Ds2, switches SW1 and SW2, and a transformer T. The transformer T has the core and the primary winding P in common and the secondary windings SU and S.
L is wound. The secondary windings SU and SL are wound with opposite polarities.

The pulse power supply primary side circuit 10 will be described. The switches SW1 and SW2 are connected in series with the primary winding P so as to apply the voltage of the DC power supply Vs to the primary winding P in a positive direction (upward toward dots in the figure). Further, the diodes Ds1 and Ds2 are connected in series with the primary winding P in a direction in which the current flowing through the primary winding P is circulated. Switches SW1 and SW2
Is a control signal Vg supplied from the drive controller 30.
On / off is driven by 1 at a predetermined cycle.

The drive controller 30 includes a basic clock generator 33, a pulse generating circuit 32, and a drive command generating section 3
Including 1 and. The basic clock generator 33 generates a basic clock signal and supplies the basic clock signal to the pulse generation circuit 32 and the drive command generation unit 31. Pulse generation circuit 3
2 generates a control signal Vg1 using the basic clock signal supplied from the basic clock generator 33, and supplies the control signal Vg1 to the pulse power supply primary side circuit 10. The drive command generation unit 31 includes a drive command inst1 for turning on / off the drive transistor T1, and a drive transistor T2.
Generates drive command inst2 to turn on / off the
Inst1 is output to the drive circuit of the upper arm, and drive command inst2 is output to the drive circuit of the lower arm.

The circuit on the secondary winding SU side of the transformer T constitutes the upper arm. The upper arm has an N-type MO so that the polarities of the built-in body diodes are opposite to each other.
S transistors M21U and M22U are connected in series. The body diode D21U is built in the N-type MOS transistor M21U. Body diode D
22U is built in the N-type MOS transistor M22U. The N-type MOS transistor M23U is connected between the base terminal and the emitter terminal of the driving transistor T1. The body diode D23U is built in the N-type MOS transistor M23U, and its anode terminal is connected to the emitter terminal of the driving transistor T1 and its cathode terminal is connected to the base terminal of the driving transistor T1.

The pulse period sense circuit 24U includes a resistor R
1U and N-type MOS transistor MSU. The DC voltage VdU is applied to one end of the resistor R1U, and the other end of the resistor R1U is an N-type MOS transistor MS.
It is connected to the non-dot side of the secondary winding SU via U.
The N-type MOS transistor MSU is turned on when the voltage V2U induced in the secondary winding SU is positive, and the induced voltage V2
Turned off when U is negative. As a result, the pulse cycle sense circuit 24U outputs a detection signal having a polarity opposite to that of the induced voltage V2U in synchronization with the induced voltage V2U of the secondary winding SU.
That is, the L level detection signal is output when the induced voltage V2U is positive, and the H level detection signal is output when the induced voltage is negative.

The waveform generation circuit 25U shapes (noise removal) the waveform disturbance (noise) of the detection signal output from the pulse period sense circuit 24U and outputs the detection signal PTU after noise removal to the timing control circuit 26U. . The timing control circuit 26U synchronizes with the change timing of the detection signal PTU according to the output level (H level = ON command, L level = OFF command) of the drive command inst1 and outputs the N-type M signal.
The control signals for the OS transistors M21U, M22U and M23U are changed.

When the drive circuit of the upper arm turns on the drive transistor T1, the drive current is supplied from the left side to the right side of the inductive load L (opposite direction to FIG. 1) through the drive transistor T1.

The circuit on the secondary winding SL side of the transformer T constitutes the lower arm. The lower arm has an N-type MO so that the polarities of the built-in body diodes are opposite to each other.
S transistors M21L and M22L are connected in series. The body diode D21L is built in the N-type MOS transistor M21L. Body diode D
22L is built in the N-type MOS transistor M22L. The N-type MOS transistor M23L is connected between the base terminal and the emitter terminal of the driving transistor T2. The body diode D23L is built in the N-type MOS transistor M23L, and its anode terminal is connected to the emitter terminal of the driving transistor T2 and its cathode terminal is connected to the base terminal of the driving transistor T2.

The pulse period sense circuit 24L includes a resistor R
1L and N-type MOS transistor MSL. The DC voltage VdL is applied to one end of the resistor R1L, and the other end of the resistor R1L is an N-type MOS transistor MS.
It is connected to the dot side of the secondary winding SL via L. N
The type MOS transistor MSL is turned on when the voltage V2L induced in the secondary winding SL is positive, and the induced voltage V2L is generated.
Is turned off when is negative. As a result, the pulse cycle sense circuit 24L outputs the detection signal PTL having the opposite polarity to the induced voltage V2L in synchronization with the induced voltage V2L of the secondary winding SL. That is, the L level detection signal is output when the induced voltage V2L is positive, and the H level detection signal is output when the induced voltage is negative.

The timing control circuit 26L uses the drive command in
According to the output level of st2 (H level = ON command, L level = OFF command), the control signals for the N-type MOS transistors M21L, M22L and M23L are changed in synchronization with the change timing of the detection signal PTL.

When the drive circuit of the lower arm turns on the driving transistor T2, the inductive load L is moved from right to left (direction shown by in FIG. 1) via the driving transistor T2.
The drive current is supplied to.

The operation timing of the above half bridge drive circuit will be described. FIG. 2 is a timing chart for explaining the operation timing of each part of the drive circuit shown in FIG. In FIG. 2, a drive command inst1, a control signal Vg1 input to the pulse power supply primary side circuit 10, and a secondary winding S
The voltage V2U induced in U, the detection signal PTU waveform-shaped by the waveform shaping circuit 25U, and the control signal Vg2 applied to the gate terminal of the N-type MOS transistor M22U.
2U, a control signal Vg21U applied to the gate terminal of the N-type MOS transistor M21U, and a control signal Vg23 applied to the gate terminal of the N-type MOS transistor M23U.
U and the waveform of the current I2U supplied to the base terminal of the driving transistor T1 are shown as the signal waveform on the upper arm side, respectively.

Further, in FIG. 2, the drive command inst2, the voltage V2L induced in the secondary winding SL, the detection signal PTL detected by the pulse period sense circuit 24L, and the N-type MO.
Control signal Vg22L applied to the gate terminal of the S transistor M22L, control signal Vg21L applied to the gate terminal of the N-type MOS transistor M21L, N-type MOS
The waveforms of the control signal Vg23L applied to the gate terminal of the transistor M23L, the current I2L supplied to the base terminal of the driving transistor T2, and the current IeL flowing to the emitter terminal of the driving transistor T2 are respectively the signal waveforms on the lower arm side. It is shown.

The control signal Vg1 is repeatedly turned on / off in a predetermined cycle as described above. Control signal Vg1 is H
When the level is reached, the switches SW1 and SW2 are turned on. The current flowing through the primary winding P of the transformer T increases, the voltage V2U induced in the secondary winding SU has a positive direction, and the voltage V2L induced in the secondary winding SL has a negative direction. . On the other hand, when the control signal Vg1 becomes L level, the switches SW1 and SW2 are turned off. At this time, the current flowing through the primary winding P of the transformer T is circulated through the diodes Ds1 and Ds2 and reduced.
The voltage V2U induced in the secondary winding SU has a negative direction, and the voltage V2L induced in the secondary winding SL has a positive direction.

At the starting point (left end) of the timing chart of FIG. 2, the driving transistor T1 is turned on in the reverse direction. That is, the driving transistor T
This is the case where the driving transistor T2 is turned on with 1 being turned off, and the driving transistor T2 is turned off after the current in the direction shown by in FIG. When the driving transistor T2 is turned off, a back electromotive force is generated from the inductive load L, and the back electromotive force raises the potential at the VM point in the figure. When the potential at the VM point becomes higher than the potential of the base terminal of the driving transistor T1 + the forward on-voltage of the body diode D23U, the diode D23U is forward biased. The current flowing through the body diode D23U injects carriers into the base terminal of the driving transistor T1 to drive the driving transistor T1.
Turn on in the opposite direction. As a result, the circulating current due to the counter electromotive force flows in the direction shown by in FIG. In this state, the timing chart of FIG. 2 starts.

When the drive command inst1 of FIG. 2 is set to the H level (ON command), the timing control circuit 26U outputs an ON signal to the drive transistor T1 in synchronization with the rising pulse of the induced voltage V2U (timing t).
1). The timing control circuit 26 sets the control signal Vg22U to the H level and sets the control signals Vg23U and Vg21U to the L level.
When set to the level, the N-type MOS transistor M22U is turned on and the N-type MOS transistors M23U and M21U are turned off. The circuit on the side of the secondary winding SU has a body diode D21 of the N-type MOS transistor M21U.
The current half-wave rectified by U is the N-type MOS transistor M
It flows into the base terminal of the driving transistor T1 via 22U. As a result, carriers are injected into the driving transistor T1. In this case, the driving transistor T1
Remains turned on in the opposite direction. Note that the current I2U having an upward pulse-like waveform that flows after timing t1 in FIG. 2 injects carriers into the base terminal of the driving transistor T1.

A parasitic inductance exists in the circuit on the side of the secondary winding SU. For this reason, the current I2U flowing through the base terminal of the driving transistor T1 gradually increases, and its waveform becomes a pulse-like waveform having an upward slope. Since the pulse period of the control signal Vg1 by the pulse generation circuit 32 is made sufficiently smaller than the lifetime of carriers in the driving transistor T1, the current I2U
Even with a pulsed drive current, sufficient carriers can be injected to turn on the transistor T1. Two
The same applies to the side of the next winding SL.

When the drive command inst1 is set to L level (OFF command), the timing control circuit 26U outputs an OFF signal at the timing t2. Timing control circuit 26
U sets the control signal Vg22U to the L level, and the control signal Vg2
When 3U and Vg21U are set to H level, N-type MOS
The transistor M22U turns off, and the N-type MOS transistors M23U and M21U turn on. Control signal Vg21
U is output in pulses at a timing synchronized with the waveform-shaped detection signal PTU.

The circuit on the side of the secondary winding SU has an N-type MOS.
The current half-wave rectified by the body diode D22L of the transistor M22U becomes the N-type MOS transistor M21U.
Through the secondary winding SU to the dot side. In FIG. 2, the downward pulsed current I2U flowing from timing t2 to timing t3 draws out carriers from the base terminal of the driving transistor T1. However, since the current flowing from the inductive load L via the turned-on N-type MOS transistor M23U continues to inject carriers into the base terminal of the driving transistor T1, the carriers in the driving transistor T1 do not decrease.

When the drive command inst2 is set to the H level (ON command) after a lapse of a predetermined time from the timing t2, the timing control circuit 26L outputs an ON signal to the driving transistor T2 in synchronization with the rising pulse of the induced voltage V2L. (Timing t4). The above-mentioned predetermined time is provided so as to output the off signal to both the driving transistors T1 and T2 from the timing t2 to the timing t4. When the timing control circuit 26L sets the control signal Vg22L to H level and the control signals Vg23L and Vg21L to L level, the N-type MOS transistor M22L is turned on and the N-type MOS transistor M23L.
And M21L turns off. In the circuit on the side of the secondary winding SL, a current half-wave rectified by the body diode D21L of the N-type MOS transistor M21L flows into the base terminal of the driving transistor T2 via the N-type MOS transistor M22L. As a result, the driving transistor T
Carrier 2 is injected with carriers and turned on, and a current flows in the direction shown in FIG. In FIG. 2, timing t
The upward pulsed current I2L flowing after 4 injects carriers into the base terminal of the driving transistor T2.

Immediately after the timing t4, the N-type MO is generated by the pulse-shaped signal of the control signal Vg21U shown in the portion B of FIG.
Since the S transistor M21U is turned on, the carriers inside the driving transistor T1 start to decrease. As a result, the driving transistor T1 is quickly turned off. In FIG. 2, the downward pulsed current I2U flowing immediately after the timing t4 is a current for extracting the carrier.

A supplementary description will be given immediately after the timing t4. When the driving transistor T2 is turned on while the driving transistor T1 is turned on in the reverse direction, the driving transistor T1 enters the reverse recovery operation, and the carriers accumulated in the driving transistor T1 stay as they are. .
If this is left unattended, the driving transistor T1 is turned off, but a current flows in the collector-emitter direction, that is, in the forward direction, and a large through-current may flow through the driving transistor T1 and the driving transistor T2. is there. However, when the current flowing through the inductive load L changes from the above direction to the above direction, the carriers in the driving transistor T1 are rapidly extracted, so that the forward current is prevented from flowing in the driving transistor T1. In the waveform of the current IeL in FIG. 2, it is shown that the waveform of the C portion is suppressed to be small and the through current is prevented.

The operation of the waveform shaping circuit 25U will be described in detail. When the driving transistor T2 is turned on at the timing t4, the potential at the VM point in FIG. 1 sharply drops. Specifically, it changes from near the potential due to the applied voltage of the DC power supply VP to near the ground potential. As a result, the voltage waveform of the induced voltage V2U is disturbed as shown by the portion A in FIG. The disturbance of the voltage waveform is also superimposed on the detection signal waveform output from the pulse period sense circuit 24U. The waveform shaping circuit 25U shapes such disturbance of the detection signal waveform.

FIG. 3 is a diagram showing a configuration example of the waveform shaping circuit 25U according to the first embodiment. FIG. 4 is a diagram showing signal waveforms of respective parts in the circuit from the input point A to the output point H of the circuit according to FIG. In FIG. 3, a detection signal is input to the input point A from the pulse period sense circuit 24U. The signal waveform SigA in FIG. 4 has the above-described waveform disturbance X. The NAND gate NAND1 in FIG. 3 receives the signal A represented by the waveform SigA and the signal C after passing the signal A through the resistor R1 and the inverter INV1.
The waveform SigB and the waveform SigC in FIG. 4 are signal waveforms of a point B before being input to the inverter INV1 and a point C after being output from the INV1, respectively. Waveform SigB
The waveform SigA rises (timing t10)
Then, the resistor R1 gradually rises with a time constant. When the waveform SigB exceeds the threshold voltage Vth1 of the inverter INV1 (timing t11), the waveform SigC changes from the H level to the L level. In FIG. 4, the propagation delay time of each gate is set to zero, and only the delay caused by the time constant of the resistor is shown.

As shown by the waveform SigD, the signal D output from the NAND gate NAND1 is output at the timing t1.
From 0 to the timing t11, it becomes L level, and the others become H level. The signal D and the signal F after passing the signal D through the resistor R2 and the inverter INV2 are input to the AND gate AND1. The waveform SigE and the waveform SigF in FIG. 4 are signal waveforms of a point E before being input to the inverter INV2 and a point F after being output from the INV2, respectively. The waveform SigE gradually rises with the time constant of the resistor R2 when the waveform SigD rises (timing t11). Waveform SigE is inverter INV
2 threshold voltage Vth2 is exceeded (timing t12)
Then, the waveform SigF changes from the H level to the L level.
As a result, the signal G output from the AND gate AND1 becomes the H level from the timing t11 to the timing t12, and the other becomes the L level, as shown by the waveform SigG. By providing the diode D1 between the points DE, connecting the anode terminal of the diode D1 to the point E, and connecting the cathode terminal of the diode D1 to the point D,
No delay occurs when the waveform SigE falls.

The signal G and the signal A are input to the OR gate OR1. The output point H of the OR gate OR1 has a timing t10 as shown by the waveform SigH.
To the L level, and after the timing t10, the H level.
As a result, the signal waveform SigH is obtained by removing the waveform disturbance X from the signal waveform SigA. The signal H is input to the timing control circuit 26U as the detection signal PTU after waveform shaping.

As described above, the waveform shaping circuit 25U has a component whose frequency is higher than the switching frequency of the induced voltage V2U (the signal waveform changes from the H level to the L level or from the L level to the H level at a time interval shorter than the switching cycle). Component), that is, waveform distortion is removed. The switching frequency is the frequency of the control signal Vg1.

If the waveform shaping circuit 25U is omitted, the detection signal having the waveform disturbance X is input to the timing control circuit 26U. In this case, the pulse-like signal of the control signal Vg21U shown in part B of FIG. 2 may disappear due to the influence of the waveform disturbance X. Control signal Vg21U
When the pulse signal of is lost, the N-type MOS transistor M2
Since 1U is not turned on, the carrier is not extracted from the driving transistor T1 after the timing t4. As a result, the driving transistor T2 is turned on while carriers are retained in the driving transistor T1, and an excessive current flows through the driving transistors T1 and T2 of the upper and lower arms. In this way, the waveform shaping circuit 25U suppresses the through current immediately after the driving transistor T2 is turned on by removing the waveform disturbance X superimposed on the detection signal by the pulse period sense circuit 24U (C portion).

The first embodiment described above will be summarized. (1) Driving transistor T forming a half bridge
1 and the driving transistor T2 are pulse-driven by using the pulse power supply transformer T. Driving transistor T1
When (T2) is turned on, a positive direction pulse current flowing out from the dot side (anti-dot side of SL) of the secondary winding SU of the transformer T is used to generate the transistor T1 (T
2) Inject carrier into the inside. Transistor T1 (T
2) is turned off, the carriers accumulated in the transistor T1 (T2) are removed by using the pulse current in the negative direction that flows into the dot side (anti-dot side of SL) of the secondary winding SU of the transformer T. Pull out. Secondary winding SU
To output a positive pulse current from (SL), N-type M
OS switch M22U (M22L) turned on, N-type MOS
The switch M21U (M21L) is turned off, and half-wave rectification is performed by the body diode D21U (D21L). To output a negative pulse current from the secondary winding SU (SL), N
Type MOS switch M21U (M21L) is turned on, N type M
The OS switch M22U (M22L) is turned off, and half-wave rectification is performed by the body diode D22U (D22L). The circuits on the secondary winding SU (SL) side of the upper and lower arms can output pulse currents in both positive and negative directions in a time-sharing manner, so that there is an effect of downsizing of the circuit and cost reduction. (2) When the driving transistor T2 of the lower arm is turned on, it is stored in the driving transistor T1 of the upper arm by using the current flowing in the dot side of the secondary winding SU of the pulse power transformer T. Pull out the carrier. Before the driving transistor T2 is turned on, the driving transistor T1 is turned on in the reverse direction, and when carriers are retained in the driving transistor T1 at the time of reverse recovery of the driving transistor T1, the accumulated carriers are transferred to the base terminal of the transistor T1. It is possible to shorten the time during which the driving transistor T1 is in the state where the current flows in the forward direction even when the driving transistor T1 is off. As a result, a through current flowing from the driving transistor T1 to the driving transistor T2 can be suppressed. (3) The current flowing in the dot side of the secondary winding SU of the pulse power supply transformer T is at the timing when the induced voltage V2U of the secondary winding SU becomes negative (= the detection signal of the pulse cycle sense circuit 24U is at the H level). The control signal Vg21U is set to the H level at the timing (1), and the N-type MOS transistor M21U is turned on to flow. At this time, since the detection signal of the pulse period sense circuit 24U is passed through the waveform shaping circuit 25U, the waveform disturbance generated in the induced voltage V2U when the driving transistor T2 is turned on (A in FIG. 2).
Even if the noise (X in FIG. 4) caused by the portion is superimposed on the detection signal of the pulse period sense circuit 24U, this noise X is removed by the waveform shaping circuit 25U. As a result, the control signal Vg21U is surely set to the H level in the portion B of FIG. 2, so that the driving transistor T1 can be quickly turned off. As a result, the through current flowing from the driving transistor T1 to the driving transistor T2 can be prevented. Can be suppressed.

The above-mentioned disturbance of the voltage waveform occurs when the driving transistor T2 is turned on after the induced voltage V2L for turning on the driving transistor T2 becomes H level. That is, the noise X (FIG. 4) superimposed on the detection signal of the pulse cycle sense circuit 24 is delayed and superimposed after the detection signal changes from the L level to the H level (timing t10). Therefore, the resistors R1 and R2 of FIG.
The resistance value of the
11 and the timing t12.

(Second Embodiment) Waveform shaping circuit 25U
May be configured by a PLL (Phase Locked Loop) circuit.
FIG. 5 is a diagram showing a configuration example of the waveform shaping circuit 25U according to the second embodiment. FIG. 6 shows the signal waveforms at the input point A2 and the output point B2 of the circuit according to FIG. In FIG. 5, the pulse period sense circuit 24U is provided at the input point A2.
A detection signal is input from (FIG. 1). This input signal includes the above-mentioned waveform disturbance X, as shown by the signal waveform SigA2 in FIG. In the phase comparator 51 of FIG. 5, the signal A2 shown by the waveform SigA2 and the PLL
The output signal B2 of the circuit is input respectively.

The phase comparator 51 compares the phases of the frequency of the signal A2 (reference frequency) and the frequency of the signal B2 (reference frequency) and outputs a signal corresponding to the phase difference. The loop filter 52 filters a low frequency component of the signal corresponding to the phase difference to filter a VCO (Voltage Control Oscillator).
lator) 53. The VCO 53 generates and outputs a pulse signal having a frequency according to the voltage of the input signal. With such a PLL circuit, feedback control is performed so that the frequencies of the signal A2 and the signal B2 are the same, and noise having a frequency component higher than the switching frequency of the induced voltage V2U (FIG. 2) is removed.

As described above, even if the waveform shaping circuit 25U is configured by the PLL circuit according to the second embodiment, the induced voltage V is generated when the driving transistor T2 is turned on.
It is possible to remove noise (X in FIG. 6) caused by waveform distortion (A portion in FIG. 2) that occurs in 2U. As a result, the driving transistor T1 can be quickly turned off, so that a through current flowing from the driving transistor T1 to the driving transistor T2 can be suppressed.

(Third Embodiment) Waveform shaping circuit 25U
May be composed of an RC filter circuit. FIG. 7 is a diagram showing a configuration example of the waveform shaping circuit 25U according to the third embodiment. In FIG. 7, the pulse cycle sense circuit 24U
The detection signal according to (FIG. 1) is input from the input point A3 of the circuit to one end of the resistor R71. This input signal contains the above-mentioned waveform disturbance X. The other end of the resistor R71 and FIG.
The capacitor C72 is connected to the VM point.
With such an RC filter circuit, the induced voltage V2U
Noise having a frequency component higher than the switching frequency of (FIG. 2) is removed, and a signal having the same frequency as the switching frequency of the induced voltage V2U is output from the output point B3.

Since the waveform shaping circuit 25U shown in FIG. 7 causes a propagation delay due to the time constant of the filter circuit, the induced voltage V
When the switching frequency of 2U (FIG. 2) is high and the effect of the propagation delay cannot be ignored, the waveform shaping circuit 2 according to the first and second embodiments described above is used.
It is recommended to use 5U.

(Fourth Embodiment) Waveform shaping circuit 25U
May be applied to another drive circuit. FIG. 8 is a diagram showing a drive circuit for a current control type element according to a fourth embodiment of the present invention. The difference from FIG. 1 is that a drive controller 30B is provided instead of the drive controller 30 and that the N-type MOS transistor M22 is provided in the drive circuit of the upper arm.
The point where the collector catcher 28U is provided at the gate terminal of U, and the collector catcher 28L is provided at the gate terminal of the N-type MOS transistor M22L in the drive circuit of the lower arm.
That is the point. Therefore, the description of the circuit common to FIG. 1 is omitted, and the points different from FIG. 1 will be described.

The drive controller 30B includes a basic clock generator 33, a variable pulse generation circuit 32B, and a drive command generator 31B. The basic clock generator 33 generates a basic clock signal and supplies the basic clock signal to the drive command generation unit 31B and the variable pulse generation circuit 32B. The drive command generation unit 31B uses the drive transistor T1.
Generates a drive command inst1 for turning on / off and a drive command inst2 for turning on / off the driving transistor T2, and outputs the drive command inst1 to the drive circuit of the upper arm and the drive command inst2 to the drive circuit of the lower arm, respectively. To do.
The drive command generator 31B further includes a drive transistor T
Switching command 1 at the timing of turning on 1 and switching command 2 at the timing of turning on the driving transistor T2
Are output respectively. The variable pulse generation circuit 32B generates the control signal Vg1B using the basic clock signal supplied from the basic clock generator 33 and the logical sum signal of the switching instruction 1 and the switching instruction 2, and the pulse power supply primary side circuit 10 To the control signal Vg1B.

The collector catcher 28U has a resistor RC.
It is composed of U and a diode DCU. The collector catcher 28U works as follows. When the collector voltage of the driving transistor T1 becomes higher than a predetermined value, the diode DCU is forward biased and the potential of the gate terminal of the N-type MOS transistor M22L becomes higher than the signal level of the control signal Vg22U output from the timing control circuit 26U. As a result, the on-resistance of the N-type MOS transistor M22L decreases, and the current I2U supplied to the base terminal of the driving transistor T1 increases, so that the carriers in the driving transistor T1 increase and the collector voltage decreases.

On the other hand, when the collector voltage of the driving transistor T1 becomes lower than the above predetermined value, the diode DCU is no longer forward biased, and the N-type MOS transistor M2.
The potential of the 2L gate terminal becomes the signal level of the control signal Vg22U output from the control circuit 26U. As a result, the on-resistance of the N-type MOS transistor M22L increases, the current I2U supplied to the base terminal of the driving transistor T1 decreases, the carriers in the driving transistor T1 decrease, and the collector voltage rises. in this way,
The collector catcher 28U keeps the number of carriers in the driving transistor T1 in an optimum state, and
Shorten the turn-on and turn-off times for 1.

Similarly, the collector catcher 28L constituted by the resistor RCL and the diode DCL is
The number of carriers in the driving transistor T2 is kept in an optimum state, and the time required for turning on and turning off the transistor T2 is shortened.

FIG. 9 is a timing chart for explaining the operation timing of each part of the drive circuit shown in FIG. Figure 2
The switching command 1 and the switching command 2 are added as compared with the timing chart of FIG. Also, as in the case of FIG.
At the start point (left end) of the timing chart, it is assumed that the driving transistor T1 is turned on in the reverse direction and current flows in the direction shown in FIG.

When the drive command inst1 of FIG. 9 is set to H level (ON command) and the switching command 1 is set to H level (timing t1), the frequency of the control signal Vg1B output from the variable pulse generation circuit 32B becomes It is set lower than the normal frequency. In the example of FIG. 9, the control signal Vg1B is maintained at the H level while the switching command 1 is at the H level. As a result, the switching frequency of the induced voltage V2U is lowered when the output of the ON signal to the driving transistor T1 is started, so that the time for which the current I2U having the upward pulsed waveform flowing after the timing t1 flows can be lengthened, and The carriers injected into the base terminal of the transistor T1 increase.

The timing control circuit 26U outputs an ON signal to the driving transistor T1 in synchronization with the rising pulse of the induced voltage V2U at the timing t1. As in the case of FIG. 2, the driving transistor T1 remains on in the reverse direction while the driving command inst1 is at the H level (ON command). The driving transistor T
Control signal Vg22U at the start of output of the ON signal for 1
The high H level is due to the collector catcher 2 described above.
It depends on the work of 8U.

When the drive command inst1 is set to L level (OFF command), the timing control circuit 26U outputs an OFF signal at the timing t2. The downward pulsed current I2U flowing from the timing t2 to the timing t3 is
The carrier is extracted from the base terminal of the driving transistor T1. However, the base terminal of the driving transistor T1 is connected to the N-type MOS transistor M which is turned on.
Since the current flowing from the inductive load L via 23U continues to inject carriers, the carriers in the driving transistor T1 do not decrease.

When the drive command inst2 is set to the H level (ON command) and the switching command 2 is set to the H level (timing t4) after a lapse of a predetermined time from the timing t2, the control signal Vg1B output from the variable pulse generation circuit 32B. The frequency of is set to be lower than the frequency at the normal time similarly to the timing t1. In the example of FIG. 9, the control signal Vg1B is maintained at the H level while the switching command 2 is at the H level. As a result, the switching frequency of the induced voltage V2L is lowered at the start of the output of the ON signal to the driving transistor T2, so that the time for which the current I2L having the upward pulse-like waveform flowing after timing t4 flows is lengthened (D portion).
Therefore, the number of carriers injected into the base terminal of the driving transistor T2 increases.

The timing control circuit 26L outputs an ON signal to the driving transistor T2 in synchronization with the rising pulse of the induced voltage V2L at the timing t4. The drive transistor T2 is injected with carriers and turned on, and a current flows in the direction shown in FIG. In FIG. 9, the upward pulsed current I2L flowing after timing t4 injects carriers into the base terminal of the driving transistor T2. The driving transistor T2
The H level of the control signal Vg22L is high at the start of the output of the ON signal to the collector catcher 28 described above.
It depends on the work of L.

Immediately after the timing t4, the N-type MO is generated by the pulse signal of the control signal Vg21U shown in the portion B of FIG.
Since the S transistor M21U is turned on, the carriers inside the driving transistor T1 start to decrease. As a result, the driving transistor T1 is quickly turned off. In FIG. 9, the downward pulsed current I2U flowing immediately after the timing t4 is a current for extracting the carrier.

The waveform shaping circuit 25U is shown in FIG.
It is composed of a circuit. Similar to the first embodiment, the noise caused by the waveform disturbance (part A in FIG. 9) generated in the induced voltage V2U when the driving transistor T2 is turned on is superposed on the detection signal of the pulse period sense circuit 24U. Also, the noise X is removed by the waveform shaping circuit 25U. As a result, the control signal Vg21U is surely set to the H level in the portion B of FIG. 9, so that the driving transistor T1 can be turned off promptly, and as a result, the through current flowing from the driving transistor T1 to the driving transistor T2 is reduced. It can be suppressed (part C in FIG. 9).

Even in the drive circuit according to the fourth embodiment described above, the noise caused by the waveform disturbance (A portion in FIG. 9) generated in the induced voltage V2U when the drive transistor T2 is turned on can be removed. Transistor T
Through current flowing from 1 to the driving transistor T2 can be suppressed. Further, since the switching frequency of the pulse power supply at the timing of turning on the driving transistor (for example, section D) is lowered to lengthen the time during which the current for injecting carriers (for example, I2L) flows, a sufficient amount of carriers are injected for driving. The turn-on transistor can be turned on quickly. Furthermore, the controllability of the drive circuit can be improved because the switching frequency is not reduced except at the timing when the drive transistor is turned on. The switching frequency of the pulse power supply is
It is determined in consideration of the inductance parasitic in the circuit on the secondary winding side of the transformer T, the loss generated in the circuit on the secondary winding side, and the like.

(Fifth Embodiment) FIG. 10 is a diagram showing an example in which the waveform shaping circuit 25U is applied to another drive circuit. 8 is different from FIG. 8 in that a drive controller 30C is provided instead of the drive controller 30B, and a pulse power supply primary side circuit 1 is used instead of the pulse power supply primary side circuit 10.
This is the point where 0C is provided. Therefore, the description of the circuits common to FIG. 8 is omitted, and the points different from FIG. 8 are described.

The drive controller 30C includes a basic clock generator 33, a pulse generation circuit 32, and a drive command generator 31C. The basic clock generator 33 generates a basic clock signal and supplies the basic clock signal to the drive command generation unit 31C and the pulse generation circuit 32. The drive command generation unit 31C includes a drive command inst1 for turning on / off the drive transistor T1, and a drive transistor T2.
Generates drive command inst2 to turn on / off the
Inst1 is output to the drive circuit of the upper arm, and drive command inst2 is output to the drive circuit of the lower arm. The drive command generation unit 31C further sends the switching command 1 to the drive transistor T2 at the timing of turning on the drive transistor T1.
The switching command 2 is output at the timing of turning on. The pulse generation circuit 32 includes a basic clock generator 33.
Control signal Vg using the basic clock signal supplied from
1 is generated, and the control signal V is supplied to the pulse power supply primary side circuit 10C.
Supply g1.

The pulse power supply primary side circuit 10C includes a DC power supply VsH for applying a voltage higher than that of the DC power supply Vs and a switch SW3 for switching between the DC power supply Vs and the DC power supply VsH as compared with the pulse power supply primary side circuit 10. Is added.
The switch SW3 is switched by the logical sum signal of the switching command 1 and the switching command 2. Switch SW3
Is on the DC power supply VsH side when the OR signal is at H level,
When the logical sum signal is at L level, it is switched to the DC power supply Vs side. As a result, the voltage V2U induced on the secondary winding SU side of the pulse power supply and the voltage V2L induced on the secondary winding SL side when the switch SW3 is switched to the DC power supply VsH side are Is higher than that when the DC power is switched to the DC power supply Vs side.

FIG. 11 is a timing chart for explaining the operation timing of each part of the drive circuit shown in FIG.
Compared to the timing chart of FIG. 9, the time for which the switching command 1 and the switching command 2 are set to the H level is shortened, and is set to be the same as the normal switching frequency of the pulse power supply. Further, as in the case of FIG. 9, at the start point (left end) of the timing chart, the driving transistor T1 is turned on in the reverse direction and the current flows in the direction shown in FIG.

When the drive command inst1 of FIG. 9 is set to H level (ON command) and the switching command 1 is set to H level (timing t1), the induced voltage V2U becomes high. In the example of FIG. 11, the induced voltage V2U for one pulse is increased. This makes it possible to increase the current I2U having an upward pulse waveform that flows after the timing t1 at the start of output of the ON signal to the driving transistor T1, and increase the carriers injected into the base terminal of the driving transistor T1. To do.

The timing control circuit 26U outputs an ON signal to the driving transistor T1 in synchronization with the rising pulse of the induced voltage V2U at the timing t1. As in the case of FIG. 9, the driving transistor T1 remains turned on in the reverse direction while the driving command inst1 is at the H level (ON command). The driving transistor T
Control signal Vg22U at the start of output of the ON signal for 1
The high H level is due to the collector catcher 2 described above.
It depends on the work of 8U.

When the drive command inst1 is set to L level (OFF command), the timing control circuit 26U outputs an OFF signal at the timing t2. The downward pulsed current I2U flowing from the timing t2 to the timing t3 is
The carrier is extracted from the base terminal of the driving transistor T1. However, the base terminal of the driving transistor T1 is connected to the N-type MOS transistor M which is turned on.
Since the current flowing from the inductive load L via 23U continues to inject carriers, the carriers in the driving transistor T1 do not decrease.

When the drive command inst2 is set to H level (ON command) and the switching command 2 is set to H level (timing t4) after a lapse of a predetermined time from the timing t2, the induced voltage V2L becomes high. In the example of FIG. 11, the induced voltage V2L for one pulse is increased (E section). As a result, at the time of starting the output of the ON signal to the driving transistor T2, the current I2L having the upward pulsed waveform flowing after the timing t4 can be increased (D portion) and is injected into the base terminal of the driving transistor T2. The number of carriers will increase.

The timing control circuit 26L outputs an ON signal to the driving transistor T2 in synchronization with the rising pulse of the induced voltage V2L at the timing t4. The driving transistor T2 is injected with carriers and turned on, and a current flows in the direction shown in FIG.
In FIG. 11, the upward pulsed current I2L flowing after timing t4 injects carriers into the base terminal of the driving transistor T2. It should be noted that the control signal Vg22 is output at the start of output of the ON signal to the driving transistor T2.
The high H level of L is due to the action of the collector catcher 28L described above.

Immediately after the timing t4, the N-type M is generated by the pulse-like signal of the control signal Vg21U shown in the portion B of FIG.
Since the OS transistor M21U is turned on, the carriers inside the driving transistor T1 start to decrease. As a result, the driving transistor T1 is quickly turned off. In FIG. 11, the downward pulsed current I2U flowing immediately after the timing t4 is a current for extracting the carrier.

The waveform shaping circuit 25U is composed of any of the circuits shown in FIGS. 3, 5 and 7. Similar to the first and fourth embodiments, noise caused by the waveform disturbance (part A in FIG. 11) occurring in the induced voltage V2U when the driving transistor T2 is turned on is detected by the pulse period sense circuit 24U. Even if superposed, this noise X
Are removed by the waveform shaping circuit 25U. As a result, the control signal Vg21U is surely set to the H level in the portion B of FIG. 11, so that the driving transistor T1 can be turned off promptly, and as a result, the through current flowing from the driving transistor T1 to the driving transistor T2 is reduced. It can be suppressed (C part in FIG. 11).

Even in the drive circuit according to the fifth embodiment described above, the noise caused by the waveform disturbance (section A in FIG. 11) generated in the induced voltage V2U when the drive transistor T2 is turned on can be removed. It is possible to suppress the through current flowing from the driving transistor T1 to the driving transistor T2. Further, since the induced voltage by the pulse power supply at the timing of turning on the driving transistor (for example, E portion) is increased to increase the current for injecting carriers (for example, I2L) (for example, D portion),
Sufficient carriers can be injected to quickly turn on the driving transistor. Further, since the current for injecting carriers is not increased except when the driving transistor is turned on, the loss generated in the driving circuit can be suppressed.

In the above description, the operation of pulling out the carriers accumulated in the driving transistor T1 of the upper arm when turning on / off the driving transistor T2 of the lower arm has been mainly described. The same applies to the operation of extracting the carrier accumulated in the driving transistor T2 of the lower arm when turning on / off the driving transistor T1.

In the above-mentioned example, the waveform forming circuit 25U is provided in the circuit forming the upper arm, but the waveform forming circuit may be provided in the circuit forming the lower arm.

The driving circuit according to the present invention is not used only for general bipolar transistors, but can be applied to various semiconductor devices. In particular, the driving according to the present invention is effective for a semiconductor element in which the transistor operates quickly and the current changes largely with time.

Correspondence between each component in the claims and each component in the embodiment of the invention will be described. The first direction corresponds to, for example, the opposite direction to. The second direction corresponds to, for example, the direction of.
The driving transistor T1 corresponds to the first current control transistor. The driving transistor T2 corresponds to the second current control type transistor. The pulse current generating means includes, for example, the pulse power supply primary side circuit 10 and the transformer T. The first switch means is composed of, for example, a body diode D21U and an N-type MOS transistor M22U. The second switch means is, for example, the body diodes D22U and N.
Type MOS transistor M21U.

The first timing detecting means is, for example,
It is composed of a pulse period sense circuit 24U. First
The timing control circuit of is composed of, for example, the timing control circuit 26U. The third switch means is
For example, body diode D21L and N-type MOS
It is composed of a transistor M22L. The fourth switch means is composed of, for example, a body diode D22L and an N-type MOS transistor M21L. The second timing detection means is composed of, for example, a pulse cycle sense circuit 24L. The second timing control circuit is, for example, the timing control circuit 26L.
Composed by. The waveform shaping means is composed of, for example, a waveform shaping circuit 25U. The predetermined period corresponds to the switching cycle, for example. The low pass filter circuit is composed of, for example, an RC filter circuit. Note that each component is not limited to the above configuration as long as the characteristic function of the present invention is not impaired.

[Brief description of drawings]

FIG. 1 is a diagram showing a drive circuit of a current control type element according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation timing of each part of the drive circuit in FIG.

FIG. 3 is a diagram showing a configuration example of a waveform shaping circuit according to the first embodiment.

FIG. 4 is a diagram showing signal waveforms of respective parts in the circuit of FIG.

FIG. 5 is a diagram showing a configuration example of a waveform shaping circuit according to a second embodiment.

6 is a diagram showing signal waveforms in the circuit of FIG.

FIG. 7 is a diagram showing a configuration example of a waveform shaping circuit according to a third embodiment.

FIG. 8 is a diagram showing a drive circuit for a current control type element according to a fourth embodiment of the present invention.

9 is a diagram illustrating operation timing of each unit of the drive circuit in FIG.

FIG. 10 is a diagram showing a drive circuit of a current control type element according to a fifth embodiment of the present invention.

FIG. 11 is a diagram illustrating operation timing of each part of the drive circuit in FIG.

FIG. 12 is a diagram showing a drive circuit of a current control element according to a conventional technique.

[Explanation of symbols]

10, 10C ... Pulse power supply primary circuit, 24U, 24L ...
Pulse cycle sense circuit, 25U, waveform shaping circuit,
26U, 26L ... Timing control circuit, 27U,
27L ... Photo coupler, 28U, 28L ... Collector catcher, 30, 30B, 30C ... Drive controller, L ... Inductive load, M21U-M23U, M21L-
M23L ... N-type MOS transistor, T ... Transformer,
T1, T2 ... Driving transistor, Vs, VP, VsH ... DC power supply

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5H740 AA04 BA11 BB05 BC01 BC02                       JA01 JB01 KK03 KK04 KK08                       LL05                 5J055 AX27 AX55 AX64 BX16 CX13                       CX20 DX04 DX56 DX72 DX83                       EX06 EX07 EY01 EY12 EY17                       EY21 EZ00 EZ07 EZ25 EZ63                       FX12 FX17 FX36 GX01

Claims (6)

[Claims] 1. A first arm located on the upper arm side with respect to an inductive load to supply a drive current in a first direction, and to flow a current due to a back electromotive force generated from the inductive load in a reverse direction.
Of the current control type transistor and the first current control type transistor are connected in series, and a driving current is located in a lower arm side with respect to the inductive load and is driven in a second direction different from the first direction. A current-controlled element drive circuit that supplies a second current-controlled transistor that supplies a current due to a back electromotive force generated from the inductive load in the opposite direction, and supplies a positive pulsed current and a negative pulse Current generating means for alternately generating a pulse-shaped current, and the positive current is inserted between the pulse current generating means and the first current control type transistor, and the positive terminal is connected to the control terminal of the first current control type transistor. A first switch means for supplying a pulsed current; and a first current control transistor interposed between the pulse current generating means and the first current control transistor. Second switch means for supplying the negative pulsed current to the control terminal of the transistor, and detection timing of the pulsed current generated in the first current control type transistor by the pulse current generation means, and detected. A first timing detecting means for outputting a signal, and (1) when turning on the first current control type transistor, the positive voltage is sent to the first switch means in response to a detection signal from the first timing detecting means. (2) When the first current control type transistor is turned off, the negative pulse is supplied to the second switch means in response to the detection signal from the first timing detection means. A first timing control circuit for instructing the supply of a constant current, and the second current control type transistor interposed between the pulse current generating means and the second current control type transistor. The third switch means for supplying the positive pulsed current to the control terminal of the current control type transistor, and the second current control type transistor interposed between the pulse current generating means and the second current control type transistor, Fourth switch means for supplying the negative pulsed current to the control terminal of the current control type transistor, and detecting the generation timing of the pulsed current generated in the second current control type transistor by the pulse current generation means. And a second timing detection means for outputting a detection signal, and (1) when the second current control type transistor is turned on, the third switch means according to the detection signal by the second timing detection means. To supply the positive pulsed current to (2) when the second current control type transistor is turned off, by the second timing detection means A second timing control circuit for instructing the fourth switch means to supply the negative pulsed current in accordance with an output signal; a detection signal by the first timing detection means; and a second timing detection means A waveform control means for removing at least the noise of the detection signal by the first timing detection means of the detection signal by the current control element drive circuit. 2. The current control element drive circuit according to claim 1, wherein the noise is caused by the third switch means supplying the positive pulsed current to a control terminal of a second current control transistor. A drive circuit for a current control type element, which is generated when the operation is started. 3. The current control element drive circuit according to claim 1 or 2, wherein the noise is generated when the first current control transistor causes a current due to the back electromotive force to flow in a reverse direction. A drive circuit for a current control type element characterized by the above. 4. The current control element drive circuit according to claim 1, wherein the waveform shaping means changes the signal level of an input signal by (1) a previous signal level. Outputs the detected signal level after the change when a predetermined time has passed from the change, and (2) continues to output the signal level before the change when the predetermined time has not passed from the previous signal level change. A drive circuit for a current control type element, which is characterized by: 5. The current control element drive circuit according to claim 1, wherein the waveform shaping means has a PLL circuit, and an input signal is a reference frequency signal of the PLL circuit. A current control element drive circuit, wherein the output signal is a comparison frequency signal of the PLL circuit. 6. The current control type element drive circuit according to claim 1, wherein the waveform shaping means is constituted by a low pass filter circuit. Drive circuit.