JP2003337844A - Method for delay adjustment and method for delay value calculation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the design period of a semiconductor integrated circuit by reducing layout man-hours required for one more delay adjustment by preventing the fluctuation of the delay adjustment under each semiconductor process condition. <P>SOLUTION: In this method for delay adjustment, a delay value and skew prior to delay adjustment are calculated under each of the plurality of process conditions of a semiconductor integrated circuit on the basis of layout information ( a step ST1). When no circuit operation can be guaranteed with the delay value prior to delay adjustment under the predetermined process condition, a predicted delay value and predicted skew under the predetermined process condition are calculated on the basis of the delay value and skew prior to the delay adjustment under a standard process condition (a step ST3). Then, when the circuit operation can be guaranteed with the predicted delay value under the predetermined process condition, the delay generated in the path is adjusted by using the delay adjusting cell (a step ST6). <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay adjusting method and a delay value calculating method in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, delay adjustment using a delay adjustment cell has been performed with the increase in scale of semiconductor integrated circuits and the increase in complexity of processes. That is, when the circuit operation is not guaranteed due to the delay time (delay value) generated in the path in the semiconductor integrated circuit, the delay adjustment cell reflects the adjustment of the delay value in the layout based on the delay value.

[0003]

However, since the delay adjustment is made individually for each semiconductor process condition, the delay adjustment varies depending on the process condition, and the circuit operation is guaranteed even after being reflected in the layout. Instead, delay adjustment may be necessary again. In this case, the layout arrangement / wiring is corrected, the delay value is calculated again from the corrected layout information, and the delay adjustment is performed again using the delay adjustment cell. As described above, the number of layout man-hours for adjusting the delay is increased, and the design period of the semiconductor integrated circuit is increased.

Therefore, an object of the present invention is to prevent variations in delay adjustment for each process condition, reduce the number of layout steps for delay adjustment, and shorten the design period of a semiconductor integrated circuit. Is provided.

[0005]

In view of the above-mentioned problems, the means taken by the invention according to claim 1 of the present invention is a delay adjusting method for adjusting a delay occurring in a path in a semiconductor integrated circuit by using a delay adjusting cell. A first step of obtaining a delay value and a skew before delay adjustment for each of a plurality of process conditions of the semiconductor integrated circuit based on the layout information, and the first step under a predetermined process condition. In the case where the circuit operation cannot be guaranteed according to the delay value or the skew before the delay adjustment obtained in, the delay value and the skew before the delay adjustment under the reference process condition are used, and When the delay generated in the path is adjusted so that the skew becomes small, the predicted delay value and the predicted skew under the predetermined process condition are obtained. The second step and the predicted delay value or predicted skew under the predetermined process condition obtained in the second step can be used to guarantee the circuit operation by using the delay adjustment cell. And a third step of adjusting by.

According to the first aspect of the invention, the delay value and the skew before delay adjustment for each of a plurality of process conditions are calculated,
Based on the delay value and skew before delay adjustment under the reference process condition, the predicted delay value and predicted skew under the predetermined process condition are obtained. This prevents variations in delay adjustment for each process condition, reduces the need for delay adjustment again, reduces layout man-hours for delay adjustment, and shortens the design period of the semiconductor integrated circuit.

According to a second aspect of the present invention, in the delay adjusting method according to the first aspect, the semiconductor integrated circuit has a hierarchical structure by a hierarchical design, and the first step is the layout information. The upper layer delay value, which is the delay value of the route necessary for delay adjustment in the upper layer, is read based on the delay values of all the routes in the upper layer read from It is assumed that the lower layer delay value which is a delay value is read, the upper layer delay value and the lower layer delay value are added, and the delay value before the delay adjustment is obtained.

According to the second aspect of the present invention, the delay value of only the path required for delay adjustment is read from the lower layer, so that the delay value calculation period before delay adjustment is shortened. as a result,
The design period of the semiconductor integrated circuit is further shortened.

According to a third aspect of the present invention, in the delay adjusting method according to the first aspect or the second aspect, the path is defined in the second step for each process condition of the semiconductor integrated circuit. In the delay value before the delay adjustment under the predetermined process condition, the gate delay coefficient corresponding to the predetermined process condition is used as the reference process condition by using the gate delay coefficient indicating the degree of the gate delay in It is assumed that the predicted delay value under the predetermined process condition is obtained by adding the value multiplied by the skew before the delay adjustment of.

According to the third aspect of the present invention, since the predicted delay value for each process condition is calculated according to the degree of the gate delay that differs for each process condition, highly accurate adjustment can be performed in the delay adjustment of only the gate delay. to enable.

According to a fourth aspect of the present invention, there is provided a delay value calculation method for obtaining a delay caused in a path in a semiconductor integrated circuit, wherein the delay value is calculated for each of a plurality of process conditions of the semiconductor integrated circuit based on layout information. The delay value and skew before adjustment are obtained.

According to the fourth aspect of the present invention, all the delay values before the delay adjustment of each of the plurality of process conditions are obtained, so that variations in the delay adjustment for each process condition can be reduced.

According to a fifth aspect of the present invention, there is provided a delay value calculating method for obtaining a delay occurring in a path in a semiconductor integrated circuit, wherein the delay value is calculated for each of a plurality of process conditions of the semiconductor integrated circuit based on layout information. A delay value and skew before adjustment are obtained, a reference process condition is designated from a plurality of process conditions of the semiconductor integrated circuit, and based on the delay value and skew before the delay adjustment under the reference process condition. Then, a predicted delay value under a predetermined process condition is obtained when the delay generated in the path is adjusted so that the skew under the reference process condition becomes small.

According to the invention of claim 5, all the delay values before the delay adjustment of each of the plurality of process conditions are obtained, and a predetermined value is obtained based on the delay value before the delay adjustment and the skew under the reference process condition. Find the expected delay value under process conditions. As a result, it is possible to perform delay adjustment without variation for each process condition, and as a result, it becomes possible to reduce the need for delay adjustment again through the layout and shorten the design period of the semiconductor integrated circuit.

The invention according to claim 6 is the delay value calculating method according to claim 4 or 5,
The semiconductor integrated circuit has a hierarchical structure by a hierarchical design, and the delay value before the delay adjustment is based on the delay values of all the routes in the upper layer read from the layout information, The upper layer delay value which is the delay value of the route necessary for delay adjustment is read, the lower layer delay value which is the delay value of the route which is necessary for the delay adjustment in the lower layer is read, and the upper layer delay value and the lower layer delay are read. It shall be obtained by adding the values and.

According to the invention of claim 6, since the delay value of only the path necessary for delay adjustment is read from the lower layer, the delay value calculation period before delay adjustment is shortened. as a result,
The design period of the semiconductor integrated circuit is further shortened.

According to a seventh aspect of the present invention, in the delay value calculating method according to the fifth aspect, the predicted delay value under the predetermined process condition is determined for each process condition of the semiconductor integrated circuit. In the delay value before the delay adjustment under the predetermined process condition, the gate delay coefficient corresponding to the predetermined process condition is used as the reference process condition by using the gate delay coefficient indicating the degree of the gate delay in It is obtained by adding a value multiplied by the skew before the delay adjustment of.

According to the invention of claim 7, the predicted delay value for each process condition is calculated according to the degree of the gate delay different for each process condition. Therefore, in the delay adjustment of only the gate delay, highly accurate adjustment can be performed. to enable.

The invention of claim 8 is the delay value calculating method according to claim 5 or 7,
The predicted skew under the predetermined process condition is further obtained based on the predicted delay value under the predetermined process condition.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart showing a delay adjusting method according to an embodiment of the present invention.

First, each step in FIG. 1 will be briefly described.

Step ST1 is a delay time (hereinafter referred to as "delay value") before delay adjustment which occurs in the path in the semiconductor integrated circuit.
That is) and the step of obtaining the skew.

Step ST2 is a step of determining whether or not the circuit operation is guaranteed.

Step ST3 is a step of obtaining a predicted delay value and a predicted skew after delay adjustment.

Step ST4 is a step of determining whether or not the circuit operation is guaranteed.

Step ST5 is a step of correcting the layout before delay adjustment.

Step ST6 is a step of reflecting the adjustment of the delay value on the layout.

The delay adjusting method according to this embodiment using the above steps will be specifically described. The semiconductor integrated circuit here will be described on the assumption that it has a hierarchical structure by a hierarchical design.

In step ST1, the delay value in the upper layer and the delay value in the lower layer, which are obtained based on the layout information of the semiconductor integrated circuit, are read to obtain the delay value and the skew before delay adjustment for each semiconductor process condition ( It corresponds to the first step and will be described in more detail later). Then, the process proceeds to step ST2 and step ST1.
Based on the skew obtained in step 1, it is determined whether the circuit operation is guaranteed. If the circuit operation cannot be guaranteed (NO in step ST2), the process proceeds to step ST3, and the predicted delay value and predicted value after delay adjustment are calculated based on the delay value and skew before delay adjustment obtained in step ST1. The skew is calculated (corresponding to the second step, which will be described in detail later).

Further, in step ST4, it is determined whether or not the circuit operation is guaranteed, based on the skew obtained in step ST3. If the circuit operation can be guaranteed (YES in step ST4), step S
Proceeding to T6, the delay adjustment cell reflects the adjustment of the delay value in the layout based on the predicted delay value and the predicted skew obtained in step ST3 (corresponding to the third step). On the other hand, when the circuit operation cannot be guaranteed (NO in step ST4), the process proceeds to step ST5, the layout and wiring are corrected in the layout before delay adjustment, and then the process returns to step ST1 to repeat the above process. If the circuit operation can be guaranteed in step ST2, there is no need to adjust the delay, and the process ends.

Next, the steps ST1 and ST3 will be described in more detail with reference to FIGS. FIG. 2 is a flowchart for specifically explaining the process of obtaining the delay value and the skew before the delay adjustment in step ST1. FIG. 3 is a flowchart for specifically explaining the process of obtaining the predicted delay value and the predicted skew after the delay adjustment in step ST3.

FIG. 4 is a diagram to be referred to when the delay value and the skew before the delay adjustment are obtained. The clock source SO is included in each group having a predetermined clock source to be subjected to the delay adjustment in the semiconductor integrated circuit. It is a figure which shows the group A which has. A group A shown in FIG. 4 includes a clock selection circuit K1 and circuits C1 to C4. Further, flip-flops FF1 to FF5 are connected inside the circuits C1 to C4, which are lower layers, as shown in the figure. Note that delay adjustment cells u1 to u6 that perform delay adjustment are arranged as illustrated. In addition, each of the points a to r is used to cite the route described below. A circuit w1 for halving the clock frequency is connected to the input side of the delay adjustment cell u3.

<Delay Value and Skew Before Delay Adjustment> In FIG. 2, first, in step ST11, in the step of opening an initial value setting file in which a predetermined initial value obtained based on the layout information of the semiconductor integrated circuit is stored. is there. That is, a file in which information such as a process condition and a route to be read in the following steps, a delay value under each process condition generated in each route of an upper layer and a lower layer is stored is opened.

Next, in step ST12, as shown in FIG. 4, the delay value for each process condition generated in each path inside the circuits C1 to C4, which is the hard macro unit of the lower hierarchy of the semiconductor integrated circuit, is excluded. , Read the delay value under each process condition that occurs in each route of the upper hierarchy. For example, in the group A shown in FIG. 4, the route abcfl, the route abcek, the route abdj, the route abdgi, and the route a.
Read each delay value of bdgh.

Next, in step ST13, a route required for delay adjustment in the upper layer is read. For example, the route abcfl and the route abcek in the upper layer
Specify and to read.

Next, in step ST14, each input / output pin information of each hard macro unit is read in the upper layer.
For example, the input / output pin information of the circuits C1 to C4 is read in the upper layer.

Next, in step ST15, based on the input / output pin information read in step ST14, the delay value under one process condition inside the lower layer hard macro required for delay adjustment (lower layer delay value) Corresponding to)
Read. Here, for the route lr inside the circuit C1 and the route kq inside the circuit C2, the delay value under the process condition TYP as the standard process condition is read. In this way, only the delay value of the hard macro part necessary for delay adjustment is read, and the internal delay value of the hard macro that is not necessary for delay adjustment is not read, which shortens the calculation period and shortens the design period of the semiconductor integrated circuit. Can contribute.

Next, in step ST16, the delay value before delay adjustment is calculated based on the information read in above. Here, since the routes necessary for delay adjustment are the route abcflr and the route abcekq, for the route abcekq, for example, the route a specified in the upper layer is used.
The delay value under the process condition TYP of bcek (corresponding to the delay value of the upper layer) and the route kq in the circuit C2 of the lower layer
By adding the delay value under the process condition TYP (corresponding to the upper layer delay value), the delay value before the delay adjustment under the process condition TYP of the route abcekq can be obtained. Note that the route abcflr can be obtained in the same manner.

Next, in step ST17, it is determined whether or not there are other process conditions as semiconductor process conditions. If there are other process conditions, step ST
Returning to 15, the delay value inside the hard macro under another process condition is obtained. For example, as another process condition,
For example, if there is the process condition MIN, the delay values under the respective process conditions MIN in the circuits C1 and C2 necessary for delay adjustment are read, and the subsequent steps are similarly performed.

Next, in step ST18, it is determined whether or not there is a next group for which delay adjustment is to be performed. That is, it is determined whether or not there is a group having another clock source as another group whose delay is to be adjusted. If there is another group, the process returns to step ST12 and the above steps are repeated for that group.

Next, in step ST19, the skew for each group / process is obtained based on the delay value for each group and for each process condition. Here, for example, in the group A, the skews before the delay adjustment under the process condition TYP and the process condition MIN are obtained based on the delay values before the delay adjustment of the route abcflr and the route abcekq.

Next, in step ST20, the delay value and the skew before delay adjustment for each group / process condition obtained above are stored.

Then, in step ST2, it is determined whether or not the circuit operation can be guaranteed, as described with reference to FIG.

In FIG. 2, the delay value before delay adjustment is calculated in step ST16, and then the delay value before delay adjustment is calculated for each process condition and each group. It is not limited to this. That is, even in the case where each process condition and each group are obtained in advance before step ST12, and the delay value before delay adjustment for each process condition and each group is obtained, the present invention is also applicable. It goes without saying that it can be implemented similarly.

<Predicted Delay Value and Predicted Skew After Delay Adjustment> If the circuit operation is not guaranteed in step ST2 of FIG. 2, the delay adjustment is performed by the processing of steps ST21 to ST25 of FIG. 3 described below. Obtain the predicted delay value and predicted skew afterwards.

In step ST21, the process condition serving as a reference for delay adjustment is designated from all the process conditions read in step ST17. For example, if there are a process condition TYP and a process condition MIN as process conditions, the process condition T
Specify YP.

Next, in step ST22, the predicted delay value after delay adjustment under the process condition of the reference specified above is obtained based on the delay value and skew before delay adjustment obtained above. Further, the predicted delay value after delay adjustment under other process conditions (corresponding to a predetermined process condition) is obtained based on the predicted delay value after delay adjustment under the reference process conditions. In other words, when delay adjustment is performed so that the skew before delay adjustment becomes zero based on the predicted delay value before delay adjustment under the reference process conditions,
Determine the expected delay value under other process conditions.

Next, in step ST23, the delay-adjusted predicted skew for each process condition is calculated based on the delay-adjusted predicted delay value calculated in step ST22.

Here, the calculation of the predicted delay value and the predicted skew after the delay adjustment will be described more specifically with reference to FIG. FIG. 5 is a diagram for explaining delay adjustment of a path in a certain group of semiconductor integrated circuits for simplification of description.

In FIG. 5, the buffer 10 is used as the starting point for delay adjustment. The route R1 has a delay adjustment cell 11 for adjusting the delay value of the route R1, and the flip-flop 13 is connected to the delay adjustment cell 11. The route R2 has a delay adjustment cell 12 for adjusting the delay value of the route r2, and the flip-flop 14 is connected to the delay adjustment cell 12.

The delay adjustment for the routes R1 and R2 will be described.

FIG. 6 is a table showing the information necessary for calculating the predicted delay value and the predicted skew after the delay adjustment and the predicted delay value and the predicted skew calculated based on the information.

In FIG. 6, it is assumed that the semiconductor process conditions for delay adjustment include a process condition TYP and a process condition MIN. In addition, the route R before delay adjustment
The delay value and the skew of the route 1 and the route R2 can be obtained according to the description of FIG. 2 above, and their respective values are as shown in the table. Furthermore, the gate delay coefficient k is a value determined for each semiconductor process condition according to the degree of gate delay in each path. Then, assuming that the reference process condition designated in step ST21 is the process condition TYP, for example, the gate delay coefficient k in the process condition TYP is set to "1.0", and the gate delay coefficient k of the process condition MIN is set. To "0.
5 ”.

Based on FIGS. 5 and 6, the predicted delay value after delay adjustment is obtained.

As shown in FIG. 6, the route R1 before delay adjustment
Has a delay value of 20 (ns) and the delay value of the route R2 is 1
Since it is 0 (ns) and is generally adjusted with a route having a large delay value as a reference, a case where the delay value of the route R2 is adjusted with the route R1 having a large delay value as a reference will be described.

First, the process condition TYP for delay adjustment
The predicted delay value after delay adjustment of the route R2 below is obtained by the following equation (1).

Predicted delay value of path R2 (under process condition TYP) = delay value before delay adjustment of path R2 (under process condition TYP) + gate delay coefficient (under process condition TYP) × skew before delay adjustment of path R2 (process Under the condition TYP) (1) That is, it is understood that 10 + 1.0 × 10 = 20, and the predicted delay value of the route R2 after delay adjustment is 20 (ns).

On the other hand, the predicted delay value after the delay adjustment of the route R2 under the semiconductor process condition MIN is obtained by the following equation (2).

Predicted delay value of path R2 (under process condition MIN) = delay value before delay adjustment of path R2 (under process condition MIN) + gate delay coefficient (under process condition MIN) × skew before delay adjustment of path R2 (process Under the condition TYP) (2) That is, it is understood that 4 + 0.5 × 10 = 9, and the predicted delay value of the route R2 after delay adjustment is 9 (ns).

Furthermore, the predicted skew after delay adjustment is the process conditions TYP and MI for the paths A and B.
It can be easily obtained from the respective predicted delay values under N. As shown in FIG. 6, the predicted skew after delay adjustment is
Under the process condition TYP and the process condition MIN, they are "0" and "1", respectively, and in this case, it can be seen that there is no variation for each process condition.

Next, returning to FIG. 3, in step ST24, the predicted delay value and predicted skew after delay adjustment calculated as described above are stored.

Finally, in step ST25, the initial value setting file is closed and steps ST1 to ST1 shown in FIG.
After the processing related to ST3 is completed, step S described in FIG.
Proceed to T4.

As described above, according to this embodiment, the delay value and the skew before the delay adjustment corresponding to all the semiconductor process conditions are calculated, and the delay value and the delay value which can be predicted after the delay adjustment based on the delay value and the skew are calculated. Ask for skew. Based on the predicted delay value and skew, the delay adjustment cell reflects the delay value adjustment on the layout. Therefore, variations in delay adjustment for each process condition are prevented, the need for delay adjustment again is reduced, the layout man-hours for delay adjustment are reduced, and the design period of the semiconductor integrated circuit can be shortened. Also, without using all the delay values of the hard macro part of the lower hierarchy,
Since the delay value before the delay adjustment is obtained by using only the delay value of the hard macro portion necessary for the delay adjustment, the calculation period can be reduced and the design period can be effectively shortened. Further, since the predicted delay value for each process condition is calculated according to the degree of the gate delay determined for each process condition, the delay adjustment of only the gate delay can be accurately performed.

[0065]

As described above, the delay adjusting method according to the present invention obtains the delay value and the skew before the delay adjustment for each of a plurality of process conditions, and determines the delay value and the skew before the delay adjustment under the reference process condition. Based on this, the predicted delay value and the predicted skew under the predetermined process conditions are obtained.
This eliminates variations in delay adjustment for each process condition, reduces the need for delay adjustment again, reduces layout man-hours for delay adjustment, and shortens the design period of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating a delay adjustment method according to an exemplary embodiment of the present invention.

FIG. 2 is a flowchart specifically showing calculation of a delay value and a skew before delay adjustment.

FIG. 3 is a flowchart specifically showing calculation of a predicted delay value and a predicted skew after delay adjustment.

FIG. 4 is a diagram showing a group having a predetermined clock source in an integrated circuit that calculates a delay value and a skew before delay adjustment.

FIG. 5 is a diagram illustrating an example of a circuit for explaining delay adjustment.

FIG. 6 is a diagram showing numerical values related to explanation of delay adjustment.

[Explanation of symbols]

ST1 Steps for obtaining delay value and skew before delay adjustment ST2, ST4 Steps for determining whether or not circuit operation is guaranteed ST3 Steps for obtaining predicted delay value and skew after delay adjustment ST5 Adjustment of delay value in layout Reflecting step ST6 Step of correcting the layout before delay adjustment ST12 Step of reading delay values other than the hard macro step ST13 Step of reading a route necessary for delay adjustment ST14 Step of reading input / output pin information of the hard macro step ST15 Setting of delay value Step ST16 for reading the delay value of the path of the hard macro part that needs adjustment Step ST17 for obtaining the delay value before delay adjustment ST17 Step ST18 for judging whether there is the next process condition ST18 It is judged whether there is the next group Step ST19 Step ST21 for obtaining skew before delay adjustment under loop process conditions Step ST22 for specifying process conditions for delay adjustment Step ST22 Step ST23 for obtaining predicted delay value after delay adjustment under one or more process conditions Step ST23 One or more Of Predicted Skew After Delay Adjustment Under Various Process Conditions

Continued front page    F-term (reference) 5B046 AA08 BA04                 5F064 AA04 BB19 BB26 BB35 DD04                       DD14 DD25 EE47 EE54 HH07                       HH10 HH11

Claims (8)

[Claims] 1. A delay adjusting method for adjusting a delay occurring in a path in a semiconductor integrated circuit by using a delay adjusting cell, wherein the delay adjusting is performed for each of a plurality of process conditions of the semiconductor integrated circuit based on layout information. It becomes a reference when the circuit operation cannot be guaranteed by the first step of obtaining the previous delay value and the skew and the delay value or the skew before the delay adjustment obtained in the first step under a predetermined process condition. Based on the delay value and the skew before the delay adjustment under the process condition, the predicted delay under the predetermined process condition when the delay caused in the path is adjusted so that the skew under the reference process condition becomes small. The second step of obtaining the value and the predicted skew, and the predetermined process condition obtained in the second step. A third step of adjusting the delay caused in the path by using the delay adjustment cell when the circuit operation can be guaranteed by the predicted delay value or the predicted skew. 2. The delay adjusting method according to claim 1, wherein the semiconductor integrated circuit has a hierarchical structure by a hierarchical design, and the first step includes all steps in an upper hierarchy read from the layout information. The upper layer delay value which is the delay value of the route necessary for the delay adjustment in the upper layer is read based on the delay value of the route of the lower layer, and the lower layer delay which is the delay value of the route required for the delay adjustment in the lower layer is read. A delay adjusting method comprising: reading a value, adding the upper layer delay value and the lower layer delay value to obtain a delay value before the delay adjustment. 3. The delay adjusting method according to claim 1, wherein the second step indicates a degree of gate delay in the path determined for each process condition of the semiconductor integrated circuit. Using a gate delay coefficient, the delay value before the delay adjustment under the predetermined process condition is added to the skew before the delay adjustment under the process condition that is the reference with the gate delay coefficient corresponding to the predetermined process condition. Is added to obtain a predicted delay value under the predetermined process condition. 4. A delay value calculating method for obtaining a delay occurring in a path in a semiconductor integrated circuit, wherein delay value and skew before delay adjustment for each of a plurality of process conditions of the semiconductor integrated circuit based on layout information. A method for calculating a delay value, which is characterized by: 5. A delay value calculation method for obtaining a delay caused in a path in a semiconductor integrated circuit, wherein delay value and skew before delay adjustment for each of a plurality of process conditions of the semiconductor integrated circuit based on layout information. And specify a reference process condition from a plurality of process conditions of the semiconductor integrated circuit,
Based on the delay value and the skew before the delay adjustment under the reference process condition, the predetermined process condition when the delay generated in the path is adjusted so that the skew under the reference process condition becomes small. A delay value calculation method characterized by obtaining a predicted delay value of. 6. The delay value calculation method according to claim 4, wherein the semiconductor integrated circuit has a hierarchical structure by hierarchical design, and the delay value before delay adjustment is: Based on the delay values of all the routes in the upper layer read from the layout information, the upper layer delay value, which is the delay value of the route necessary for the delay adjustment in the upper layer, is read and necessary for the delay adjustment in the lower layer. The delay value calculation method is characterized in that it is obtained by reading a lower layer delay value which is a delay value of another route and adding the upper layer delay value and the lower layer delay value. 7. The delay value calculation method according to claim 5, wherein the predicted delay value under the predetermined process condition is a gate indicating the degree of gate delay in the path, which is determined for each process condition of the semiconductor integrated circuit. Using the delay coefficient, the delay value before the delay adjustment under the predetermined process condition, the gate delay coefficient corresponding to the predetermined process condition to the skew before the delay adjustment under the reference process condition A delay value calculation method characterized by being obtained by adding a multiplied value. 8. The delay value calculation method according to claim 5, further comprising the step of calculating a predicted skew under the predetermined process condition based on a predicted delay value under the predetermined process condition. A method for calculating a delay value, which is characterized by obtaining.