JP2003333849A - Power supply and inorganic el display employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply in which a variation in output voltage caused by the variation of a load condition is suppressed. <P>SOLUTION: The power supply for receiving an input voltage Vin and supplying output voltages -Vth and Vm, respectively, to output terminals 204 and 203 comprises a transformer 210 receiving the input voltage Vin on the primary winding thereof, a switching element 231 connected with the primary winding of the transformer 210, an output circuit connected with the secondary winding of the transformer 210 and producing the output voltages -Vth and Vm, a circuit 232 for controlling the operation of the switching element 231 based at least on the output voltage -Vth, and a regulation circuit 290 for varying resistance between at least one of the output terminals and the ground. According to the arrangement, a variation in output voltage caused by the variation of a load condition is effectively suppressed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device,
In particular, the present invention relates to a power supply device suitable for application to an inorganic EL display device. The present invention also relates to an inorganic EL display device.

[0002]

2. Description of the Related Art In recent years, an inorganic EL display device using an inorganic EL panel has attracted attention as a thin display device capable of displaying high quality images. A general inorganic EL display device has an inorganic EL panel in which a large number of data wirings (column wirings) and a large number of scanning wirings (row wirings) are laid so as to intersect each other, and between the data wirings and the scanning wirings. By applying a voltage Vth + Vm exceeding the threshold value Vth to the pixel, a desired pixel can emit light.

For example, when only one specific pixel is made to emit light, the voltage -Vth and the voltage Vm are applied to the corresponding scanning wiring and the corresponding data wiring, respectively, and the other scanning wirings are set in the open state, and the other data wirings are made. It suffices to apply the ground potential (GND). As a result, in the specific one pixel, the voltage between the data wiring and the scanning wiring becomes Vth + Vm, so that light is emitted, while in the other pixels, the voltage between the data wiring and the scanning wiring is less than Vth. Therefore, it does not emit light. In addition, inorganic EL
Since the display device generally needs to be driven by an alternating current, when the specific one pixel is made to emit light next, the voltage V is applied to the corresponding scan line and the corresponding data line, respectively.
It is necessary to apply th + Vm and the ground potential (GND), open the other scanning wirings, and apply the voltage Vm to the other data wirings.

As described above, the inorganic EL display device requires a plurality of voltages such as a voltage to be applied to the data wiring and a voltage to be applied to the scanning wiring. In the above example, the voltage Vm is required as the voltage to be applied to the data wiring, and the voltage −V is required as the voltage to be applied to the scanning wiring.
th and voltage Vth + Vm are required.

FIG. 32 is a circuit diagram of a conventional power supply device for an inorganic EL display device.

As shown in FIG. 32, the conventional power supply device for an inorganic EL display device transforms the DC voltage Vin supplied to the input terminal 1 and outputs the voltages Vth + Vm, Vm and -Vth to the output terminals 2a to 2c, respectively. Is a device for generating the primary winding 10a and the secondary windings 10b to 10d.
A switching element 20a provided on the primary side of the transformer 10, a control circuit 20b for controlling the switching element 20a, and an output circuit 30 provided on the secondary side of the transformer 10.

In the conventional power supply device having such a configuration, the switching element 20a is PWM-controlled under the control of the control circuit 20b, whereby the voltage Vt is applied to the secondary windings 10b to 10d of the transformer 10, respectively.
It is possible to generate h, Vm and -Vth. The secondary side voltage is rectified and smoothed by the diode and the capacitor forming the output circuit 30, and the voltages Vth + Vm and Vth are respectively applied to the output terminals 2a to 2c.
m and -Vth will appear.

The control by the control circuit 20b is performed by monitoring any of the voltages appearing at the output terminals 2a to 2c. Therefore, for example, the output terminal 2c
When monitoring the voltage appearing on the switching element 20, the control circuit 20b controls the switching element 20 so that it stabilizes at the voltage -Vth.
PWM control of a. As a result, not only the voltage to be monitored (for example, -Vth) but also other voltages not directly monitored (for example, Vth + Vm and Vm) will be monitored depending on the winding ratio of the transformer 10. It is possible to keep it constant, as in.

[0009]

However, when the load connected to the output terminals 2a to 2c is large, there is a problem that the voltage not directly monitored tends to fluctuate as compared with the voltage to be monitored. .

For example, the load on the output terminal 2b (the line of the voltage Vm) becomes the maximum when the ratio of the pixels in the selected scanning wiring to the lighting state is 50%, and from 50%. The load decreases as the distance increases. Therefore, when the control circuit 20b monitors the voltage appearing at the output terminal 2c, the voltage Vm is lowered when the ratio of pixels in the lighting state is 50% or close to 50%, which causes the actual luminance. However, there is a problem in that On the other hand, the output terminal 2c (voltage-Vth
Line), the load increases with the ratio of the pixels that are turned on among the pixels on the selected scanning wiring. Therefore, when the control circuit 20b monitors the voltage appearing at the output terminal 2c, the load is turned on. 10 pixels
If it is 0% or close to 0%, the voltage Vm rises due to the cross regulation, which causes a problem that the actual luminance becomes higher than the desired luminance.

As described above, in the conventional power supply device for an inorganic EL display device, there is a problem in that the voltage which is not directly monitored easily fluctuates, which causes an error in the luminance of the actual pixel. Further, since the fluctuation of the load state is particularly remarkable in the line of the voltage (Vm) to be applied to the data wiring, in the case where the control circuit 20b controls by monitoring other voltage, The fluctuation of the voltage becomes particularly remarkable.

Therefore, an object of the present invention is to provide a power supply device in which the fluctuation of the output voltage due to the fluctuation of the load state is suppressed and an inorganic EL display device using the same.

[0013]

The object of the present invention is to:
At least a first voltage that receives the input voltage and has a different voltage from each other
A power supply device for generating a first output voltage and a second output voltage, and supplying the second output voltage to the first and second output terminals, respectively, the transformer having a primary winding receiving the input voltage, and the primary winding of the transformer. A switching element connected to the transformer, a first output circuit connected to the secondary winding of the transformer and generating the first output voltage and a second output voltage, respectively, and at least the first output voltage. A control circuit for controlling the operation of the switching element based on the above, and based on a load state occurring in at least one of the first and second output terminals, at least one of the first and second output terminals, and And a means for changing a resistance value between voltage lines having different voltages, which is achieved by the power supply device.

According to the present invention, based on the state of the load,
Since the resistance value between at least one of the first and second output terminals and the voltage line is changed, the control circuit can perform appropriate control according to the load state. This makes it possible to effectively suppress the fluctuation of the output voltage caused by the fluctuation of the load state.

Further, it is preferable that the means reduces the resistance value between the first output terminal and the voltage line as the load generated on the second output terminal increases.
According to this, it is possible to effectively suppress the fluctuation of the second output voltage due to the increase of the load on the second output terminal.

Further, it is preferable that the means increases the resistance value between the second output terminal and the voltage line as the load generated on the second output terminal increases.
According to this, it is possible to effectively suppress the fluctuation of the second output voltage due to the increase of the load on the second output terminal.

Further, it is preferable that the voltage line is a ground line.

Further, the transformer includes first and second transformers, and the switching element is a first switching element connected to a primary winding of the first transformer and a primary of the second transformer. A second switching element connected to the winding, wherein the first output circuit is connected to the secondary winding of the first transformer, and the second output circuit is connected to the second transformer. A first control circuit connected to a secondary winding, the control circuit controlling the operation of the first switching element based on the first output voltage, and the first control circuit based on the second output voltage. A second control circuit for controlling the operation of the second switching element is preferably included. According to this, it becomes possible to more effectively suppress the variations in the first and second output voltages.

In this case, the first and second control circuits respectively connect the first and second switching elements to P
It is more preferable that the same sawtooth wave is used for the PWM control by the first and second control circuits, which is a circuit for WM control. According to this, even if the secondary side of the first transformer and the secondary side of the second transformer can interfere with each other, it is possible to prevent the interference, and thereby the abnormal oscillation due to the interference can be prevented. Can be effectively suppressed.

Further, in the PWM control by the first and second control circuits, the first and second frequencies in which one frequency is an integral multiple of the other frequency and the timings of peak values substantially coincide with each other. It is also preferred that each sawtooth wave is used. This also makes it possible to effectively suppress abnormal oscillation due to interference between the secondary side of the first transformer and the secondary side of the second transformer.

The object of the present invention is also to provide an inorganic EL panel having a plurality of scanning wirings and a plurality of data wirings, a row driver for driving the plurality of scanning wirings, and a column driver for driving the plurality of data wirings. An inorganic EL display device comprising: a power supply device that generates a voltage used in the row driver and the column driver, wherein the row driver has a first output voltage supplied through at least a first output voltage line. The column driver operates based on a second output voltage supplied through at least a second output voltage line, and the power supply device includes a transformer that receives an input voltage in a primary winding. A switching element connected to the primary winding of the transformer, a secondary winding of the transformer, and the first and second output voltages First and second output circuits respectively provided between the input and output terminals, a control circuit that controls the operation of the switching element based on at least the first output voltage, and the first and second output voltages Based on the state of the load occurring on at least one of the lines, the first
And a means for changing a resistance value between at least one of the second output voltage lines and a voltage line having a voltage different from the second output voltage line.

In this case, it is preferable that the means determines the load state based on the total number of data lines and the number of pixels which are turned on in one scanning line.

[0023]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
A preferred embodiment of the present invention will be described in detail.

FIG. 1 is a block diagram schematically showing the overall structure of the inorganic EL display device.

As shown in FIG. 1, the inorganic EL display device includes n data wirings (column wirings) 101 ₁ to ₁ 1.
01 _n and m scanning wirings (row wirings) 102 _{1 to} 102
Inorganic EL panel 100 in which _m and _m intersect with each other
And the column driver 11 that drives each data line 101
0, and a row driver 120 that drives each scan line 102
A column voltage control circuit 130 that supplies the pulse voltage VmD to the column driver 110, a row voltage control circuit 140 that supplies the pulse voltages VSP and VSN to the row driver 120, and a controller 150 that controls the overall operation of the inorganic EL display device. And a power supply device 200 for generating various voltages required in the inorganic EL display device.

In the inorganic EL panel 100, each intersection of the data wiring 101 and the scanning wiring 102 becomes a pixel 103. As a result, n × m pixels 103 are arranged in a matrix on the inorganic EL panel 100.

2A and 2B are diagrams schematically showing the structure of the pixel 103. FIG. 2A is a schematic plan view thereof, and FIG. 2B is a schematic sectional view taken along the line AA.

As shown in FIGS. 2 (a) and 2 (b), one pixel 103 includes a scanning wiring 10 laid on a substrate 104.
2 and the data wiring 101 intersecting with the wiring 2. In the pixel 103, since the direction in which the data wiring 101 is provided is the viewing direction of the inorganic EL panel 100, it is necessary to use a transparent conductive material for at least the data wiring 101, and there is no particular limitation. It is preferable to use ITO. On the other hand, the scanning wiring 102 does not need to be transparent, and a metal such as gold can be used. Further, an inorganic light emitting layer 106 sandwiched between the first dielectric layer 105 a and the second dielectric layer 105 b is provided between the data wiring 101 and the scanning wiring 102, and on the data wiring 101. A transparent protective film 107 is provided. The material of the first dielectric layer 105a and the second dielectric layer 105b is not particularly limited, but is a perovskite type ferroelectric material, a tungsten bronze type ferroelectric material, Y ₂ O ₃ , Ta. _Two
Transparent dielectric thin films such as O ₃ , Al ₂ O ₃ , SiN, and BaTiO ₃ can be used. In addition, the inorganic light emitting layer 10
The material of 6 is not particularly limited, but S
rS: Ce / Zns: Mn or the like can be used.

FIG. 3 is an equivalent circuit diagram of the pixel 103.

As shown in FIG. 3, in the pixel 103, the resistance R, the load capacitance Cp and the load capacitance Cd, and the load capacitance Cp connected in series between the data wiring 101 and the scanning wiring 102.
Zener diodes Z1 and Z2 connected in parallel with respect to each other and connected in series so that their polarities are opposite to each other.
Can be represented by The resistance R is the data wiring 10
The wiring capacitance is 1, and the load capacitance Cp is the inorganic light emitting layer 106.
The load capacitance Cd is a capacitance component due to the first dielectric layer 105a and the second dielectric layer 105b. Generally, the load capacitance Cp is larger than the load capacitance Cd.

The two Zener diodes Z1 and Z2 are elements based on the current-voltage characteristics of the inorganic light emitting layer 106, and when the voltage across both ends exceeds the threshold voltage Vth, Zener break occurs and light emission occurs. . Therefore, the capacitance between the data wiring 101 and the scanning wiring 102 is substantially Cd during light emission and (Cp × Cd) / (Cp + Cd) during non-light emission.

FIG. 4 is a graph showing the light emission characteristics of the pixel 103.

As shown in FIG. 4, the pixel 103 emits light when the voltage applied between the data line 101 and the scan line 102 (pixel 103) exceeds the threshold value Vth, and the amount of light is from Vth. In the range of Vth + Vm, it is almost proportional to the voltage applied to the pixel 103, but Vth + V
If it exceeds m, it will be saturated and no more light will be obtained. Therefore, the voltage applied to the pixel 103 is changed from Vth to Vt.
The emission intensity can be set to a desired level by controlling up to h + Vm. On the other hand, when only lighting / non-lighting control is performed, the voltage applied to the pixel 103 is V
It may be turned on by setting th + Vm, and may be turned off by setting less than Vth.

Therefore, in order to make the specific pixel 103 on the inorganic EL panel 100 emit light (light up), the voltage -Vth is applied to the corresponding scanning wiring 102, while the other scanning electrodes 102 are opened and corresponding. The voltage Vm may be applied to the data electrode 101, and the ground voltage (GND) may be applied to the other data wirings 101.
As a result, only the voltage applied to the particular pixel 103 becomes Vth + Vm, and all the voltages applied to the other pixels 103 become less than Vth.
Only 03 can emit light (light up).

However, in the inorganic EL panel 100, unless the pixel 103 is driven by an alternating current, dielectric polarization occurs and the brightness is lowered. Therefore, after the voltage −Vth is applied to the predetermined scan line 102 and the voltage Vm is applied to the predetermined data electrode 101 to cause the specific pixel 103 to emit light, next, the pixel 103 concerned.
It is necessary to emit light again by applying a voltage in the opposite direction. Specifically, the voltage Vth + Vm may be applied to the scanning wiring 102, and the ground voltage (GND) may be applied to the data electrode 101 to emit light. In this case, it is necessary to apply the voltage Vm to the data wiring 101 corresponding to the pixel 103 that is not illuminated. In this way, the inorganic EL panel 100 is AC-driven,
This prevents the brightness from being lowered due to dielectric polarization. In the present specification, in the AC driving of the inorganic EL panel 100, the case where the pixel 103 is caused to emit light by driving so that the voltage on the data wiring 101 side becomes high is driven in the forward direction, and conversely, the voltage on the scanning wiring 102 side. The case where the pixel 103 is driven to emit light by driving so as to be higher is called negative direction drive.

FIG. 5 is a partial equivalent circuit diagram of the inorganic EL panel 100 when all the pixels 103 on the selected scanning wiring 102-i are turned on by the forward drive. In FIG. 5, the pixels 103 that are lit (emits light) are circled.

As shown in FIG. 5, by the forward drive,
When all the pixels 103 on the scanning wiring 102-i are turned on, this is brought into a selected state by applying the voltage −Vth to the scanning wiring 102-i, and the voltage Vm is applied to all the data wirings 101 _{1 to} 101 _n. Is applied. The other scan wirings 102 that are not selected are in a floating state (Hi
Z). As a result, for all the pixels 103 on the scanning wiring 102-i, the corresponding data wiring 101
The voltage between the scan line 102 and the scan line 102 becomes Vth + Vm and exceeds the threshold value Vth, so that light is emitted. For the other pixels 103, the voltage between the corresponding data line 101 and the scan line 102 is less than Vth. It does not emit light.

In this case, in the pixel 103 which is emitting light, the Zener diode Z2 shown in FIG. 3 has a Zener break, so that the capacitance between the data wiring 101 and the scanning wiring 102 becomes Cd (in FIG. 5, Is "C
In the other pixels 103, the capacitance between the data wiring 101 and the scanning wiring 102 is (Cp × Cd) / (Cp + C).
d) (notated as “Cp, Cd” in FIG. 5 and the same in the following figures).

Here, the scan wirings 102 not selected
Is in a floating state (HiZ), and no specific voltage is applied to each data line 101.
Between the pixel 103 and the non-selected scanning wiring 10
2 is formed, as shown in FIG. 5, when all the pixels 103 on the scanning wiring 102-i are turned on, the voltage of all the data wirings 101 _{1 to} 101 _n is Vm. Since there is no potential difference between them, no current flows in this path. Therefore, in this case, the load on the line of the voltage Vm is relatively small. On the other hand, with respect to the selected scanning wiring 102-i, since charges must be supplied to all the pixels 103 on the scanning wiring 102-i, the load applied to the line of voltage −Vth becomes relatively large.

FIG. 6 is a partial equivalent circuit diagram of the inorganic EL panel 100 in the case where all the pixels 103 on the selected scanning wiring 102-i are turned on by the negative driving, and also in FIG. , The pixels 103 that are lit (emits) are circled.

As shown in FIG. 6, by the negative drive,
When all the pixels 103 on the scan wiring 102-i are turned on, this is brought into a selected state by applying the voltage Vth + Vm to the scan wiring 102-i, and all the data wirings 101 _{1 to} 101 _n are connected to the ground potential ( GND) is applied. The other scan wirings 102 that are not selected are brought into a floating state (HiZ). As a result, for all the pixels 103 on the scanning wiring 102-i, the voltage between the corresponding data wiring 101 and scanning wiring 102 is Vt.
It emits light when it becomes h + Vm and exceeds the threshold value Vth, and does not emit light in the other pixels 103 because the voltage between the corresponding data wiring 101 and the scanning wiring 102 becomes less than Vth.

In this case, since the Zener diode Z1 shown in FIG. 3 has a Zener break in the pixel 103 which is emitting light, the capacitance between the data line 101 and the scanning line 102 becomes Cd (Cd only). ,
In the other pixels 103, the capacitance between the data wiring 101 and the scanning wiring 102 is (Cp × Cd) / (Cp +
Cd) (Cp, Cd).

As described above, in the case of driving in the negative direction, when all the pixels 103 on the scanning wiring 102-i are turned on, the data wiring 101 to which the voltage Vm is applied is applied.
Is not present, the voltage Vm line is hardly loaded. On the other hand, the selected scan wiring 102-
For i, all pixels 10 on the scan wiring 102-i
Since the electric charge must be supplied to 3, the voltage Vt
The load on the h + Vm line is relatively large.

FIG. 7 is a partial equivalent circuit diagram of the inorganic EL panel 100 in the case where all the pixels 103 on the selected scanning wiring 102-i are brought into a non-lighting state in the forward driving.

As shown in FIG. 7, when all the pixels 103 on the scanning wiring 102-i are not turned on in the forward driving, this is selected by applying a voltage -Vth to the scanning wiring 102-i. In addition, the ground potential (GND) is applied to all the data wirings 101 _{1 to} 101 _n . The other scan wirings 102 that are not selected are brought into a floating state (HiZ). As a result, the scanning wiring 10
2-i not only all pixels 103 on but also all pixels 1
03, the corresponding data wiring 101 and scanning wiring 1
Since the voltage between the pixel No. 02 and Vp is less than Vth, no pixel 103 emits light.

As described above, in the case of performing the forward drive, when all the pixels 103 on the scanning wiring 102-i are not turned on, the data wiring 10 to which the voltage Vm is applied is applied.
Since 1 does not exist, the line of the voltage Vm is hardly loaded. Moreover, the selected scanning wiring 10
In each pixel 103 on 2-i, the data wiring 101
Since the capacitance between the scanning line 102 and the scanning line 102 is small, and the voltage between both ends is also small, the load applied to the voltage-Vth line is relatively small.

Although not shown, when all the pixels 103 on the scanning wiring 102-i are not turned on in the negative driving, the voltage Vth + Vm is applied to the scanning wiring 102-i to bring it into the selected state. In addition, the voltage Vm is applied to all the data wirings 101 _{1 to} 101 _n . The other scan wirings 102 that are not selected are brought into a floating state (HiZ). As a result, the scan wiring 102-i
Not only all the pixels 103 above, but all the pixels 103, since the voltage between the corresponding data wiring 101 and the scanning wiring 102 is less than Vth, no pixel 103 emits light.

As described above, in the case of driving in the negative direction, when all the pixels 103 on the scanning wiring 102-i are not lit, all the data wirings 101 _{1 to} 101 _n.
Since the voltage is Vm and there is no potential difference between them, no current flows in the path formed between the data wirings 101. Therefore, in this case, the voltage Vm
The load on the line is relatively small. On the other hand, in each pixel 103 on the selected scanning wiring 102-i, the capacitance between the data wiring 101 and the scanning wiring 102 is small, and the voltage between both ends is also small.
The load on the + Vm line is relatively small.

FIG. 8 shows the data wiring 1 of the pixels 103 on the selected scanning wiring 102-i in the forward drive.
Pixel 1 corresponding to 01 _2j (j is an integer of 1 to n / 2)
03 is turned on and other data wiring 101
2D is a partial equivalent circuit diagram of the inorganic EL panel 100 when the pixel 103 corresponding to _2j-1 is in a non-lighting state. FIG. Note that, in FIG. 8 as well, the pixel 1 that is lit (emits)
03 is circled, and the selected scanning wiring 10
It can be seen that every other pixel 103 on 2-i is in a lighting state. Such a lighting pattern is sometimes called a "checker pattern".

As shown in FIG. 8, when the checker pattern is displayed in the forward drive, the scanning wiring 102-
and selected this by applying a voltage -Vth to i, and applies the voltage to the data line _{101 2j} Vm, ground potential to the data line _{101 2j-1} a (GND). The other scanning lines 102 that are not selected are in a floating state (HiZ). As a result, the scanning wiring 102
Regarding the pixel 103 corresponding to the data wiring _1012j to which the voltage Vm is applied among the pixels 103 on −i, the voltage between the corresponding data wiring 101 and the scanning wiring 102 becomes Vth + Vm and becomes the threshold value. It emits light when it exceeds Vth, and does not emit light for the other pixels 103 because the voltage between the corresponding data wiring 101 and scanning wiring 102 becomes less than Vth.

Further, although not shown, when displaying a checker pattern in the negative direction drive, the scanning wiring 1
And selected this by applying a voltage Vth + Vm to 02-i, and the ground potential to the data line _{101 2j} (GND), for applying a voltage Vm to the data line _{101 2j-1.} As a result, among the pixels 103 on the scanning wiring 102-i, the pixel 103 corresponding to the data wiring _1012j to which the ground potential (GND) is applied is between the corresponding data wiring 101 and the scanning wiring 102. Light is emitted when the voltage becomes Vth + Vm and exceeds the threshold value Vth.
Since the voltage between the corresponding data wiring 101 and scanning wiring 102 is less than Vth, it does not emit light.

As described above, except when all the pixels 103 on the selected scanning wiring 102 are turned on or off, the data wiring 10 to which the voltage Vm is applied is applied.
1 and the data wiring 1 to which the ground potential (GND) is applied
01 is mixed, the data wirings 101 ₁ to 10 ₁ to 10
A potential difference occurs between 1 _n . As a result, as shown in FIG. 8, the current I flows in the path passing through the scanning line 102 in the non-selected state, and the capacitance component (Cp × C) of the pixel 103 is generated.
d) / (Cp + Cd) is charged. The current I is
Since the larger the number of the data wirings 101 to which the voltage Vm is applied and the number of the data wirings 101 to which the ground potential (GND) is applied are, the larger the number becomes.
When the number of pixels 103 that are turned on is equal to the number of pixels 103 that are not turned on, the current I becomes maximum.

Therefore, the load applied to the line of the voltage Vm becomes larger as the number of the pixels 103 which are in the lighting state and the number of the pixels 103 which are in the non-lighting state are closer to each other, and the lighting state is set like the checker pattern. When the number of pixels 103 to be turned on is equal to the number of pixels to be turned off, the maximum value is obtained. Here, since the current I is a charging current for the capacitance component (Cp × Cd) / (Cp + Cd) of the pixel 103, it increases in proportion to the display area of the inorganic EL panel 100. On the other hand, the voltage-Vth line and the voltage V
The load applied to the th + Vm line increases in proportion to the number of pixels 103 that are turned on.

FIG. 9 is a graph schematically showing the relationship between the proportion of pixels that are turned on and the load on each voltage line, and FIG. 9A is the proportion of pixels that are turned on and the voltage line. The relationship between Vth and the load applied to the voltage line Vth + Vm is shown, and (b) shows the relationship between the proportion of pixels that are turned on and the load applied to the voltage line Vm.

As shown in FIG. 9A, the load on the voltage line -Vth and the voltage line Vth + Vm corresponding to the row side increases substantially in proportion to the ratio of the pixels which are turned on. Therefore, the selected scan wiring 10
The load is minimum when all the pixels 103 on 2 are not lit, and the load is maximum when all the pixels 103 on the selected scanning wiring 102 are lit.

On the other hand, as shown in FIG. 9B, in the load applied to the voltage line Vm corresponding to the column side, the ratio of the pixels in the lighting state to the pixels 103 on the selected scanning wiring 102 is large. Maximum when 50%, 50%
The load decreases with increasing distance from. Here, in the case of driving in the positive direction, the load becomes almost zero in the case where all the pixels 103 on the selected scanning wiring 102 are not lit, and in the case of driving in the negative direction, The load becomes almost zero when all the pixels 103 on the selected scanning wiring 102 are turned on.

The voltage line -Vt corresponding to the low side
h and the load on the voltage line Vth + Vm, and
Although the load applied to the voltage line Vm corresponding to the column side becomes heavier as the inorganic EL panel 100 is larger,
Voltage line -Vth and voltage line V corresponding to the low side
The load on th + Vm depends on the selected scan wiring 102.
However, the load applied to the voltage line Vm corresponding to the column side increases in proportion to the display area of the inorganic EL panel 100 as described above. Therefore, inorganic E
The larger the L panel 100 is, the more the load applied to the voltage line Vm is the voltage line −Vth and the voltage line Vt.
It tends to be larger than the load on h + Vm. Therefore, in most cases, the load applied to the voltage line Vm is the voltage line −Vth and the voltage line Vth + Vm.
Will be greater than the load on.

Next, a specific configuration of the power supply device 200 characterizing the inorganic EL display device according to this embodiment will be described in detail.

FIG. 10 shows the power supply device 2 according to this embodiment.
It is a circuit diagram of 00.

As shown in FIG. 10, the power supply device 200 according to the present embodiment transforms the DC voltage Vin supplied to the input terminal 201 to output the voltages Vth + Vm, Vm, -Vth, to the output terminals 202 to 208, respectively. RVDD, RV
A device for generating SS, CVDD and CVSS,
A transformer 210 having a primary winding 211 and secondary windings 212 to 216, a switching element 231 provided on the primary side of the transformer 210, and a control circuit 2 for controlling the switching element 231.
32, an output circuit group provided on the secondary side of the transformer 210, a sawtooth wave generation circuit 270 that supplies a sawtooth wave CT to the control circuit 232, and a load generated on the line of the voltage Vm (output terminal 203). A load state determination circuit 280 for determining the state and an adjustment circuit 290-1 for adjusting the load applied to the voltage-Vth line (output terminal 204) according to the load state are provided.

The output circuit group provided on the secondary side of the transformer 210 has a diode 25 whose anode is connected to one end of the secondary winding 212 and whose cathode is connected to the output terminal 202.
0 and the anode is the other end of the secondary winding 212 (secondary winding 21
3) and a cathode connected to the output terminal 203, and an anode connected to the output terminal 204.
And a cathode connected to one end of the secondary winding 214, a diode 252 having an anode connected to one end of the secondary winding 215 and a cathode connected to the output terminal 205, and an anode connected to the secondary winding. It is connected between the output terminal 202 and the other end of the secondary winding 213 (the other end of the secondary winding 214, GND), and the diode 254 connected to one end of the line 216 and the cathode of which is connected to the output terminal 207. Capacitor 255, the output terminal 203 and the secondary winding 213
256 connected to the other end (the other end of the secondary winding 214, GND) and the other end of the output terminal 204 and the secondary winding 213 (the other end of the secondary winding 214, GND) A capacitor 257 connected between the output terminal 205 and the output terminal 206,
The capacitor 259 is connected between the output terminal 207 and the output terminal 208.

As a result, the diode 250 and the capacitor 255, the diode 251 and the capacitor 256,
In addition, the diode 252 and the capacitor 257 constitute an output circuit for the output voltages Vth + Vm, Vm, and −Vth, respectively.
Reference numeral 8 constitutes an output circuit for the output voltages RVDD and RVSS, and the diode 254 and the capacitor 259 constitute an output circuit for the output voltages CVDD and CVSS.

The control circuit 232 has an input terminal 232a to which the voltage -Vth is supplied, an input terminal 232b to which the sawtooth wave CT is supplied, and an output terminal 232c for outputting the PWM signal 231a. In order to stabilize the received voltage -Vth, PW
The pulse width of the M signal 231a is adjusted.

FIG. 11 is a circuit diagram showing an example of a concrete circuit configuration of the control circuit 232.

The control circuit 232 according to the example shown in FIG.
Error amplifier 301, photocoupler 302, resistor 303
~ 307, the capacitor 308, and the comparator 309
It has and.

The error amplifier 301 has an inverting input terminal (−), a non-inverting input terminal (+) and an output terminal, and the voltage −Vth is applied to the resistor 303 at the inverting input terminal (−).
The voltage divided by 304 and 304 is supplied, and the reference voltage Vref is supplied to the non-inverting input terminal (+).
A resistor 305 and a capacitor 308 are connected in parallel between the inverting input terminal (−) and the output terminal of the error amplifier 301. Here, the reference voltage Vref corresponds to the voltage obtained by the voltage division of the resistors 303 and 304 when the voltage −Vth matches the target voltage. Therefore, the error amplifier 301 outputs the actual voltage −V.
If th is higher than the target voltage, the output level is lowered, and conversely, if the actual voltage −Vth is lower than the target voltage, the output level is raised.
Further, the responsivity of the error amplifier 301 is limited by the resistor 305 and the capacitor 308 connected between the inverting input terminal (−) and the output terminal, which prevents abnormal oscillation of the voltage −Vth and the like. There is.

The photocoupler 302 is a transformer 1 of the transformer 210.
While insulating the secondary side from the secondary side, it plays a role of transmitting the output of the error amplifier 301 belonging to the secondary side to the primary side, and the light emitting side element 302a is driven by the secondary side power supply Vcc2 supplied via the resistor 306. The light-receiving side element 302b operates and is operated by the primary-side power supply Vcc1 given through the resistor 307.

The comparator 309 has an inverting input terminal (-), a non-inverting input terminal (+) and an output terminal, and the sawtooth wave CT is supplied to the inverting input terminal (-) via the input terminal 232b. The non-inverting input terminal (+) is supplied with the feedback signal FB taken out from the connection point between the light receiving element 302b of the photocoupler 302 and the resistor 307. The output terminal of the comparator 309 is the output terminal 2
The PWM signal 231a, which is connected to 32c and is an output signal thereof, is supplied to the switching element 231.

FIG. 12 is a waveform diagram of the PWM signal 231a generated by the comparator 309.

As shown in FIG. 12, the comparator 309
The PWM signal 231a generated by the above becomes high level when the level of the feedback signal FB is higher than the level of the sawtooth wave CT, and conversely, the sawtooth wave C
When the level of T is higher than the level of the feedback signal FB, it becomes low level. Here, since the waveform of the sawtooth wave CT is always kept constant, the duty of the PWM signal 231a increases as the level of the feedback signal FB increases, and decreases as the level of the feedback signal FB decreases. . As a result, the operation of the switching element 231 is controlled so that the actual voltage −Vth approaches the target value.

FIG. 13 is a circuit diagram showing the circuit configuration of the load state determination circuit 280.

As shown in FIG. 13, the load state discrimination circuit 2
Reference numeral 80 denotes a counter 281 that receives a column selection signal C_select and a row selection signal R_select supplied from the controller 150, and a count value COUNT of the counter 281.
Discriminating circuit 282 for activating any one of the selection signals dam1 to dam3 based on the above.

The counter 281 has a column selection signal C_sel.
This is a circuit that counts the number of bits "1" included in ect, and the count value COUNT is the row selection signal R_sel.
Resets every time ect is activated. The counting method is not particularly limited. For example, the column selection signal C
When _select is supplied bit by bit, the count value CO is supplied every time a bit having a value of "1" is supplied.
Just increment UNT. The maximum count value of the counter 281 matches the number of data wirings, and the value is n. That is, the count value COUNT of the counter 281 represents the number of lighting pixels (or non-lighting pixels) on the currently selected scan wiring.

The count value COUNT of the counter 281 is supplied to the discriminating circuit 282, and the discriminating circuit 282 receives this and activates one of the selection signals dam1 to dam3. As the reference, when the count value COUNT is 0 or its vicinity and when it is n or its vicinity, the selection signal dam1 is activated and the count value COUNT is
When T is n / 2 or its vicinity, the selection signal dam
3 is activated, and the selection signal dam2 is activated when none of these is satisfied. As shown in FIG. 14, which of the selection signals is activated matches the state of the load applied to the line of the voltage Vm (output terminal 203) corresponding to the column side, and the load applied to the line of the voltage Vm. Is small (area 1 or area 5), the selection signal da
When m1 is activated and the load on the line of voltage Vm is large (region 3), the selection signal dam3 is activated and when the load on the line of voltage Vm is in the middle (region 2 or region 4). The selection signal dam2 will be activated.

As a concrete configuration of the discrimination circuit 282,
The present invention is not particularly limited as long as any of the selection signals dam1 to dam3 can be activated based on the above-mentioned criteria, but some specific examples thereof will be described below.

FIG. 15 is a circuit diagram showing an example of a specific circuit configuration of the discrimination circuit 282. Discrimination circuit 2 according to this example
Reference numeral 82 denotes a highly versatile circuit that can be applied regardless of the numerical value of the maximum number (n) of the count value COUNT.

The discrimination circuit 282 according to the example shown in FIG.
Four comparison circuits 283a to 283d and these comparison circuits 2
83a to 283d based on the output of the selection signal dam1
It is composed of a logic circuit 284 which activates any of the dam3. Of these four comparison circuits 283a to 283d, the comparison circuit 283a has a region 1 and a region 2 shown in FIG.
A number (eg, n / 6) that defines the boundary between and is stored,
The comparison circuit 283b stores a number (for example, n / 3) that defines the boundary between the regions 2 and 3 shown in FIG. 14, and the comparison circuit 283c stores the boundary between the regions 3 and 4 shown in FIG. The specified number (for example, 2n / 3) is stored, and the comparison circuit 283d stores the number (for example, 5n / 6) that defines the boundary between the regions 4 and 5 shown in FIG. The circuits 283a to 283d compare the count value COUNT supplied from the counter 281 with the stored value, and determine the logic level of each output based on the result. For example, if the count value COUNT is larger than the stored value, the output is set to high level.

Therefore, in the above example, if the count value COUNT is n / 2, the outputs of the comparison circuits 283a and 283b are at high level, and the comparison circuits 283c and 283 are not output.
The output of 83d becomes low level and the count value COUNT
When T is 3n / 4, the outputs of the comparison circuits 283a to 283c are high level, and the output of the comparison circuit 283d is low level.

The logic circuit 284 receives the outputs from the four comparison circuits 283a to 283d, and selects the selection signal da according to the number of high level signals among them.
One of m1 to dam3 is activated. Specifically, the number of high-level signals among the outputs from the four comparison circuits 283a to 283d is “0” or “4”.
If it is, the selection signal dam1 is activated, and if it is "1" or "3", the selection signal dam2 is activated,
If it is "2", the selection signal dam3 is activated.

With the above configuration, in the discrimination circuit 282 according to the example shown in FIG. 15, when the load applied to the line of the voltage Vm is the region 1 or the region 5, the selection signal dam is selected.
1 is activated, the selection signal dam2 is activated when the load applied to the line of the voltage Vm is the region 2 or the region 4, and the selection signal dam3 is activated when the load applied to the line of the voltage Vm is the region 3. Can be activated.

FIG. 16A is a circuit diagram showing another example of the specific circuit configuration of the discrimination circuit 282. The determination circuit 282 according to the present example determines the maximum number (n) of count values COUNT.
Is an effective circuit when is a power of 2 or a number close to this, and has a very simple circuit configuration.

Discrimination circuit 28 according to the example shown in FIG.
2 is an exclusive OR (EXOR) circuit 285 to 287
And a NOR (NOR) circuit 288 and a logical product (AN
D) circuit 289. Further, as shown in FIG. 16A, the exclusive OR (EXOR) circuit 285 has the most significant bit (bit1 = MS) of the count value COUNT.
B) and the second upper bit (bit 2) are supplied to the exclusive OR (EXOR) circuit 286 and the count value COU
The most significant bit (bit 1) and the upper 3rd bit (bit 3) of NT are supplied, and the outputs of these exclusive OR (EXOR) circuits 285 and 286 are exclusive OR (EXOR) circuit 287 and negative logic. It is commonly supplied to a sum (NOR) circuit 288 and a logical product (AND) circuit 289.

The truth table of the discrimination circuit 282 according to this example is as shown in FIG. 16B, and when bit1 to bit3 are "000" (count value COUNT <n /
8) or "111" (count value COUNT
≧ n7 / 8), the selection signal dam1 becomes a high level (active state), and bit1 to bit3 are “001” or “010” (n / 8 ≦ count value COUNT).
<3n / 8) or when bit1 to bit3 are “101” or “110” (5n / 8 ≦ count value COUNT)
When T <7n / 8), the selection signal dam2 becomes a high level (active state), and bit1 to bit3 are “011” or “100” (3n / 8 ≦ count value COU).
At NT <5n / 8, the selection signal dam3 becomes high level (active state).

With the above configuration, also in the discrimination circuit 282 according to the example shown in FIG. 16A, when the load applied to the line of the voltage Vm is the region 1 or the region 5, the selection signal dam1 is activated and the voltage When the load applied to the line of Vm is the region 2 or the region 4, the selection signal dam2 can be activated, and when the load applied to the line of the voltage Vm is region 3, the selection signal dam3 can be activated. .

FIG. 17 is a circuit diagram of the adjusting circuit 290-1.

As shown in FIG. 17, adjustment circuit 290-1
Is composed of dummy resistors 291 to 293 having different resistance values and switches 294 to 296 provided corresponding to the dummy resistors 291 to 293, respectively, whereby a dummy is provided between the output terminal 204 and the ground potential (GND). A series body including a resistor 291 and a switch 294, a series body including a dummy resistor 292 and a switch 295, and a series body including a dummy resistor 293 and a switch 296 are connected in parallel. Dummy resistors 291 to
Although the specific resistance value of 293 is not particularly limited,
Set the resistance values of the dummy resistors 291 to 293 to R291.
~ R293, R291>R292> R293
Is set to.

Further, the selection signals dam1 to dam3 are supplied to the switches 294 to 296, respectively, and the switches are turned on when the corresponding selection signals are activated. Therefore, the resistance value between the output terminal 204 and the ground potential (GND) becomes R291 when the selection signal dam1 is in the active state, and becomes R292 when the selection signal dam2 is in the active state. , Selection signal dam3
Is active, R293 is set. In other words, the resistance value between the output terminal 204 and the ground potential (GND) is such that the load applied to the line of the voltage Vm is in the region 1
Or “large” in the case of the region 5, “medium” in the case where the load applied to the line of the voltage Vm is the region 2 or the region 4,
When the load applied to the line of the voltage Vm is in the region 3, it is “small”.

The above is the power supply device 200 according to the present embodiment.
It is the structure of. In this embodiment, with such a configuration, the larger the load on the line of the voltage Vm (output terminal 203), the larger the output terminal 204 and the ground potential (GND).
And the ON time of the switching element 231 becomes longer, so that the voltage drop of the line of the voltage Vm (the output terminal 203) due to the change of the load state is effectively suppressed. Therefore, the brightness of the pixel 103 can be maintained at a desired level.

Next, the operation of the controller 150 will be described.

The controller 150 is a circuit for controlling the operation of the entire inorganic EL display device, receives a video signal supplied from the outside, and generates a column selection signal C_select and a row selection signal R_select based on the video signal. Timing signals Vm_charge and Vm_discharg for controlling the operation timing of the voltage control circuit 130.
e, Vm / 2_charge and Vm / 2_discharge, and
Timing signals P_charge, P_discharge, N_char for controlling the operation timing of the row voltage control circuit 140.
Generate ge and N_discharge. Of the various signals generated by the controller 150, the column voltage control circuit 1
The waveforms of the timing signal for controlling the operation timing of the operation signal 30 and the waveform of the timing signal for controlling the operation timing of the low voltage control circuit 140 will be described later.

The column selection signal C_select is a signal supplied to the column driver 110 and the power supply device 200, and the column driver 110 outputs the column selection signal C_selec.
Based on t, the data wiring 101 corresponding to the pixel 103 to be turned on is selected from the _n data wirings 101 _{1 to} 101 _n . As described above, the voltage Vm is applied to the selected data line 101 in the positive direction drive, and the ground potential (GND) is applied to the negative direction positive drive. On the other hand, the row selection signal R
_select is a signal supplied to the row driver 120, and the row driver 120 sequentially selects (scans) the _m scanning lines 102 _{1 to} 102 m based on the row selection signal R_select. As described above, the voltage −Vth is applied to the scanning wiring 102 in the selected state in the positive direction driving, and the voltage Vth + Vm is applied in the negative positive direction driving.

FIG. 18 is a circuit diagram showing a specific configuration of the column voltage control circuit 130 and the column driver 110.

As shown in FIG. 18, the column voltage control circuit 130 is composed of switches 131a to 131d, diodes 132a to 132d, a capacitor 133, and an inductor 134. Switches 131a-1
The control signal of 31d has a timing signal Vm /
2_charge, Vm / 2_discharge, Vm_charge and Vm
_discharge is supplied, and the switches 131a to 13a
1d becomes conductive when the corresponding timing signal becomes high level and becomes non-conductive when it becomes low level.

As shown in FIG. 18, one end of the switch 131a and one end of the switch 131b are connected to the capacitor 133.
Is commonly connected to one end of the capacitor 133, and a ground potential (GND) is applied to the other end of the capacitor 133. The other end of the switch 131a is connected to the anode of the diode 132a, and the other end of the switch 131b is connected to the cathode of the diode 132b. Diode 13
The cathode of 2a and the anode of the diode 132b are commonly connected to the contact A. On the other hand, the voltage V is applied to one end of the switch 131c and one end of the switch 131d, respectively.
m and ground potential (GND). The other ends of the switch 131c and the switch 131d are commonly connected to serve as an output end of the pulse voltage VmD, and the pulse voltage VmD is supplied to the column driver 110 as shown in FIG.

Further, the inductor 134 is connected between the contact A and the output end of the pulse voltage VmD. Furthermore, the anode of the diode 132c and the diode 13
The cathode of 2d is commonly connected to the contact A, and the voltage Vm is applied to the cathode of the diode 132c.
The ground potential (GN) is applied to the anode of the diode 132d.
D) is given. The inductor 134 resonates with the load capacitance of the inorganic EL panel 100 to efficiently charge and discharge the load capacitance.

In the column voltage control circuit 130 having such a configuration, the timing signal Vm / 2_charg
e, Vm / 2_discharge, Vm_charge and Vm_dischar
The switches 131a to 131d are sequentially turned on based on ge, whereby the pulse voltage VmD has a pulse waveform having an amplitude from the ground potential (GND) to the voltage Vm.

Further, as shown in FIG.
The bar 110 is supplied from the column voltage control circuit 130.
Contact between the pulse voltage VmD and the ground potential (GND)
Switch 111a continued₁~ 111a_nAnd switch
111b₁~ 111b_nN series circuit consisting of
And a control circuit 112 for controlling the operation of these switches.
Data corresponding to the connection point of each switch.
Wiring 101₁~ 101 _nBecomes The control circuit 112 is
Voltages CVDD and CVSS provided by source device 200
Is a logic circuit that operates using the
Operation of the column voltage control circuit 130 based on C_select
In synchronization with the switch 111a₁~ 111a_nAnd Sui
111b₁~ 111b_nControl on / off of.

In such control, one of the two switches forming each series circuit is in the conductive state and the other is in the non-conductive state, whereby the pulse voltage VmD and the ground potential (GND) are applied to each data line 101. Either one will be supplied. Specifically, when driven in the forward direction, a pulse voltage VmD is applied to the data line 101 corresponding to the pixel 103 to be turned on, and a ground potential (GND) is applied to the data line 101 corresponding to the pixel 103 to be turned off. When supplied, and conversely, when driven in the negative direction, the data wiring 1 corresponding to the pixel 103 to be turned on.
01 is a ground potential (GND), and a pulse voltage Vm is applied to the data wiring 101 corresponding to the pixel 103 to be turned off.
D is supplied.

FIG. 19 is a timing chart showing the operations of the column voltage control circuit 130 and the column driver 110.

As shown in FIG. 19, first, when the timing signal Vm / 2_charge is set to a high level and the switch 131a is turned on, the charge charged in the capacitor 133 is changed to the switch 131a and the diode 132.
The column driver 110 via the a and the inductor 134.
Is supplied to. Thus, among the switches 111a ₁ ~111a _n connected to the pulse voltage VmD side capacitance of the pixel 103 corresponding to the switches in a conductive state (panel capacitance) and the inductor 134 resonates, the capacitor 133 is As it is discharged, the panel capacity is charged.

Next, almost simultaneously with the end of such resonance, the timing signal Vm / 2_charge is set to the low level and the timing signal Vm_charge is set to the high level, and when the switch 131c is turned on, the pulse voltage VmD is clamped to the voltage Vm. The panel capacity is completely charged.

Several microseconds to several tens of microseconds from the completion of such charging
After ec, the timing signal Vm_charge is set to a low level and the timing signal Vm / 2_discharge is set to a high level in order to discharge the charged panel capacitance, and when the switch 131b is turned on, the charge stored in the panel capacitance is charged. Is inductor 134, diode 13
2b and the switch 131b, and returns to the capacitor 133. As a result, the panel capacitance and the inductor 134 resonate, the panel capacitance is discharged, and the capacitor 133 is charged.

When the timing signal Vm / 2_discharge is set to the low level and the timing signal Vm_discharge is set to the high level almost at the end of such resonance, the pulse voltage Vm is set when the switch 131d becomes conductive.
D is clamped to the ground potential (GND) and the discharge of the panel capacitance is completed.

On the side of the column voltage control circuit 130,
By repeating such an operation, the voltage Vm
To the ground potential (GND), a pulse voltage VmD having an amplitude is generated.

On the other hand, on the column driver 110 side, as shown in FIG. 19, the output content of the control circuit 112 is changed in synchronization with the operation of the column voltage control circuit 130. Therefore, the voltage of each data line 101 becomes Vm when the switch on the pulse voltage VmD side among the two switches forming the corresponding series circuit is on, and the switch on the ground potential (GND) side is on. When it does, it becomes the ground potential (GND).

FIG. 20 is a circuit diagram showing a specific configuration of the row voltage control circuit 140 and the row driver 120.

As shown in FIG. 20, the row voltage control circuit 1
40 is a switch 141a-141d and the diode 1
42a-142d and inductors 143a and 143b
Composed of and. The control electrodes of the switch have P_charge, P_discharge, N_charge and N_disch, respectively.
arge is supplied, and switches 141a to 141d
Are conductive when the corresponding timing signals are high level, and are non-conductive when they are low level.

As shown in FIG. 20, the switches 141a ...
141d is connected in series between the terminal to which the voltage Vth + Vm is supplied and the terminal to which the voltage −Vth is supplied. Similarly, the diodes 142a to 142d are also connected to the voltage Vth.
It is connected in series between the terminal supplied with th + Vm and the terminal supplied with voltage −Vth. Diode 142
The connection point between the anode of a and the cathode of the diode 142b becomes the output terminal of the pulse voltage VSP, and the diode 14
The connection point between the anode of 2c and the cathode of the diode 142d becomes the output end of the pulse voltage VSN. Both the pulse voltage VSP and the pulse voltage VSN are supplied to the row driver 120.

The inductor 143a is connected to the switch 1
41a and the switch 141b are connected between the common connection point and the output terminal of the pulse voltage VSP, and the inductor 1
43b is connected between the common connection point of the switches 141c and 141d and the output end of the pulse voltage VSN. Further, the anode of the diode 142c and the cathode of the diode 142c have a ground potential (GN).
D) is given.

In the row voltage control circuit 140 having such a configuration, the timing signals P_charge and P_disc are used.
The switches 141a to 141d are sequentially turned on based on harge, N_discharge, and N_charge, whereby the pulse voltage VSP has a pulse waveform having an amplitude from the ground potential (GND) to the voltage Vth + Vm, and the pulse voltage VSN is the voltage. -Vth to ground potential (G
The pulse waveform has an amplitude up to ND).

In addition, as shown in FIG. 20, a row driver
120 is a pulse supplied from the row voltage control circuit 140.
Switch 12 connected between the voltage VSP and VSN
1a ₁~ 121a_mAnd switch 121b₁~ 121b
_mThe operation of these switches with m series circuits consisting of
The control circuit 122 for controlling the
Scanning wiring 102 with corresponding connection points₁-10_m
Becomes The control circuit 122 is supplied from the power supply device 200.
Of operating with the supplied voltages RVDD and RVSS as power sources
It is a logic circuit, and the row is selected based on the row selection signal R_select.
The switch 121 is synchronized with the operation of the voltage control circuit 140.
a₁~ 121a_mAnd switch 121b ₁~ 121b_m
Control on / off of.

In such control, one switch of the series circuit corresponding to the selected scanning wiring 102 is turned on and the other is turned off, whereby the selected scanning wiring 102 receives the pulse voltage Vth + Vm and Either one of the pulse voltage −Vth will be supplied. Specifically, when driven in the forward direction, the pulse voltage Vth + Vm is supplied to the selected scan wiring 102,
On the contrary, when driven in the negative direction, the selected scan wiring 10
The pulse voltage −Vth is supplied to 2. In addition, in the series circuit corresponding to the other scanning lines 102 that are not selected, both switches are in the non-conduction state, so that the scanning lines 102 that are not selected are in the high impedance state (HiZ).

The operations of the row voltage control circuit 140 and the row driver 120 differ depending on how the positive direction driving and the negative direction driving are switched, that is, the driving method on the row side. The driving method on the row side is not particularly limited, but in the first frame, the scanning wirings 102 assigned with odd numbers are driven in the positive direction, the scanning wirings 102 assigned with even numbers are driven in the negative direction, and conversely, Scan wiring 102 assigned an odd number in the frame
Drive in the negative direction, scan wiring 10 assigned an even number
2 in the positive direction (first driving method), all scanning wirings 102 in the first frame are driven in the positive direction, and all scanning wirings 102 in the next frame are driven in the negative direction (second driving method). Driving method), and in the first frame, the positive direction driving / negative direction driving is switched for every several continuous scanning wirings 102, and in the next frame, the group driven in the positive direction in the previous frame is changed to the negative direction. It is possible to use a method (third driving method) or the like in which the pair is driven in the direction and driven in the negative direction in the previous frame in the positive direction.

When the first driving method is used, since the positive direction driving and the negative direction driving are switched for each scan, the load applied to the line of the voltage Vth + Vm and the voltage −V.
The load applied to the th line becomes equal within a short unit time, and the capacitors 255, 25 of the power supply device 200
7 and the switching frequency of the switching element 231 can be set low. However, since the positive direction driving and the negative direction driving are switched for each scan, the inorganic EL panel 1
In some cases, the vibration frequency of 00 itself becomes high and audible noise is noticeable.

On the other hand, when the second driving method is used, positive direction driving and negative direction driving are switched for each frame, so that the vibration frequency of the inorganic EL panel 100 itself is low and audible noise is suppressed. However, in one frame, the power from one of the voltage Vth + Vm line and the voltage-Vth line continues to be consumed, and the other power is hardly consumed. Therefore, in some cases, the capacitances of the capacitors 255 and 257 may be increased. Alternatively, the switching frequency of the switching element 231 needs to be set high.

Thus, the merits of the first driving method
The disadvantages and the advantages and disadvantages of the second driving method are in the opposite relationship. Therefore, when audible noise is conspicuous when the first driving method is used, the scanning wiring 102 is divided into a plurality of groups as in the third driving method.
It is effective to switch between positive direction driving and negative direction driving for each set. According to this, it is possible to suppress the audible noise while setting the capacities of the capacitors 255 and 257 to some extent small and setting the switching frequency of the switching element 231 to some extent low.

Next, the operations of the row voltage control circuit 140 and the row driver 120 when the first driving method is used will be described.

FIG. 21 is a timing chart showing the operations of the row voltage control circuit 140 and the row driver 120.

As shown in FIG. 21, first, when the timing signal P_charge is set to the high level and the switch 141a is turned on, the voltage Vth + Vm supplied from the power supply device 200 is output to the output terminal of the pulse voltage VSP via the inductor 143a. Is supplied to. As a result, the pulse voltage VSP rises to the voltage Vth + Vm. next,
After the timing signal P_charge is set to low level, the timing signal P_discharge is set to high level. As a result, when the switch 141b becomes conductive, the pulse voltage VS
Since the output terminal of P is grounded via the inductor 143a, the pulse voltage VSP is equal to the ground potential (GND).
Falls to.

Next, the timing signal N_charge is set to high level, and when the switch 141d becomes conductive, the voltage -Vth supplied from the power supply device 200 is supplied to the output end of the pulse voltage VSN via the inductor 143b. As a result, the pulse voltage VSN becomes equal to the voltage −V.
to th. Next, after the timing signal N_charge is set to low level, the timing signal N_discharge is set to high level. As a result, when the switch 141c is turned on, the output terminal of the pulse voltage VSN is connected to the inductor 14
Since it is grounded via 3b, the pulse voltage VSN
Rises to the ground potential (GND).

On the row voltage control circuit 140 side, by repeating such an operation, the pulse voltage VSP having the amplitude from the ground potential (GND) to the voltage Vth + Vm and the ground potential (GND) to the voltage −Vth. A pulse voltage VSN having an amplitude of is generated. Here, the effective pulse of the pulse voltage VSP (voltage V
The state where the voltage rises to th + Vm) occurs every other scan timing, and similarly, the effective pulse of the pulse voltage VSN (the state where the pulse voltage decreases to −Vth) also occurs every one scan timing. However, as shown in FIG. 21, the waveform of the pulse voltage VSP and the waveform of the pulse voltage VSN are 180 degrees out of phase with each other, and effective pulses of the pulse voltage VSP and the pulse voltage VSN do not occur at the same time.

On the other hand, on the row driver 120 side,
As shown in FIG. 21, the output content of the control circuit 122 is changed in synchronization with the operation of the row voltage control circuit 140. Therefore, the voltage of the selected scanning wiring 102 constitutes the corresponding series circuit when driven in the forward direction.
Of the two switches, the switch on the pulse voltage VSP side is turned on to Vth + Vm, and in the case of being driven in the negative direction, the switch on the pulse voltage VSN side of the two switches forming the corresponding series circuit is It becomes conductive and becomes -Vth. In addition, the other scan wirings 102 that are not selected are in a high impedance state because both of the two switches that form the corresponding series circuit are in a non-conductive state.

Hereinafter, the voltage applied to the selected scan wiring 102 will be referred to as the scan voltage VSCAN, and the voltage on the predetermined data wiring 101 will be referred to as the modulation voltage VMMOD, which will be referred to as the scan voltage VSCAN when the first driving method is used. The relationship with the modulation voltage VMMOD will be described.

FIG. 22 is a timing chart showing the relationship between the scan voltage VSCAN and the modulation voltage VMMOD when the first driving method is used. Note that FIG. 22 also shows the waveform of the pulse voltage VmD.

As shown in FIG. 22, when the first driving method is used, the scan voltage VSCAN is equal to the pulse voltage Vm.
Each time the voltage of D rises to Vm, the polarity is inverted. In this case, the timing at which the scan voltage VSCAN reaches the peak value (voltage Vth + Vm or voltage −Vth) is preferably slightly delayed from the timing at which it reaches the peak value (voltage Vm) of the pulse voltage VmD, as shown in FIG. (In FIG. 22, such a delay is described as “delay”). In this way, the load on the power supply device 200 can be dispersed over time.

Further, the period in which the effective pulse of the scan voltage VSCAN is the voltage Vth + Vm is the period driven in the positive direction, and the period of the voltage −Vth is the period driven in the negative direction. Here, as shown in FIG. 22, when the modulation voltage VMMOD is at the ground potential (GND) in the positive direction driving period, and in the negative direction driving period, the modulation voltage VMMOD is generated.
Is the voltage Vm, the corresponding pixel 103 is turned on. On the other hand, when the modulation voltage VMMOD is the voltage Vm in the positive direction driving period and when the modulation voltage VMMOD is the ground potential (GND) in the negative direction driving period, the corresponding pixel 103 is not lit. It becomes a state.

Therefore, each of the data wirings 101 ₁ to 10 ₁
By setting the voltage of 1 _n to Vm or the ground potential (GND), each pixel 103 on the selected scan wiring 102 can be turned on or off, so that the scan wiring 102 to be selected is sequentially switched. However, by setting the voltage of each of the data wirings 101 _{1 to} 101 _n to Vm or the ground potential (GND), it becomes possible to display desired characters, figures, etc. on the inorganic EL panel 100.

Thus, the inorganic EL according to this embodiment
In the display device, by providing the load state determination circuit 280 and the adjustment circuit 290-1 in the power supply device 200, the output terminal 204 and the ground potential (G
Since the resistance value between (ND) and (ND) is lowered, it is possible to effectively suppress the voltage drop in the line (output terminal 203) of the voltage Vm due to the change in the load state.

In the above embodiment, by using the load state discriminating circuit 280 and the adjusting circuit 290-1, the output terminal 204 and the ground potential (GND) are grounded based on the load state of the line of the voltage Vm (output terminal 203). ) Is changed in three steps, but the resistance value is changed in four steps or more by finely determining the load state of the line (output terminal 203) of the voltage Vm, and finer adjustment is made. Alternatively, the resistance value may be changed only in two stages by determining the load state of the line of the voltage Vm (output terminal 203) in two stages, and the circuit configuration may be simplified. Absent.

Further, in the above-mentioned embodiment, the adjustment according to each load state is performed by turning on any of the switches 294 to 296 included in the adjustment circuit 290-1. The switches may be turned on at the same time. For example, resistors 291 to 293
14 are set equal to each other, and when the load applied to the line of the voltage Vm is the region 1 or the region 5 shown in FIG. 14, only one switch is turned on, and the load applied to the line of the voltage Vm is shown in FIG. When the region is the region 2 or the region 4 shown, two switches are made conductive, and when the load applied to the line of the voltage Vm is the region 3 shown in FIG. 14, all the switches (three) may be made conductive. Absent. Further, a variable resistor may be used as a dummy resistor in the adjustment circuit 290-1 and the resistance value may be changed by this.

Furthermore, in the above embodiment, the adjusting circuit 290-1 is connected between the output terminal 204 (voltage-Vth line) and the ground potential (GND), but instead, as shown in FIG. , The adjustment circuit 290-2 having the same circuit configuration as the adjustment circuit 290-1 is output terminal 2
03 (line of voltage Vm) and the ground potential (GND). In this case, contrary to the above-described embodiment, the larger the load on the line of the voltage Vm, the larger the output terminal 203 (line of the voltage Vm) and the ground potential (GN).
D) The resistance between the output terminal 203 (the line of the voltage Vm) and the ground potential (GND) is made smaller as the load applied to the line of the voltage Vm becomes smaller. It is possible to suppress the voltage drop in the line of the voltage Vm (output terminal 203) due to.

As shown in FIG. 24, the output terminal 20
4 (voltage-Vth line) and ground potential (GND)
An adjustment circuit 290-1 is provided between the output terminal 2 and
03 (line of voltage Vm) and the ground potential (GND), the adjustment circuit 290-2 may be provided. in this case,
As for the adjusting circuit 290-1, the resistance between the output terminal 204 (voltage-Vth line) and the ground potential (GND) is decreased as the load applied to the voltage Vm line is increased as described above. Is the voltage Vm
The larger the load on the line is, the larger the resistance between the output terminal 203 (the line of the voltage Vm) and the ground potential (GND) may be.

Next, another preferred embodiment of the present invention will be described.

FIG. 25 is a circuit diagram of a power supply device 300 according to another preferred embodiment of the present invention. As shown in FIG. 25, the power supply device 300 according to the present embodiment is the same as the power supply device 200 according to the above-described embodiment.
A part for generating a voltage (Vm) to be applied to 1 _{1 to} 101 _n is separated from the other parts and has an independent structure. In FIG. 25, the same components as those of the power supply device 200 according to the above-mentioned embodiment are designated by the same reference numerals, and the duplicated description thereof will be omitted.

As shown in FIG. 25, the power supply device 300 according to this embodiment has a primary winding 221 and a secondary winding 222.
And a switching element 241 provided on the primary side of the transformer 220, a control circuit 242 for controlling the switching element 241, and an output circuit provided on the secondary side of the transformer 220. The output circuit provided on the secondary side of the transformer 220 includes a diode 261 having an anode connected to one end of the secondary winding 222 and a cathode connected to the output terminal 203, an output terminal 203 and a secondary winding 222. It is composed of a capacitor 262 connected between the terminals and these, and these constitute an output circuit for the output voltage Vm. The other end of the secondary winding 212 of the transformer 210 is connected to the wiring 2
It is connected to the output terminal 203 via 97.

The control circuit 242 has an input terminal 242a to which the voltage Vm is supplied, an input terminal 242b to which the sawtooth wave CT is supplied, and an output terminal 242c which outputs the PWM signal 241a, and is supplied to the input terminal 242a. The PWM signal 2 so that the received voltage Vm becomes stable.
Adjust the pulse width of 41a. As shown in FIG. 25, since the sawtooth wave CT supplied from the sawtooth wave generation circuit 270 is commonly supplied to the control circuit 232 and the control circuit 242, the switching operation of the switching element 231 and the switching operation of the switching element 241 are performed. The operation is synchronized with any of the sawtooth waves CT.
A circuit similar to the circuit shown in FIG. 11 can be used as a specific circuit of the control circuit 242.

In the present embodiment, the voltage −Vt
A load state determination circuit 380 that determines the state of the load occurring on the h line (output terminal 204) and an adjustment circuit 290 that adjusts the load applied to the voltage-Vth line (output terminal 204) according to the load state. 3 and 3 are provided.

As the circuit configuration of the load state determination circuit 380, the same circuit configuration as the load state determination circuit 280 shown in FIG. 11 can be used, and the determination circuit 2 included therein.
Reference numeral 82 activates one of the selection signals dam4 to dam6 based on the count value COUNT of the counter 281. As the reference, when the count value COUNT is 0 or in the vicinity thereof, the selection signal dam4 is activated, and when the count value COUNT is n or in the vicinity thereof, the selection signal dam6 is activated. If the above does not apply, the selection signal dam5 is activated. As shown in FIG. 26, which of the selection signals is activated coincides with the state of the load applied to the line (output terminal 204) of the voltage −Vth corresponding to the row side, and is applied to the voltage −Vth line. When the load is small (region 1 or region 2), the selection signal dam4 is activated and the voltage −Vt
When the load applied to the h line is large (region 4 or 5), the selection signal dam6 is activated, and when the load applied to the voltage-Vth line is in the middle (region 3), the selection signal dam5 is activated. Will be changed. Incidentally, FIG.
Areas 1 to 5 shown in 6 correspond to the areas 1 to 5 shown in FIG.

The specific configuration of the determination circuit 282 in the load state determination circuit 380 is not particularly limited in the present invention as long as it can activate any of the selection signals dam4 to dam6 based on the above-mentioned criteria. Alternatively, a circuit including a plurality of comparison circuits 283 and logic circuits 284 may be used as described with reference to FIG. 15, or based on the upper bits of the COUNT value as described with reference to FIG. It is also possible to use a plurality of gate circuits that generate the selection signals dam4 to dam6. The adjustment circuit 290-3 is the adjustment circuit 290-1 described above.
A circuit similar to can be used.

With the above configuration, in the power supply device 300 according to the present embodiment, the larger the load applied to the voltage-Vth line (output terminal 204), the more the output terminal 204 becomes.
And the resistance value between the ground potential (GND) and
As a result, the ON time of the switching element 231 becomes longer, so that the voltage drop of the voltage-Vth line (output terminal 204) due to the change in the load state is effectively suppressed. Therefore, the brightness of the pixel 103 can be maintained at a desired level.

Moreover, in the present embodiment, the portion for generating the voltage (Vm) to be applied to the data wirings 101 _{1 to} 101 _n is separated from the other portions and has an independent structure. , Data wiring 101 _{1 to} 101
_The voltage (Vm) to be applied to _n and the scanning wirings 102 ₁ to 1
Both of the voltages (-Vth) to be applied to 01 _m can be stabilized more accurately.

Further, in the present embodiment, since the control circuit 232 and the control circuit 242 use the common sawtooth wave CT, both the switching operation of the switching element 231 and the switching operation of the switching element 241 are performed. It becomes synchronized with the sawtooth wave CT. Therefore, the secondary side of the transformer 210 and the transformer 22
Although the secondary side of 0 is connected via the wiring 297, these transformers 210 and 220 almost never interfere with each other, and therefore the wiring 29
The abnormal oscillation due to the connection by 7 is effectively suppressed.

In the above embodiment, the control circuit 2
These operations are synchronized by supplying a common sawtooth wave CT to 32 and 242.
It is not essential to use a common sawtooth wave CT as long as the operation of 32 and the operation of the control circuit 242 are synchronized.

Therefore, for example, as shown in FIG. 27, the first sawtooth wave CT1 and the first sawtooth wave CT
By using a second sawtooth wave CT2 having a frequency that is an integral multiple of 1 (twice in FIG. 27), one of them is supplied to the control circuit 232, and the other is supplied to the control circuit 242 to synchronize them. May be secured. In this case, in order to synchronize the operation of the control circuit 232 and the operation of the control circuit 242, the timing when the first sawtooth wave CT1 reaches the peak value and the timing when the second sawtooth wave CT2 reaches the peak value are substantially set. Need to be matched.

Further, in this case, it is preferable to supply the sawtooth wave (CT2) having a high frequency to the control circuit corresponding to the portion of the power supply device 300 where the load is heavy. Therefore, as described above, as the size of the inorganic EL panel 100 is larger, the load applied to the voltage line Vm corresponding to the column side is larger than the load applied to the voltage line Vth + Vm or the voltage line −Vth corresponding to the row side. In the usual inorganic EL panel 100, the load applied to the voltage line Vm corresponding to the column side is more likely to be the voltage line Vth + Vm or the voltage line −V corresponding to the row side.
It is preferable that the second sawtooth wave CT2 having a high frequency is supplied to the control circuit 242 and the first sawtooth wave CT1 having a low frequency is supplied to the control circuit 232 because the load is larger than the load applied to th.

In the above embodiment, by using the load state determining circuit 380 and the adjusting circuit 290-3, the output terminal 204 and the ground potential (based on the load state of the line of voltage −Vth (output terminal 204)) GND)
The resistance value between and is changed in 3 steps, but the voltage -V
The load value of the th line (output terminal 204) may be more finely discriminated to change the resistance value in four or more steps for finer adjustment. Conversely, the voltage-Vth line (output terminal) may be adjusted. By making the determination of the load state of 204) in two stages, the resistance value may be changed in only two stages, and the circuit configuration may be simplified. Also, a plurality of switches included in the adjusting circuit 290-3 may be turned on at the same time according to the load state, and the adjusting circuit 29 may be turned on.
A variable resistor may be used as a dummy resistor in 0-3, and the resistance value may be changed by this.

Furthermore, in the above embodiment, the adjusting circuit 290-3 is connected between the output terminal 204 (voltage-Vth line) and the ground potential (GND), but instead, as shown in FIG. , The adjustment circuit 290-4 having the same circuit configuration as the adjustment circuit 290-3 is output terminal 2
03 (line of voltage Vm) and the ground potential (GND). In this case, the adjusting circuit 290-4
A load state determination circuit 280 is used as a circuit for controlling the voltage V.
The larger the load applied to the m line, the output terminal 203
The resistance between (the line of voltage Vm) and the ground potential (GND) is reduced, and conversely, the smaller the load applied to the line of the voltage Vm, the resistance between the output terminal 203 (line of the voltage Vm) and the ground potential (GND). Should be increased. Accordingly, the larger the load applied to the line of the voltage Vm, the longer the ON time of the switching element 241, so that the voltage drop of the line of the voltage Vm (the output terminal 203) due to the change of the load state is effectively suppressed. . Therefore, the brightness of the pixel 103 can be maintained at a desired level.

As shown in FIG. 29, the output terminal 20
4 (voltage-Vth line) and ground potential (GND)
An adjustment circuit 290-3 is provided between the output terminal 2 and
03 (line of voltage Vm) and the ground potential (GND) may be provided with the adjusting circuit 290-4. in this case,
As for the adjusting circuit 290-3, as described above, the voltage -Vt.
The larger the load applied to the h line, the more the output terminal 204
In the adjustment circuit 290-4, the resistance between the (voltage-Vth line) and the ground potential (GND) is reduced, and as the load applied to the voltage Vm line increases, the output terminal 20 increases.
The resistance between 3 (line of voltage Vm) and the ground potential (GND) may be reduced.

Next, still another preferred embodiment of the present invention will be described.

FIG. 30 is a circuit diagram of a power supply device 400 according to still another preferred embodiment of the present invention. Figure 30
As shown in, the power supply device 400 according to the present embodiment is
A control circuit 24 provided in the power supply device 300 shown in FIG.
2 is replaced with the control circuit 442. Since other configurations are similar to those of the power supply device 300 according to the above-described embodiment, the same components are designated by the same reference numerals, and the duplicate description will be omitted.

The control circuit 442 has an input terminal 442a supplied with a voltage -Vth, an input terminal 442b supplied with a sawtooth wave CT, an input terminal 442d supplied with a voltage Vth + Vm, and an output for outputting a PWM signal 241a. And a terminal 442c for receiving the voltage Vm supplied to the input terminal 442a and adjusting the pulse width of the PWM signal 241a so as to stabilize the voltage Vm.
When Vm becomes an overvoltage state, the PWM signal 241
The pulse width of a is narrowed rapidly.

FIG. 31 is a circuit diagram of the control circuit 442. As shown in FIG. 31, the control circuit 442 is different from the control circuit 242 in that the photo coupler 401 and the resistors 402 and 4 are provided.
03, the transistor 404, and the Zener diode 4
05 and 05 are added. Since other configurations are similar to those of the control circuit 242 described above,
The same components are designated by the same reference numerals, and duplicate description will be omitted.

The photocoupler 401 comprises a light emitting side element 401a.
And a light receiving side element 401b, and a light emitting side element 401a
Is connected to the secondary side power supply Vcc2 via the resistor 402, and the other end of the light emitting side element 401a is connected to the transistor 404.
Is connected to the ground potential (GND) via. The light-receiving side element 401b of the photocoupler 401 is connected between the non-inverting input terminal (+) of the comparator 309 and the ground potential (GND).

The Zener diode 405 has an anode connected to the base electrode of the transistor 404 and a cathode connected to the input terminal 442d. The resistor 403 is connected between the base electrode of the transistor 404 and the ground potential (GND), and is connected to the transistor 40.
This prevents the base electrode of No. 4 from floating.

In the control circuit 442 having such a structure, the voltage Vth + supplied to the input terminal 442d is increased.
When Vm is less than the predetermined value (normal state), the transistor 404 remains in the non-conducting state, and therefore operates exactly the same as the control circuit 242 described above. On the other hand, when the voltage Vth + Vm supplied to the input terminal 442d becomes overvoltage and exceeds the breakdown voltage of the Zener diode 405, the transistor 404 becomes conductive. As a result, a current flows through the light emitting side element 401a of the photocoupler 401 to emit light, and a current also flows through the light receiving side element 401b of the photocoupler 401 that receives the current. For this reason, the feedback voltage FB, which is the level of the non-inverting input terminal (+) of the comparator 309, rapidly decreases, and as a result, the pulse width of the PWM signal 241a, which is the output of the comparator 309, is significantly narrowed.

Here, the overvoltage state of voltage Vth + Vm is likely to occur in the following cases. In other words, the number of pixels 103 that should be turned on during the forward drive is large, so that the addition applied to the line of the voltage −Vth becomes large (see FIG. 9A) and its level rises (close to the ground potential). ) And the control circuit 232 monitoring the voltage −Vth, the PWM signal 2 in order to reduce it.
The pulse width of 41a is made wider. PWM signal 241a
Although the voltage Vth + Vm rises when the pulse width of the PWM signal becomes wider, the control circuit 232 does not monitor the voltage Vth + Vm. Therefore, the pulse width of the PWM signal 241a is not narrowed based on this and therefore When the addition of the line of the voltage Vth + Vm is small, the voltage Vth + Vm may be in the overvoltage state. When the voltage Vth + Vm becomes an overvoltage state, the column driver 1
Since a large voltage is applied to the inorganic EL panel 100 (pixel 103) as well as 10 and the row driver 120,
These may be destroyed, and the reliability of the inorganic EL display device is reduced.

However, in the power supply device 400 according to this embodiment, when the voltage Vth + Vm becomes the overvoltage state, the voltage Vm is lowered by narrowing the pulse width of the PWM signal 241a. A voltage Vth + V generated by the supply of Vm
The level of m also decreases. Thereby, the inorganic EL panel 100, the column driver 110, and the row driver 1
It is possible to prevent the destruction of 20.

Here, in order to decrease the voltage Vth + Vm, the voltage Vm is decreased by using the control circuit 242 regardless of the control circuit 232. Generally, the load of the line of the voltage Vm is different from that of the other voltage lines. Because it is large compared to the load. Therefore, when the load of the voltage Vm line is not so large as compared with the loads of the other voltage lines, the voltage Vth + Vm may be directly reduced by narrowing the pulse width of the PWM signal 231a.

Also in the above embodiment, the adjusting circuit 290 is used.
-3 is connected between the output terminal 204 (voltage-Vth line) and the ground potential (GND), but instead, as described using FIG. 28, a circuit configuration similar to that of the adjustment circuit 290-3. Adjustment circuit 290-4 having an output terminal 2
03 (line of voltage Vm) and the ground potential (GND). Further, as described with reference to FIG. 29, the adjusting circuit 290-3 is provided between the output terminal 204 (voltage-Vth line) and the ground potential (GND), and the output terminal 203 (voltage Vm line) and ground are provided. The adjustment circuit 290-4 may be provided between the potentials (GND).

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. It goes without saying that it is a thing.

For example, in the above embodiment, the case where the power supply device 200, 300, 400 is used as a power supply device for an inorganic EL display device has been described as an example, but the application target of the power supply device according to the present invention is not limited to this. The present invention is not limited to this, and can be applied to any device as long as it requires a plurality of voltages.

[0162]

As described above, according to the present invention,
In a power supply device that requires a plurality of voltages (Vm, Vth + Vm, -Vth, etc.) like a power supply device for an inorganic EL display device, connect to at least one voltage line based on the load state of at least one voltage line Since the resistance value of the dummy resistance is changed, it is possible to effectively suppress the fluctuation of the output voltage due to the fluctuation of the load state.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing an overall configuration of an inorganic EL display device according to this embodiment.

2 is a diagram schematically showing a structure of a pixel 103, FIG.
(A) is the schematic plan view, (b) is a schematic sectional view taken along the line AA.

FIG. 3 is an equivalent circuit diagram of the pixel 103.

FIG. 4 is a graph showing emission characteristics of the pixel 103.

FIG. 5 shows the scanning wiring 10 selected by the forward drive.
FIG. 2 is a partial equivalent circuit diagram of the inorganic EL panel 100 when all the pixels 103 on 2-i are in a lighting state.

FIG. 6 is a scanning wiring line 10 selected by driving in a negative direction.
FIG. 2 is a partial equivalent circuit diagram of the inorganic EL panel 100 when all the pixels 103 on 2-i are in a lighting state.

FIG. 7 is a diagram showing a selected scanning wiring 102 in the forward drive.
FIG. 6 is a partial equivalent circuit diagram of the inorganic EL panel 100 when all the pixels 103 on −i are in a non-lighting state.

FIG. 8 is a diagram showing a selected scanning wiring 102 in the forward drive.
FIG. 7 is a partial equivalent circuit diagram of the inorganic EL panel 100 when a checker pattern is displayed on -i.

FIG. 9 is a graph schematically showing the relationship between the proportion of pixels that are turned on and the load applied to each voltage line,
(A) is the ratio of pixels that are turned on and the voltage line -V
The relationship between th and the load applied to the voltage line Vth + Vm is shown, and (b) shows the relationship between the proportion of pixels that are turned on and the load applied to the voltage line Vm.

FIG. 10 is a circuit diagram of a power supply device 200 according to the present embodiment.

FIG. 11 is a circuit diagram showing an example of a specific circuit configuration of a control circuit 232.

FIG. 12: PWM generated by comparator 309
It is a wave form diagram of signal 231a.

FIG. 13 is a circuit diagram showing a circuit configuration of a load state determination circuit 280.

FIG. 14 is a ratio of pixels that are turned on and a voltage line V
It is a graph which shows typically the relation with the area | region 1 of the load concerning m.

FIG. 15 is a circuit diagram showing an example of a specific circuit configuration of a discrimination circuit 282.

16A is a circuit diagram showing another example of a specific circuit configuration of the discrimination circuit 282, and FIG. 16B is a truth table of the circuit shown in FIG.

FIG. 17 is a circuit diagram of an adjustment circuit 290-1.

FIG. 18 is a circuit diagram showing a specific configuration of a column voltage control circuit 130 and a column driver 110.

FIG. 19 is a timing diagram showing operations of the column voltage control circuit 130 and the column driver 110.

FIG. 20 shows a row voltage control circuit 140 and a row driver 1.
It is a circuit diagram which shows the specific structure of 20.

FIG. 21 is a row voltage control circuit 140 and a row driver 1.
20 is a timing chart showing the operation of 20. FIG.

FIG. 22 is a timing chart showing the relationship between the scan voltage VSCAN and the modulation voltage VMMOD.

23 is a circuit diagram showing a modified example of the power supply device 200 shown in FIG.

24 is a circuit diagram showing a modified example of the power supply device 200 shown in FIG.

FIG. 25 is a circuit diagram of a power supply device 300 according to another preferred embodiment of the present invention.

FIG. 26 shows the ratio of pixels that are turned on and the voltage line.
It is a graph which shows typically the relation with the area | region 1 of the load concerning Vth.

FIG. 27 is a waveform diagram showing waveforms of a first sawtooth wave CT1 and a second sawtooth wave CT2.

28 is a circuit diagram showing a modified example of the power supply device 300 shown in FIG.

29 is a circuit diagram showing a modified example of the power supply device 300 shown in FIG.

FIG. 30 is a circuit diagram of a power supply device 400 according to still another preferred embodiment of the present invention.

FIG. 31 is a circuit diagram of a control circuit 442.

FIG. 32 is a circuit diagram of a conventional power supply device for an inorganic EL display device.

[Explanation of symbols]

100 inorganic EL panel 101 data lines 102 scanning lines 103 pixel 104 substrate 105a first dielectric layer 105b second dielectric layer 106 inorganic light-emitting layer 107 protective film 110 column drivers _{111a 1 ~111a n, 111b 1 ~111b} n switch 112 control circuit 120 row driver _{121a 1 ~121a m, 121b 1 ~121b} m switch 122 control circuit 130 column voltage control circuit 131a~131d switch 132a~132d diode 133 capacitor 134 inductor 140 row voltage control circuit 141a~141d switch 142a~142d Diode 143a, 143b Inductor 150 Controller 200, 300, 400 Power supply device 201 Input terminal 202-208 Output terminal 210, 220 Transformer 2 1,221 primary winding 212～216,222 secondary winding 231 and 241 switching elements 232,242,442 control circuit 232a, 232b, 242a, 242b, 442a,
442b, 442d input terminal 232c, 242c, 442c output terminal 250-254, 261 diode 255-259, 262 capacitor 270 sawtooth wave generation circuit 280, 380 load state determination circuit 281 counter 282 determination circuit 283a-283d comparison circuit 284 logic circuit 285 ˜287 Exclusive OR (EXOR) circuit 288 NOR (NOR) circuit 289 Logical product (AND) circuits 290-1 to 290-4 Adjustment circuits 291 to 293 Dummy resistors 294 to 296 Switch 297 Wiring 301 Error amplifier 302, 401 photo coupler 302a, 401a light emitting side element 302b, 401b light receiving side element 303-307, 402, 403 resistor 308 capacitor 309 comparator 404 transistor 405 zener diode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/30 G09G 3/30 J H05B 33/14 H05B 33/14 Z F term (reference) 3K007 AB17 BA06 DA05 GA04 5C080 AA06 BB05 DD05 EE01 EE17 EE28 FF03 FF12 5H730 AA04 AS01 AS19 BB23 BB82 EE02 EE73 FD03 FF02 FF19 FG05

Claims (9)

[Claims] 1. A power supply device that receives an input voltage, generates at least first and second output voltages having different voltages, and supplies these to a first output terminal and a second output terminal, respectively. A transformer for receiving the input voltage in the winding,
At least a switching element connected to the primary winding of the transformer; first and second output circuits connected to the secondary winding of the transformer to generate the first and second output voltages, respectively; A control circuit for controlling the operation of the switching element based on the first output voltage; and a state of a load generated in at least one of the first and second output terminals, based on the first and second And a means for changing a resistance value between at least one of the output terminals and a voltage line having a voltage different from the output terminal. 2. The means for reducing the resistance value between the first output terminal and the voltage line as the load generated at the second output terminal is larger. Power supply. 3. The means for increasing the resistance value between the second output terminal and the voltage line as the load generated at the second output terminal is larger. The power supply device according to. 4. The power supply device according to claim 1, wherein the voltage line is a ground line. 5. The transformer includes first and second transformers, and the switching element is a first switching element connected to a primary winding of the first transformer and a primary of the second transformer. A second switching element connected to the winding, wherein the first output circuit is connected to the secondary winding of the first transformer, and the second output circuit is connected to the second transformer. A first control circuit connected to a secondary winding, the control circuit controlling the operation of the first switching element based on the first output voltage, and the first control circuit based on the second output voltage. The power supply device according to claim 1, further comprising: a second control circuit that controls an operation of the second switching element. 6. The first and second control circuits are circuits for performing PWM control of the first and second switching elements, respectively, and the PW by the first and second control circuits is provided.
The power supply device according to claim 5, wherein the same sawtooth wave is used for the M control. 7. A PW by the first and second control circuits
In the M control, the first frequency in which one frequency is an integral multiple of the other frequency and the timings of the peak values substantially coincide with each other.
The power supply device according to claim 5, wherein a second sawtooth wave and a second sawtooth wave are used, respectively. 8. An inorganic EL panel having a plurality of scanning wirings and a plurality of data wirings, a row driver for driving the plurality of scanning wirings, a column driver for driving the plurality of data wirings, the row driver and the An inorganic EL display device comprising: a power supply device that generates a voltage used in a column driver, wherein the row driver operates based on at least a first output voltage supplied via a first output voltage line, The column driver operates based on a second output voltage supplied through at least a second output voltage line, and the power supply device includes a transformer receiving an input voltage at a primary winding and a primary of the transformer. A switching element connected to the winding, a secondary winding of the transformer and the first and second output voltage lines, respectively. Generated in at least one of the first and second output circuits, the control circuit that controls the operation of the switching element based on at least the first output voltage, and the first and second output voltage lines. And a means for changing a resistance value between at least one of the first and second output voltage lines and a voltage line having a voltage different from the first and second output voltage lines, based on the state of the loaded load. EL display device. 9. The method according to claim 8, wherein the means determines the load state based on the total number of data lines and the number of pixels turned on in one scan line. Inorganic EL display device.