JP2003324199A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for preventing the mating deviation of two gate electrodes at the time of manufacturing a double gate type transistor, and for making it unnecessary to perform a flattening process prior to adhesion accompanied by the formation of the gate electrodes. <P>SOLUTION: An SOI substrate having a lower insulating film 4, a conductive film 3, an upper layer insulating film 2, and SOI layer 1 is formed. A mask layer 6 is formed on the SOI layer 1 of the SOI substrate, and oxygen ions are injected to the conductive film 3 with the mask layer 6 as a mask to insulate the conductive film 3 so that an insulating film 7 can be formed. A backgate electrode 3a surrounded by the insulating film 7 is formed so as to be self-aligned immediately under the mask layer 6, and the forming place of the mask layer 6 is exchanged with a front gate electrode so that the front gate electrode and a backgate electrode 3a can be formed so as to be self- aligned with the SOI layer 1 interposed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a double gate.

[0002]

2. Description of the Related Art In recent years, SOI (Silicon On Insulator)
As an element, a technique of forming a semiconductor element such as a transistor on an insulating film is drawing attention. In general, SOI devices are
Effects such as improvement of operation speed, high integration, and improvement of soft error resistance are expected. Further, in the above-mentioned SOI element, the double gate type MOS transistor having a back gate electrode under the insulating film can improve the driving capability of the transistor by controlling the voltage from above and below by the double gate, In particular, it is promising for realizing a transistor having a gate length of 0.1 μm or less.

An example of a conventional method of manufacturing a double gate type MOS transistor will be described with reference to FIGS. First, as shown in FIG. 8A, a groove M having a depth of about 50 nm is formed in a semiconductor substrate 100 made of silicon by a trench (dry etching) method or the like,
A silicon oxide film is deposited to a thickness of about 50 nm by a thermal oxidation method to form a back gate insulating film 101.

Next, as shown in FIG. 8B, a CVD (Chemical Vapor Depos) is formed on the back gate insulating film 101.
)) to deposit about 300 nm of polysilicon to form the back gate conductive film 102.

Next, as shown in FIG. 8C, a resist is applied on the back gate conductive film 102 and patterned into a desired pattern by a lithography technique, and the patterned resist film (not shown). The back gate electrode 1 is patterned by performing etching using the back gate electrode 1 as a mask.
02a is formed.

Next, as shown in FIG. 9D, a silicon oxide film is deposited to a thickness of about 600 nm on the back gate electrode 102a and the back gate insulating film 101 by the CVD method to completely surround the back gate electrode 102a. An insulating film 103 is formed so as to surround. At this time, the insulating film 10
3 is the film thickness 3 of the back gate electrode 102a.
From 00 nm and the depth of the groove M of 50 nm, it becomes about 350 nm.

Next, as shown in FIG. 9 (e), polysilicon is deposited by a CVD method to fill the step created by the formation of the trench M and the back gate electrode 102a, and a planarizing film 104 is formed. To do. As described above, the step is 350 nm at this point, and the thickness of the flattening film 104 for flattening needs to be about 2 to 3 μm. Is required, and a large amount of gas and time are required. Further, in order to deposit a thick film of 5 μm, a gas is caused to flow in the CVD furnace for a long time, so that a large amount of polysilicon is deposited also in the furnace, which necessitates frequent cleaning inside the furnace, resulting in a high work efficiency. Cause worse.

Next, as shown in FIG. 9F, the flattening film 104 made of polysilicon deposited in the previous step is flattened by flattening and polishing, and the surface thereof is finished to be a surface capable of being bonded. . The flattening polishing is performed with a polishing pad made of polyurethane foam and a polishing slurry made of colloidal silica having an average particle diameter of 80 nm to remove steps and to form a flattening film 10.
4 is performed, and then the surface roughness that allows laminating is finished to a level of Ra = 0.4 nm by a polishing slurry of colloidal silica having an average particle diameter of 40 nm.

Next, as shown in FIG. 10G, the side of the flattening film 104 of the semiconductor substrate 100 whose surface has been flattened in the previous step and the base substrate 105 are overlapped with each other so that both substrates are flattened. Join. Here, in the drawing, as compared with FIG. 9F, the semiconductor substrate 100 on which the planarization film 104 and the like are formed is shown.
Is drawn upside down. The semiconductor substrate 100 and the base substrate 105 are bonded to each other by RCA cleaning or the like so that particles and the like are not attached to the surface and OH groups are present on the surface so that bubbles are not caused at the time of bonding. After stacking both substrates, in an oxygen or nitrogen atmosphere,
Heat treatment is performed at 1100 ° C. for 30 minutes to 120 minutes to form a strong joined state.

Next, as shown in FIG. 10 (h), the semiconductor substrate 100 side of the joined semiconductor substrate 100 and base substrate 105 is ground, and damage at the time of grinding reaches the SOI layer which becomes an active layer. Do not grind to a thickness. Grinding uses a diamond grindstone and grindstone with a grindstone number # 2000. It grinds while rotating at high speed, so the grinding speed is fast and the accuracy of the grinding surface is relatively good, but the damage caused by diamond is deep and the surface roughness is also high. Since it is rough, it is not suitable for producing a transistor. To remove roughness and damage,
Polishing of about 3 μm is performed so that the semiconductor substrate 100 of about 7 μm remains on the back gate insulating film 101. Further, in order to make the film thickness of the semiconductor substrate 100 on the back gate insulating film 101 uniform, the PAC by the plasma etching method is used.
E processing is performed to finish the thickness of the semiconductor substrate 100 on the back gate insulating film 101 to 200 nm ± 50 nm.

Next, as shown in FIG. 11I, the semiconductor substrate 100 having a thickness of about 200 nm left on the back gate insulating film 101 is selectively polished to leave only the step of the groove M, and the required SOI layer 100a is formed. And the SOI substrate. Selective polishing is performed with a polishing pad and ethylenediamine (S
i) and a polishing liquid having a large polishing rate ratio of SiO ₂ ) are used, and when the polishing progresses on the convex portion caused by the groove portion M of the back gate insulating film 101, the polishing is stopped in the state where the polishing progresses. . Therefore, the silicon remaining in the concave portion between the groove portions M of the back gate insulating film 101, that is, the SOI layer 100
The thickness a remains as much as the depth of the groove M.

Next, as shown in FIG. 11 (j), a silicon oxide film is formed by a thermal oxidation method on the SOI layer 100a of the base substrate 105 on which the embedded back gate electrode 102a is formed, and the front gate is formed. The insulating film 106 is formed, a conductive film for a front gate is deposited on the front gate insulating film 106, and the conductive film for a front gate is etched by using a resist film patterned by a lithographic technique as a mask. The front gate electrode 107 having the pattern is formed.

As described above, when a MOSFET having a double-gate structure is conventionally manufactured, an embedded back gate electrode 102a is manufactured in advance, and after element isolation,
Bonding with the base substrate 105, the SOI layer 100a
A method of using an SOI substrate having The method has the following problems and has not been put to practical use.

[0014]

That is, according to the conventional method, the substrate manufacturing process is performed until the step of bonding the base substrate 105 after the element-separated already-fabricated embedded back gate electrode 102a is manufactured. Since the front gate electrode 107 is newly patterned to form the front gate electrode 107, a misalignment between the back gate electrode 102a and the front gate electrode 107 occurs, and the back gate electrode 102a and the front gate that should be symmetrically arranged in the vertical direction. Misalignment occurs in the electrode 107 as shown in FIG. 11 (j). Therefore, the transistor characteristics become asymmetric, and stable device characteristics cannot be obtained,
In particular, if the patterns are further miniaturized in the future, misalignment of the patterns will cause fatal damage, resulting in difficulty in manufacturing the device.

After the back gate electrode 102a is formed, it is necessary to flatten the bonding surface in order to bond the base substrate 105, and a large amount of polysilicon is deposited to form the flattening film 104. Gas and time are required, and further, time required for the maintenance of the CVD apparatus and the like is also required, resulting in an increase in cost.

Further, the back gate electrode 102a described above is used.
The level difference of the planarizing film 104 due to the formation of the film is large, and if the planarizing film 104 serving as the bonding surface is not sufficiently planarized, bubbles will be generated at the time of bonding, resulting in a decrease in the yield of substrate fabrication. As a result, the cost will increase.

The present invention has been made in view of the above circumstances, and an object thereof is to form a gate electrode without causing misalignment of two gate electrodes when a double gate type transistor is manufactured. Another object of the present invention is to provide a method for manufacturing a semiconductor device, which does not require a flattening step before bonding due to the above.

[0018]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a first insulating film,
Forming a semiconductor substrate in which a conductive film, a second insulating film, and a semiconductor layer are sequentially stacked; forming a mask layer having a predetermined pattern on the semiconductor layer; and masking the mask layer. As a step of introducing a reactive species that can insulate the conductive film and leaving the conductive film in a region facing the mask layer as a first gate electrode while insulating the conductive film in another region. Forming a coating film covering the periphery of the mask layer on the semiconductor layer, removing the mask layer, and forming an opening in the coating film to expose the semiconductor layer, The method includes forming a gate insulating film on the semiconductor layer exposed in the opening, and forming a second gate electrode on the gate insulating film in the opening.

In the step of forming the mask layer, the mask layer is formed on the pattern of the second gate electrode.

In the step of forming the mask layer, the mask has a film thickness such that the film thickness of the second gate electrode formed in the opening obtained after the step of removing the mask layer becomes a predetermined film thickness. Form the layers.

In the step of insulating the conductive film by introducing a reactive species capable of insulating the conductive film, oxygen ions are ion-implanted.

The step of insulating the conductive film by introducing a reactant capable of insulating the conductive film includes a step of performing a heat treatment after implanting the oxygen ions.

The step of forming the coating film covering the periphery of the mask layer on the semiconductor layer has a film thickness capable of covering at least the periphery of the mask layer on the mask layer and the semiconductor layer. The method includes depositing a coating film, and polishing the coating film until the mask layer is exposed, and leaving the coating film around the mask layer as the coating film.

In the step of forming the second gate electrode on the gate insulating film in the opening, a second gate electrode film is formed on the gate insulating film and the coating film in the opening. A step of depositing, a step of polishing the second gate electrode film until the coating film is exposed, and leaving the second gate electrode film in the opening as the second gate electrode. Have.

The first insulating film, the conductive film, and the second
Forming the second insulating film on the first substrate including the semiconductor layer, and forming the second insulating film on the first substrate including the semiconductor layer. Forming the conductive film on an insulating film; forming the first insulating film on the conductive film; and forming the first substrate on a region of a predetermined depth of the first substrate. A step of introducing a peelable impurity, a step of bonding the second substrate from the side of the first insulating film, and a heat treatment while leaving the semiconductor layer of the first substrate on the second insulating film. And a step of peeling the first substrate in the region where the impurities are introduced, and a step of polishing the semiconductor layer so that the semiconductor layer has a desired film thickness.

Before the step of forming the second insulating film,
The method further comprises the step of forming a groove having a predetermined pattern and having a predetermined depth in the first substrate including the semiconductor layer, wherein in the step of forming the second insulating film, the inside of the groove and the first substrate are formed. In the step of forming the second insulating film thereon and polishing the semiconductor layer, the semiconductor layer is polished using the second insulating film having a shape protruding at the bottom of the groove as a stopper.

In the step of introducing the impurities capable of peeling the first substrate, hydrogen ions are ion-implanted.

In the step of forming the groove, a groove having a predetermined depth is formed in the outer peripheral region of the circuit pattern of the semiconductor chip formed on the semiconductor layer.

According to the above-described method for manufacturing a semiconductor device of the present invention, after forming a semiconductor substrate in which a first insulating film, a conductive film, a second insulating film, and a semiconductor layer are sequentially stacked,
By forming a mask layer on the semiconductor layer and introducing a reactive species into the conductive film using the mask layer as a mask, the first gate electrode surrounded by the insulating film is formed directly below the mask layer in a self-aligned manner. The mask layer is formed in the second position.
By replacing the first gate electrode with the second gate electrode, the first gate electrode and the second gate electrode are formed so as to face each other in a self-aligned manner with the semiconductor layer in between.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings.

First, a method of manufacturing an SOI substrate used when manufacturing a MOS transistor having a double gate structure according to this embodiment will be described with reference to FIGS.

First, as shown in FIG. 1A, on the surface of the first silicon semiconductor substrate (first substrate) 10, in the outer peripheral region of the circuit pattern of the semiconductor chip formed in the semiconductor layer of the SOI substrate, for example, a pitch of 20 mm. So that the RIE (Reactive Ion
Etching) or the like, for example, a width of 10
A groove G of 0 μm and a depth of 50 nm is formed. Then, the groove G
For example, CVD (Chemical V
The upper insulating film 2 is formed by depositing silicon oxide in a film thickness of 400 nm by the apor Deposition method, and further CMP is performed.
The upper insulating film 2 is polished by (Chemical Mechanical Polishing) process to flatten the surface. In the CMP process, for example, a polyurethane foam is used as a polishing pad and a colloidal silica having an average particle diameter of 80 nm is used as a polishing slurry to polish the surface of the upper insulating film 2 to 200 nm.
The surface is stepped to remove steps.

Next, as shown in FIG. 1B, for example, C
Polysilicon is deposited on the upper layer of the upper insulating film 2 by the VD method.
The conductive film 3 is formed by depositing it to a film thickness of 00 nm. Conductivity is imparted to the above-described polysilicon by mixing a reaction gas with a conductive impurity during deposition so that the impurity is contained during film formation or by ion implantation of the impurity after deposition.

Next, as shown in FIG. 1C, for example, C
The lower insulating film 4 is formed by depositing silicon oxide with a film thickness of 300 to 400 nm by the VD method. Next, the surface of the lower insulating film 4 is subjected to a polishing treatment using a polishing pad such as a non-woven fabric type continuous foam to make colloidal silica having an average particle diameter of 40 nm as a polishing slurry, so that the surface roughness Ra = 0.4n.
Polish to m level and finish to a surface that can be laminated.

Next, as shown in FIG. 2D, for example, hydrogen ions D are ion-implanted to form a peeling surface 11 in a region of the first substrate 10 having a predetermined depth. Here, peeling surface 1
The depth of 1 is, for example, the groove G in consideration of damage at the time of peeling.
The depth is about 200 nm from the bottom. The order of the step of forming the peeled surface by introducing the impurities and the step of polishing processing for finishing the bonded surface may be interchanged.

Next, as shown in FIG. 2E, a second silicon semiconductor substrate (second substrate) 5 is attached from the lower insulating film 4 side formed on the first substrate 10. Here, the first substrate 10 on which the upper layer insulating film 2, the conductive film 3 and the lower layer insulating film 4 are formed is vertically inverted with respect to FIG. At the time of the above bonding, the second substrate 5
The surface of is subjected to a polishing treatment in advance so as to be a surface that can be bonded similarly to the first substrate 10, and further, for example, RCA cleaning treatment (ammonia water, hydrogen peroxide water and high-purity water (NH ₃ : H ₂ O ₂ : H ₂ O = 1: 2: 7) cleaning solution)
The surface of the lower insulating film 4 of the first substrate 10 and the surface of the second substrate 5 which are the bonding surfaces are cleaned (removal of particles on the bonding surface) and hydrophilized (introduction of OH group to the bonding surface). This makes it possible to stabilize the bonding.

Next, as shown in FIG. 3 (f), in an oxygen or inert gas atmosphere, first, heat treatment at about 400 ° C. is performed to increase the adhesive strength of the bonded surfaces, and then heat treatment at about 600 ° C. By performing the above, while leaving the semiconductor layer 1 on the upper insulating film 2 on the peeled surface 11, the first
The substrate 10 'is peeled off. The above-mentioned first substrate 10 ′ can be reused as the first substrate or another semiconductor substrate after being recovered and having its surface flattened. In order to further increase the adhesive strength of the bonding surface between the second substrate 5 and the lower insulating film 4, the heat treatment is performed at a temperature of 800 to 1100 ° C. for about 30 minutes to 2 hours. For example, when impurities such as boron have already been introduced into the semiconductor layer 1, it is preferable to perform it at a low temperature of about 800 ° C. in order to prevent diffusion.

Next, as shown in FIG. 3 (g), for example, C
The upper insulating film portion 2a embedded in the groove G by the MP method
The semiconductor layer 1 is polished by a film thickness of 200 nm with the surface of as a stopper to remove damage at the time of peeling and the surface of the semiconductor layer is flattened to obtain a desired SOI substrate having the semiconductor layer 1 (SOI layer). In the CMP treatment, for example, a urethane foam such as a non-woven fabric type continuous foam is used as a polishing pad, and a polishing treatment using colloidal silica having an average particle diameter of 40 nm or an ethylenediamine solution as a polishing slurry is performed to obtain a surface roughness required for an LSI device. And the SOI layer thickness.

In the above CMP polishing treatment, the first
The upper insulating film portion 2a embedded in the groove G formed in the substrate 10 has a shape protruding upward from the surface of the second substrate 5, and the silicon oxide of the upper insulating film 2 is larger than the silicon of the semiconductor layer 1. Since it has a polishing rate ratio, it is possible to polish the semiconductor layer 1 using the surface of the upper insulating film portion 2a buried in the groove G as a stopper. As a result of the above polishing process, the semiconductor layer (SOI layer) 1 can be formed by the upper insulating film 2 as shown in FIG. 3G, which is separated for each region forming the circuit pattern of the semiconductor chip. The upper insulating film portion 2a embedded in the groove G is
A scribe line SL can be used when a semiconductor chip circuit pattern is formed on the SOI substrate obtained above and then divided (diced) into individual semiconductor chips. Although the film thickness of the SOI layer 1 depends on the conditions of the polishing process, the thickness of the SOI layer 1 is controlled by the depth of the groove G because the surface of the upper insulating film portion 2a embedded in the groove G serves as a stopper. For example, by setting the depth of the groove G to 50 nm, the film thickness of the SOI layer 1 can be set to about 50 nm.

A method of manufacturing the MOS transistor having the double gate structure according to the present embodiment using the SOI substrate manufactured as described above will be described with reference to FIGS.

FIG. 4H shows a region where a circuit pattern of a semiconductor chip is formed in the SOI substrate in which the lower layer insulating film 4, the conductive film 3, the upper layer insulating film 2 and the SOI layer 1 are formed on the second substrate 5. It is a figure which shows a part of FIG. 1, and is a board | substrate produced in the process of FIGS. As mentioned above,
In the production of the substrate, a factor such as a step difference is only a variation due to the CVD process and does not become a factor for generating bubbles at the time of bonding. Therefore, it is possible to produce a stable substrate without the need for special flattening. It also leads to improved yield.

Then, as shown in FIG.
On the layer 1, for example, silicon nitride (Si ₃
A mask layer 6 is formed by depositing N ₄ ) to a thickness of about 150 nm and patterning the silicon nitride film on a portion required as a back gate electrode. continue,
Using the mask layer 6 as a mask, oxygen ions are implanted by an ion implantation method so that the oxygen ions reach the conductive film 3 from the substrate surface side.

Next, as shown in FIG. 4 (j), the substrate after the oxygen ion implantation is heat-treated at 1000 ° C. for about 1 hour to remove the implanted oxygen ion and the polysilicon of the conductive film 3. By reacting, the portions of the conductive film 3 immediately below the mask layer 6 are converted to SiO ₂ to form an insulating film 7 made of silicon oxide. By this step, the back gate electrode 3a is formed immediately below the mask layer 6. At this time, the volume of the portion changed to the insulating film 7 is increased by 2.2 times and the thickness thereof is increased to have a shape as illustrated.

Next, as shown in FIG. 5K, a silicon oxide film for forming a front gate electrode is formed on the entire surface of the mask layer 6 and the SOI layer 1 after the heat treatment by CVD.
Then, the coating insulating film 8 is formed. The deposition thickness of the silicon oxide film to be the covering insulating film 8 is a film thickness that completely covers the periphery of the mask layer 6, and is 200 nm in this embodiment, for example.

Next, as shown in FIG. 5 (l), the surface of the mask layer 6 is polished by CMP in order to remove the covering insulating film 8 made of silicon oxide grown in a convex shape on the mask layer 6. Simultaneously with the removal of the convex portion of the covering insulating film 8 on 6, the surface of the covering insulating film 8 is flattened. Polishing is IC1000 +
Polishing pad of Suba400 (made by Rodel Nitta),
Polishing slurry SC112 (made by Cabot) or the like is used. At this time, the remaining thickness of the covering insulating film 8 becomes equal to the thickness of the mask layer. For example, in the present embodiment, it is 1
It becomes about 50 nm. The remaining thickness of the covering insulating film 8 remaining after the planarization, that is, the thickness of the mask layer 6 becomes the thickness of the front gate electrode. Further, at this time, since the mask layer 6 used when implanting oxygen is used as it is for the positional relationship with the back gate electrode 3a, misalignment due to patterning does not occur.

Next, as shown in FIG. 5 (m), the mask layer 6 on the surface of the substrate which has been flattened in the previous step is removed to form a front gate groove 8a in the covering insulating film 8. , SOI exposed in the front gate groove 8a by the thermal oxidation method
A silicon oxide film is formed on the layer 1 to form the front gate insulating film 9. The front gate groove 8a is formed by
Only the mask layer 6 can be etched by etching with a phosphoric acid boil having selectivity for the mask layer 6. Since the front gate insulating film 9 needs to be an insulating film having excellent insulating properties as the gate insulating film of the front gate electrode, the thermal oxidation method is adopted in this embodiment, but at this time, the SOI layer is used. Since the film thickness of 1 is slightly reduced, the film thickness of the SOI layer 1 formed in FIGS. 1 to 3 is determined in consideration of the film reduction when the front gate insulating film 9 is formed. For example, when the thickness of the front gate insulating film 9 is set to 30 nm, the SOI layer 1 is formed to have a film thickness obtained by adding 15 nm to the required thickness.

Next, as shown in FIG. 6N, the entire surface of the front gate insulating film 9 in the front gate groove 8a of the covering insulating film 8 and the entire surface of the covering insulating film 8 is coated with polysilicon by a CVD method. Deposited by the conductive film for front gate 1
Form 2. The thickness of the polysilicon is at least the thickness required to be embedded in the front gate trench 8a of the covering insulating film 8, and is, for example, about 250 nm.

Next, as shown in FIG. 6 (o), the front gate conductive film 12 deposited by the CVD method in the previous step.
The surface of the insulating film 8 is selectively polished by the CMP method until the insulating film 8 is exposed to remove the front gate conductive film 12 deposited on the insulating film 8 so that only the front gate groove 8a of the insulating film 8 is fronted. By leaving the gate conductive film 12, the front gate electrode 12a embedded in the front gate groove 8a is formed. The selective polishing at this time is performed with a polishing pad of a nonwoven fabric base cloth and an ethylenediamine solution having a large selection ratio. Ethylenediamine has a concentration of 0.
By using the one diluted to 0005%, silicon or polysilicon can be polished, but the silicon oxide film cannot be polished, and the polishing is stopped by the silicon oxide film of the covering insulating film 8. To be confirmed,
The thickness of the front gate electrode 12a can be easily controlled. The polishing pad is, for example, Suba800 manufactured by Rodel Nitta.
Nonwoven Fabric Cloth, Hardness 8 ((Asker-c) -J
Pad according to ISK-6301) is used. In addition,
The selective polishing slurry is not limited as long as the polishing rate ratio between the polysilicon film and the silicon oxide film is large.

Next, as shown in FIG. 6P, the silicon oxide film of the covering insulating film 8 is etched to form the SOI layer 1
And the polysilicon of the front gate electrode 12a are not etched, and a selective gas such as
The cover insulating film 8 around the front gate electrode 12a is removed by dry etching with C ₄ F ₈ or the like.

Next, as shown in FIG. 7 (q), conductive impurities are ion-implanted by using the front gate electrode 12a as a mask to form a low-concentration impurity region (not shown) in the SOI layer 1, and then a normal impurity is formed. Similar to the process, a silicon nitride film is deposited on the entire surface by the CVD method, and the silicon nitride film is etched back to form the sidewall insulating film 13 on the side portion of the front gate electrode 12a. Then, by using the front gate electrode 12a and the sidewall insulating film 13 as a mask, conductive impurities are ion-implanted at a high concentration to form a high-concentration impurity region, thereby forming a source / source of an LDD (Lightly Doped Drain) structure. A drain region is formed.

Next, as shown in FIG. 7 (r), for example, cobalt is deposited to a thickness of about 5 nm by a sputtering method,
By performing a thermal treatment (RTA: Rapid Thermal Annealing), only the cobalt film formed on the source / drain regions of the SOI layer 1 and on the front gate electrode 12a is silicidized (CoSi) to form the SOI layer 1 On the surface of the source / drain region and the front gate electrode 12a,
The silicide films 14 and 15 are formed, respectively. continue,
The cobalt film remaining without being silicided is removed by a mixed solution of sulfuric acid and hydrogen peroxide.

In the subsequent steps, for example, silicon oxide is deposited by a CVD method to form an interlayer insulating film, a contact hole is formed in the interlayer insulating film by a lithography method and dry etching, and the contact hole is formed in the contact hole. A conductive plug is formed by embedding tungsten or the like, and a wiring layer made of aluminum or the like connected to the conductive plug is formed, whereby a MOS transistor having a double gate structure is manufactured on the SOI substrate.

According to the method of manufacturing a semiconductor device according to the present embodiment described above, after the SOI substrate shown in FIG. 4H is formed, the mask layer 6 is formed on the SOI layer 1 of the SOI substrate. By implanting oxygen ions into the conductive film 3 using the mask layer 6 as a mask, the back gate electrode 3a surrounded by the insulating film 7 is formed immediately below the mask layer 6 in a self-aligned manner, and the mask layer 6 described above is formed. By replacing the formation location of the front gate electrode 12a with the front gate electrode 12a, the front gate electrode 12a and the back gate electrode 3a face each other in a self-aligned manner with the SOI layer 1 interposed therebetween. There is no misalignment with 3a. In this way, since the back gate electrode 3a and the front gate electrode 12a are arranged vertically symmetrically in a self-aligned manner with the SOI layer 1 interposed therebetween, stable device characteristics can be obtained. As a result, the control of the threshold voltage (Vth) becomes easy, and it is possible to cope with further miniaturization of the line width in the future.

Further, in this embodiment, after the substrates are bonded to each other to form the SOI substrate in which the lower layer insulating film 4, the conductive film 3, the upper layer insulating film 2 and the SOI layer 1 are formed on the substrate 5, the mask layer is formed. Since the back gate electrode is formed as described above using 6 as a mask,
Since the step of flattening the bonding surface accompanying the formation of the back gate electrode before manufacturing the SOI substrate is not required, a large amount of gas and time required for flattening the step can be saved, Significant cost reduction can be achieved.

The method of manufacturing the semiconductor device of the present invention is not limited to the above description of the embodiment. For example, the processes other than the self-aligning process of the front gate electrode 12a and the back gate electrode 3a are not particularly limited to the above-described embodiment, and, for example, the formation process of the sidewall insulating film 13 and the silicide films 14 and 15 is performed. It can be omitted if necessary. Further, the material for forming the mask layer and the front gate electrode is not particularly limited.

Further, for example, in the process of manufacturing the SOI substrate of FIGS. 1 to 3, the pattern for separating the SOI layer by the insulating film is not limited to each region of the circuit pattern of the semiconductor chip, but a plurality of semiconductor chips. It is also possible to change for each area. The insulating film or conductive film such as the upper insulating film or the lower insulating film may have a single-layer structure or a multi-layer structure. Besides, various modifications can be made without departing from the scope of the present invention.

[0057]

According to the present invention, when a double gate type transistor is manufactured, the two gate electrodes are not misaligned with each other, and a flattening step before bonding due to the formation of the gate electrode is unnecessary. Therefore, the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view after formation of a lower insulating film.

FIG. 2 is a plan view of a semiconductor device manufacturing method according to the present embodiment.
It is sectional drawing after the bonding process of a board | substrate.

FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to the present embodiment.
It is sectional drawing after manufacture of the SOI substrate which has an SOI layer.

FIG. 4 is a plan view of the semiconductor device manufacturing method according to the present embodiment.
It is sectional drawing after forming a back gate electrode.

FIG. 5 is a view showing manufacturing of the semiconductor device according to the present embodiment.
It is sectional drawing after the groove | channel for front gates is formed.

FIG. 6 is a view showing manufacturing of the semiconductor device according to the present embodiment.
It is sectional drawing after the formation of the front gate electrode.

FIG. 7 is a view showing manufacturing of the semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after formation of a silicide film.

FIG. 8 is a cross-sectional view after formation of a back gate electrode in manufacturing a transistor having a double gate structure according to a conventional example.

FIG. 9 is a cross-sectional view after flattening a step on the surface of a flattening film due to formation of a back gate in manufacturing a transistor having a double gate structure according to a conventional example.

FIG. 10 is a cross-sectional view after the substrates are bonded together in the manufacturing of the double-gate structure transistor according to the conventional example.

FIG. 11 is a cross-sectional view after a front gate electrode is formed in the manufacturing of the double-gate structure transistor according to the conventional example.

[Explanation of symbols]

1 ... Semiconductor layer (SOI layer), 2 ... Upper insulating film, 2a ... Insulating film part, 3 ... Conductive film, 3a ... Back gate electrode, 4 ...
Lower layer insulating film, 5 ... Second silicon semiconductor substrate (second substrate), 6 ... Mask layer, 7 ... Insulating film, 8 ... Covering insulating film, 8
a ... Front gate groove, 9 ... Front gate insulating film,
10 ... First silicon semiconductor substrate (first substrate), 10 '...
First substrate, 11 ... Release surface, 12 ... Front gate conductive film, 12a ... Front gate electrode, 13 ... Side wall insulating film, 14, 15 ... Silicide film, 100 ... Semiconductor substrate, 100a ... Semiconductor layer (SOI layer) , 101 ... Back gate insulating film, 102 ... Back gate conductive film, 10
2a ... Back gate electrode, 103 ... Insulating film, 104 ... Planarization film, 105 ... Base substrate, 106 ... Front gate insulating film, 107 ... Front gate electrode, D ... Hydrogen ion, M ... Trench, G ... Trench.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/12 H01L 21/76 L 21/265 J 21/76 R (72) Inventor Akira Ohno Tokyo Metropolitan Government 6-35, Kita-Shinagawa, Shinagawa-ku F-terms in Sony Corporation (reference) 5F032 AA06 AA07 AA34 AA44 AA77 BB01 CA17 DA02 DA23 DA33 DA60 DA71 DA74 DA78 5F110 AA16 DD05 DD13 EE05 EE09 EE14 EE30 EE32 EE41 FF02 EE44 EE44 EE44 FF44 EE02 GG02 GG12 GG25 HJ13 HK05 HK33 HK40 HL03 HL04 HL11 HM15 NN02 NN23 NN35 NN62 QQ08 QQ11 QQ16 QQ19

Claims (11)

[Claims] 1. A step of forming a semiconductor substrate in which a first insulating film, a conductive film, a second insulating film, and a semiconductor layer are sequentially stacked, and a mask layer having a predetermined pattern on the semiconductor layer. And a step of forming a reactive species capable of insulating the conductive film by using the mask layer as a mask and leaving the conductive film in a region facing the mask layer as a first gate electrode while Insulating the conductive film in a region; forming a coating film on the semiconductor layer to cover the periphery of the mask layer; removing the mask layer to form the semiconductor on the coating film. Forming an opening exposing the layer, forming a gate insulating film on the semiconductor layer exposed in the opening, and forming a second gate electrode on the gate insulating film in the opening A semiconductor having a process Method of manufacturing location. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the mask layer, the mask layer is formed in a pattern of the second gate electrode. 3. In the step of forming the mask layer, the film thickness of the second gate electrode formed in the opening obtained after the step of removing the mask layer has a predetermined film thickness. The method of manufacturing a semiconductor device according to claim 1, wherein the mask layer is formed. 4. The method of manufacturing a semiconductor device according to claim 1, wherein oxygen ions are ion-implanted in the step of insulating the conductive film by introducing a reactive species capable of insulating the conductive film. 5. The step of introducing a reactant capable of insulating the conductive film to insulate the conductive film includes a step of performing a heat treatment after implanting the oxygen ions.
A method for manufacturing a semiconductor device as described above. 6. A film capable of covering at least the periphery of the mask layer on the mask layer and the semiconductor layer in the step of forming the coating film covering the periphery of the mask layer on the semiconductor layer. Depositing a coating film with a thickness, and polishing the coating film until the mask layer is exposed,
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of leaving the coating film around the mask layer as the coating film. 7. The step of forming the second gate electrode on the gate insulating film in the opening includes: forming the second gate electrode on the gate insulating film and the coating film in the opening;
Depositing a second gate electrode film, polishing the second gate electrode film until the coating film is exposed, and removing the second gate electrode film in the opening from the second film. Remaining as a gate electrode of
A method for manufacturing a semiconductor device as described above. 8. The first insulating film, the conductive film, and the second film.
The step of forming the insulating film and the semiconductor substrate in which the semiconductor layer is sequentially stacked, the step of forming the second insulating film on the first substrate including the semiconductor layer; and the step of forming the second insulating film. Forming the conductive film on an insulating film; forming the first insulating film on the conductive film; and forming the first substrate on a region of a predetermined depth of the first substrate. A step of introducing a peelable impurity, a step of laminating a second substrate from the side of the first insulating film, and a step of heat treating the semiconductor layer of the first substrate to the second layer.
The step of peeling the first substrate in the region where the impurities are introduced while leaving it on the insulating film, and the step of polishing the semiconductor layer so that the semiconductor layer has a desired film thickness. 1. The method for manufacturing a semiconductor device according to 1. 9. Before the step of forming the second insulating film,
The method further comprises the step of forming a groove having a predetermined depth and having a predetermined pattern in the first substrate including the semiconductor layer, in the step of forming the second insulating film, the inside of the groove and the first substrate. The semiconductor layer is polished by using the second insulating film having a shape protruding at the bottom of the groove as a stopper in the step of forming the second insulating film thereon and polishing the semiconductor layer. Of manufacturing a semiconductor device of. 10. The method of manufacturing a semiconductor device according to claim 8, wherein hydrogen ions are ion-implanted in the step of introducing an impurity capable of peeling the first substrate. 11. The method of manufacturing a semiconductor device according to claim 9, wherein in the step of forming the groove, a groove having a predetermined depth is formed in an outer peripheral region of a circuit pattern of a semiconductor chip formed in the semiconductor layer.