JP2003323417A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simultaneously satisfy both of the reduction of power consumption and the improvement of performance in a finely-divided system LSI wherein several eight figure pieces of transistors are loaded on one chip, so that the threshold voltage is lowered to realize high-speed motion of the transistors, which causes the increase of the leakage of current and the increase of the power consumption in the entire system. <P>SOLUTION: This semiconductor integrated circuit device comprises a CPU 110 of low power consumption and a CPU 120 of high performance, a command analyzing part 132 for analyzing the command to be executed, and determines the CPU which executes the command, a mode control register 130 for registering the determined information, and a power supply switching part 131 for controlling the power supply on the basis of the information of the register. In the processing needing high performance, the processing is performed by the CPU of high performance 120, and the power source is cut off when the processing is not performed by the CPU of high performance 120, whereby the leakage of current is reduced, and the both of high performance and low power consumption can be realized. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device compatible with miniaturization.

[0002]

2. Description of the Related Art In recent years, miniaturization of semiconductor manufacturing technology has advanced,
The threshold voltage of the transistor and the power supply voltage applied to the semiconductor integrated circuit tend to decrease. Due to this decrease in the threshold voltage, the leak current between the source and drain increases. Further, in order to realize a high-speed operation of the transistor, it is necessary to further reduce the threshold voltage, but with that, the leak current further increases.

In the miniaturization process, this leak current is becoming a major cause of an increase in the power consumption of the LSI. Therefore, in order to realize the low power consumption of the LSI in the miniaturization process, it is an important issue not only to reduce the power consumption during operation but also to further reduce the leak current.

As a method of reducing this leakage current,
A method of reducing the leak current by increasing the threshold voltage of the transistor, and a threshold voltage can be controlled by controlling the back gate bias as in VTCMOS to reduce the leak current in the standby mode and speed up the operation. Further, as in the technique disclosed in Japanese Patent Laid-Open No. 05-29551, a design is made so that the power can be turned on / off for each of the functional blocks that make up the LSI, and the power is turned on when the individual functional blocks are not required to operate. There is a method of reducing the leak current by turning it off.

Further, in the miniaturization process, not only the conventional leak current between the source and the drain but also the leak current from the gate of the transistor increases remarkably.
This is an essential technique for reducing the gate oxide film thickness in order to increase the speed of the transistor in the miniaturization process, but this thinning causes a large increase in gate leakage.

[0006]

However, when the threshold voltage of the transistor is increased to reduce the leak current, there is a merit in reducing the power, but it is difficult to realize high performance.

Regarding the method of controlling the back gate bias and changing the threshold voltage according to the operation mode as in VTCMOS, after the process of the 0.13 μm generation, if scaling is performed to improve the operation speed of the circuit, the The dependency of the threshold voltage on the gate bias voltage tends to decrease, and even if the back gate bias voltage control technology is used, the effect of reducing the leak current is less noticeable, and the leak current is reduced or the performance is improved. Becomes difficult.

Further, in the technique disclosed in Japanese Patent Laid-Open No. 05-29551, it is possible to turn on / off the power supply in functional block units forming an LSI, but there is no mention of the transistors forming each block, and it is low. It is not possible to achieve both power consumption and high performance in a loose state.

Nowadays, with the progress of miniaturization of semiconductor manufacturing processes, it has become possible to realize a system LSI in which a complicated system is realized on one chip.
Millions or tens of millions of transistors are mounted on one chip, and when the leak current is considered on one chip, the absolute value of the leak current increases significantly.
Further, the leakage current further increases due to the remarkable leakage current. Therefore, how to reduce this leak current is one of the major issues in the design of a system LSI that requires low power consumption. On the other hand, in order to realize the operation of the system LSI, high performance is required at the same time, and in order to realize the system LSI, it is a major issue to achieve both low power consumption and high performance by reducing leakage current. .

An object of the present invention is to provide a semiconductor integrated circuit device capable of achieving both low power consumption and high performance.

[0011]

In order to solve the above problems, it is most effective to cut off the power supply voltage in order to reduce the leak current, and it is effective to lower the threshold voltage in order to realize high performance. Is.

A semiconductor integrated circuit device according to claim 1 of the present invention is a high-performance CPU configured by using a transistor having a low threshold voltage, and a low power consumption CPU configured by using a transistor having a high threshold voltage. And an instruction analysis unit that analyzes the input instruction to determine which one of the high performance CPU and the low power consumption CPU should be executed, and the instruction analysis unit that is input based on the determination of the instruction analysis unit. A power control unit that stores information designating a CPU that executes an instruction, and a power supply control unit that controls the supply of a power supply voltage to the high-performance CPU based on the stored information in the mode control register. Stops the supply of the power supply voltage to the high performance CPU when the information for designating the low power consumption CPU is stored in the mode control register, and And so as to supply a power supply voltage to a high performance for the CPU when information specifying the use CPU is stored.

According to the first aspect of the present invention, the high-performance CPU and the low-power-consumption CPU, which are composed of transistors having different threshold voltages, are provided, the input instruction is analyzed, and the processing is performed according to the processing content. When high-performance (high-speed) processing is required, it is executed by the high-performance CPU, and when other processing is executed, it is executed by the low-power consumption CPU.
When it is executed by the PU, the leakage current can be reduced by stopping the supply of the power supply voltage to the high performance CPU. In this way, both high performance and low power consumption can be achieved by properly using the CPU and controlling the power supply voltage according to the processing content of the instruction to be executed.

A semiconductor integrated circuit device according to a second aspect of the present invention is a high-performance CPU configured by using a transistor with a low threshold voltage, and a low power consumption CPU configured by using a transistor with a high threshold voltage. Which one of the high-performance CPU and the low-power-consumption CPU, the register file and the memory shared to execute the instructions by the high-performance CPU and the low-power-consumption CPU, and the high-performance CPU and the low-power-consumption CPU by analyzing the input instruction An instruction analysis unit that determines whether the instruction is to be executed by the CPU, a mode control register that stores information that specifies a CPU that executes an instruction that is input based on the determination of the instruction analysis unit, and storage information of the mode control register And a power supply control unit that controls the supply of power supply voltage to the high performance CPU and the low power consumption CPU based on
When the information for designating the low power consumption CPU is stored in the mode control register, the power supply voltage is supplied to the low power consumption CPU, the power supply voltage to the high performance CPU is stopped, and the high power is supplied to the mode control register. High-performance CPU when information specifying the high-performance CPU is stored
The power supply voltage is supplied to the CPU and the supply of the power supply voltage to the low power consumption CPU is stopped.

According to the second aspect of the present invention, two CPUs for high performance and low power consumption, which are composed of transistors having different threshold voltages, and a register file and a memory shared by these two CPUs are provided. And analyzes the input instructions and executes them with a high-performance CPU when high-performance (high-speed) processing is required according to the content of the processing, and with low-power consumption CPU in the case of other processing. When the power supply voltage is supplied to one of the two CPUs and the supply to the other is stopped, simultaneous access from the two CPUs to the shared register file and the memory can be prevented and low power consumption is achieved. The CPU can stop the supply of the power supply voltage to the high-performance CPU at the time of executing the instruction to reduce the leakage current. In this way, both high performance and low power consumption can be achieved by properly using the CPU and controlling the power supply voltage according to the processing content of the instruction to be executed. Further, by sharing the register file and the memory by the two CPUs, the circuit resources can be reduced.

A semiconductor integrated circuit device according to a third aspect of the present invention is the semiconductor integrated circuit device according to the second aspect, wherein the register file and the memory are configured by using transistors having a high threshold voltage, and the power supply control unit is a register. It also controls the supply of the power supply voltage to the file and the memory, and when the information for designating the high performance CPU is stored in the mode control register, the power supply voltage higher than the power supply voltage supplied to the high performance CPU is set in the register file and The feature is that it is supplied to the memory.

According to the structure of claim 3, in addition to the same effect as that of claim 2, a register file and a memory configured by using a high threshold voltage transistor at the time of executing an instruction in a high performance CPU. By supplying a power supply voltage higher than that of the high-performance CPU, it is possible to maximize the performance of the high-performance CPU.

A semiconductor integrated circuit device according to a fourth aspect of the present invention is a high-performance CPU configured by using a transistor having a low threshold voltage, and a low power consumption CPU configured by using a transistor having a high threshold voltage. And an instruction to be input to analyze the instruction to determine which of the high-performance CPU and the low-power-consumption CPU should execute the instruction, and the instruction to be executed by the high-performance CPU. The instruction analysis unit that determines the clock frequency for executing the instruction and the minimum power supply voltage required to realize this clock frequency, and the instruction that is input based on the determination by the instruction analysis unit. When storing the information that specifies the CPU to be executed, and when storing the information that specifies the high-performance CPU, the clock frequency when the high-performance CPU executes Of the power supply voltage to the high-performance CPU based on the information stored in the mode control register and the mode control register that stores information indicating the minimum power supply voltage necessary to realize this clock frequency. And a clock frequency control unit for controlling the frequency of the clock supplied to the high-performance CPU based on the stored information in the mode control register.
When the information for designating the low power consumption CPU is stored in the mode control register, the supply of the power supply voltage to the high performance CPU is stopped, and the high performance CP is stored in the mode control register.
When the information designating U is stored, the high performance CP is based on the stored information indicating the power supply voltage.
The power supply voltage is supplied to U, and when the mode control register stores information designating the high-performance CPU, the clock frequency control unit further determines the high-performance CPU based on the stored information indicating the clock frequency. A clock is supplied to the CPU.

According to the fourth aspect of the present invention, the high-performance CPU and the low-power-consumption CPU, which are composed of the transistors having different threshold voltages, are provided, the input instruction is analyzed, and the processing is performed according to the processing content. When high-performance (high-speed) processing is required, it is executed by the high-performance CPU, and when other processing is executed, it is executed by the low-power consumption CPU.
When it is executed by the PU, the leakage current can be reduced by stopping the supply of the power supply voltage to the high performance CPU. In this way, both high performance and low power consumption can be achieved by properly using the CPU and controlling the power supply voltage according to the processing content of the instruction to be executed. Furthermore, high performance CP
When an instruction is executed in U, the clock frequency required according to the processing content of the instruction is clarified, and the power supply voltage is controlled to the minimum voltage required to realize that clock frequency. It is possible to reduce power consumption during operation of the performance CPU, and it is possible to further reduce power consumption.

A semiconductor integrated circuit device according to a fifth aspect of the present invention is a high-performance CPU configured by using a transistor having a low threshold voltage, and a low power consumption CPU configured by using a transistor having a high threshold voltage. Which one of the high-performance CPU and the low-power-consumption CPU, the register file and the memory shared to execute the instructions by the high-performance CPU and the low-power-consumption CPU, and the high-performance CPU and the low-power-consumption CPU by analyzing the input instruction It is necessary to determine whether the instruction is to be executed by the CPU, and when it is determined that the instruction is to be executed by the high-performance CPU, the clock frequency for executing the instruction and the clock frequency for realizing this clock frequency. And an instruction analysis unit that determines the lowest power supply voltage and information that specifies a CPU that executes an instruction input based on the determination of the instruction analysis unit. In addition, when storing the information for designating the high-performance CPU, the information indicating the clock frequency at which the high-performance CPU executes is stored and the information indicating the lowest power supply voltage required to realize this clock frequency. Mode control register, and high performance CPU and low power consumption C based on the stored information of the mode control register
A power supply control unit that controls the supply of the power supply voltage to the PU, the register file, and the memory, and a clock frequency control that controls the frequency of the clock supplied to the high-performance CPU, the register file, and the memory based on the stored information in the mode control register. The power supply control unit supplies the power supply voltage to the low power consumption CPU and stores the power supply voltage to the high performance CPU when the mode control register stores information designating the low power consumption CPU. Stop the supply,
When the information for designating the high-performance CPU is stored in the mode control register, the power-supply voltage is supplied to the high-performance CPU, the register file, and the memory based on the stored information indicating the power-supply voltage, and the low power consumption is achieved. The supply of the power supply voltage to the CPU for power supply is stopped, and the clock frequency control unit is based on the information indicating the stored clock frequency when the information for designating the high performance CPU is stored in the mode control register. The clock is supplied to the high-performance CPU, the register file, and the memory.

According to the structure of claim 5, in addition to the same effect as in claim 4, the register file and the memory are shared by the two CPUs, so that the circuit resources can be reduced.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a block diagram of the semiconductor integrated circuit device of the embodiment of FIG.

In FIG. 1, reference numeral 10 denotes a semiconductor integrated circuit device according to this embodiment, to which an instruction executed by a CPU and a power supply voltage are input from the outside. In the semiconductor integrated circuit device of the present invention, in the region 100 having a high threshold voltage, the transistor formed there has a small leak current, but the performance is low, and a circuit suitable for low power consumption is realized. In the region 101 where the threshold voltage is low, the transistor formed there has a large leak current, but the performance is high, and a circuit suitable for high performance is realized.

In this semiconductor integrated circuit device, the CPU 1
A low power consumption CPU 10 includes a memory 111 and a register file 112. The CPU 120 becomes a high-performance CPU, and has a memory 121 and a register file 122.
Is included.

The instruction analysis unit 132 analyzes the instructions executed by the CPU and classifies which CPU is processed.

The mode control register 130 sets which CPU executes an instruction based on the result analyzed by the instruction analysis unit 132, and the power supply voltage application processing and the execution of the instruction are optimal based on the setting of this register. It is executed by the CPU.

In the power supply switch unit 131, it is determined whether the power supply voltage is applied or cut off.
Then, the power supply is applied.

In this semiconductor integrated circuit device, a normal instruction is executed by the low power consumption CPU 110, and at that time, the power supply to the high performance CPU 120 is cut off to reduce the leak current. Execution of processing that requires high performance (speedup)
By executing the processing with the high-performance CPU 120, it is possible to realize a process that satisfies the demand. However, since the CPU 120 also has a large amount of leak current and the like, low power consumption can be realized by turning off the power when it is not necessary to use.

The operation of the semiconductor integrated circuit device of this embodiment will be described in detail with reference to the processing flow shown in FIG.

In this semiconductor integrated circuit device, the low power consumption CPU 110 always operates. That is,
The voltage input to the power supply switch unit 131 via the power supply line P100 is always applied to the CPU 110 via the power supply line P102. High performance CP
U120 may or may not be used depending on the processing content, and the power supply switching unit 131 controls the voltage of the power supply line P101 to enable power supply only when necessary.

In the command input step 200, the signal line S
The instruction input via 100 is the instruction analysis step 20.
1 is analyzed by the instruction analysis unit 132, and the signal line S10
Based on the analysis result transmitted via 1, the value is set in the mode control register 130 in the mode control register updating step 202. The processing is classified into the following three types based on the setting contents.

(1) Same CPU (110 or 12
0) Continue processing (2) Low power consumption CPU 110 to high performance CPU 120
Process transition to (3) High-performance CPU 120 to low power consumption CPU 110
Here, in the case of the processing in the same CPU of (1), the same CP is directly used in the instruction execution step 208.
When the process is executed in U and the command execution is completed, in the command completion notification step 210, the mode control register 130 is notified of the completion of the process via the signal line S103 or S104, and the next command input is awaited.

In the case of (2) the process transition from the low power consumption CPU 110 to the high performance CPU 120, first, in the voltage application step 203 to the high performance CPU, the power supply switching unit 131 causes the power supply line P101 to perform high voltage operation. The voltage is applied to the performance CPU 120, and then, in the register file and memory transfer step 204, the signal line S10
5, the contents of the memory 111 and the register file 112 are transferred to the memory 121 and the register file 12 via S106.
2, and the high-level CPU 120 executes the command input through the signal line S100 in the high-level CPU's command execution step 207 for the first time in this state. When the instruction execution is completed, the instruction completion notification step 21
At 0, the completion of processing is notified to the mode control register 130 via the signal line S104, and the next command input is awaited. With this migration processing, the semiconductor integrated circuit device of the present embodiment achieves the highest performance, but also consumes the maximum power.

In the case of the process transition from the high performance CPU 120 to the low power consumption CPU 110 of (3), in the register file and memory transfer step 205, the signal line S1
05, through S106, the contents of the memory 121 and the register file 122 are transferred to the memory 111 and the register file 1
Transfer to 12 and shut down voltage of high performance CPU Step 206
, The voltage applied via the power supply line P101 is cut off by the power supply switch unit 131, and in the instruction execution step 209 in the low power consumption CPU, the command input via the signal line S100 is converted into the low power consumption CPU.
Execute at 110. When the instruction execution is completed, in the instruction completion notifying step 210, the mode control register 130 is notified of the processing completion through the signal line S103, and the next instruction input is awaited. By this transition processing, the semiconductor integrated circuit device of this embodiment is in a low power consumption state.

As described above, by selecting the CPU according to the performance desired by the instruction to be executed, performing the processing, and cutting off the unnecessary power source, the performance and the power consumption are optimized. A semiconductor integrated circuit device can be realized, and both high performance and low power consumption can be achieved.

In this embodiment, the high performance CPU 1
Although the power supply voltage is applied to the low power consumption CPU 110 when the instruction is executed at 20, the power supply switch unit 13
By configuring the power supply voltage to the low power consumption CPU 110 to be cut off by 1, the power consumption can be further reduced.

The low power consumption CPU 110 and the high performance C
The power supply voltage applied to the PU 120 does not necessarily have to be the same voltage, and it is possible to further reduce power consumption by making the voltage variable according to the performance particularly required.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
3 is a block diagram of the semiconductor integrated circuit device of the embodiment of FIG.

In FIG. 3, reference numeral 30 denotes a semiconductor integrated circuit device according to this embodiment, which receives commands to be executed by the CPU and power supply voltage from the outside. In the semiconductor integrated circuit device of the present invention, in the region 300 having a high threshold voltage, the transistor formed there has a small leak current, but the performance is low, and a circuit suitable for low power consumption is realized. In the region 301 where the threshold voltage is low, the transistor formed there has a large leak current, but the performance is high, and a circuit suitable for high performance is realized. In this semiconductor integrated circuit device, the CPU 310 is a low power consumption CPU and the CPU 320 is a high performance CPU. Memory 311
And the register file 312 are connected to the signal lines S305 and S30.
6 is connected to the CPU 310, and signal lines S307 and S30
8 are connected to the CPU 320, and are commonly used by the low power consumption CPU 310 and the high performance CPU 320, respectively, but since access from two CPUs is not allowed at the same time, the CPUs that are not used are always powered. Shall be cut off.

The instruction analysis unit 332 analyzes the instructions executed by the CPU and classifies which CPU is processed.

The mode control register 330 sets which CPU executes an instruction based on the result analyzed by the instruction analysis unit 332, and the power supply voltage application processing and the instruction execution are optimal based on the setting of this register. It is executed by the CPU.

The power supply switch unit 331 determines whether the power supply voltage is applied or cut off by the mode control register 330.
Then, the power supply is applied.

The power supply voltage control unit 333 determines whether to apply the input voltage as it is, to apply a voltage higher than the input voltage, or to cut off the power supply according to the contents of the mode control register 330. Apply power.

In this semiconductor integrated circuit device, the memory 31
1. Low power consumption CPU 310 register file 312
It is shared by the high-performance CPU 320 and the high-performance CPU 320 to reduce the circuit resources.
Since simultaneous access from one CPU 310, 320 is not permitted, it is necessary to take care so that a state where the power supply voltage is simultaneously applied to both the two CPUs 310, 320 does not occur.

Normal instructions are executed by the low power consumption CPU 310, and at that time, the power supply to the high performance CPU 320 is cut off to reduce the leak current. The high-performance CPU 320 can execute the process that requires high performance, and the process that satisfies the request can be realized. However, at this time, the low-power-consumption CPU 310 needs to be powered off. At this time, the high-performance CPU 320 is composed of transistors having a low threshold voltage, but the memory 311 and the register file 312 are composed of transistors having a high threshold voltage, so that the operation is slower than that of the CPU 320, and maximum performance is achieved. In this semiconductor integrated circuit device, the voltage applied to the memory 311, the register file 312, and the like can be made higher than usual by the power supply voltage control unit 333 because it cannot be extracted.

The operation of the semiconductor integrated circuit device of this embodiment will be described in detail with reference to the processing flow shown in FIG.

In this semiconductor integrated circuit device, the instruction input through the signal line S300 in the instruction input step 400 is analyzed by the instruction analysis unit 332 in the instruction analysis step 401, and the analysis result transmitted through the signal line S301 is obtained. Based on the mode control register update step 40
2, the value is set in the mode control register 330. The processing is classified into the following three types based on the setting contents.

(A) Same CPU (310 or 32
0) Continuation of processing (b) Low power consumption CPU 310 to high performance CPU 320
Process transition to (c) High performance CPU 320 to low power consumption CPU 310
Here, in the case of the processing by the same CPU in (a), the same CP is directly used in the instruction execution step 405.
When the process is executed in U and the command execution is completed, in the command completion notification step 411, the mode control register 330 is notified of the completion of the process through the signal line S304, and the next command input is awaited.

In the case of the process transition from the low power consumption CPU 310 to the high performance CPU 320 of (b), first, in the voltage cutoff step 412 of the low power consumption CPU, the power supply voltage control unit 333 applies the power via the power supply line P303. In step 403 of applying a voltage to the high-performance CPU, the power supply switch 33 is shut off.
1, the high-performance CPU 32 through the power line P301
A voltage is applied to 0, and then the instruction input via the signal line S300 in the instruction execution step 404 in the high-performance CPU is executed in the high-performance CPU 320. When the instruction execution is completed, in the instruction completion notification step 411,
The processing is notified to the mode control register 330 via the signal line S304, and the next command input is awaited. With this migration processing, the semiconductor integrated circuit device of this embodiment achieves high performance, but consumes a large amount of power.

In this method, the high-performance CPU 320 is composed of transistors having a low threshold voltage, whereas the memory 311 and the register file 312 to be used are composed of transistors having a high threshold voltage, resulting in poor performance. Therefore, the performance of the high performance transistor cannot be maximized. Therefore, here, the high-performance CPU 320
As a method of extracting the maximum performance of the above, it is conceivable to increase the voltage applied to the memory 311 and the register file 312 designed with a high threshold voltage. The method will be described below.

Voltage application step 403 to high performance CPU
In the step S <b> 406, after applying a voltage to the high-performance CPU 320 via the power supply line P <b> 301 by the power supply switch unit 331, the high voltage generated by the power supply voltage control unit 333 is applied in the high voltage application step 406 to the register file and the memory. The memory 311 via the power line P302,
The command is applied to the register file 312, and then the command input via the signal line S300 in the command execution step 407 in the high-performance CPU is executed in the high-performance CPU 320. When the instruction execution is completed, in step 407 of releasing the high voltage to the register file and the memory, the high voltage generated by the power supply voltage control unit 333 is returned to the normal voltage and applied through the power supply line P302, and then the instruction completion notification is issued. In step 411, the mode control register 330 is notified of the completion of processing through the signal line S304, and the next command input is awaited. With this transition processing, the semiconductor integrated circuit device of the present embodiment achieves the highest performance, but is in a state of consuming the maximum power consumption.

In the case of processing transition from the high performance CPU 320 to the low power consumption CPU 310 of (c), the high performance CPU
In the voltage cut-off step 409 of 320, the voltage applied via the power supply line P301 is cut off by the power supply switch section 331, and in the voltage application step 413 to the low power consumption CPU, the voltage applied by the power supply voltage control section 333 is changed to Low power consumption CPU 31 through the power line P303
0, instruction execution in low power consumption CPU Step 4
In 10, the low power consumption CPU 310 executes the command input via the signal line S300. When the instruction execution is completed, in the instruction completion notifying step 411, the mode control register 330 is notified of the completion of processing through the signal line S304, and the next instruction input is awaited. By this transition processing, the semiconductor integrated circuit device of this embodiment is in a low power consumption state.

In this way, by selecting the CPU according to the performance desired by the instruction to be executed, performing the processing, and cutting off the unnecessary power source, the performance and the power consumption are optimized. A semiconductor integrated circuit device can be realized, and both high performance and low power consumption can be achieved. In addition, the memory 311,
By sharing the register file 312, circuit resources can be reduced and high performance can be achieved at the same time.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
3 is a block diagram of the semiconductor integrated circuit device of the embodiment of FIG.

In FIG. 5, reference numeral 50 denotes the semiconductor integrated circuit device of this embodiment, to which instructions executed by the CPU, power supply voltage, and clock are input from the outside. In the semiconductor integrated circuit device of the present invention, in the region 500 having a high threshold voltage, the transistor formed there has a small leak current, but the performance is low, and a circuit suitable for low power consumption is realized. In the region 501 where the threshold voltage is low, the transistor formed there has a large leakage current, but the performance is high, and a circuit suitable for high performance is realized. In this semiconductor integrated circuit device, the CPU 510 is a low power consumption CPU, and the memory 511 and the register file 512 are used.
Is included. The CPU 520 is a high performance CPU and includes a memory 521 and a register file 522.

The instruction analysis unit 532 analyzes the instruction executed by the CPU to determine which CPU is to be processed, and when the instruction is executed by the high performance CPU 520, the required operating frequency and To determine the minimum required power supply voltage. To add a little explanation, the CPU 520 executes a process (instruction) that requires high-speed processing (high performance), and at that time, since there is an operating frequency required in accordance with the instruction, the instruction is executed at that frequency. This frequency is closely related to the power supply voltage, and must be a certain voltage or more to realize a certain frequency.

The mode control register 530 sets which CPU should execute the instruction based on the result analyzed by the instruction analysis unit 532, and how much frequency should be set for the instruction executed by the high performance CPU 520. The power supply voltage is set, the power supply voltage application process and the clock frequency adjustment process are performed based on the setting of this register, and the instruction is executed by the optimum CPU with the optimum power consumption.

The power supply voltage control unit 531 determines whether to apply or cut off the power supply voltage according to the contents of the mode control register 530, and executes the application of power. Further, when the high-performance CPU 520 executes processing, a voltage for realizing the required frequency is applied.

The clock frequency control section 533 transmits a clock having a frequency to be applied to each CPU according to the contents of the mode control register 530.

In this semiconductor integrated circuit device, a normal instruction is executed by the low power consumption CPU 510, and at that time, the power supply to the high performance CPU 520 is cut off to reduce the leak current. Execution of processing that requires high performance requires high performance CP
By executing the process in U520, it is possible to realize a process that satisfies the request. At that time, by applying the minimum voltage necessary for realizing the desired frequency, it is possible to reduce the power consumption during operation. Further, since the high-performance CPU 520 has a large amount of leak current, low power consumption can be realized by shutting off the power when it is not necessary to use it.

The operation of the semiconductor integrated circuit device of this embodiment will be described in detail with reference to the processing flow shown in FIG.

In this semiconductor integrated circuit device, the low power consumption CPU 510 is assumed to operate constantly. That is,
It is assumed that the voltage input to the power supply voltage control unit 531 via the power supply line P500 is always applied to the CPU 510 via the power supply line P502 as it is. The clock input to the clock frequency control unit 533 via the clock line C500 is always supplied to the CPU 510 as it is via the clock line C502. The high-performance CPU 520 may or may not be used based on the processing content, and the power supply voltage control unit 531 controls the voltage of the power supply line P501 to enable power supply only when necessary. Also, the applied voltage is the minimum voltage that satisfies the required performance.

In the command input step 600, the signal line S
The instruction input via 500 is the instruction analysis step 60.
1 is analyzed by the instruction analysis unit 501, and the signal line S50
Based on the analysis result transmitted via 1, the value is set in the mode control register 530 in the mode control register update step 602. The processing is classified into the following three types based on the setting contents.

(A) Same CPU (510 or 52)
0) Continuation of processing (B) Low power consumption CPU 110 to high performance CPU 120
Process transition to (C) High performance CPU 120 to low power consumption CPU 110
Here, in the case of the processing by the same CPU in (A), when the low power consumption CPU 510 is continuously used,
In the instruction execution step 611, processing is executed by the same CPU, and when the instruction execution is completed, in the instruction completion notification step 613, the mode control register 530 is notified of the completion of processing through the signal line S503, and the next instruction input is input. I will wait. When the high-performance CPU 520 is continuously used, a voltage application step 60 to the high-performance CPU
6, the power supply voltage determined based on the information obtained from the mode control register 530 is applied via the signal line S502, and the clock is supplied to the high-performance CPU in step 607.
Then, through the signal line S507, the mode control register 530
A clock having a frequency determined based on the information obtained from is applied through the clock line C501, and under this condition, in the instruction execution step 611, the high performance CPU 5
When the processing is executed in step 20 and the instruction execution is completed, in step 613 of the instruction completion notification, after the processing completion is notified to the mode control register 530 via the signal line S504, the clock supply to the high-performance CPU 520 is stopped (this The steps are not shown), and the next command input is awaited.

In the case of the process transition from the low power consumption CPU 510 to the high performance CPU 520 in (B), first, in the voltage application step 603 to the high performance CPU, the signal line S
The power supply voltage determined based on the information obtained from the mode control register 530 via the power supply voltage control unit 502.
High-performance CP
In the step 604 of supplying the clock to U, the signal line S50
7, a clock having a frequency determined based on the information obtained from the mode control register 530 is applied from the clock frequency control unit 533 via the clock line C501,
Next, in the register file and memory transfer step 605, the memory 51 is accessed via the signal lines S505 and S506.
1, the contents of the register file 512, the memory 521,
The instruction input via the signal line S500 in the instruction execution step 610 in the high-performance CPU is first transferred to the register file 522, and this state is brought into this state.
Run at 20. When the instruction execution is completed, in the instruction completion notifying step 613, after the processing completion is notified to the mode control register 530 via the signal line S504, the clock supply to the high performance CPU 520 is stopped (this step is not shown), It will wait for the next command input. By this migration processing, the semiconductor integrated circuit device of the present embodiment can realize optimum execution in terms of performance and power consumption for the instruction to be executed.

In the case of the process shift from the high performance CPU 520 to the low power consumption CPU 510 of (C), in the register file and memory transfer step 608, the signal line S5
05, through S506, the contents of the memory 521 and the register file 522 are transferred to the memory 511 and the register file 5
Transfer to 12 and shut down voltage of high-performance CPU Step 609
, The voltage applied through the power supply line P501 is cut off by the power supply voltage control unit 531, and in the instruction execution step 612 in the low power consumption CPU, the signal line S
A low power consumption CPU 51 executes an instruction input via 500.
Run at 0. When the instruction execution is completed, in the instruction completion notification step 613, the processing completion is notified to the mode control register 530 via the signal line S503, and the next instruction input is waited. By this transition processing, the semiconductor integrated circuit device of this embodiment is in a low power consumption state.

As described above, the CPU is selected according to the performance desired by the instruction to be executed, and the performance
By performing optimal processing with electric power and shutting off unnecessary power, a semiconductor integrated circuit device with optimal performance and power consumption can be realized, and both high performance and low power consumption can be achieved. Can be planned.

In this embodiment, the high performance CPU 5
Although the power supply voltage is applied to the low power consumption CPU 510 when the instruction is executed in 20, the power supply voltage control unit 531 cuts off the power supply voltage to the low power consumption CPU 510 to reduce the power consumption. Electricity can be saved.

The configuration of the third embodiment is the same as that of the first embodiment except that the clock frequency and the power supply voltage are controlled according to the instruction to be executed at the time of processing by the high-performance CPU. However, this configuration can be similarly applied to the second embodiment. in this case,
Regarding the clock supply to the memory 311 and the register file 312, the specified frequency is supplied to the CPU specified in the mode control register 330. Power supply voltage is cut off for unused CPUs, but at this time the power supply voltage is cut off
The clock supply to U is also stopped. Also, a high-performance CPU
At the time of the processing in 1, the clock having the voltage and frequency according to the processing is supplied to the memory 311 and the register file 312.

[0071]

As described above, according to the present invention,
The CPU to be used is selected according to the processing contents to be actually executed in the semiconductor integrated circuit. When high performance processing is required, the high performance CPU is used. At other times, low power consumption CPU is used. It is also possible to take measures against leak current etc. by cutting off the voltage applied to the high-performance CPU at that time, and to achieve both high performance and low power consumption even in today's system LSI whose process is miniaturized. It can be automated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a process flow chart in the semiconductor integrated circuit device shown in FIG.

FIG. 3 is a block diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a process flow chart in the semiconductor integrated circuit device shown in FIG.

FIG. 5 is a block diagram showing a semiconductor integrated circuit device according to a third embodiment of the present invention.

6 is a process flow chart in the semiconductor integrated circuit device shown in FIG.

[Explanation of symbols]

100, 300, 500 High threshold voltage region 101, 301, 501 Low threshold voltage region 110, 310, 510 Low power consumption CPU 111, 121, 311, 511, 521 Memory 112, 122, 312, 512, 522 Register files 120, 320, 520 High-performance CPUs 130, 330, 530 Mode control registers 131, 331 Power supply switch units 132, 332, 532 Command analysis units 333, 531 Power supply voltage control unit 533 Clock frequency control unit

Claims (5)

[Claims] 1. A high-performance CPU configured by using a transistor with a low threshold voltage, a low-power consumption CPU configured by using a transistor with a high threshold voltage, and a high-performance CPU by analyzing an input instruction. An instruction analysis unit that determines which of a performance CPU and a low power consumption CPU should execute the instruction, and a CPU that executes the input instruction based on the determination of the instruction analysis unit A mode control register for storing information; and a power supply control unit for controlling supply of a power supply voltage to the high-performance CPU based on the stored information in the mode control register, wherein the power supply control unit is the mode control register. When the information for designating the low power consumption CPU is stored in, the supply of the power supply voltage to the high performance CPU is stopped, and the mode control register stores the information. Semiconductor product circuit device to supply a power supply voltage to the high performance for the CPU when information specifying the performance for the CPU are stored. 2. A high performance CPU configured by using a low threshold voltage transistor, a low power consumption CPU configured by using a high threshold voltage transistor, and the high performance CPU and low power consumption A register file and a memory shared for executing instructions by the CPU, and an instruction to be analyzed to determine which of the high performance CPU and the low power consumption CPU should execute the instruction. An instruction analysis unit for determining, a mode control register for storing information designating a CPU that executes the input instruction based on the determination of the instruction analysis unit, and the high performance type based on the storage information of the mode control register A power supply control unit that controls the supply of a power supply voltage to the CPU and the low power consumption CPU, wherein the power supply control unit stores the mode control register in the mode control register. When the information designating the low power consumption CPU is stored, the power supply voltage is supplied to the low power consumption CPU, the power supply voltage to the high performance CPU is stopped, and the high voltage is stored in the mode control register. A semiconductor integrated circuit device configured to supply a power supply voltage to the high performance CPU and to stop the supply of a power supply voltage to the low power consumption CPU when information for designating a performance CPU is stored. 3. The register file and the memory are configured by using a transistor having a high threshold voltage, the power supply control unit also controls the supply of the power supply voltage to the register file and the memory, and the high voltage is stored in the mode control register. 3. The power supply voltage higher than the power supply voltage supplied to the high performance CPU is supplied to the register file and the memory when the information designating the performance CPU is stored. Semiconductor integrated circuit device. 4. A high-performance CPU configured by using a transistor with a low threshold voltage, a low-power consumption CPU configured by using a transistor with a high threshold voltage, and a high-performance CPU by analyzing an input instruction. The CPU for performance or the CPU for low power consumption determines which instruction is to be executed, and when it is determined that the instruction is to be executed by the CPU for high performance, the instruction is executed. And an instruction analysis unit that determines a clock frequency and a minimum power supply voltage necessary to realize this clock frequency, and information that specifies a CPU that executes the input instruction based on the determination of the instruction analysis unit. When storing the information for designating the high-performance CPU, the information indicating the clock frequency for execution by the high-performance CPU and this information are stored. A mode control register that stores information indicating the minimum power supply voltage required to realize the clock frequency, and a power supply that controls the supply of the power supply voltage to the high-performance CPU based on the stored information in the mode control register. And a clock frequency control unit that controls a frequency of a clock supplied to the high-performance CPU based on information stored in the mode control register, wherein the power supply control unit stores the low power consumption in the mode control register. When the information designating the power CPU is stored, the supply of the power supply voltage to the high performance CPU is stopped, and further stored when the information designating the high performance CPU is stored in the mode control register. The power supply voltage is supplied to the high-performance CPU based on the information indicating the supplied power supply voltage, and the clock frequency control is performed. The section supplies a clock to the high-performance CPU based on the stored information indicating the clock frequency when the mode control register stores information designating the high-performance CPU. Integrated circuit device. 5. A high performance CPU configured by using a low threshold voltage transistor, a low power consumption CPU configured by using a high threshold voltage transistor, and the high performance CPU and low power consumption A register file and a memory shared for executing instructions by the CPU, and an instruction to be analyzed to determine which of the high performance CPU and the low power consumption CPU should execute the instruction. At the same time as determining the instruction to be executed by the high performance CPU, the clock frequency for executing the instruction and the minimum power supply voltage required to realize the clock frequency are determined. The instruction analysis unit stores information specifying a CPU that executes the input instruction based on the determination of the instruction analysis unit, and A mode control for storing information designating an active CPU, which stores information indicating a clock frequency when the high-performance CPU executes, and information indicating a minimum power supply voltage required to realize this clock frequency. A register, a power supply control unit that controls supply of a power supply voltage to the high-performance CPU and the low-power-consumption CPU, the register file and the memory based on information stored in the mode control register, and storage of the mode control register And a clock frequency control unit that controls a frequency of a clock supplied to the register file and the memory based on information. The power supply control unit includes the low power consumption CPU in the mode control register. When the specified information is stored, the power supply voltage is supplied to the low power consumption CPU. If the information for designating the high-performance CPU is stored in the mode control register, the supply of the power-supply voltage to the high-performance CPU is stopped based on the information indicating the stored power-supply voltage. The power supply voltage is supplied to the high-performance CPU, the register file, and the memory, and the supply of the power supply voltage to the low-power consumption CPU is stopped, and the clock frequency control unit stores the high-voltage in the mode control register. A semiconductor integrated circuit device configured to supply a clock to the high performance CPU, the register file and the memory based on the stored information indicating the clock frequency when the information designating the high performance CPU is stored.