JP2003323338A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor having a memory control function for avoiding a collision and competition in an image memory such as VRAM in operation adaptive to a multiprocess. <P>SOLUTION: This image processor has an address converter for converting a logical address used for designating an address of the image memory into a corresponding physical address, and a plurality of picture element arithmetic operation means for respectively arithmetically operating a picture element, and making access to the image memory by using this physical address by acquiring the physical address by imparting the logical address to the address converter when making access to the image memory accompanied by an arithmetic operation of the picture element. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for performing pixel calculation, and more particularly to an image processing apparatus having a memory management function required during multi-process operation.

[0002]

2. Description of the Related Art In recent years, a graphics processor (GP
In U), higher clocks and higher parallelization are progressing due to the explosive increase in the required calculation amount. In addition, generalization is progressing to improve expressiveness, and in the future, MPEG (Motion Pic)
ture Experts Group) 2 or MPEG4, and is likely to be used for processing other than 3D graphics such as image recognition. In such a case, it is quite possible that multiple processes utilize the graphics processor at the same time.

In principle, the graphics processor operates under the control of the central processing unit (CPU), and the graphics processor does not operate the rasterizer autonomously. Also, when only one process uses the graphics processor,
The process uses all of the rasterizers as computing elements. However, when using a graphics processor from a multi-process, a plurality of rasterizers are grouped for each process unit, and a plurality of rasterizers are shared by each group.

[0004]

In the configuration of the conventional graphics processor, memory access is always performed by using a physical address. Therefore, when a plurality of rasterizers are separately used by a plurality of processes, an image memory such as VRAM is used. However, there is a problem in that a collision or a conflict occurs. For example, when one process draws and draws a 3D polygon using a certain rasterizer group, another process uses another rasterizer group to perform MPEG decoding.

Conventionally, no workaround for this problem has been taken in consideration of the use of multi-process. This is because, as described above, only one process conventionally uses the graphics processor, and at this time, the process uses all the rasterizers as the calculation elements, and such a conflict cannot occur. .

The present invention has been made in view of the above circumstances, and an object thereof is an image processing apparatus having a memory management function capable of avoiding collision and conflict in an image memory such as VRAM during an operation compatible with multi-process. The purpose is to provide.

[0007]

In order to solve the above problems and achieve the object, the present invention is constructed as follows.

According to the present invention, in an image processing apparatus for accessing an image memory and performing image processing, an address converter for converting a logical address used for addressing the image memory into a corresponding physical address, and a pixel operation respectively. The physical address is acquired by giving a logical address to the address converter when accessing the image memory associated with the pixel calculation, and accessing the image memory using the physical address. And a plurality of pixel calculation means for performing the calculation.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a graphics processor system according to a first embodiment of the present invention. This system includes a central processing unit (CPU) 2, a main memory 3, a graphics processor 5 and a VRAM on a system bus 1.
It is composed of a graphic card 4 having an (image memory) 6 and a display 7. The system shown in the figure can be regarded as a general-purpose computer system, and the memory protection mechanism according to the features of the present invention is provided between the graphics processor 5 and the VRAM 6. The configuration is shown in FIG. 4 and subsequent figures. . The graphics card 4 has a configuration including a VRAM 6 as an external unit dedicated to the graphics processor 5, and such a VRAM 6 is usually mounted on the same substrate as the graphics processor 5. According to this configuration, the graphics processor 5 can occupy the access to the VRAM 6, which is preferable in terms of performance. The arrangement position of the VRAM may be different depending on the difference in the graphics system. Other configuration examples in this case are shown in FIGS. 14 and 15 described later.

FIG. 2 is a block diagram showing the schematic arrangement of the graphics processor according to this embodiment. As shown in the figure, a geometry section (T & L) 51, a setup 52 constituting a rasterizer section, and n pixel pipelines 531, 532 ,. ． ． It is composed of 53n. Pixel pipelines 531, 532 ,. ． ． 5
Each 3n can access the texture memory 61 and the frame buffer 62 of the VRAM 6, respectively. The VRAM 6 holds information for generating color data in the texture memory 61. Alternatively, in some cases, only the color data may be held in the texture memory 61. In this specification, this information is referred to as “texture”.
Called.

The rasterizer part is composed of 3 parts by the geometry part.
A unit for finally obtaining pixel data to be displayed on a screen from data such as vertices, colors, and texture coordinates that are perspective-transformed from a two-dimensional space into a two-dimensional plane. The pixel pipelines 531, 532 ,. ． ． 53n includes texture mapping and fragment processing (R
Responsible for MW (Read Modify Write) and logical address generation.

That is, when the screen coordinates and the texture coordinates from the geometry section are input, the pixel pipelines 531 to 53n forming the pixel calculation section read the texture data from the texture memory 61 and calculate the pixel value. Then, the writing process to the frame buffer 62 is performed. Here, the color data is made to correspond to the input screen coordinates. Some kind of calculation is performed on the information of the color data to generate color data after calculation, and the color data is associated with the screen coordinates. This operation is called "texture mapping". After texture mapping, the color data is stored in frame buffer 6
It is written in the position on 2 corresponding to the screen coordinates. The frame buffer 62 holds color data for each screen.

At the final stage of the pixel pipeline, some operation is performed between the color data already existing in the frame buffer 62 and the generated color data, and the color data is written in the frame buffer 62. This process is RMW.

FIG. 3 is a diagram showing the flow of three-dimensional display processing by the graphics processor system according to this embodiment.

The three-dimensional display process is basically an application process S1, a geometry process S2, and a rasterizer process S.
Broadly divided into three. The application process S1 is, for example, in the case of assuming a racing game, a process according to the rotation of the steering wheel by the user and the movement of the enemy vehicle. The direction of the viewpoint changes according to the handle rotation operation, and the model information is passed to the geometry processing S2. The geometry process S2 is a process of converting the data, which was treated as three-dimensional in the application process S1, into two-dimensional plane data for displaying on the display (CRT) 7. This is called perspective transformation. Further, the geometry processing S2 includes processing for determining the color of the model based on the light source information in the three-dimensional space.
The main processing of the rasterizer processing S3 is processing (texture mapping) of coloring the polygons of the model converted into two dimensions. The final color is determined from the color obtained from the light source information and the texture information associated with the polygon data.

In the configuration of the graphics processor system according to this embodiment, the application processing S
The CPU 2 performs 1 and the graphics processor 5 performs the geometry processing S2 and the rasterization processing S3.
Note that the rasterizer process S3 is generally unsuitable for the CPU 2, but the geometry process S2 is based on a simple matrix operation. Therefore, the geometry process by the CPU 2 having a multimedia instruction (SSE) is performed. There may be a configuration in which S2 is performed instead of the graphics processor 5.

FIG. 4 is a block diagram showing a first structural example of the memory protection mechanism according to this embodiment.

The memory protection mechanism according to the first configuration example of the present embodiment has a page table 63 on the VRAM 6 and one memory management unit (provided between the plurality of pixel pipelines 531 to 53n and the page table 63). It is composed of an MMU (Memory Management Unit) 54.

Each of the pixel pipelines 531 to 53n as a pixel operation unit has a storage area (or register) holding a process ID. Alternatively, the MMU 54 may be the pixel pipelines 531-5.
Information indicating the correspondence between each of the 3n and the process ID is held. This allows the pixel pipeline 531 to
Different process IDs can be associated with each of the 53n, and thus each pixel pipeline can have a different address space. VR on the logical address space corresponding to the physical address space of VRAM6
The AM is called "virtual VRAM" in this embodiment.

It should be noted that the process can utilize as many pixel pipelines as necessary according to the load. Normal,
There are a plurality of units of pixel pipelines 531 to 53n. For example, in this embodiment, 8 units (n = 8) are mounted.

The access from the pixel pipelines 531 to 53n to the VRAM 6 occurs at two points, when reading from the texture memory 61 and when writing to the frame buffer 62. The memory protection mechanism is provided for the purpose of preventing a problem (memory protection) due to different processes accessing the same area on the VRAM 6.

FIG. 5 shows an example of address conversion by the memory protection mechanism according to the first configuration example. The MMU 54 receives the process ID from each of the pixel pipelines 531 to 53n.
When it receives the logical address and the logical address, it refers to the page table 63 and converts it into a physical address on the VRAM 6. In the example of FIG. 5, the upper 20 bits of the 32-bit address are the page number and the lower 12 bits are the offset. The MMU 54 has a pixel pipeline 531.
The upper 20 bits of the process ID and the logical address received from ˜53n are searched in the page table 63 to obtain the physical address stored in the corresponding entry. In this example, the physical address obtained from the page table 63 with the offset added is the physical address corresponding to the logical address. In the example of FIG. 5, the page number bit number is 20 bits and the offset bit number is 12 bits, but it goes without saying that these values are arbitrary depending on the system configuration and the like.

A TLB (Translation Lookaside Buf) is provided between the MMU 54 and the page table 63 of the VRAM 6.
fer; conversion index buffer)
B may be used to perform conversion from a logical address to a physical address so that each rasterizer can operate the same process in cooperation with each other.

The specific operation of this embodiment will be described below.
The texture mapping processing by the graphics processor 5 will be described. This process includes a first half process involving a read operation from the VRAM 6 and a second half process involving a write operation to the VRAM 6.

FIG. 6 is a diagram showing how VRAM accesses from a plurality of processes collide.

As a possibility that different processes use the same VRAM area, consider simultaneous rendering by two different processes (process 1 and process 2). Process 1 and process 2 have unique process numbers p1 and p
Have two. Further, the process 1 is 4 of 531 to 534.
It is assumed that rendering is performed using a pixel pipeline of four books, and Process 2 performs rendering using four pixel pipelines of 535 to 538. The two processes have their own textures and framebuffers, and it is usually not allowed for different processes to access the same texture area or framebuffer.

Access to the VRAM occurs in two stages, that is, texture read and frame buffer writing. At this time, in the case where the graphics processor system has the conventional configuration without the MMU 54 as shown in FIG. 4, a different process is performed. The same physical memory area on VRAM may be accessed (VRAM access collision or contention). For example, there is a situation in which the process 1 and the process 2 set the frame buffer 620 in the same physical memory area and write the frame buffer 620 alternately. In such a situation, for example, if the programs of process 1 and process 2 are
It can be easily assumed that this may occur in the case where they are created using the same library. When a VRAM access collision occurs, the data stored in the frame buffer 620 may be inconsistent.

On the other hand, FIG. 7 is a view showing the operation of the memory protection mechanism according to the first configuration example of this embodiment. The MMU 54 performs logical-to-physical address translation so that access to VRAM from different processes does not conflict or conflict.

First, it is assumed that the process 1 has been activated first. In FIG. 7, reference numeral 81 indicates a memory map of the virtual VRAM of the process 1. Process 1 has an area to hold its own texture and a frame buffer, so
The operating system (OS) refers to the page table 63 when the process 1 is activated, and reserves an unused memory area as a usable memory area of the process 1. Since only one process has been started yet, there is no memory conflict. Next, it is assumed that the process 2 is activated. In FIG. 7, reference numeral 82 is a virtual VR of process 2.
The memory map of AM is shown. When the process 2 is activated, the OS similarly refers to the page table 63 and maps the unused memory area as an area dedicated to the process 2.

If a memory access from either process 1 or process 2 occurs, the MMU 5
4 performs the conversion from the logical address to the physical address, and the control is performed so as not to cause a conflict with each other. If it is guaranteed that the VRAM is always accessed through the MMU 54, no conflict will occur on the VRAM 6. Therefore, the process 1 and the process 2 do not interfere with each other, and the image display processing can be performed under the safe memory protection management.

For example, it is assumed that the process 2 is a process created by a maliciously created program, and the process 2 is a process that attempts to steal the drawing content on the display 7 by the process 1. In this case, the conventional configuration without the memory protection mechanism as in the present embodiment cannot protect against such a malicious process.
According to the memory protection mechanism by the MMU 54 or the like as in the present embodiment, the physical memory space is always separated even if the logical memory space is the same, so the process 2 accesses the frame buffer of the process 1. I will not receive it. Even if an access that overflows the buffer occurs, the MMU 54 can be configured not to allow this access and notify the upper OS of the error. This can eliminate malicious processes and greatly enhance security.

It is easily understood that the memory protection mechanism of this embodiment is useful for debugging. For example, when a process goes out of control and tries to access an area that should not normally be accessed, an error similar to
S can be notified, the process runaway can be stopped, and information necessary for debugging can be obtained.

The specific operation of this embodiment will be described below.
The texture mapping processing by the graphics processor 5 will be described. This process includes a first half process involving a read operation from the VRAM 6 and a second half process involving a write operation to the VRAM 6.

FIG. 8 is a flowchart showing the first half processing of texture mapping. As shown in FIG. 8, this process is performed by calculating the texture logical address (step S20).
1), physical address generation (step S202), VRA
It consists of M access (step S203) and texture data processing (step S204).

First, in step S201, logical addresses of texture color data and the like (texture data) stored in the VRAM 6 are calculated. Then step S2
02, the pixel pipelines 531 to 53n are currently
Of the process performing the process in step S2
A physical address on the VRAM 6 storing the data is generated from the logical address calculated in 01.
Next, in step S203, using the physical address generated in step S201, the VRAM 6 is accessed and the texture data is read. Then, in step S204, texture data processing such as calculating a pixel value using the texture data read in step S203 is performed.

Here, the step S202 is executed by the MMU 54 and the page table 63 shown in FIG. The MMU 54 has a different VRAM for each process identifier.
It has a function of allocating 6 physical address spaces. The page table 63 uses part or all of the logical address generated by the MMU 54, and its data is VRAM.
Address data indicating which area of 6 exists is held.

Different VRAM for different process identifiers
According to the function of the MMU 54 for allocating the physical address space on 6, the processes 1001 and 200100 are generated as physical addresses when the processes with process identifiers 1 and 2 try to access the same logical address 100, respectively. It becomes possible to do. As a result, the accessible memory space can be separated for each process, and the memory protection function at the time of reading the VRAM 6 is realized.

FIG. 9 is a flowchart showing the latter half process of the texture mapping. As shown in FIG. 9, this process is performed by calculating the frame buffer logical address (step S3).
01), physical address generation (step S302), VR
It consists of AM access (step S303).

First, in step S301, the logical address of the frame buffer 63 arranged in the VRAM 6 is calculated from the pixel coordinates. Next, in step S302,
A physical address on the VRAM 6 is calculated using the process identifier and the frame buffer logical address obtained in step S301. Then, in step S303, the VRAM 6 is accessed using the physical address of the frame buffer obtained in step S302, and the process of rewriting the data in the frame buffer indicated by the address is performed.

The step S302 is executed by the MMU 54 and the page table 63 shown in FIG. 4, and the address conversion is performed in the same manner as when reading the texture data. Therefore, it becomes possible to protect the portion to be written (frame buffer) in the VRAM 6.

The memory protection mechanism shown in FIG. 4 can be modified in various ways and will be described below. The original function of the memory protection mechanism for preventing unauthorized access to the VRAM 6 remains the same.

FIG. 10 is a block diagram showing a second configuration example of the memory protection mechanism.

In the first configuration example shown in FIG. 4, the VRAM 6 is accessed every time the page table 53 is referenced, but this second configuration example operates at high speed as a page table cache near the MMU 54. SRAM5
5 is provided. According to the second configuration example, the SRAM 5 is used for the frequently accessed logical address.
5 is referred to (that is, a cache hit occurs), the number of accesses to the VRAM 6 is reduced,
The processing speed can be increased.

FIG. 11 is a block diagram showing a third structural example of the memory protection mechanism.

In the third configuration example, the page table itself is stored in the dedicated SRAM 56 instead of the VRAM 6. In the third configuration example, the MMU 54 does not access the VRAM 6 for referring to the page table, and it is expected that the speed will be further increased as compared with the second configuration example. However, the configuration using the SRAM, which is generally more expensive than the DRAM or the like used for the VRAM 6, has a disadvantage of increasing the cost of the entire device. Note that this is the same for the second configuration example.

FIG. 12 is a block diagram showing a fourth structural example of the memory protection mechanism.

This fourth configuration example is a page table SR.
The AM 56 is provided, and the MMUs 541 to 54n are provided in the pixel pipelines 531 to 53n, respectively. According to the fourth configuration example, although the number of parts is slightly increased, the load of the address conversion processing by the MMU can be distributed according to the number of pixel pipelines, and the improvement of performance can be expected.

FIG. 13 is a block diagram showing a fifth structural example of the memory protection mechanism. In the fifth configuration example, the MMU is provided in each of the pixel pipelines as in the fourth configuration example, but the page table body is arranged in the VRAM 6. Incidentally, also in the fifth configuration example, the SRAM 55 is provided for the cache of the page table.

According to the first embodiment of the present invention described above, the memory protection mechanism including the MMU 54, the page table 63 and the like allows the V processor to control the V
Access to the RAM 6 side can be appropriately managed by logical address / physical address conversion. Therefore, in the rendering process or the like in the three-dimensional image display, it is possible to prevent collision or conflict of access to the VRAM 6 from different processes, and improve the reliability of the device.

Note that the pixel rasterization process has almost no dependency on the processing of each piece of data, unlike an ordinary processor (such as a CPU application). Therefore, for the purpose of improving the throughput, the pixel pipeline in the rasterizer has a far longer number of pipeline stages than a normal processor (the pipeline of a normal processor is about 5 to 8 stages at most, and about 20 stages at the longest). On the other hand, the number of pixel pipelines is usually 150 to 200 or more), and the number of pixel pipelines is increased to operate in parallel.

In such a situation, in order to operate a plurality of processes in the graphics processor and prevent the memory contention, it is basically a method of switching each process. In that case, every time the process is switched, it is necessary to wait until all the data that has entered the pipeline having hundreds of stages is output (swapped). You also have to use all pixel pipelines, even if one process isn't too heavy. Therefore, by configuring the memory protection mechanism by the MMU as in the embodiment of the present invention, it is possible to prevent the memory contention, and the user basically does not need to manage the memory. Moreover, a plurality of processes can be operated at the same time or individually without swapping pipeline data. In view of this point, the significance of configuring the memory protection mechanism that cooperates with the graphics processor using the MMU as in the embodiment of the present invention is not the significance of providing the MMU or the like in the normal processor. Is different.

The first embodiment described above can be modified and implemented as follows.

FIG. 14 is a diagram showing a first modification, showing another graphics processor system having a VRAM position different from that of FIG. This first modification is
The present invention is applied to a configuration that is often found in a personal computer (PC) such as an entry model. However, VR by the graphics processor 5
The access to the AM 6 and the access to the main memory 3 of the CPU 2 often collide with each other, and the performance may deteriorate as compared with the case where the dedicated VRAM is provided. In order to avoid this, the graphics processor 5 and the main memory 3
Often configured to take a wider bus band.

FIG. 15 is a diagram showing a second modification, in which the VRAM 5 is provided in the same chip as the graphics processor 5.
8 is mounted. In the sense of having a dedicated VRAM, it is similar to the configuration having an external dedicated VRAM 6, but since it is mounted in the same chip, it has overwhelming performance in terms of latency and bandwidth compared to the external configuration. Is high.
However, it cannot have more capacity than the external configuration. In the configuration having the external dedicated VRAM 6, the capacity is about 64 MB to 128 MB, whereas in the configuration of the second modification, it is about 2 to 4 M at present.

(Second Embodiment) The second embodiment of the present invention will be described below. FIG. 16 is a block diagram showing a schematic configuration of a graphics processor system according to the second embodiment of the present invention. In this structure, the same components as those in the first embodiment are designated by the same reference numerals. Of these, the memory protection mechanism composed of the MMU 54 and the page table 63 can be modified similarly to the first embodiment described above.

From the viewpoint of the pixel pipelines 531 to 53n, it is efficient to compress the read-only data and store it in the memory. However, in this case, two types of compressed data and non-compressed data are mixed on the VRAM 6, so it is necessary to decompress the data by determining whether or not it is compressed data when reading the data.

Therefore, in the configuration of this embodiment, the MMU 54
A decompression processing circuit (HW) 59 is inserted between the pixel pipelines 531 to 53n. The VRAM 6 has a texture compression area 611 and a texture non-compression area 6
12 and.

The decompression processing circuit 59 selectively reads compressed or uncompressed texture data from either the texture compression area 611 or the texture non-compression area 612, and decompresses the compressed texture data. And sends it to the pixel pipelines 531 to 53n. The timing at which the decompression processing is performed is, for example, immediately before the compressed data enters the cache of the pixel pipelines 531 to 53n.

The MMU 54 refers to the page table 63. At this time, the MMU 54 determines whether the data at the corresponding address is compressed data, based on the flag, and decompresses the decompression processing circuit 59 according to the determination result. Outputs an instruction as to whether or not to perform processing.

The arrangement position and the number of the decompression processing circuits 59 and the processing procedure are arbitrary. For example, a decompression processing circuit may be provided in each of the pixel pipelines 531 to 53n, or
As long as it has sufficient capability, a configuration may be adopted in which the only expansion processing circuit 59 is provided at the signal output port of the VRAM 6 as in the configuration of FIG.

FIG. 17 is a diagram showing address conversion by the memory protection mechanism according to the second embodiment. In the page table 63 of this embodiment, in addition to associating a logical address with a physical address, the VRA indicated by the physical address is associated with the page address.
In the area on M6, a flag indicating whether or not compressed data is stored by "Yes (true)" or "No (false)" is added. In this embodiment, the flag is "Y.
es ”, the VR indicated by the physical address
The area on AM6 is the texture compression area 611,
When the flag is “No (false)”, the area on the VRAM 6 indicated by the physical address is the texture uncompressed area 6
Twelve.

A configuration may be considered in which a flag indicating whether or not the data is compressed data is added to the data other than the page table. However, since the data area will increase to some extent and the logic for determining whether compression or non-compression will increase. Since there are expected disadvantages in terms of chip area and processing speed,
It is preferable that the page table and the MMU correspond to each other as in the present embodiment. Further, although the present embodiment has a configuration relating to texture compression / decompression, it is possible to obtain the same configuration as the present embodiment regarding data encryption / decryption.

The present invention is not limited to the above-mentioned embodiment and can be implemented by variously modifying.

[0064]

As described above, according to the present invention, it is possible to provide an image processing apparatus having a memory management function capable of avoiding a collision and a conflict in an image memory such as a VRAM during a multi-process compatible operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a graphics processor system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a graphics processor according to the above embodiment.

FIG. 3 is a diagram showing a flow of three-dimensional display processing by the graphics processor system according to the above embodiment.

FIG. 4 is a block diagram showing a first configuration example of a memory protection mechanism according to the above embodiment.

FIG. 5 is a diagram showing address conversion by the memory protection mechanism according to the first configuration example.

FIG. 6 is a diagram showing a situation in which VRAM accesses from multiple processes compete with each other.

FIG. 7 is a diagram showing an operation of the memory protection mechanism according to the first configuration example.

FIG. 8 is a flowchart showing a read operation from the VRAM in the above embodiment.

FIG. 9 is a flowchart showing a write operation to the VRAM in the above embodiment.

FIG. 10 is a block diagram showing a second configuration example of the memory protection mechanism.

FIG. 11 is a block diagram showing a third configuration example of the memory protection mechanism.

FIG. 12 is a block diagram showing a fourth configuration example of a memory protection mechanism.

FIG. 13 is a block diagram showing a fifth configuration example of the memory protection mechanism.

FIG. 14 is a block diagram illustrating another graphics processor system having a different VRAM position from that of FIG.

FIG. 15 is a block diagram showing another graphics processor system having a VRAM position different from that of FIG. 1;

FIG. 16 is a block diagram showing a schematic configuration of a graphics processor system according to a second embodiment of the invention.

FIG. 17 is a diagram showing address conversion by the memory protection mechanism according to the second embodiment of the present invention.

[Explanation of symbols]

1 ... System bus 2 ... Central processing unit (CPU) 3 ... Main memory 4 ... Graphic card 5 ... Graphics processor 6 ... VRAM (video memory) 7 ... Display 51 ... T & L 52 ... Setup 531 to 53n ... Pixel pipeline 54 ... MMU (memory management unit) 61 ... Texture memory 62 ... Frame buffer 63 ... Page table

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Jiro Amamiya             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center F-term (reference) 5B060 AB26 AC13 GA01

Claims (5)

[Claims] 1. An image processing apparatus for accessing an image memory to perform image processing, and an address converter for converting a logical address used for addressing the image memory into a corresponding physical address, and performing pixel calculation respectively. Which obtains a physical address by giving a logical address when accessing the image memory associated with the pixel calculation to the address converter,
An image processing apparatus, comprising: a plurality of pixel calculation means for accessing the image memory using the physical address. 2. An image processing apparatus for accessing an image memory and performing image processing, comprising: an address converter for converting a logical address used for addressing the image memory into a corresponding physical address; and a pixel operation. A pixel for giving a logical address when accessing the image memory associated with the pixel calculation to the address converter to obtain a physical address, and accessing the image memory using the physical address An image processing apparatus comprising a plurality of sets of arithmetic means. 3. A first physical address area of the image memory is allocated to a first process, and a second physical address area which does not overlap with the first physical address area is allocated to a second process.
3. The image processing apparatus according to claim 1, further comprising area allocation means for allocating the physical address area. 4. The image processing apparatus according to claim 1, further comprising a table that stores the correspondence between the logical address and the physical address, which is referred to by the address converter. 5. The image processing apparatus according to claim 1, wherein the pixel calculation unit includes a pixel pipeline unit.