JP2003317403A - Data reproduction system and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reproduction system which decreases data errors and provides higher reliability by correcting the vertical asymmetry as the effect of a PRML (Partial Response Maximum Likelihood) is not obtainable if a vertically asymmetric reproduced signal is generated in the reproduced signals of an optical disk or the like. <P>SOLUTION: The system has an analog-to-digital converter for converting the analog signal reproduced from a recording medium to a digital signal, a filter for digitally filtering the converted digital signal, a decoder of subjecting the digitally filtered signal to maximum likelihood decoding, and a demodulator for demodulating the decoded signal, and corrects the 0/1 decision level of waveforms and the vertical asymmetry by controlling the analog-to-digital converter by using the digital signal. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing method, a data recording / reproducing method, a data reproducing system and a data recording / reproducing system, and in particular, it is possible to reduce the occurrence of errors when reproducing data recorded on a recording medium. Data reproducing method and data reproducing system.

[0002]

2. Description of the Related Art Conventionally, when reproducing a signal from an optical disk, a method of binarizing an analog signal read by an optical head from the optical disk by a reproduction clock has been adopted. It was difficult to sufficiently reduce the errors that occur.

On the other hand, in a magnetic disk, PRML (Partial Response Maximum Likelihood) has been conventionally used as a transmission system technology in order to improve data reliability.
Has been adopted. PRML is a system that uses interference generated between codes in a reproduced signal to reduce the occurrence of errors in the transmission system as compared with the conventional determination of slicing in bit units.

Recently, a method using this technique has been proposed for optical discs, and is described, for example, in "Data Compression and Digital Modulation, 1998 Edition, Digital Modulation" (p.201-p.215), published by Nikkei BP. The system like this is introduced.

By thus reproducing the data using PRML, the bit error rate can be improved and the system margin can be secured.

[0006]

However, in the case of an optical disc, when the power control during recording is not optimally performed, the upper and lower amplitudes of the reproduced signal are asymmetric with respect to the center of the waveform as shown in FIG. The following phenomenon may occur. FIG. 2 shows the waveforms when a signal of a single frequency is continuously reproduced, in which (1) shows an ideal reproduced waveform and (2) spreads 10% downward. 10%
The reproduced waveform in which vertical asymmetry occurs is shown. If the reproduced signal including such a phenomenon is directly processed using PRML, the balance between the upper and lower amplitude values is lost,
Correct reproduction processing may not be performed and incorrect data may be output. Therefore, in order to perform PRML, it is necessary to correct the vertical asymmetry correctly. This is because in the conventional method of binarizing and determining 0/1 at the timing of the reproduced clock, accurate 0/1 determination could be made if the slice level and the amplitude direction at the time of clock punching were correct, so correction is necessary. Did not occur.

The present invention has been made in view of the above points,
The purpose is to reduce erroneous reproduction signal processing and reduce the occurrence of data errors in an optical disc recording / reproducing apparatus.

[0008]

According to the present invention, in a data reproducing system for reading a signal recorded on a recording medium and performing a reproducing process, a clock generating circuit for generating a clock using the signal reproduced from the recording medium. An A / D converter for converting an analog signal reproduced from the recording medium into a digital signal; a filter for digitally filtering the digital signal converted by the A / D converter; and a digital filter for the filter. A decoder for performing maximum likelihood decoding on the multiplied signal and a demodulator for demodulating the signal decoded by the decoder, and controlling the A / D converter using the digital signal It is to solve the above-mentioned object.

Further, according to the present invention, in a data reproducing system for reading a signal recorded on a recording medium and performing a reproducing process, a clock generating circuit for generating a clock using the signal reproduced from the recording medium, and the recording device. A / which converts an analog signal reproduced from a medium into a digital signal
D converter, filter for applying digital filter to the digital signal converted by the A / D converter, decoder for performing maximum likelihood decoding on the signal digitally filtered by the filter, and the decoder A demodulator that demodulates the signal decoded by, and controlling the A / D converter using the analog signal,
This is to solve the above object.

Further, according to the present invention, in a data reproducing system for reading a signal recorded on a recording medium and reproducing the signal, a clock generating circuit for generating a clock using the signal reproduced from the recording medium, and the recording device. A / which converts an analog signal reproduced from a medium into a digital signal
D converter, filter for applying digital filter to the digital signal converted by the A / D converter, decoder for performing maximum likelihood decoding on the signal digitally filtered by the filter, and the decoder And a demodulator that demodulates the signal decoded by, wherein the filter is a filter in which the characteristics of the filter change in accordance with the change of the signal reproduced from the recording medium, and the decoder is one of the characteristics of the filter. The above object is achieved by switching the determination for decoding according to the change.

Further, according to the present invention, in a data reproducing system for reading a signal recorded on a recording medium and reproducing the signal, a clock generating circuit for generating a clock using the signal reproduced from the recording medium, and the recording device. A / which converts an analog signal reproduced from a medium into a digital signal
D converter, filter for applying digital filter to the digital signal converted by the A / D converter, decoder for performing maximum likelihood decoding on the signal digitally filtered by the filter, and the decoder A demodulator that demodulates the signal decoded by, the filter switches the characteristics according to a plurality of recording methods, the decoder, by switching the decoding process according to the switching of the characteristics of the filter, The above object is achieved.

According to the present invention, in a data reproducing apparatus for reading a signal recorded on a recording medium and performing a reproducing process, a clock generating circuit for generating a clock using the signal reproduced from the recording medium, and the recording apparatus. A / D for converting analog signal reproduced from medium to digital signal
A converter, a filter for digitally filtering the digital signal converted by the A / D converter, a decoder for performing maximum likelihood decoding on the signal digitally filtered by the filter, and the decoder A demodulator for demodulating a decoded signal is provided, and the above object is achieved by controlling the identification value of the decoder according to the value of the digital signal.

Further, according to the present invention, in a data reproducing method of reading a signal recorded on a recording medium and reproducing the signal, a clock is generated using the signal reproduced from the recording medium and reproduced from the recording medium. The analog signal to a digital signal, the digital signal is subjected to a digital filter, the digital filtered signal is subjected to maximum likelihood decoding, and the maximum likelihood decoded signal is demodulated to obtain the digital signal. The above object is achieved by controlling the conversion by using.

Further, according to the present invention, in a data reproducing method for reading a signal recorded on a recording medium and reproducing the signal, a clock is generated using the signal reproduced from the recording medium and reproduced from the recording medium. A converted analog signal to a digital signal, a digital filter is applied to the digital signal, maximum likelihood decoding is performed on the digital filtered signal, the signal after maximum likelihood decoding is demodulated, and the analog signal The above object is achieved by controlling the conversion by using.

Further, according to the present invention, in a data reproducing method for reading a signal recorded on a recording medium and reproducing the signal, a clock is generated using the signal reproduced from the recording medium and reproduced from the recording medium. Converted analog signal into a digital signal, the digital signal,
A digital filter whose characteristics change in response to a change in a signal reproduced from a recording medium is applied, and a decision for decoding is switched for the signal subjected to the digital filter in accordance with a change in the characteristics of the digital filter. The above-mentioned object is achieved by performing maximum likelihood decoding according to the above.

Further, according to the present invention, in a data reproducing method for reading a signal recorded on a recording medium and reproducing the signal, a clock is generated using the signal reproduced from the recording medium and reproduced from the recording medium. Converted analog signal into a digital signal, the digital signal,
By switching characteristics according to a plurality of recording methods and applying a digital filter, the signal subjected to the digital filter is switched in decoding processing in accordance with switching of the digital filter to perform maximum likelihood decoding,
The above object is achieved.

Further, according to the present invention, in a data reproducing method for reading a signal recorded on a recording medium and reproducing the signal, a clock is generated using the signal reproduced from the recording medium and reproduced from the recording medium. The analog signal to a digital signal, the digital signal is subjected to a digital filter, the digital filtered signal is subjected to maximum likelihood decoding, and the maximum likelihood decoded signal is demodulated to obtain the digital signal. In accordance with the above, by controlling the identification value of the maximum likelihood decoding, the above object is achieved.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A conventional general optical disk reproducing system will be described below, and then an embodiment of the present invention will be described.

First, a conventional general optical disk reproducing system will be described with reference to FIG.

As the operation on the recording side, in order to record the data on the optical disk 11, the recording data generating circuit 12 adds an ID indicating the address of the data and adds a parity for error correction to perform recording. Generate data. In order to record this record data on the disc, the modulator 13 performs predetermined modulation, and the optical head 14 is used to record on the optical disc. As a modulation method, a method of controlling so that the number of 0/1 in the recording data is the same,
It is selected according to the signal to be transmitted, such as a method of controlling the ratio of 0/1 to be a constant value.

As an operation on the reproducing side, an analog signal (reproduced signal) read from the optical disk 11 through the optical head 14 passes through a low pass filter 15 for removing noise other than the signal band and is binarized. It is input to the circuit 36. Here, the reproduced signal is judged to be 0/1,
As shown above, there are cases where it is asymmetrical, so 0
/ 1 Judgment is performed while adjusting the judgment level. For example, as shown in FIG. 4, when a reproduction signal waveform that is vertically asymmetrical to the ideal reproduction waveform is obtained, the slice adjustment is turned off, that is, the signal level is corrected without correcting the 0/1 determination level. If the judgment is made based on the center of amplitude, it should be 11T /
The data of 11T may be judged as 12T / 10T. However, if the slice adjustment is turned on, that is, the determination level of 0/1 determination is corrected and determination is performed at the optimum point, a correct signal of 11T / 11T is obtained, which is as expected. Here, in the adjustment of the determination level, when the modulation method is such that the occurrence probability of 0 and 1 is always the same, the occurrence statuses of 0 and 1 are held and the occurrence times are the same or different. The adjustment can be performed by moving the determination level position so that the value becomes 0. After the binarization is performed in this way, the PLL 37 of FIG. 3 generates a clock synchronized with the reproduction signal, punches the reproduction signal by the generated clock to make 0/1 determination, and the demodulator 38 outputs the data. Demodulate. Since the decoding process after the demodulation is the decoding process matched with the data generation process at the time of recording, it is omitted here. As described above, in the conventional method, binarization adjustment is performed by using the reproduced signal as an analog signal.

Next, a first embodiment of the present invention will be described. FIG. 1 is a diagram showing a main part relating to the present invention in a block diagram of a data recording / reproducing system for an optical disc.

As the operation on the recording side, in order to record the data on the optical disk 11, in the recording data generation 12, the ID indicating the address of the data is added, the parity for error correction is added, and the like. To generate. In order to record this record data on the disc, the modulator 13 performs a predetermined modulation, and the optical head 14 records it on the disc.

As an operation on the reproducing side, an analog signal (reproduced signal) read from the optical disk 11 via the optical head 14 passes through a low-pass filter 15 for removing noise other than the signal band, and is A / D. It is input to the converter 16. Here, the analog signal is represented by the A / D converter 16 as a digital signal having a predetermined bit width. P
The LL 17 is a clock generation circuit that generates a clock synchronized with the reproduction signal from the reproduction signal, and includes an A / D converter 16
And the clock is distributed to the processing blocks thereafter. The adaptive equalization circuit 19 performs PR equalization by an equalization method corresponding to the modulation method, and the corresponding Viterbi decoder 2
Processing is performed by combining 0s. That is, the adaptive equalization circuit 1
Reference numeral 9 has a role as a filter for applying a digital filter to the digital signal, and the Viterbi decoder 20 has a role as a decoder for performing a maximum likelihood decoding on the digitally filtered signal and making a 0/1 decision. Have
Then, the signal subjected to such processing is demodulated by the demodulator 21, and thereafter, the decoding processing is performed according to the data processing performed at the time of recording.

Here, from the output of the Viterbi decoder 20,
Since the determined 0/1 signal is output, it is used to correct the determination level of the vertically asymmetric reproduction signal. However, since the analog judgment level correction shown in FIG. 3 is not performed here, for example, by controlling the A / D converter 16 as shown in FIG. 1, the reproduction signal judgment level correction is performed. Will be done.

Here, an example of a specific A / D correction of the present invention will be described. Here, (1) correction of the judgment level of 0/1 judgment (correction by the judgment level correction circuit 22 of FIG. 1), (2) correction of vertical asymmetry of reproduced waveform (A / of FIG. 1)
Two corrections (correction by the D correction circuit 18) will be considered.

First, the correction of the judgment level (1) will be described with reference to FIG. The analog signal reproduced from the disc is amplified and passed through the filter to be input to the differential input A / D converter 52 as the A / D input 51, and the differential input A
The / D converter 52 outputs the difference between the input level and the center level as a positive / negative digital signal. However, when a discrepancy occurs in the determination level, it is necessary to correct it, and in particular, it is necessary to appropriately correct it according to the modulation system of the signal recorded on the disc. The determination level correction circuit 22 performs such correction. Here, the A / D is not limited to the A / D that outputs the difference between the input level with respect to the center level as a positive / negative digital signal, but is generally used such as the A / D that digitizes the difference between two input signals. If it is a thing, it is the same.

The decision level correction circuit 22 is controlled and modulated so that the number of appearances of 0 and 1 of the signal recorded on the disk becomes the same number (symmetrical code system), that is, the DC component is not included. When it is controlled and modulated as described above, the number of appearances of 0 and 1 of the signal output from the Viterbi decoder 20 (not shown) is controlled to be equal. Therefore, an A / D determination level correction value is obtained, and correction is performed so as to adjust the level that is the center of determination.

On the other hand, 0 and 1 of signals recorded on the disc
Asymmetry is not the same (asymmetric coding method) and is controlled and modulated at a constant rate, that is, when the DC component is controlled and modulated so as to have a constant rate, the asymmetry The A / D determination level correction value is calculated in accordance with the variation of the determination level caused by. The detection cycle of the correction value of the determination level at this time may be the same as or longer than the control cycle of the number of appearances of 0 and 1 of the signal recorded on the optical disc. By performing such control, whether the signal recorded on the disc is recorded by a symmetric code or asymmetric code modulation method, the judgment level is appropriately corrected and the center of A / D conversion is correctly controlled. Is possible. Controlling the number of appearances of 0 and 1 is equivalent to controlling the DC component contained in the modulated signal.

Next, the correction of the vertical asymmetry of the reproduced waveform of (2) will be described. This correction is performed by the output value correction multiplier 54 of the A / D correction circuit 18 and the vertical asymmetry detector 55. That is, the output value correction multiplier 54 receives the detection result of the vertical asymmetry detector 55, calculates and corrects according to the value, and outputs the A / D output 56. More specifically, the up-down asymmetry detection circuit 55 compares the maximum value of the positive signal amplitude with the maximum value of the negative signal amplitude, obtains the ratio, and corrects the output value correction multiplier 54. If the synchronization signal is a modulation method capable of outputting the maximum amplitude, the maximum amplitudes of the upper and lower signals are detected according to the cycle of the synchronization signal.

Assuming that the positive signal amplitude is less than the negative signal amplitude
If 0.9 times, the A / D output correction multiplier 54
/ D output is multiplied by 1.11 which is the reciprocal of 0.9 to output. By performing such processing, it is possible to correct the positive signal amplitude and the negative signal amplitude so that they have substantially the same value, and it is possible to correctly perform A / D conversion even on vertically asymmetric signals. .

However, in such a case, there is a possibility that the expected number of bits may be exceeded by performing the correction process. Therefore, it is necessary to secure a sufficient number of bits. On the contrary, if the one with the larger amplitude is matched with the one with the smaller amplitude, the resolution deteriorates. Therefore, in order to perform the correction processing more accurately, when the upper side is shifted by 10% as shown in FIG. 2, the upper side amplitude is set to 50 / (50-10) and the lower side amplitude is set to 50 / (50-10). By correcting as (50 + 10), it is possible to correct asymmetrical signals at the top and bottom. Of course, the signals do not appear at the same time in the vertical direction, and only one of the signals always comes out. Therefore, the arithmetic circuit for the correction processing may be mounted for one series and processed in time series.

When asymmetry occurs, the strain may exceed 20% at a large number. Therefore, A / D
It is difficult for the correction circuit 13 to make the corrected amplitudes completely equal. Also, the resolution and accuracy of A / D, A / D
The accuracy of correction differs depending on the accuracy of the arithmetic unit included in the D correction circuit 13. Therefore, as the target value to be corrected, the detection error can be reduced by setting the size of the error to be equal to or less than half of the narrowest boundary of the Viterbi decoding identification value.

As for the correction of these asymmetries, there is also a method of performing fine correction while constantly changing the correction value, but the asymmetric state of the reproduced signal is roughly classified into several and the correction values are It is stored in advance and the correction value is switched when the change exceeds the threshold of the classification. The correction control can be simplified by such a method.

FIG. 6 shows the flow of the A / D correction method shown in FIG. It is detected from the signal output from the Viterbi output that the deviation of the judgment level is included (ST
61) Then, the judgment level shift is Yes, and the judgment level is corrected (ST62) to control the judgment level to an appropriate value. As described above, the determination level shift may be based on the number of times 0 and 1 are generated, or may be detected whether the DC component is different from the control value. On the other hand, when the discrepancy in the judgment level is not detected, the case level discrepancy is No, and the process proceeds to ST63 without correcting the judgment level. Here, an example in which the deviation of the determination level is detected by using the Viterbi output in order to improve the reliability has been described, but it may be detected from the signal immediately after the A / D output, or the analog signal of the analog signal may be detected. It is also possible to detect in stages.

When the reproduction waveform has vertical asymmetry, that is, when it is detected that the upper and lower amplitude values are different from the determination level (ST63), the amplitude difference is Yes, and the amplitude value is corrected (ST64). ). Regarding the difference between the upper and lower amplitudes, the maximum value of the amplitude is held for each of the upper side and the lower side, and the maximum value within a predetermined period is detected. At this time, erroneous detection can be reduced by setting the detection period within a range in which the maximum amplitude always occurs a plurality of times.

Here, two corrections, that is, the correction of the determination level and the correction of the vertical asymmetry of the reproduced waveform are performed in order, but they may be performed independently. Also,
The detection may be always performed, or may be performed when the number of errors in the reproduced signal increases. Detection of an abnormal state of the reproduced signal, that is, error detection can be performed by the amplitude of the reproduced signal or the tracking error signal. Also, check the width of the playback signal envelope, and if it is decreasing or if the data is unreliable such as a scratch detection signal, gate it so that it will not be included in the detection process. Is desirable.

FIG. 7 shows a configuration example of the adaptive equalization circuit 19. The equalization circuit uses a normally used n-tap transversal filter, delays the signal of the A / D correction output 71 by the n-stage delay element 72, and multiplies each delayed value by a multiplier. A predetermined tap coefficient is multiplied by 73, and the result is added by the adder 74. The equalized output 75 outputs a waveform-equalized signal. The latch 76 temporarily stores the equivalent output, inputs the A / D correction output 71, and delays the processing time by the tap coefficient control 77.
At, the deviation of the tap coefficient from the target value is detected, and the multiplier 7
Control is performed so that the tap coefficient of 3 is changed. The transversal filter described here has been shown to be calculated using the values of all delay elements, but the shape of the filter is not limited, such as one using only every other stage value.

FIG. 8 shows an example of the configuration of the Viterbi decoding 20. Input to Viterbi decoding from equalized output 8
1 is added to the branch metric 82 that calculates the square of the Euclidean distance for all branches according to the trellis, the calculation results of the branch metric 82 are added, and the comparison result is selected and output (ACS (add comparesele)
ct) is a path metric 83, and a path memory 84 is a delay for making a maximum likelihood judgment according to the state of each metric. With this configuration, Viterbi decoding is realized.

FIG. 9 shows another embodiment for performing the A / D determination level correction shown in FIG. As the detection signal for performing the decision level correction, in FIG. 1, the decision level correction value is obtained from the positive / negative ratio of the output signal after Viterbi decoding,
An example in which correction is performed so as to adjust the level that is the center of determination has been described. However, in Viterbi decoding, path memories 91
Since the maximum likelihood decoding is performed by using 93 (here, used as a delay memory), the time required for the calculation and the delay corresponding to the path memory occur before the output. Therefore, A / D
Even if the judgment level shift occurs, the response will be delayed. Therefore, in order to reduce the delay, the determination level deviation detection signal 94 is output from the output of the path memory 91, for example, in the middle of the path memory. Further, according to the control loop of the judgment level deviation, the judgment level deviation detection signal 9
Switch the output point of the path memory that outputs 4,
Make sure you get the right properties. With such a configuration, it is possible to follow the determination level deviation in a short time.

FIG. 10 shows the A / D determination level deviation detection
The detection is performed by using the binarized signal without using the output of Viterbi decoding. Positive of signal after binarization /
Each negative time is measured, and if there is a time difference, control is performed so as to adjust the determination level. Further, this output is not the output after binarization, but the same effect can be obtained by punching out the reproduced signal with the clock generated by the PLL and comparing the number of 0/1.

FIG. 11 shows the configuration of an adaptive equalization circuit compatible with a plurality of partial response systems.
A system equipped with different adaptive equalization circuits may be considered depending on the band of the signal to be transmitted and the modulation method, but here, an example is shown in which it is configured by one adaptive equalization circuit. The characteristics of the filter are changed by switching the number of stages of the transversal filter and the tap coefficient of each delay element according to the identification signal 111 for identifying the difference in the method. Regarding the number of stages of the delay elements, the output of the unused delay elements is cut by the switch 112 to match the number of stages. Also,
As the tap coefficient, an initial value is stored in advance according to the method, and the value is input. With such a configuration, it is possible to realize an adaptive equalization circuit corresponding to a plurality of systems.

FIG. 12 shows how the ideal reproduced waveform values after equalization output are distributed in the case (1) when the phenomenon in which the reproduced signal is vertically asymmetrical as shown in FIG. 2 occurs. And (2) shows how the values after equalization output of the vertically asymmetrical reproduction waveform spread downward are distributed. The shape with the mountain on the right side is a graph showing how many times a certain value was output, that is, a graph showing the distribution of output values after equalization, and ideal reproduction as in (1). In the case of a waveform, the values after equalization are (j) (k) (l) (m) (n)
Then, they are distributed with a Gaussian distribution centered on them. At this time, in Viterbi decoding, the Euclidean distance is obtained by setting the identification values to (a), (b), (c), and (d). In the case of a vertically asymmetric reproduction waveform as shown in (2), the equalized values are (j ') (k') (l ').
If it becomes (m ') (n'), they are similarly distributed with these as the centers. At this time, the upper side has a small interval because the amplitude is small, and the lower side has a wide interval because the amplitude is large. In this case, the identification value in Viterbi decoding is controlled so that the reproduced waveform is different from the ideal case (1),
Euclidean distances are obtained by changing (a ′), (b ′), (c ′), and (d ′). By using such a method, it is possible to perform appropriate Viterbi decoding by changing the identification point of Viterbi decoding without performing correction after A / D output, even for a signal having vertically asymmetrical amplitude. It is possible to reduce the occurrence of errors.

In this system, the adaptive equalizer circuit as shown in FIG. 11 is used, and when the center value and the discriminant value of the output values after equalization change, the Viterbi decoding is performed accordingly. Control the discriminant point to allow proper decoding.

The control for changing the discrimination point is shown in FIG.
By measuring the output value after equalization as in 2, the distribution corresponding to the central value (j ') (k') (l ') (m') (n ') is detected, and the ideal Center value (j) for a typical waveform
Compared with (k) (l) (m) (n), the values of (a) (b) (c) (d) are changed to (a ′) (b ′) according to the change.
Change it to (c ') (d'). If the adaptive equalization circuit operates with a combination of several types of coefficients, the identification value corresponding to the combination is stored in advance, and the stored value is called according to the change of the adaptive equalization circuit. May be.
With such a method, it is possible to control the change point of the identification point of Viterbi decoding, perform appropriate Viterbi decoding, and reduce the occurrence of errors.

FIG. 13 shows the reproduced analog signal as A /
It is the figure which showed how it was distributed when D-converting and converting into a digital value. Here, at the rising edge of the PLL that matches the captured clock with the reproduced data, A
A digital value is acquired by performing D / D conversion. Depending on the recording power at the time of recording, the size of the mark recorded on the disk is deformed from an appropriate shape and reproduced as a vertically asymmetrical waveform at the time of reproduction. Thus, the distribution of digital values after A / D conversion Will also be biased. For example, the ideal reproduced waveforms (a), (b), and (c) will be distributed with deviated values such as (a '), (b'), and (c ') when vertical asymmetry occurs. Therefore, by detecting this distribution, it is possible to know the magnitude of the deviation of the vertically asymmetrical waveform. Therefore, the output value of the adaptive equalization circuit in the subsequent stage is corrected according to this shifted distribution, and the Euclidean distance is calculated based on the corrected value to perform Viterbi decoding, thereby performing proper binarization. It will be possible.

FIG. 14 shows an example of a method for adapting the Viterbi algorithm according to the change of the distribution when the digital value after A / D conversion has a biased distribution as shown in FIG. Is. Reference numeral 141 is a distribution detection circuit, and 142 is a target value correction circuit for correcting the target value. Distribution detection circuit
At 141, the frequency of occurrence of the digital value after A / D conversion is obtained, the state of the distribution is detected, and what level and how the deviation from the ideal distribution is detected. The target value correction circuit 142 changes the Viterbi algorithm using the detection result of the distribution detection circuit 141 and the equalization characteristic of the adaptive equalization circuit 19. Particularly, in the branch metric 82 for calculating the square of the Euclidean distance shown in FIG. 8, the target value is changed according to the distribution and the equalization characteristic, and the Euclidean distance is calculated using the target value. Further, similarly to the example of FIG. 1, the A / D determination level correction value may be used. By using such a method, it is possible to perform appropriate Viterbi decoding according to the fluctuation of the reproduced waveform, and it is possible to suppress the occurrence of error. Further, by detecting the change in the reproduced waveform based on the amplitude value, since the subsequent processing is the amplitude value, the adjustment can be performed with good matching.

FIG. 15 shows an example of the configuration of the distribution detection circuit 141. Reference numeral 151 is a digital value fetching circuit, 152 is a register for holding how many times each digital value has occurred, 153 is a register for reading the number of occurrences from the held register according to the generated digital value, and adding 1 time An adder 154 for returning is a detection circuit for detecting the distribution state of the occurrence frequency of each digital value, and 155 is a detection circuit for detecting how the distribution state differs from the ideal state. With this configuration, the distribution of the occurrence frequency can be detected, and the magnitude of the deviation from the target value at each level can be detected. Register 152 is A /
It is desirable to have only the types that can be obtained from the digital bit width of the D converter, but even if the number of registers is grouped according to the accuracy of target value adjustment to the extent that the amount of deviation from the target value at each level can be detected I do not care. Also, although this configuration is described assuming a circuit, the processing may be performed by software processing by a system control microcomputer or the like.

FIG. 18 shows an example of the distribution detecting method by software. Here, the start is to take in the digital signal which is A / D converted from the reproduced signal. Reference numeral 1801 denotes a digital value fetching process, which fetches the digital value after A / D conversion,
In 02, with respect to the digital value of the amplitude, two types of occurrence counts are counted with a coarse threshold value and a fine and fine threshold value, and the number of occurrences of each is measured. For example, when a digital value of 0.15 is output after A / D conversion, the coarse threshold value is 0.5 units, and when it has a range of 0 to 0.5, the output of that range is counted as once.
Further, the dense threshold value is 0.1 unit, and when it has a range of 0.1 to 0.2, the output in that range is counted as once. Next, in 1803 peak distribution detection, 180
The number of peak positions and the distribution tendency of the deviation are detected from the number of occurrences of the rough count obtained in 2. Further, from this distribution tendency, a value with a high occurrence frequency and a value with a low occurrence frequency are roughly detected. 1
A peak position detection 804 detects a digital value having a large number of occurrences and a digital value having a small number of occurrences from the number of occurrences counted in a detailed range in 1802. Here, there are variations in the number of occurrences, and a large number of occurrences is not always the center of the coarse distribution. Therefore, 1
In the 805 distribution bias detection, the bias of the distribution is detected from the 1803 peak distribution detection result and the 1804 peak position detection result. For example, when the 1803 peak distribution detection detects that the distribution is biased, the number of convexes and concaves and the positional deviation thereof are detected. Next, by detecting the 1804 peak position,
The peak position in the range of one convex sandwiched between concaves or the position where the number of occurrences is small is detected, the distribution of the occurrence frequency is detected, and the magnitude of the deviation from the case where it becomes a reference that is known in advance To detect Of course, both 1803 peak distribution detection and 1804 peak position detection are not necessarily required, and the deviation of the distribution may be detected from either one of the detection results.

Further, the processing shown in FIG. 18 may not be all performed by software, but the same processing may be performed by hardware, or, for example, the number of occurrences may be counted by hardware and the distribution The bias detection process may be performed by software.

FIG. 19 shows an example of a hardware configuration for realizing the flow of processing shown in FIG.
1901 is an input that takes in a digital value after A / D conversion, 1902 is a coarse threshold value for the number of occurrences, an occurrence number counter (coarse) for measuring how many times it has occurred, 1903 is a fine threshold value for the number of occurrences. Occurrence counter (dense) for measuring whether or not occurrence has occurred, 1904 is peak distribution detection, 190
Reference numeral 5 is a peak position detection, 1906 is a detection signal for passing the peak distribution detection result to the peak position detection, 1907 is a distribution bias detection, and 1908 is a signal output for bias detection.

FIG. 20 is a diagram showing the output states of the occurrence count counter (coarse) 1902 and the occurrence count counter (fine) 1903 shown in FIG. (A) shows the state of the occurrence counter (coarse), (B) shows the occurrence counter (fine)
It shows the state of. The dotted line graph in the graph of (A) is obtained by connecting the centers of the bar graphs, and thus the unevenness can be detected. In the example of this graph, it can be regarded as four convexes divided into three concaves. These four convexes are referred to as convex (1), convex (2), convex (3), and convex (4). Here, the case where four protrusions are generated is shown, but this is not particularly limited because it depends on the characteristics of the reproduction signal. The threshold value Δv (Δ represents delta) for the graph coarse detection in (A) is the step if the one having the same function as the target value correction circuit 142 shown in FIG. You may match the width of. By thus using the coarse threshold value counter and the fine threshold value counter together, it is possible to easily and accurately detect the bias of the distribution.

FIG. 21 shows another embodiment of the configuration shown in FIG. The same numbers as those in FIG. 19 indicate the same functions. 2101 is a period average detection circuit,
When there are n convexes, which convex is included is determined, and the average value of the samples included therein is obtained. Due to this change in the average value, it is possible to detect the deviation of the distribution as in the peak position detection.

FIG. 22 shows an embodiment of the period average detection circuit 2101 shown in FIG. 2201 is a signal input which takes in the digital value after A / D conversion, 2202 is a detection signal 1906 which passes the result of peak distribution detection to a period average detection circuit, and switches the value of each convex association to input the digital value. A convex (n) discriminating circuit 220 which discriminates which convex is included in the signal and switches to a predetermined SW.
Reference numerals 3 to 2206 are convex (n) average detection circuits for obtaining an average value of data included in the n-th convexities 1 to 4, for example. 2207 is a FIFO that stores the determined data and outputs the oldest data in the order of input, 2208 is a subtractor, and 2209 is a register that stores the oldest sample output from the FIFO. 2210 is an adder, 2211 is a register for storing the total of the added sample values, and outputs the average value from the output signal 2212. For example, in the case where an average is always obtained from 32 new samples and the bias of the distribution is corrected, the difference between the newest sample and the oldest sample 2209 is obtained by the subtractor 2210, and only the difference is added up to the total 2211. The sum of the latest 32 samples can always be obtained by adding to. Also, dividing the total sample value 2211 by 32 is equivalent to shifting by 5 bits, so the lower 5
The bits can be truncated and the average value can be output at output 2212. If the number of added samples is a power of 2, division processing for averaging becomes simple.

FIG. 17 shows another embodiment of the present invention and shows another method of the correction means when the vertical amplitude deviation of the reproduced waveform occurs. 171 is a decision level correction circuit, 1
Reference numeral 72 is a center shift detection circuit. Judgment level correction circuit 1
At 71, the digitized signal is received, and the center shift detection circuit 172 detects the center level. As a detection method at this time, the decision level correction circuit 171 corrects the digital value to equalize by detecting which one of the positive and negative occurrence frequencies of the digital signal is biased and correcting the deviation. Hand it over to the circuit. As a result, it is possible to correct only the output signal without correcting the A / D conversion circuit.

Further, in order to confirm whether the reproduced waveform has vertical asymmetry, a specific pattern is recorded on the recording medium, and it is confirmed whether the vertical asymmetry occurs by using the reproduced signal of the specific portion. Good. At this time, a distribution can be obtained from the distribution of values after A / D conversion and the value after equalization. FIG. 16 shows the recording signal format of the recording field and the header field of the DVD-RAM. The signal of the DVD-RAM includes the specific pattern VFO for pulling in the data as described above, and this portion may be used for detection or VF.
Even in a portion other than O, the amplitude distortion can be detected by comparing the reproduction waveform of the signal known in advance with the expected value of the waveform.

Up to this point, the present invention has been shown as an example in which the present invention is applied to a recording / reproducing system for an optical disc, but the present invention is not limited to this, and of course it can be applied to a reproducing system for a magnetic disc or a magneto-optical disc. Instead, it can be used for general systems including reproduction processing of transmission signals. For example, from broadcast waves and mobile phone radio waves,
The present invention can be applied to a wireless system for reproducing a signal and a signal transmission system using a cable or the like.

The present invention is not limited to the recording / reproducing system, but can be applied to a reproduction-only system.

[0059]

As described above, according to the present invention, the characteristics of the reproduced analog signal or the converted digital signal are used to control the A / D conversion reference value and the amplitude. Proper PR by performing such control
It is possible to perform the ML operation, reduce data errors, and realize a more reliable reproducing system.

[Brief description of drawings]

FIG. 1 is a block diagram of a reproducing system using an optical disc according to an embodiment of the present invention, and is a diagram showing a main part relating to the present invention.

FIG. 2 is a diagram showing a waveform of a vertically asymmetric reproduction signal.

FIG. 3 is a diagram showing a block configuration example of a conventional optical disc reproducing system.

FIG. 4 is a diagram showing a case where a judgment level shift of a reproduction signal occurs.

FIG. 5 is a diagram showing a main part relating to A / D correction of the present invention according to an embodiment of the present invention.

FIG. 6 is a diagram showing a processing flow of a main part relating to A / D correction of the present invention according to an embodiment of the present invention.

FIG. 7 is a diagram showing an example of the configuration of an adaptive equalization circuit of the present invention according to an embodiment of the present invention.

FIG. 8 is a diagram showing an example of a configuration of a Viterbi decoding circuit of the present invention according to an embodiment of the present invention.

FIG. 9 is a diagram showing another example of the configuration of the Viterbi decoding circuit of the present invention according to the embodiment of the present invention.

FIG. 10 is a block diagram of a reproducing system using the optical disc of the present invention, and is a diagram showing a main part relating to the present invention.

FIG. 11 is a diagram showing another example of the configuration of the adaptive equalization circuit of the present invention.

FIG. 12 is a diagram showing a waveform of a vertically asymmetric reproduction signal and a distribution of equalized output values.

FIG. 13 is a diagram showing a distribution state when a reproduced analog signal is converted into a digital value.

FIG. 14 is a diagram showing an example of a method of adapting the Viterbi algorithm according to the change of distribution of the present invention.

FIG. 15 is a diagram showing an example of a configuration of a distribution detection circuit of the present invention.

FIG. 16 is a diagram showing a recording signal format of a recording field and a header field of a DVD-RAM.

FIG. 17 is a diagram showing an example of a method of adjusting center levels according to the present invention.

FIG. 18 is a diagram showing an example of a bias detection process of the present invention.

FIG. 19 is a diagram showing an example of a circuit configuration for performing the bias detection processing of the present invention.

FIG. 20 is a diagram showing another example of the circuit configuration for performing the bias detection processing of the present invention.

FIG. 21 is a diagram showing an example of an output state by two kinds of occurrence count processing of the present invention.

FIG. 22 is a diagram showing an example of a circuit configuration for obtaining the latest sample average of the present invention.

[Explanation of symbols]

11 optical disc 12 Recording data generation circuit 13 modulator 14 Optical head 15 LPF (low pass filter) 16 A / D converter 17 PLL 18 Adaptive equalization circuit 19 Viterbi Decoder 20 demodulator

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5D044 BC02 CC04 DE33 EF01 FG06                       GL02 GL32                 5J022 AA01 BA01 CA07 CD02 CD03                       CE03                 5J065 AA01 AB01 AC03 AE08 AF02                       AG05 AH05 AH17 AH23

Claims (38)

[Claims] 1. A data reproducing system for reading a signal recorded on a recording medium and reproducing the signal, and a clock generating circuit for generating a clock using the signal reproduced from the recording medium; A / D converter for converting the analog signal into a digital signal, a filter for digitally filtering the digital signal converted by the A / D converter, and a filter for digitally filtering the digital signal by the filter. A data reproducing system comprising a decoder for performing likelihood decoding and a demodulator for demodulating a signal decoded by the decoder, and controlling the A / D converter using the digital signal. 2. A data reproducing system for reading a signal recorded on a recording medium and performing a reproducing process, and a clock generating circuit for generating a clock using the signal reproduced from the recording medium, and reproducing from the recording medium. A / D converter for converting the analog signal into a digital signal, a filter for digitally filtering the digital signal converted by the A / D converter, and a filter for digitally filtering the digital signal by the filter. A data reproduction system comprising a decoder for performing likelihood decoding and a demodulator for demodulating a signal decoded by the decoder, and controlling the A / D converter using the analog signal. 3. The data reproducing system according to claim 1, wherein when the signal recorded on the recording medium is modulated by controlling a DC component and recorded, the converted signal is converted into a DC signal. A data reproducing system, wherein the A / D converter is controlled so that the DC component has a predetermined value when the component is different from the controlled value. 4. The data reproducing system according to claim 3, wherein when the signal recorded on the recording medium is controlled so as not to contain a direct current component and is modulated and recorded, the converted signal is converted into the converted signal. A data reproducing system characterized by controlling the A / D converter so as to reduce the DC component when the DC component is contained. 5. The data reproducing system according to claim 4, wherein, when the conversion is judged as a positive or negative signal with the judgment level as a center, there is a time difference between the times when the positive and negative signals are generated. A data reproducing system characterized by controlling the judgment level of the A / D converter so as to reduce the time difference when it occurs. 6. The data reproducing system according to claim 1, wherein, when the analog signal is judged as a positive or negative signal centering on a judgment level, the amplitude of the digital signal is different between the positive side and the negative side. In order to make the amplitude of the converted signal almost the same on the positive side and the negative side,
A data reproducing system characterized by controlling a D converter. 7. The data reproducing system according to claim 2, wherein, when the analog signal is judged to be a positive or negative signal centering on a judgment level, the amplitude of the analog signal is different between the positive side and the negative side. In order to make the amplitude of the converted signal almost the same on the positive side and the negative side,
A data reproducing system characterized by controlling a D converter. 8. The data reproducing system according to claim 6, wherein the control of the A / D converter is performed with respect to the converted signal.
A data reproducing system characterized by performing arithmetic processing according to the ratio of the maximum value on the positive side and the maximum value on the negative side. 9. The data reproducing system according to claim 6, wherein the output of the decoder is used to detect the determination level for determining the analog signal as a positive or negative signal. Playback system. 10. The data reproduction system according to claim 9, wherein, when the decoder uses a delay memory for the determination, the determination level uses an output in the middle of the delay memory. A data reproduction system characterized by. 11. The data reproducing system according to claim 1, wherein when the signal reproduced from the recording medium is not in a normal state, the signal is not used. . 12. The data reproducing system according to claim 11, wherein the abnormal state of the reproduced signal from the recording medium is detected by using the amplitude of the signal or a tracking error signal for the recording medium. A data reproduction system characterized in that 13. The data reproducing system according to claim 1, wherein when the error contained in the reproduced signal exceeds a predetermined value, conversion control of the A / D converter is performed. Characteristic data reproduction system. 14. The data reproducing system according to claim 1, wherein the clock generating circuit reproduces from the analog signal, a judging device that judges the analog signal as a positive or negative signal centering on a judgment level. And a reproduction clock generation circuit for generating a clock synchronized with the signal, and when the signal recorded on the recording medium is modulated by controlling the DC component and recorded, the DC component is controlled from the output of the judging device. The data reproducing system is characterized in that the A / D converter is controlled so that the DC component has a predetermined value when the calculated value is different from the specified value. 15. The data reproduction system according to claim 1, wherein the clock generation circuit reproduces from the analog signal, a judgment device that judges the analog signal as a positive or negative signal with a judgment level as a center. A reproduction clock generation circuit for generating a clock synchronized with the signal, and when the signal recorded on the recording medium is modulated and recorded by controlling the occurrence probability of 0 and 1, the reproduction clock generation circuit A data reproducing system, wherein the A / D converter is controlled so that the occurrence probabilities of 0 and 1 differ from a controlled value from the output so that the occurrence probabilities of 0 and 1 become a predetermined value. . 16. A signal recorded on a recording medium is read out,
In a data reproducing system that performs a reproducing process, a clock generating circuit that generates a clock using a signal reproduced from the recording medium, and an A / D converter that converts an analog signal reproduced from the recording medium into a digital signal. A filter for digitally filtering the digital signal converted by the A / D converter, a decoder for performing maximum likelihood decoding on the signal digitally filtered by the filter, and a decoder for decoding by the decoder. A demodulator for demodulating a signal, wherein the filter is a filter in which the characteristics of the filter change according to the change of the signal reproduced from the recording medium, and the decoder according to the change of the characteristics of the filter. A data reproducing system characterized by switching judgment for decoding. 17. A signal recorded on a recording medium is read out,
In a data reproducing system that performs a reproducing process, a clock generating circuit that generates a clock using a signal reproduced from the recording medium, and an A / D converter that converts an analog signal reproduced from the recording medium into a digital signal. A filter for digitally filtering the digital signal converted by the A / D converter, a decoder for performing maximum likelihood decoding on the signal digitally filtered by the filter, and a decoder for decoding by the decoder. And a demodulator for demodulating a signal, wherein the filter switches characteristics according to a plurality of recording methods, and the decoder switches decoding processing according to switching of characteristics of the filter. system. 18. A signal recorded on a recording medium is read out,
In a data reproducing device that performs a reproducing process, a clock generating circuit that generates a clock using a signal reproduced from the recording medium, and an A / D converter that converts an analog signal reproduced from the recording medium into a digital signal. A filter for digitally filtering the digital signal converted by the A / D converter, a decoder for performing maximum likelihood decoding on the signal digitally filtered by the filter, and a decoder for decoding by the decoder. And a demodulator that demodulates a signal, and controls the identification value of the decoder according to the value of the digital signal. 19. A signal recorded on a recording medium is read out,
In a data reproducing method for performing a reproducing process, a clock is generated using a signal reproduced from the recording medium, an analog signal reproduced from the recording medium is converted into a digital signal, and a digital filter is applied to the digital signal, A data reproducing method, wherein maximum likelihood decoding is performed on the signal subjected to the digital filter, the signal after the maximum likelihood decoding is demodulated, and the conversion is controlled using the digital signal. 20. A signal recorded on a recording medium is read out,
In a data reproducing method for performing a reproducing process, a clock is generated using a signal reproduced from the recording medium, an analog signal reproduced from the recording medium is converted into a digital signal, and a digital filter is applied to the digital signal, A data reproducing method, wherein maximum likelihood decoding is performed on the digitally filtered signal, the signal after the maximum likelihood decoding is demodulated, and the conversion is controlled using the analog signal. 21. The data reproducing method according to claim 19, wherein when the signal recorded on the recording medium is modulated by controlling a DC component and recorded, the converted signal is converted into a DC signal. When the component is different from the controlled value, the conversion is controlled so that the DC component has a predetermined value. 22. The data reproducing method according to claim 21, wherein when the signal recorded on said recording medium is controlled and modulated so as not to contain a direct current component and recorded, said signal converted by said conversion. When the DC component is included in the data recovery method, the conversion is controlled so that the DC component is reduced. 23. The data reproducing method according to claim 22, wherein in the conversion, when the analog signal is judged as a positive or negative signal with a judgment level as a center, there is a time difference between the times when the positive signal and the negative signal are generated. If so, the data reproduction method is characterized in that the determination level of the conversion is controlled so that the time difference is reduced. 24. The data reproducing method according to claim 19, wherein when the analog signal is judged to be a positive or negative signal centering on a judgment level, and the amplitude of the digital signal is different between the positive side and the negative side. The data reproducing method, wherein the conversion is controlled so that the converted signal becomes substantially the same on the positive side and the negative side. 25. The data reproducing method according to claim 20, wherein when the analog signal is judged to be a positive or negative signal centering on a judgment level, and the amplitude of the analog signal is different between the positive side and the negative side. The data reproducing method, wherein the conversion is controlled so that the converted signal becomes substantially the same on the positive side and the negative side. 26. The data reproducing method according to claim 24, wherein the conversion control is performed so that the converted signal is processed according to the ratio of the maximum value on the positive side to the maximum value on the negative side. A data reproducing method characterized by controlling conversion. 27. The data reproducing method according to claim 24, wherein the detection of the determination level for determining the analog signal as a positive or negative signal uses the output of the maximum likelihood decoding. Data playback method. 28. The data reproducing method according to claim 27, wherein when the output of the maximum likelihood decoding is delayed for the determination, the information for the determination level is not detected. A data reproducing method characterized by outputting with a small delay. 29. The data reproducing method according to claim 19 or 20, wherein when the signal reproduced from the recording medium is not in a normal state, the signal is not used. Data playback method. 30. The data reproducing method according to claim 29, wherein the abnormal state of the signal reproduced from the recording medium is detected by using the amplitude of the signal or a tracking error signal for the recording medium. A data reproducing method characterized by. 31. The data reproducing method according to claim 19 or 20, wherein the conversion is controlled when an error included in the reproduced signal exceeds a predetermined value. Method. 32. The data reproducing method according to claim 19 or 20, wherein in the generation of the clock, the analog signal is judged as a positive or negative signal centering on a judgment level, and the analog signal is synchronized with the reproduced signal. When the signal recorded on the recording medium is recorded by being modulated by controlling the DC component, when the DC component is different from the controlled value from the output of the judgment. Is a data reproducing method, wherein the conversion is controlled so that the DC component has a predetermined value. 33. The data reproducing method according to claim 19 or 20, wherein in the generation of the clock, the analog signal is judged as a positive or negative signal centered on a judgment level, and the analog signal is synchronized with the reproduced signal. When the signal recorded in the recording medium is modulated and recorded by controlling the occurrence probabilities of 0 and 1, the reproduced clock is generated from the output of the reproduced clock generation means. A data reproducing method, wherein the conversion is controlled so that the occurrence probabilities of 0 and 1 become a predetermined value when the occurrence probability is different from the controlled value. 34. A signal recorded on a recording medium is read out,
In a data reproducing method for performing a reproducing process, a clock is generated using a signal reproduced from the recording medium, an analog signal reproduced from the recording medium is converted into a digital signal, and the digital signal is recorded from the recording medium. A digital filter whose characteristics change according to the change of the reproduced signal is applied, and for the signal subjected to the digital filter, the determination for decoding is switched according to the change of the characteristics of the digital filter to change the maximum likelihood. A data reproducing method characterized by performing decoding. 35. A signal recorded on a recording medium is read out,
In a data reproducing method for performing a reproducing process, a clock is generated using a signal reproduced from the recording medium, an analog signal reproduced from the recording medium is converted into a digital signal, and a plurality of recordings are performed on the digital signal. Data reproduction characterized in that the characteristics are switched according to the system and a digital filter is applied, and the decoding processing is switched and maximum likelihood decoding is performed on the digitally filtered signal in accordance with the switching of the digital filter. Method. 36. A signal recorded on a recording medium is read out,
In a data reproducing method for performing a reproducing process, a clock is generated using a signal reproduced from the recording medium, an analog signal reproduced from the recording medium is converted into a digital signal, and a digital filter is applied to the digital signal, Maximum likelihood decoding is performed on the signal subjected to the digital filter, the signal after the maximum likelihood decoding is demodulated, and an identification value of the maximum likelihood decoding is controlled in accordance with the digital signal. Data playback method. 37. A data processing system for performing signal processing on a transmission signal, converting a transmitted analog signal into a digital signal, generating a clock using the transmitted signal, and applying a digital filter to the digital signal. And a demodulation circuit for performing maximum likelihood decoding on the signal subjected to the digital filter and demodulating the signal after the maximum likelihood decoding, and controlling the A / D converter using the digital signal. A data reproduction system characterized by. 38. A data processing method for performing signal processing on a transmission signal, including a conversion circuit for converting a transmitted analog signal into a digital signal, and a clock generation circuit for generating a clock using the transmitted signal. A digital filter is applied to the digital signal, a decoder for performing maximum likelihood decoding on the digital filtered signal, a demodulator for demodulating the signal after maximum likelihood decoding, and the digital signal are used. A data reproducing system comprising a control circuit for controlling the A / D converter.