JP2003303349A - Anti-aliasing drawing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently execute the anti-aliasing process in an anti-aliasing drawing device. <P>SOLUTION: The device comprises a plurality of drawing regions, a plurality of graphic drawing processors for drawing graphics by applying different offsets to the drawing regions for the same graphic, and a blending means for blending graphics drawn in the drawing regions. Accordingly, the loads on the drawing processors are equalized so that drawing can be efficiently achieved. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antialiasing drawing device, and more particularly to an antialiasing drawing device in a bitmap display system.

[0002]

2. Description of the Related Art In computer graphics,
A bit map display system is generally used to display figures and the like. In this system, a raster scan type CRT display and a display memory (frame buffer) for supplying bit pattern data corresponding to a display figure to the display are used. In such a system, if you draw diagonal lines or curves, jaggies will occur due to pixel display,
Aliasing appears. In order to eliminate such aliasing, it is known that the intervals between the display pixel grids may be narrowed.

[0003]

Although narrowing the spacing of the grid improves aliasing, it does require that the horizontal scanning frequency of the raster in the display system be increased, which is a limitation. Therefore, in the raster scan type display system, it is necessary to improve the aliasing by a method other than narrowing the grid interval. The generic term for these processes is called antialiasing.

Usually, antialiasing is performed by calculating the contribution area of a drawing figure to each pixel and expressing a halftone by a pixel value according to the ratio of the area. Such processing is generally very heavy, and has a drawing speed of about 1/10 to 1/100 of that when anti-aliasing processing is not performed, and is not suitable for real-time processing. Also,
It is difficult to realize from the viewpoint of hardware because it requires a very complicated structure.

Therefore, various measures have been taken to solve this problem, and in particular, a series of techniques called full screen antialiasing (FSAA) has been proposed. These techniques are based on a super-sampling method that calculates multiple sample values for one pixel. The simplest implementation is as follows.

That is, when the number of pixels of a desired display screen is W in the horizontal direction and H in the vertical direction, N × W and M × H.
Secure a drawing area of size. Here, N and M are arbitrary constants, and the larger they are, the higher the anti-aliasing effect is, but the larger the processing amount becomes. Then, the vertex coordinates of the figure to be drawn are scaled and drawn. For example, the vertex coordinates are (X1, Y
1), (X2, Y2), (X3, Y3), when drawing a triangle, (N × X1, M ×)
Y1), (NxX2, MxY2), (NxX3, MxY
3) Draw a triangle. Then, the image formed in the drawing area is reduced to the display area. At this time, the pixel value of the display area is obtained by calculating the average of the N × M pixel values adjacent to each other in the drawing area.

This method is widely used because the drawing speed drops to about 1 / (N × M), but the conventional hardware configuration can be used and control software can be easily implemented. However, this method only works for drawing a graphic with an area. For example, when a straight line is drawn, if the coordinates at both ends are scaled as they are, the apparent thickness of the straight line will be different when comparing the images with and without processing. In order to prevent this, it is necessary to change the treatment of the straight line as a rectangle with a thickness.

In order to obtain a higher drawing speed in a system using this method, either a more powerful drawing processor is installed, or a plurality of drawing processors are connected to perform parallel processing. You will need When the latter is selected, it is necessary to divide the drawing area into several parts and share the processing with each drawing processor. However, there is a problem in that the amount of drawing is not uniform depending on the division method, the load on a specific drawing processor is high, and efficient division of labor is not performed.

Therefore, an object of the present invention is to enable efficient antialiasing processing.

[0010]

In order to achieve this object, the present invention provides a plurality of drawing areas and a plurality of graphic drawing processors for drawing the same figure by giving different offsets to the respective drawing areas. And blending means for synthesizing the figures drawn in the respective drawing areas. This makes it possible to equalize the load on each drawing processor and enable efficient drawing.

Further, according to the present invention, in a plurality of graphic drawing processors, the offsets are set in advance so that the remaining control can be performed in the same procedure. This enables the control CPU
Can reduce the burden.

Further, according to the present invention, the blending means is constructed so that the drawing result by the drawing processor can be combined in real time. As a result, the number of connection terminals of the circuit can be reduced.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION First, a normal drawing process without antialiasing, which is the basis of the present invention, will be described, and then an antialiasing process based on the present invention will be described.

(1) Frame buffer The frame buffer is a display memory for supplying a display with bit pattern data corresponding to a display figure, and is a two-dimensional array having a size of the display screen width × height. There is. The contents of the array store the color code corresponding to each pixel. The drawing processor writes a display figure in the frame buffer. The written data is sequentially read by the display output device and sent to the display.

(2) Straight Line Drawing Algorithm by DDA Here, a straight line drawing algorithm will be described.
Although the present invention can be applied to figures other than straight lines, only straight lines will be described in this specification.

FIG. 2 is a flow chart showing a straight line drawing algorithm by DDA. "DDA" is an abbreviation for Digital Differential Analyzer. Although various other methods have been devised for the straight line drawing algorithm, and the present invention can be applied to other algorithms, the description thereof will not be given here.

In FIG. 2, first, the coordinates (X1, Y1) and (X2, Y2) at both ends of the straight line are given as parameters. In step S00 for making a determination, the displacement in the X direction and the displacement in the Y direction of the coordinates are checked from the coordinates (X1, Y1), (X2, Y2) at both ends of the straight line, and branching is performed depending on which is larger. When the displacement in the X direction is larger, the process branches to step S01 and is processed by the DDA in the X direction. When the displacement in the Y direction is larger, the process branches to step S11 and the DDA is performed in the Y direction. Perform processing.

When performing processing by DDA in the X direction,
In step S01 of making a determination, the drawing direction is checked. This is a process for making the value added in the X direction in the subsequent loop to be "positive", and when it becomes "negative", the start point and the end point are exchanged in step S02 to correspond. In step S03, the displacement in the Y direction is calculated.
In step S04, the coordinates (X1, Y1) are rounded to a suitable integer by a process such as rounding, and data is written to the frame buffer corresponding to the rounded coordinates (X1, Y1). A step S05 for making a determination checks the end of drawing. If the integer parts of the X coordinates of the start point and the end point match, the drawing is completed. In step S06, the parameters are updated.

The steps S11 to S16 for performing the DDA processing in the Y direction are the same as the steps S01 to S06. An example of a straight line drawn by the DDA algorithm is shown in FIG. Jagging occurs due to the display by pixels.

(3) Graphic drawing processor The graphic drawing processor is a device which has the above-mentioned frame buffer inside or outside thereof and performs drawing processing independently of the CPU. Generally, it has a function of performing the above-described DDA straight line drawing and the like, and is devised so that the drawing processing can be performed at high speed. Also, many have a function of display output from the frame buffer to the display. The present invention has a drawing function and a display function,
It is assumed that multiple things that work independently are used.

(4) Antialiasing Realization Algorithm The antialiasing realization algorithm proposed in the present invention will be described. First, a plurality of areas having the same size as the display screen are prepared. Here, FIG.
Consider the case where four are prepared as an example shown in (e). Draw delicately shifted figures in the prepared area. In the example shown in the drawing, figures shifted by ± 0.25 in the X and Y directions are drawn. That is, in the first area (FIG. 1B), the Y coordinate of the figure to be drawn is all offset by −0.25 to perform drawing. Similar offsets are applied to the second to fourth areas (FIGS. 1C to 1E).

By averaging and blending the pixel values of the corresponding areas of the four drawing results obtained in this way,
An image having an anti-aliasing effect is obtained as shown in FIG. This is realized by the fact that the carry timing to the integer part in the DDA algorithm differs depending on the given offset, and thereby a slightly different drawing result is obtained. Even if there are areas other than four, the anti-aliasing effect can be obtained by using an appropriate offset.

When further 3D display is performed, 3
A process of converting the dimensional coordinate system (X ′, Y ′, Z ′) into the two-dimensional coordinate system (X, Y) by the following equation is performed. X ″ = A ₀₀ X ′ + A ₀₁ Y ′ + A ₀₂ Z ′ + A ₀₃ Y ″ = A ₁₀ X ′ + A ₁₁ Y ′ + A ₁₂ Z ′ + A ₁₃ Z ′ ′ = A ₂₀ X ′ + A ₂₁ Y ′ + A ₂₂ Z ′ + A ₂₃ X = X ″ / Z ″ ″ Y = Y ″ / Z ″ ′ Since these expressions are calculated by including decimals, applying an offset to these results results in a more antialiasing effect. Will increase.

(5) Parallel execution of anti-aliasing Although the above-mentioned algorithm can be realized by a single drawing processor by performing drawing in sequence, by implementing these processes by a plurality of drawing processors, higher speed drawing can be achieved. The processing can be efficiently realized. FIG. 3 shows an example in which four drawing processors and four display area memories are connected in parallel. 1 is a CPU, 2-5 are drawing processors, 6
9 is a drawing memory, and 10 is a display output synthesizer. Since the drawing processors A to D are responsible for drawing the four drawing areas in the preceding paragraph, the drawing processing is performed in the same processing time as when a single drawing processor performs the processing when antialiasing is not performed. Can be completed.

The number of drawing areas and the number of drawing processors are not necessarily the same. For example, it is also possible to distribute the four drawing areas to the two drawing processors and perform drawing. If the offset value can be designated for each of the drawing processors A to D, the CPU can process all other processes with the same instruction. That is, since it is not necessary to individually control each drawing processor, an increase in load on the CPU can be ignored. Further, by adding the display output synthesizing device 10 that performs the blending process of the drawing result in real time, it is possible to reduce the memory area for storing the blending result and to omit the processing time. At this time, the display output synthesizer 10
If the connection is not made to the drawing memories 6 to 9 as shown in the drawing but to the component display outputs of the drawing processors 2 to 5, the input to the display output synthesizer 10 can be greatly reduced. it can.

[0026]

As described above, according to the present invention, a plurality of drawing areas, a plurality of graphic drawing processors that perform drawing by giving different offsets to the same figure for each drawing area, and each drawing area By providing the blending means for synthesizing the drawn figures, the load on each drawing processor can be equalized, and efficient drawing can be performed.

Further, according to the present invention, since the offsets are set in advance in each of the plurality of graphic drawing processors so that the remaining control can be performed in the same procedure, the load on the control CPU is reduced. be able to.

Further in accordance with the present invention, the blending means comprises:
Since the drawing results by the drawing processor can be combined in real time, the number of connection terminals of the circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a drawing result drawn in each drawing area and an image displayed after being blended in a case of antialiasing drawing according to the present invention.

FIG. 2 is a flowchart showing a straight line drawing algorithm by DDA.

FIG. 3 is a diagram showing an example of a connection between a control CPU and a graphic processor according to the present invention.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tomoaki Kozaki             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5B057 CA08 CA12 CA17 CB08 CB12                       CB16 CC04 CE08 CE11 CF05                       CH02 CH08 CH11                 5B080 CA03 FA08 FA14

Claims (3)

[Claims] 1. A plurality of drawing areas, a plurality of graphic drawing processors for drawing the same figure by giving different offsets to the respective drawing areas, and a blending means for synthesizing the figures drawn in the respective drawing areas. An anti-aliasing drawing device comprising: 2. The anti-aliasing drawing apparatus according to claim 1, wherein the plurality of graphic drawing processors are configured so that the respective controls can be performed in the same procedure by setting offsets in advance. 3. The anti-aliasing drawing apparatus according to claim 1, wherein the blending means is configured to be able to synthesize the drawing result by the drawing processor in real time.