JP2003303168A - Semiconductor integrated circuit for communication control - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems that two transmission buffers and two reception buffers, of maximum packet size, are required for conventional transmission/ reception buffer forming methods, which enlarges chip size and increases costs while enhancing transfer velocity, and that time required for data transfer can not be sufficiently abridged when transmission/reception buffers are each formed of a single buffer having storage capacity of the maximum packet size in order to reduce costs. <P>SOLUTION: This circuit is provided with a buffer memory 610 for holding received data up until the completion of error detection/correction, a reception allowing threshold register 613 capable of setting an arbitrary threshold address in a reception buffer part 262A having a write pointer for generating write address signals and a read pointer for generating read address signals, and a comparison circuit 616 for comparing a set value of the register with the value of the read pointer. This circuit is provided with the function of allowing the reception of a next data packet when the set value of the register is equal to a read address generated by the read pointer. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control technique and a technique effective when applied to a data processing device having an interface unit for packet communication.
B (Universal Serial Bus) standard and IEEE 1394 (I
nstitute of Electrical and Electronics Engineers 13
94) A technology effectively applied to a data processing LSI (large-scale semiconductor integrated circuit) such as a communication control processor having a standard communication function.

[0002]

2. Description of the Related Art As an interface standard between a computer and its peripheral devices, there are a USB standard and an IEEE13 standard.
In addition to the 94 standard, SCSI (Small Computer System Inte
rface), Fiber Channel, etc. Among them, the USB standard and the IEEE 1394 standard are standards for serially transmitting and receiving data via a cable, and since there are few signal lines, the cable is thin and the connector is small. It is used as an interface for peripheral devices such as printers and various storage media drivers. Communication according to the USB or IEEE 1394 standard is performed by a packet communication method that serially transmits data in units called packets. In such a packet communication system, functions such as generation of a check code and error detection and correction according to an error detection system such as CRC (cyclic code) are provided.

Conventionally, in a microprocessor system having a packet communication function, two or more receiving and transmitting buffers each having a maximum data size that can be stored in one packet are provided in order to improve the data transfer rate. . Considering the case of data reception, this is to judge whether or not there is an error in the received data, so calculate whether there is an error while receiving the data, and if it is judged that there is an error, receive it. Since the data must be discarded, the data in the receive buffer cannot be read until the error detection is completed after the data is received.

Similarly, in the case of data transmission, it is confirmed whether or not an error exists in the transmitted data, and if an error exists (a response packet notifying that the data was normally received within a predetermined time is not received). In this case, the transmitted data must be retransmitted.Therefore, the transmitted data is held in the buffer until the error detection on the data receiving side is completed, and the transmitted data is discarded after confirming that there is no error. This is because it is necessary to write the next data. Therefore, conventionally, two reception buffers and two transmission buffers each capable of storing at least the maximum packet size data are provided, and while one buffer waits for a reception or transmission result, The efficiency of data transfer has been improved by making it possible to receive data or write transmitted data.

[0005]

However, depending on the communication standard, the maximum packet size may increase at the same time as the communication speed increases. At this time, in the conventional transmission / reception buffer configuration method, two transmission buffers and a reception buffer each having the maximum packet size are required, so that the transfer speed is improved but the chip size is increased and the cost is increased. There is. Further, in order to reduce the cost, if the transmission / reception buffer is configured by a single-sided buffer having a storage capacity of the maximum packet size, the reception data cannot be read from the reception buffer during data reception, and the transmission buffer is stored during data transmission. Since the next transmission data cannot be written,
There is a problem in that the time required for data transfer cannot be sufficiently shortened despite the increase in external communication speed.

It is an object of the present invention to reduce the time required for data transfer while preventing an increase in chip size in a communication control semiconductor integrated circuit having an interface for packet communication. Another object of the present invention is to achieve a cost reduction in a communication control semiconductor integrated circuit having an interface for packet communication by suppressing an increase in buffer capacity accompanying an increase in packet size to a necessary minimum. To do. Still another object of the present invention is to provide a storage medium which is provided with an interface for packet communication and can be used for developing a new semiconductor integrated circuit capable of performing high-speed data transfer and having a low cost and a packet communication function in a short period of time. To provide. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in a communication control semiconductor integrated circuit having an interface for packet communication, a buffer memory that holds received data until error detection and correction is completed, and a write address signal that writes the received data to the buffer memory are generated. An arbitrary threshold address can be set in the reception buffer unit having write control means (write pointer) for controlling and read control means (read pointer) for generating a read address signal for reading data written in the buffer memory. A reception permission threshold value register and a comparison circuit for comparing the set value of the register and the value of the read pointer are provided, and when the set value of the register and the read address generated by the read control means are equal, Receive buffer function that allows the reception of data packets It is obtained so as to have to.

A buffer memory for holding transmission data until error detection and correction on the receiving side is completed,
Write control means (write pointer) that generates an address signal for writing the transmission data in the buffer memory
And a reception permission threshold register capable of setting an arbitrary threshold address in a transmission buffer having a read control unit (read pointer) for generating an address signal for reading data written in the buffer memory, and setting of the register. The transmission buffer unit has a function of permitting the transmission of data already written in the buffer memory when the value becomes equal to the write address generated by the write control means.

Generally, the buffer memory is constructed so as to have a capacity capable of storing the maximum received data which can be stored in one transmission packet, but when the capacity of the buffer memory becomes large, all the data is read or written. Takes longer. Further, there is rarely an extreme difference between the read speed and the write speed of the buffer memory. Therefore, when reading of data from the receive buffer memory progresses to some extent, writing is started from the area that has already been read, and a threshold address that prevents the write address from overtaking the read address is calculated in advance and stored in the receive permission threshold register. By setting in advance, the apparent data transfer speed can be increased and the total data transfer time can be shortened. Similarly, when writing of transmission data to the transmission buffer memory progresses to some extent, reading is started from the area where writing has already finished, and a threshold address that prevents the read address from overtaking the write address is calculated in advance and transmission is permitted. By setting it in the threshold register, the apparent data transfer speed can be increased and the total data transfer time can be shortened.

Further, in the present invention, the packet communication interface section having the buffer memory and its read / write control means is modularized, and its design data is I
The data is stored in the storage medium as P data. As a result, it becomes possible to develop a new semiconductor integrated circuit which can perform data transfer at high speed, has a low cost, and has a packet communication function in a short period of time.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration example of a device having a serial communication interface according to the present invention. Examples of such devices include peripheral devices such as personal computers, printers, and various storage media drivers. Further, as the serial communication interface, for example, an interface of USB standard or IEEE1394 standard is available.

FIG. 1 shows a state in which 100 is a personal computer, 200 is a peripheral device, and the personal computer 100 and the peripheral device 200 are connected via a cable 300. According to the USB standard, the personal computer 100 is called a host device, and the peripheral device 200 is called a device device. Peripheral device 20
It is also possible to connect another personal computer instead of 0. In addition, as shown in FIG.
0) and the device equipment (200) are directly connected, it is also possible to connect the device equipment 200A, 200B, 200C such as a tablet, a scanner, and a printer via a relay device 400 called a hub as shown in FIG. Is. Thereby, a plurality of device devices can be connected to one host device. In the embodiment of FIG. 1, only the internal system configuration of the device equipment (200) is shown in detail, but since the host equipment (100) side also has a similar system configuration, the device equipment (20) will be described below.
0) The internal system configuration will be described, and description of the system configuration on the host device (100) side will be omitted.

The internal system of the device unit (200) is a central processing unit (hereinafter referred to as CPU) 210.
And a memory such as a ROM 220 that stores a program executed by the CPU 210 and fixed data and a RAM 230 that provides a work area of the CPU 210, a peripheral controller 240 such as a DMA controller or an interrupt controller, a timer circuit, etc., which is provided according to the system, and the system. A custom logic unit 250, CP that provides functions specific to
The packet communication interface unit 260 is connected to the U210 via the CPU bus 270 and performs serial communication according to a predetermined protocol. Bus 27
0 is a signal line group (data bus) for transmitting data signals
And a signal line group for transmitting an address signal (address bus)
And a signal line group (control bus) for transmitting a control signal.

Although not particularly limited, these circuits can be formed as a communication control LSI (hereinafter, referred to as a processor) formed on one semiconductor chip such as single crystal silicon. CPU 210, packet communication interface unit 260, and CPU bus 270
When it is configured as a processor LSI including
The SI can be provided with a port connected to the bus 270 or the custom logic unit 250, and can be connected to an external system bus or electronic component via the port. Although not shown in FIG. 1, in the actual device equipment, in addition to the processor, a mechanism and parts for realizing the functions of the equipment are provided. Some of them are connected to the processor.

In the processor of the embodiment shown in FIG. 1, the packet communication interface section 260 includes the CPU bus 27.
CPU interface unit 261 for enabling transmission / reception of signals to / from CPU 210 via 0, data transfer speed on the bus side and data on the protocol control unit 263 side for temporarily holding transmission data and reception data, respectively. Transmission / reception buffer unit 262 that buffers the difference in processing speed
And adding a header according to a preset protocol,
A protocol control unit 263 having a packet processing function such as assembling and disassembling a packet having a format according to a communication standard and a function for generating a check code and an error detection according to an error detection method such as CRC (cyclic code). And a transceiver unit 264 that transmits and receives a signal on the cable side in accordance with an instruction from the protocol control unit 263. The transceiver unit 264 includes a transmission driver circuit that drives a signal line of the cable 300 with a voltage to transmit a signal, and a reception driver circuit that detects a potential of a signal sent via the cable 300 to determine the signal. To be done.

The packet communication interface unit 26
Each circuit that constitutes 0 includes C as a module and C
PU 210, memories 220 and 230, custom logic unit 2
Communication control LS on one semiconductor chip with 40 etc.
Although it may be configured as an I or data processing LSI, only the interface section 260 may be formed on one semiconductor chip and configured as a communication interface LSI. Send data from CPU 210 to C
Although it may be directly supplied to the packet communication interface unit 260 via the PU bus 270, the RAM 230 is controlled by DMA (direct memory access) transfer control.
Or may be transferred from the custom logic unit 240 to the packet communication interface unit 260.

FIG. 2 shows the transmission / reception buffer unit 262.
A more detailed structure of the reception buffer unit 262A is shown in FIG. 5, and a more detailed structure of the transmission buffer unit 262B is shown in FIG. As shown in FIG. 2, the receiving buffer unit 262A receives the read address RAD for the receiving buffer memory 610 and the receiving buffer memory 610 based on the memory read control signal MRD11 and the clock signal CLK supplied from the CPU interface unit 261. Read pointer 611 including a counter circuit for generating
And a read data register 612 that takes in the received data read from the reception buffer memory 610 and outputs it onto the bus 270, and a transmission permission threshold register 613 that holds the transmission permission threshold supplied from the CPU via the bus.
And a data size register 614 that holds the size (number of bytes) of the received data written in the receive buffer memory 610 and outputs it onto the bus 270, a write control signal MWT1 from the protocol control unit 263, and a clock signal CLK. A write pointer 615 including a counter circuit for generating a write address WAD for the receive buffer memory 610 based on the write pointer 6;
15, the write address WAD generated in step 15 and the value of the transmission permission threshold register 613, and the write address WAD and the read address RA generated in the read pointer 611.
A comparing unit 616 that compares D with the protocol
A read permission generation circuit 617 for generating a read permission signal RDP of the buffer memory for the CPU based on the data confirmation signal DST from the control unit 263 is provided.

The reception buffer memory 610 is constructed to have a capacity capable of storing the maximum reception data that can be stored in one transmission packet. The receive buffer memory 610 is activated by the write control signal MWT1 from the protocol control unit 263, and at that time, the data supplied from the protocol control unit 263 via the input data bus 618 is generated by the write pointer 615. It is written in the address indicated by the written write address WAD.

The transmission permission threshold register 613 has a register write control signal W from the CPU interface unit 261.
With TC1, the threshold data currently output by the CPU 210 onto the CPU bus 270 is fetched and held. The value of the write pointer 615 at the time when the reception data is completely stored in the buffer memory 610 is transferred to the data size register 614, so that the size of the reception data can be obtained. The difference between the value of the read pointer 611 and the value of the write pointer 615 may be taken and stored in the data size register 614.

The read data register 612 and the transmission data size register 614 are provided in the CPU interface unit 26.
Register read control signals RRC1 and RRC2 from 1 enable reading onto the CPU bus 270. The register write control signal WTC1, the register read control signals RRC1, RRC2, and the memory read control signal MRD11 are read / write control signals output from the CPU 210 on the address bus 270 by the address decoder provided in the CPU interface unit 261. And is generated by decoding the address signal. The read data register 612 may be provided in the CPU interface unit 261.

The comparison unit 616 determines when the value of the read pointer 611 matches the value of the data size register 614 or the value of the read pointer 616 is the transmission permission threshold register 6
When the set value of 13 is met, the write permission signal WPM output to the protocol control unit 263 is changed to the valid level, and when the read permission signal RDP from the read permission generation circuit 617 is set to the valid level, the write permission signal WPM. To the invalid level.

The read permission generation circuit 617 changes the read permission signal RDP of the buffer memory 610 to the CPU to the valid level when the data confirmation signal DST supplied from the protocol control unit 263 is set to the valid level, and this signal When the CPU (or the DMA controller) starts reading the buffer memory 610 and the value of the read pointer 611 matches the value of the data size register 614, the read permission signal RDP is changed to the invalid level. The read permission signal RDP is output as an interrupt signal to the CPU 210 or a transfer request signal to the DMA controller.

The operation of the reception buffer unit 262B will be described below.
This will be described with reference to the timing charts of FIGS. 3 and 4. Of these, FIG. 3 shows the timing of each signal when the reception permission threshold register is not used, and FIG. 4 shows the timing of each signal when the reception permission threshold register is used.

When the protocol control unit 263 receives a packet, the protocol control unit 263 converts the serial data into parallel data such as 8 bits while extracting data from the packet and performing error check and error correction of the data by, for example, the CRC method, The write control signal MWT1 is output to the buffer memory 610 on the condition that the write permission signal WPM from the reception buffer unit 262A is at the effective level, and the converted reception data is transmitted via the input data bus 618 to the buffer memory 610. It is supplied to 610 (reference numeral T1 in FIG. 3). Then, the reception buffer unit 2
At 62A at that time, the data on the input data bus 618 is stored in the address WAD indicated by the write pointer 615. After that, the write pointer 615 is counted up by the clock CLK to update the write address WAD. Then, the buffer memory 610 successively stores the data on the input data bus 618 at the address indicated by the write address WAD.

The protocol control unit 263 changes the write control signal MWT1 to low level when all the received data is transferred to the reception buffer unit 262A, and when the CRC error check result shows no error, the protocol control unit 263 outputs the data confirmation signal DST. It is changed to a high level (reference numeral T2 in FIG. 3). Then, the reception buffer unit 262
In A, the read permission generation circuit 617 changes the read permission signal RDP to the CPU to the valid level and the comparison unit 616 changes the write permission signal WPM to the protocol control unit 263 to the invalid level with one clock delay (FIG. 3). Code T3). At this time, after the value of the write pointer 615 is transferred to the data size register 614, the write pointer is reset.

FIG. 3 shows the timing when the same amount of received data as the storage capacity of the buffer memory 610 is stored, but the received data is stored in the buffer memory 610.
In some cases, the storage capacity is less than. By transferring the value of the write pointer 615 to the data size register 614, the CPU can know the size of the received data. When the read permission signal RDP is enabled, CP
The read control signal MRD1 supplied from the CPU interface unit 261 to the reception buffer unit is changed by U outputting the address and the read / write signal for selecting the reception buffer unit 262A using the bus 270, and the read control signal MRD1 is received from the buffer memory 610. The data is read and output onto the bus 270 via the read data register 612 (reference numeral T4 in FIG. 3). Further, the read pointer 611 is counted up by the clock CLK, the read address RAD is updated, and the received data in the buffer memory 610 is sequentially read.

Next, the operation of the reception buffer unit when the reception permission threshold value register 614 is used will be described with reference to FIG. When the reception permission threshold value register 614 is used, a threshold value address that allows writing of the next reception data from the protocol control unit side even when the CPU is reading the reception data in the buffer memory 610 in advance due to initialization or the like is set. It is set in the reception permission threshold register 614 in advance.

FIG. 4 shows the timing when the address "A360" is set in the register 614 as the reception permission threshold as an example. As shown in FIG. 4, when the read address RAD indicated by the read pointer becomes "A360" which is the same as the reception permission threshold value, the write permission signal WPM for the protocol control unit is changed to a valid level (reference numeral T5 in FIG. 3). Then, in response to this, the buffer memory 61 is sent from the protocol control unit 263.
The write control signal MWT1 supplied to 0 is changed to a valid level, and the first 1 byte D000 of the received data is output onto the input data bus 618 (reference numeral T6 in FIG. 3). As a result, the buffer memory 610 then stores the data on the input data bus 618 at the address corresponding to the address WAD indicated by the write pointer 615. After that, the write pointer 615 is counted up by the clock CLK to update the write address WAD. Then, the buffer memory 610 successively stores the data on the input data bus 618 at the address indicated by the write address WAD. During this time, on the read side, the read address RAD is set to "A36" by the read pointer.
1 ”,“ A362 ”, ..., And the remaining data in the buffer memory 610 is continuously read.

FIG. 4 shows the case where the received data has the maximum size, but when the size of the received data is small, the value of the read pointer 611 is the reception permission threshold register 613.
If it matches the value set in the data size register 614 before matching the reception permission threshold value in the above, the write permission signal WPM to the CPU is changed to a valid level at that time, and the transmission data to the buffer memory 610 is changed. Writing can be started. The buffer memory 610 is configured to have a capacity capable of storing the maximum received data that can be stored in one transmission packet, but when the capacity of the buffer memory becomes large, the time required to read or write all the data. Becomes longer. Further, there is rarely an extreme difference between the read speed and the write speed of the buffer memory. Therefore, when reading of data from the reception buffer memory progresses to some extent, writing is started from an already read area, and a threshold address that prevents the write address from overtaking the read address is calculated in advance and the reception permission threshold register 613 is calculated. By setting to 1, the apparent data transfer speed can be increased and the total data transfer time can be shortened.

An example of how to calculate and set the threshold value set in the reception permission threshold value register 613 will be described with reference to the flowchart of FIG. First, the CPU 210 calculates the data transfer rate (byte / second) R1 on the protocol control unit 263 side (step S1). The data transfer rate on the protocol control section 263 side can be easily calculated from the bit rate determined by the standard for each applied protocol. Next, the data transfer rate R2 on the CPU 210 side is calculated (step S2). The data transfer rate on the CPU 210 side is a data transfer rate of a bus peculiar to the system to which it is applied, and is a value determined when the system is determined. At this time,
If the bus width of the CPU bus 270 and the bus width of the input data bus 618 on the protocol control unit 263 side are different, the data transfer rate is calculated in consideration of the difference.

Next, the ratio A (= R1 / R2) of the data transfer rate R1 on the protocol side and the data transfer rate R2 on the CPU side calculated in steps S1 and S2 is calculated (step S3). Then, the product B (= SMAX × A) of the maximum data size (number of bytes) SMAX that can be stored in one packet and the speed ratio A calculated in step S3 is calculated (step S4). Next, the difference C (= S) obtained by subtracting the value of the product B calculated in step S4 from the maximum data size SMAX.
MAX-B) is calculated (step S5). Then, a value larger than the difference C is determined as a threshold value, and the CPU writes the value in the reception permission threshold value register 613 to complete the setting (step S6).

If the threshold value calculated as described above is set, the protocol control unit 263 stores the next reception data in the buffer memory 6 while the CPU 210 is reading the reception data from the reception buffer memory 610.
Even if writing is started from the beginning in 10, the write address does not overtake the read address, and by starting writing in parallel with reading, the total time required for data transfer can be shortened. In addition, here
Although the description is made assuming that the CPU 210 executes the calculation and setting of the threshold value as the initialization process when the system starts up, the threshold value is determined in advance by the same procedure as in FIG. 5, and the determined threshold value is initially stored in the ROM 220 or the like. It is stored as a set value and is stored in the CPU 21 at initialization.
0 may read the threshold from the ROM and set it in the reception permission threshold register 613. Further, since the size of the data transmitted in one packet is not fixed but variable, the threshold value calculation process of FIG. 7 is performed for each received data to set the threshold value set in the reception permission threshold value register. It is also possible to change it every time.

Next, a configuration example of the transmission buffer unit 262B will be described with reference to FIG. As shown in FIG. 5, the transmission buffer unit 262B includes the transmission buffer memory 6
20 and the write address W for the transmission buffer memory 620 based on the write control signal MWT2 and the clock signal CLK supplied from the CPU interface unit 261.
A write pointer 621 including a counter circuit that generates AD, a write data register 622 that captures the transmission data that is supplied via the bus 270 and should be stored in the transmission buffer memory 620, and passes the transmission data to the transmission buffer memory 620, and the bus. A transmission permission threshold value register 623 that holds a transmission permission threshold value that is supplied from the CPU via the bus; a transmission data size register 624 that captures and holds the transmission data size (the number of bytes) supplied from the CPU via the bus; A read address RA for the transmission buffer memory 620 based on the read control signal MRD2 from the control unit 263 and the clock signal CLK.
A read pointer 625 including a counter circuit for generating D, a read address RAD generated by the read pointer 625, the value of the transmission permission threshold register 623, a write address WAD generated by the write pointer 621, and a data size register 624. A comparing unit 616 that compares the set value with the protocol,
Based on the transmission completion signal TXE from the control unit 263, the write permission signal W of the buffer memory to the CPU
A write permission generation circuit 627 for generating TP is provided.

The transmission buffer memory 620 is configured to have a capacity capable of storing the maximum transmission data that can be stored in one transmission packet, and the CPU interface unit 2
The data which is accessed by the write control signal MWT2 supplied from 61 and the write address WAD generated by the write pointer 621 and which is stored in the write data register 622 at that time is stored in the address indicated by the write address WAD. Further, the transmission buffer memory 620 is
The data read and accessed by the read control signal MRD2 from the protocol control unit 263 and the read address RAD from the read pointer 625 is passed to the protocol control unit 263 via the output data bus 628. Write control signal MWT2 is CP
The U interface unit 261 generates by decoding the address signal on the bus 270 and the write enable signal output by the CPU 210.

The transmission permission threshold value register 623 and the transmission data size register 214 are register write control signals WTC2 and WTC from the CPU interface unit 261 respectively.
The TC3 is configured to capture and hold the threshold data output by the CPU 210 onto the CPU bus 270. The register decoder control signals WTC2 and WTC3 and the memory write control signal MWT2 are output by the address decoder provided in the CPU interface unit 261.
It is generated by decoding the read / write control signal and the address signal output onto the address bus 270 by the CPU 210. Write data register 622
May be provided in the CPU interface unit 261.

When the value of the write pointer 621 matches the value of the data size register 624, the comparing section 626 determines that
The read permission signal RPM output to the protocol control unit 263 is changed to a valid level, and when the value of the read pointer 625 matches the value of the data size register 624, the read permission signal RPM is changed to an invalid level.

The write permission generation circuit 627 receives the transmission completion signal T supplied from the protocol control unit 263.
When XE is set to valid level or write pointer 62
When the value of 1 matches the set value of the transmission permission threshold value register 623, the write permission signal WTP of the buffer memory 620 to the CPU is changed to the effective level, and the CPU (or DMA controller) buffers the next transmission data by this signal. It becomes possible to write in the memory 620. Further, the write permission generation circuit 627 changes the write permission signal WTP to the invalid level when the value of the write pointer 621 matches the value of the data size register 614. When the write permission signal WTP is at the invalid level, CP
U210 is prevented from writing to the transmit buffer memory 620.

The operation of the transmission buffer unit 262B will be described below.
This will be described with reference to the timing chart of FIG. In FIG. 6, as an example, the address “A36” is set as the reception permission threshold.
The timing when 0 "is set in the register 614 is shown. The CPU 210 or the DMA controller outputs the device designation address and the write data on the bus 270 and changes the read / write signal when a transmission request is generated. Then, the write control signal MET2 supplied from the CPU interface unit 261 to the transmission buffer unit 262B is changed, the write data on the bus at that time is taken into the write data register 622, and the write pointer 621 generates the write data. The write data is written in the address of the buffer memory 620 indicated by the address WAD, and the write pointer 6
Reference numeral 21 is counted up by the clock CLK to update the write address WAD, and write data is written in the buffer memory 620.

When the value of the write pointer 621 becomes "A360" which is the same as the reception permission threshold value in the register 623, the read permission signal RPM to the protocol control unit is changed to the valid level (reference numeral T7 in FIG. 6).
Then, in response to this, the read control signal M supplied from the protocol control unit to the transmission buffer unit 262B.
RD2 is changed to a valid level (reference numeral T8 in FIG. 6), and at that time, the read address RA indicated by the read pointer 625.
Address 0 of buffer memory 620 (A00
The transmission data written in 0) is read. Then, the read pointer 625 is counted up by the clock CLK, the read address RAD is updated, and the transmission data in the buffer memory 620 is sequentially read. While the transmission data in the buffer memory 620 is being read by the read pointer 625, the CPU
When writing to the buffer memory 620 by
The write permission generation circuit 627 changes the write permission signal WTP to the CPU 210 to an invalid level, and writing of the next transmission data is disabled (reference numeral T9 in FIG. 6).

When all the transmission data is read out, the read control signal MRD2 is changed to a valid level, and when the protocol control unit subsequently receives a packet indicating that the data has been normally received from the destination device, the transmission completion signal TXE is sent. When the write permission generation circuit 627 changes to the valid level and the write permission signal WTP to the CPU 210 changes to the valid level, the next transmission data can be written (reference symbols T10 to T12 in FIG. 6). If the packet indicating that the data has been normally received is not transmitted from the destination device after the transmission is completed, the protocol control unit keeps the transmission completion signal TXE at the invalid level, and the write permission generation circuit 627. Also CP
The write permission signal WTP for U210 is maintained at an invalid level. Therefore, since the CPU cannot write the next transmission data, the transmission data already written is held in the transmission buffer memory 620 as it is. Therefore, the protocol control unit can read the transmission data in the transmission buffer memory 620 again and retransmit it.

FIG. 6 shows the case where the transmission data has the maximum size. When the size of the transmission data is small, the value of the write pointer 621 is the reception permission threshold register 623.
When the value matches the value set in the data size register 624 before matching the reception permission threshold value in the above, the read permission signal RPM to the protocol control unit is changed to a valid level at that time and transmission in the buffer memory is performed. The reading of data can be started.

Since the method of calculating the threshold value set in the transmission permission threshold value register 623 can be performed by a procedure substantially similar to the procedure of calculating the reception permission threshold value shown in FIG.
Detailed explanation is omitted. The calculation of the transmission permission threshold differs from the calculation of the reception permission threshold only in that the transfer rate ratio is calculated as R2 / R1 instead of R1 / R2 in step S3. Note that the calculation and setting of this transmission permission threshold may be executed by the CPU 210 as an initialization process when the system starts up. The threshold value may be read from and set in the transmission permission threshold value register 623. Furthermore, it is also possible to perform a threshold value calculation process for each size of data to be transmitted and change the threshold value set in the transmission permission threshold value register 623 every time.

Further, the packet communication interface unit of the above embodiment is modularized so that it can be handled as an independent circuit (IP core) separately from the others, and the circuit design information of the module is converted into IP data (data having intellectual property value). ) Is stored in a storage medium such as an optical disk (for example, a CD), the circuit design information is read from the storage medium at any time and incorporated into an arbitrary LSI, so that a new interface function is required. It can be used when developing an LSI. Note that IP data is designed as one unitary circuit and stored in a database or the like, and when developing an LSI that requires a circuit having the same function, the already designed data is read from the database and The data is such that a desired function can be realized by combining with the circuit of. The circuit design information stored in the storage medium may be in the form of a netlist or the like, but it is preferable that the circuit design information is described in HDL (hardware description language) because of its high versatility.

FIG. 9 shows a workstation (which may be a personal computer) as an example of an apparatus for utilizing IP using such a storage medium. In the figure, reference numeral 500 is an optical disk as a storage medium for the circuit design information (IP data) of the communication module, and reference numeral 600 is a workstation body for reading information from the storage medium 500 and reproducing an actual circuit on the display screen 610. . Thereby, the circuit design information (I) of the communication module formed in the semiconductor integrated circuit device such as the microprocessor is obtained.
(P data) can be stored in a storage medium and used. The storage medium is not limited to the optical disc, and may be a flexible disc or MO (magneto-optical disc).

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the embodiment, the device provided with only one serial communication interface has been described, but in addition to the serial communication interface for the device device itself to communicate with the host device as in the embodiment, the device itself It is also possible to provide a second serial communication interface for becoming a device and enabling communication with the device device, and apply the above embodiment to each interface section.
Further, in the above embodiment, the transceiver for transmitting and receiving signals is formed on the same chip as the processor, but the transceiver can be configured as another semiconductor integrated circuit.

In the above description, the USB, which is the field of application behind the invention made mainly by the present inventor, is the background.
L for communication control that constitutes a standard interface system
The case where the present invention is applied to SI has been described.
A communication control LSI forming an IEEE 1394 standard interface system or a system having both a USB standard interface function and an IEEE 1394 standard interface function, and further a USB standard and IEEE 13
It can also be used when configuring a system having a serial communication interface other than the 94 standard. Further, the present invention is not limited to the interface of serial communication, but can be applied to the interface for packet communication.

[0047]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, in a communication control semiconductor integrated circuit having an interface for packet communication, it is possible to reduce the time required for data transfer while preventing an increase in chip size, and to reduce the buffer capacity accompanying an increase in packet size. The increase can be suppressed to the necessary minimum and the cost can be reduced. Further, since the packet communication interface is modularized and its design data is stored as IP data in the storage medium, a new semiconductor integrated circuit which can transfer data at a high speed and has a packet communication function in a short time at low cost. Will be able to develop.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a communication control LSI in a device provided with a packet communication interface unit to which the present invention is applied and a system using the same.

FIG. 2 is a block diagram showing a more detailed configuration example of a reception buffer unit that constitutes the packet communication interface unit of FIG.

FIG. 3 is a timing chart showing signal timings during a reception operation that does not use the reception permission threshold register in the reception buffer unit of the embodiment of FIG.

FIG. 4 is a timing chart showing signal timings during a reception operation using the reception permission threshold register in the reception buffer unit of the embodiment of FIG.

5 is a block diagram showing a more detailed configuration example of a transmission buffer unit that constitutes the packet communication interface unit of FIG.

FIG. 6 is a timing chart showing signal timings during a transmission operation using the transmission permission threshold value register in the transmission buffer unit of the embodiment of FIG.

FIG. 7 is a flowchart showing an example of a method of calculating and setting a threshold value set in the reception permission threshold value register of the transmission buffer unit in the embodiment of FIG.

FIG. 8 is a block diagram showing a configuration example of a system using a device provided with a packet communication interface.

FIG. 9 is a storage medium in which circuit design information (IP data) of the packet communication interface unit according to the present invention is stored;
It is a perspective view showing a workstation as an example of an apparatus which reads information from this storage medium and reproduces a real circuit.

[Explanation of symbols]

260 packet communication interface 261 CPU interface section 262 transmission / reception buffer section 262A reception buffer unit 262B transmission buffer unit 263 Protocol Control Unit H.264 transceiver 270 bus 610 Receive buffer memory 613 Reception permission threshold register 620 transmission buffer memory 623 Transmission permission threshold register

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takayuki Suzuki             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F term (reference) 5B077 DD04 DD15 DD23 MM02 NN08

Claims (11)

[Claims] 1. A semiconductor integrated circuit for communication control, comprising a CPU, a memory, a communication interface section for transmitting and receiving data to and from an external device, and a bus connecting these, wherein the communication interface section Is a reception buffer memory for sequentially storing reception data, a transmission buffer memory for sequentially storing transmission data, a control means for performing an error check on the reception data and configuring the transmission data in a format conforming to a communication standard, A semiconductor integrated circuit for communication control, comprising: a register capable of setting a threshold address that permits writing of other received data while reading the received data from the buffer memory. 2. A comparison means for comparing a read address signal generated for reading the reception data from the reception buffer memory with a threshold address set in the register, and the comparison means compares the read address signal with the read address signal. 2. The semiconductor integrated semiconductor device for communication control according to claim 1, wherein the semiconductor integrated circuit for communication control is configured to permit writing of other received data to the reception buffer memory based on a match with a set value of the register. circuit. 3. After the completion of writing a series of received data to the receive buffer memory, whether or not to permit the read of the received data in the receive buffer memory based on the error check result of the received data in the control means. The semiconductor integrated circuit for communication control according to claim 1 or 2, wherein a signal indicating that is output from the communication interface unit. 4. The semiconductor integrated circuit for communication control according to claim 1, wherein the threshold address is set in the register by the CPU when the system starts to operate. 5. A semiconductor integrated circuit for communication control, comprising a CPU, a memory, a communication interface section for transmitting and receiving data to and from an external device, and a bus connecting these, wherein the communication interface section Is a reception buffer memory for sequentially storing reception data, a transmission buffer memory for sequentially storing transmission data, a control unit for performing an error check on the reception data and configuring the transmission data in a format conforming to a communication standard, A semiconductor integrated circuit for communication control, comprising: a register capable of setting a threshold address that permits writing of other transmission data while reading the transmission data from the buffer memory. 6. A comparison means for comparing a read address signal generated for reading transmission data from the transmission buffer memory with a threshold address set in the register, and the comparison means compares the read address signal with the read address signal. 6. The communication control semiconductor integrated circuit according to claim 5, wherein writing of other transmission data to the transmission buffer memory is permitted based on a match with a set value of the register. circuit. 7. After the completion of writing a series of transmission data to the transmission buffer memory, whether or not to permit the reading of the transmission data in the transmission buffer memory based on the presence or absence of the transmission completion signal from the control means. 7. The semiconductor integrated circuit for communication control according to claim 5, wherein a signal indicating that is output from the communication interface unit. 8. The communication control semiconductor integrated circuit according to claim 5, wherein the setting of the threshold address in the register is performed by the CPU when the operation of the system is started. 9. The device according to claim 5, further comprising a second register capable of setting a threshold address for permitting writing of other received data while the received data is being read from the receive buffer memory. A semiconductor integrated circuit for communication control according to any one of 1. 10. A circuit provided in the semiconductor integrated circuit device for communication control according to claim 1, wherein at least the communication interface unit is modularized, and circuit design information of the module is intellectual property. A storage medium characterized by being stored as valuable data. 11. The storage medium according to claim 10, wherein the circuit design information is expressed in a hardware description language.