JP2003302952A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost and the size of a display device which displays an image in apparently higher resolution by pixel shifting than in the resolution of a display. <P>SOLUTION: The display 10 performs each subframe display by directly inputting image data transferred to a controller of the display 10 into an image processing circuit 11 for image-processing them, obtaining image data for a plurality of subframes by decomposing the image data for each frame after the image processing, and based on the image data for each subframe. In this case, it is preferred to decompose the image data by storing the image data in frame memory 12, and reading only the data necessary for displaying each subframe. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device which displays an image having a resolution apparently higher than that of a display element by shifting pixels.

[0002]

2. Description of the Related Art Conventionally, in a display device for displaying an image using a display such as a liquid crystal display, one frame of image data is divided into a plurality of subframes and displayed (or projected) for each subframe. ) There is known a display device which displays an image having a resolution apparently higher than the resolution of a display device by performing display by shifting the position. And such a method is called pixel shift.

As such a display device, for example, in Patent Document 1, one frame is composed of four fields (subframes), an image of each field is written in a corresponding frame memory, and a liquid crystal panel for display is displayed. A liquid crystal panel for controlling the polarization direction and a crystal plate for shifting the display position
The image of the first field is displayed without changing the display position, and the image of the second field is 1 / horizontally in the horizontal direction.
The image of the third field is displayed shifted by 2 pixel pitch, the image of the third field is displayed shifted by 1/2 pixel pitch in the vertical direction, and the image of the fourth field is displayed by 1 in the horizontal and vertical directions.
A display device is disclosed in which images are displayed with a shift of / 2 pixel pitch, and the images of these fields are combined and displayed.

According to such a display device, a high-definition image having four times as many pixels as the display liquid crystal panel can be displayed. Finer definition is possible. In addition, Patent Document 2
Discloses an image display device having a plurality of wobbling modes in which an optical axis of light from a liquid crystal display panel is vibrated in a predetermined direction to shift pixels, and such a device is disclosed. It is possible to achieve high definition by shifting pixels even for different types of input video signals.

Further, as a related technique, Patent Document 3
Discloses a projection display device in which image data is distributed to 2 to 4 frame memories for each field, and the image data is read from each frame memory and each field is displayed by a display liquid crystal panel. Patent Document 4
The two field memories are alternately set to the write mode and the read mode, and while the video signal is being written to one field memory, the video signal written from the other field memory is read at N times the writing speed. Thus, there is disclosed a video display device that creates N images that are gradually shifted in the horizontal direction and shifts the pixels in synchronization with the display.

[0006]

[Patent Document 1] Japanese Patent Laid-Open No. 4-63332.

[Patent Document 2] Japanese Patent Laid-Open No. 2001-157229

[Patent Document 3] Japanese Patent No. 2939826

[Patent Document 4] Japanese Unexamined Patent Publication No. 9-230833

[0007]

However, in the display device disclosed in Patent Document 1 or 3,
Since the image data to be displayed is once distributed by the distributor to the frame memory corresponding to each field and then transferred to the display unit, the peripheral circuits required for image processing and read / write control to the frame memory are complicated. However, the cost of the parts increases accordingly, and there is a problem that the cost of the entire apparatus increases. There is also a problem that the device becomes large in size because a complicated circuit is formed. In particular, this tendency is remarkable when high definition and large capacity are advanced, but improvement of this point is not particularly mentioned not only in Patent Documents 1 and 3 but also in Patent Documents 2 and 4. Further, in these documents, image processing necessary for displaying an image, for example, resolution conversion, brightness correction, contrast adjustment, color tone adjustment, operation when the number of pixels of image data and the number of pixels (resolution) of a display element do not match. There is no description about the relationship between the processing such as superimposing of the instruction screen and the pixel shift, and no description about the arrangement of these image processing circuits.

[0008] Further, Japanese Patent Application Laid-Open No. 2004-242242 discloses that image data is read at N times the speed at the time of writing. Considering, for example, pixel shift that decomposes an image into four subframes, the frame rate of the original image is considered. Is 60 Hz, each subframe needs to be displayed at 240 Hz. Since the definition of images has been increasing in recent years, the number of pixels in each subframe, and thus the amount of image data, has increased, and it is costly to use a memory that reads such a large amount of image data at high speed. Although it leads to a high price, there is no particular description about improvement in this point. The present invention solves such a problem, and in a display device that displays an image with a resolution apparently higher than the resolution of the display device by pixel shifting, enables cost reduction and size reduction of the device while enabling image processing on image data. The purpose is to

[0009]

In order to achieve the above object, a display device of the present invention is an image processing means for performing image processing on input image data, and each frame after image processing by the means. The image data is displayed by sequentially decomposing the display position for each subframe based on the image data of each subframe acquired by the decomposing unit that decomposes the image data of The display means for performing is provided.

The display device of the present invention also includes buffer means for storing the input image data, image processing means for performing image processing on the image data, and image processing for the image data stored in the buffer means. Means for inputting to the image processing means at a timing suitable for the above, a decomposing means for decomposing the image data of each frame after the image processing by the image processing means to obtain image data of a plurality of subframes, and the decomposing means. Display means is provided for sequentially switching the display position for each subframe based on the acquired image data of each subframe and displaying the image.

In such a display device, the buffer means may be composed of a memory for asynchronously writing and reading. Further, the buffer means,
The image data for one frame is stored in one of the memories, and the image data for the next frame is stored in one of the memories. The image data stored in the other memory may be read out during the period in which the image data is being written in the other memory.

Further, in each of the above display devices, storage means for storing the image data after the image processing is provided, and the decomposition means is necessary for displaying each sub-frame from the image data stored in the storage means. It may be a means for acquiring the image data of each sub-frame by reading only the data. Further, it is preferable that the storage means has a storage element provided on the data transfer side to the display means with an output bus having a bus width equal to a width of a signal input bus of a display element forming the display means.

Alternatively, in the above-mentioned display device, a storage means for storing the image data after the image processing for each frame sequentially corresponding to addresses from the head address of the storage area is provided, and the disassembling means includes The address of the image data of the sub-frame to be displayed is obtained from the sub-frame number indicating the order of the sub-frames, and the image data stored at the obtained address of the storage area in the storage means is sequentially read out to obtain the sub-frame of each sub-frame. It may be a means for acquiring image data. Further, the sub-frame number of each sub-frame and the address information including the start address where the image data of the sub-frame is stored in the storage area and the information of the increase pattern of the storage address are stored in association with each other. An address storage means is provided, and the decomposing means generates an address at which the image data of each subframe should be read from the subframe number and the address information, and the image stored in the generated address in the storage area. It may be a means for acquiring the image data of each sub-frame by sequentially reading the data.

Alternatively, the above-mentioned display device has a storage area corresponding to each of the sub-frames, and switching means for switching a storage area in which data is to be written and read out of each storage area according to a predetermined signal. Storage means for storing the image data after the image processing is stored in the storage area corresponding to each subframe while incrementing the write address by the write clock signal in accordance with the switching by the switching means. The disassembling means may be means for acquiring image data of each sub-frame by reading the storage area corresponding to the sub-frame for each sub-frame while incrementing the read address by the read clock signal in accordance with the switching by the switching means. .

Alternatively, it has a storage area corresponding to each of the sub-frames, and a means for fixing the output of each storage area to a high impedance in accordance with a read permission signal for permitting reading from the storage area, and the image processing described above. Storing the subsequent image data for each subframe in the storage area corresponding to the subframe while incrementing the write address by the write clock signal in accordance with the write enable signal for permitting writing to each of the storage areas. Means for providing the read address from the storage area corresponding to the subframe by the read clock signal for each subframe according to the read permission signal for each storage area set according to the subframe number. Image data is output while incrementing the It may be a means for acquiring image data of each sub-frame by the outputs of the storage area other than the storage area to respond causes fixed to high impedance.

Alternatively, the rule storage means for storing the rule of address movement and the write address of the image data after the image processing by the write clock signal according to the rule selected from the rule storage means according to the configuration of the sub-frame. And a storage means for storing the data in the storage area while moving the image data, and the decomposing means reads the image data stored in the storage means while incrementing the read address by the read clock signal for each subframe. It may be a means for acquiring the image data of the frame. In these display devices, the storage means and the disassembly means may be formed on the same chip.

Further, according to the present invention, image processing is performed on the input image data, and the image data for each frame after the image processing is arranged for each of a plurality of sub-frames. Image processing means for outputting in a state of being arranged in order, and display means for displaying images by sequentially switching the display position for each subframe based on the image data of each subframe acquired by the means, A display device is also provided in which the predetermined order is the order required for display by the display means. In these display devices, subframe data buffer means for storing the image data of each subframe, and the image data of each subframe stored in the means are displayed at a timing suitable for display for each subframe. Means for inputting to the means are provided, and the subframe buffer means may be configured by a memory that performs writing and reading asynchronously.

Further, in these display devices, the display means includes a light source, a homogenizing means for homogenizing the light from the light source, and a separating means for separating the homogenized light into light of a plurality of colors. A modulating means for respectively modulating the separated lights of respective colors in accordance with the input image data, a combining means for combining the modulated lights of the respective colors, and a projection means for projecting the combined lights. Good to do. Alternatively, the display means is a light source, a homogenizing means for homogenizing the light from the light source, a separating means for separating the homogenized light into light of a plurality of colors in a time division manner, and after the separation. It is preferable to have a modulation unit that modulates each color of light in accordance with the input image data and a projection unit that projects the modulated light.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. [First Embodiment: FIG. 1, FIG. 2, FIG. 9, FIG. 10] First,
A liquid crystal projector which is a first embodiment of the display device of the present invention will be described. 1 is a block diagram showing a configuration of a display controller in the liquid crystal projector, FIG. 2 is a block diagram showing a configuration of a display controller in the liquid crystal projector of the first comparative example, and FIG. 9 is a first view of the present invention. FIG. 10 is a diagram showing a schematic configuration of the liquid crystal projector of the embodiment, and FIG. 10 is a diagram for explaining a pixel shift and a subframe configuration in the liquid crystal projector.

The liquid crystal projector is a monochrome liquid crystal projector, and as shown in FIG.
S) 67, a pixel shift element 68, and a projection lens 69, and each of these members constitutes display means. And
This is a device for displaying an image on the screen 70 by modulating the light emitted from the light source on the display 10 based on the image data of the image to be displayed and projecting the light on the screen 70.

As the light source 61, an ultrahigh pressure mercury lamp of 120 W is used here, and the light source 61 is filtered by the filter 62.
Ultraviolet rays and infrared rays that are unnecessary for display are cut off from the light emitted from the. Then, the light is condensed by the lens 63, homogenized by an integrator 64 which is a homogenizing means composed of a fly-eye lens in which a plurality of lenses are arranged on a plane and combined, and the polarization direction is polarized by a polarization conversion element 65 such as a polarizing plate. Align in one direction. The light with the uniform polarization direction is reflected by the polarization beam splitter 67 and enters the display 10 composed of a liquid crystal panel. Here, as the display device 10, a twisted nematic (TN) liquid crystal is used and a thin film transistor (TFT) is provided for each pixel 640 ×
Although a liquid crystal display panel (liquid crystal display element) of 480 pixels was used, other elements may of course be used. This display 10
Constitutes a modulation means together with a pixel shift element which will be described later.

The display 1 based on the input image data
The light modulated by 0 is the polarization beam splitter 67.
And is incident on the pixel shift element 68. This pixel shift element is configured by using two sets of a polarization direction controlling liquid crystal panel and a crystal plate which is a birefringent plate,
It is a unit that can selectively shift the position of the light (image) modulated by the display 10 by 1/2 pixel in the vertical direction and the horizontal direction of the image according to a predetermined signal. An image based on the image data can be displayed by enlarging and projecting the light, the position of which is shifted by the pixel shift element 68, onto the screen 70 by the projection lens 69 which is a projection means.

Here, in this liquid crystal projector, the apparent resolution is increased by performing the pixel shift processing by the pixel shift element 68. That is, one frame of image data is divided into four subframes, the display device 10 modulates the image data based on the image data of each subframe, and the image is sequentially displayed by the pixel shift element 68 for each subframe. By switching and projecting on the screen 70, the afterimage effect makes it appear to the observer of the image as if the image of each sub-frame is displayed by different pixels, and apparently the number of pixels of the display 10 in each of the vertical and horizontal directions. Twice as large as 1280 × 9
Display can be performed with a resolution of 60 pixels.

Therefore, the image data of one frame of the image to be displayed is composed of data of 1280 × 960 pixels. Then, the data of 4 pixels in 2 rows and 2 columns separated by a bold line in FIG. 10 is the image data used for displaying 1 pixel of the display 10, and in the first sub-frame, FIG.
Only the image data of 640 × 480 pixels of the portion indicated by is input to the display device 10 for display, and similarly, in the second subframe, the position of the position of the third subframe, the position of the fourth subframe, The data will be displayed only.

In such a liquid crystal projector, the controller of the display 10 includes an image processing circuit 11, a frame memory 12, and a control circuit 13, as shown in FIG. The image processing circuit 11 is an image processing unit, and is a main control functioning as an input unit for inputting image data of an image to be displayed, which is input from an external device or generated by a main control unit (not shown) that integrally controls the entire device. It is a circuit that performs image processing such as gamma correction, contrast adjustment, and brightness adjustment on image data transferred by a unit in synchronization with a predetermined clock. These image processing is 1
The processing is performed pixel by pixel in the input order, and the processed image data is also output in that order. Here, it is assumed that the image data is transferred line by line in order from the smallest data (column) number (row / column order).

The frame memory 12 includes the image processing circuit 11
Is a storage unit for storing the image data after the image processing by, and stores the image data after the image processing and outputs the image data of the subframe to the display unit 10 for each subframe. As a result, the display device 10 can display the sub-frame for each sub-frame. Here, it is assumed that the image data is stored for each frame in the input order from 0 to ascending addresses. The control circuit 13 is a circuit that controls image processing by the image processing circuit 11 and also controls transfer of image data from the frame memory 12 to the display device 10. Then, the image data of each frame stored in the frame memory is decomposed into the image data of the first to fourth subframes to obtain the image data of each subframe, and the image data of the subframe is obtained for each subframe. Functions as a disassembling unit that causes the display 10 to output. In addition, "acquisition" includes "extraction" here.

Here, as shown in FIG. 10, the image data of the first sub-frame is pixel data of odd rows and odd columns,
The image data of the second sub-frame is the data of pixels in odd-numbered rows and even-numbered columns, and the storage positions of the image data of each sub-frame are regularly arranged, and the storage order is the row / column order as described above. Therefore, the storage address of the image data of each subframe can be obtained by a relatively simple calculation. Therefore, by setting or storing this calculation formula in the control circuit 13 in advance, the address where the image data of each subframe is stored is calculated, and the address is designated to execute only the image data of that subframe. / It can be read out in column order and transferred to the display 10. That is, the image data of each frame can be decomposed. In order to perform display by the display device 10, it is necessary to input the image data used for display in row / column order, but by using the controller as described above, the image data of each sub-frame is read from the frame memory 12 in rows. / It is possible to read out in column order and directly input to the display 10.

According to such a liquid crystal projector, the controller of the display can be constructed with a memory having a small storage capacity, and the processing circuit and control circuit provided therein can be simplified, so that the cost and size of the controller can be reduced. Therefore, the cost and size of the entire apparatus can be reduced. This point will be further described using a comparative example. The first feature of the liquid crystal projector of this embodiment is that the transferred image data is directly processed by the image processing circuit 11.
The image data after image processing is decomposed into image data of each sub-frame. However, the inventors of the present invention have confirmed that the effect of such a configuration is confirmed by a comparative example (first comparative example). As a result, a liquid crystal projector having the same controller as that shown in FIG. 2 in the display 10 and the other points being the same as those of the first embodiment was prototyped.

In the liquid crystal projector of the first comparative example, the image data transferred to the controller is temporarily stored in the frame memory 12, and each is controlled by the control circuit 23 which functions as the disassembling means as in the case of the above embodiment. The image data is decomposed into sub-frame image data, and the image processing circuit 21a provided for each sub-frame individually performs image processing for each sub-frame. Then, each image processing circuit 21a
The image data of the sub-frame to be displayed is selected by the signal switching circuit 24 from the output from and output to the display device 10. When the liquid crystal projector of the first embodiment and the liquid crystal projector of this comparative example were compared, the results are as shown in Table 1. The component cost and the circuit scale are shown as relative values with respect to the controller only in the case of the first embodiment.

[0030]

[Table 1]

As described above, the final display quality is the same in the first embodiment and the first comparative example, but in the first comparative example, the component cost is 2.5 times and the circuit scale is 1. It takes 5 times. Furthermore, the operability was also better in the first embodiment. From this comparison, in the liquid crystal projector of the first embodiment, since the image data of each frame is collectively processed before being decomposed into the image data of each sub-frame, only one image processing circuit 11 is required. Of course, since it is not necessary to provide the image processing circuit 21a for each sub-frame unlike the case of the image processing circuit 21 of the comparative example, it is possible to reduce the circuit scale and the component cost accordingly. Recognize.

The second feature of the liquid crystal projector of this embodiment is that only the image data necessary for displaying each sub-frame is read out from the image data of one frame after the image processing stored in the frame memory 12 and the display device is displayed. This is a point for outputting to 10. In order to confirm the effect of such a configuration, the inventors provided a frame memory for each sub-frame instead of the frame memory 12 as a comparative example (second comparative example), and provided image data after image processing. A prototype of a liquid crystal projector was constructed in which image data for each sub-frame was decomposed, stored in a corresponding memory, and then output to the display 10. When the liquid crystal projector of the first embodiment and the liquid crystal projector of the second comparative example were compared, the results are as shown in Table 2. The component cost and the circuit scale are shown as relative values with respect to the controller only in the case of the first embodiment.

[0033]

[Table 2]

As described above, the final display quality is the same in the first embodiment and the second comparative example, but in the second comparative example, the component cost is 2.2 times and the circuit scale is 1. It takes 8 times. Among these, the main reason why the component cost is significantly high in the second comparative example is that the total storage capacity of the memory is twice as large as that in the first embodiment. From this comparison, as in the case of the first embodiment, by providing only one frame memory 12 and reading the image data necessary for the display of each sub-frame from there, it is possible to reduce the component cost. It can be seen that miniaturization can be achieved. In addition, the above-mentioned first
Even when a device having only one of the characteristics and the second characteristics is configured, the effect of the characteristics can be obtained.

[Second Embodiment: FIGS. 3 to 5 and 1]
1] Next, a liquid crystal projector which is a second embodiment of the display device of the present invention will be described. FIG. 3 is a block diagram showing a configuration of a display controller in the liquid crystal projector, and FIG. 4 is a block diagram showing a configuration of a display controller in the liquid crystal projector of the third comparative example.
FIG. 5 is a diagram showing the operation timing of the 32-bit latch shown in FIGS. 3 and 4, and FIG. 11 is a diagram showing a schematic configuration of the liquid crystal projector of the second embodiment of the present invention.

This liquid crystal projector is a color liquid crystal projector and its structure is almost the same as that of the liquid crystal projector of the first embodiment shown in FIG. 9, but as shown in FIG. 11, it has a lens 63 and an integrator 64. In between, a rotary color filter 71 and a second lens 72 equivalent to the lens 63 are provided. Further, as the liquid crystal used for the display device 10, a ferroelectric liquid crystal is adopted with an emphasis on high-speed response. The rotating color filter 71 is a separating means, includes three color filters of red (R), green (G), and blue (B), and rotates about an axis parallel to the optical path from the light source to the polarization beam splitter 67. It is a possible color filter.
By rotating the rotary color filter 71 at a predetermined timing, the light from the light source 61 is time-divisionally R,
It is possible to separate light of each color of G and B.

Then, in synchronization with this, the display 10 performs modulation based on the image data of each color,
Images of each color can be displayed in a time division manner. By projecting the image of each of these colors at the same position on the screen 70, the images are overlaid and recognized by the afterimage effect, and are recognized as a full-color image. Such a color image display method is called field sequential. Also in this liquid crystal projector, pixel shifting is performed as in the case of the first embodiment, and by dividing an image of one frame into four sub-frames, a display unit 10 of 640 × 480 pixels has 1280 × 96 pixels.
An image of 0 pixels is displayed. Of course, the image of each color of RGB is displayed for each sub-frame. Further, the frame rate is 60 Hz, and the image data of each pixel has a size of 8 bits that realizes 256 gradations for each color of RGB.

In such a liquid crystal projector, the display 10 has a data input bus having a bus width of 32 bits, and its controller has an image processing circuit 31, a 32-bit buffer 33, and a frame memory 3 as shown in FIG.
2. A control circuit 34 is provided. Here, the 32-bit buffer 33 and the frame memory 32 are provided with three of the same configurations corresponding to the respective colors of RGB. Each of these is indicated by adding a suffix of R, G, B to the reference numeral, and when collectively referred to, it is indicated by a reference numeral without a suffix. The image processing circuit 31 is a circuit that performs image processing on input image data, as in the case of the image processing circuit 11 described in the first embodiment with reference to FIG.
However, since the image data of this embodiment is composed of image data of three colors of RGB, these data are 32 bit buffers 33 (33R, 33R) corresponding to each color.
G, 33B).

Each frame memory 32 is a storage means corresponding to the frame memory 12 described with reference to FIG. 1 in the first embodiment, but the data output of the memory unit which is a storage element constituting this frame memory 32. The bus width of the bus is 32 bits, which is equal to the bus width of the signal input bus in the display unit 10. Therefore, each frame memory 3
The image data read from No. 2 can be input to the display device 10 without passing through a latch or the like. The output data of each frame memory 32R, 32G, 32B is the display 1
Although they are connected to the same input bus of 0, data will not be output from each frame memory 32 at the same time as will be described later. Therefore, for example, by setting the output of the frame memory 32 that does not output data to high impedance, You can enter the required data normally. The bus width of the data input bus of the memory unit is 32 bits, which is the same as the bus width of the output bus.

The storage element of the frame memory 32 having this 32-bit input / output bus is constructed by providing four 8-bit memory units in parallel, and addresses can be specified individually or simultaneously for each memory unit. Thus, an address switching circuit is provided. The storage area of each of these memory units becomes a part of the storage area of the frame memory 32. Further, here, the storage capacity of each frame memory 32 is set to a capacity capable of storing image data of two frames of each color, but in order to obtain the effects of the present invention, a capacity capable of storing at least one frame of image data is required. I wish I had it.

On the other hand, since the output bus of the image processing circuit 11 has an 8-bit width, each 32-bit buffer 33 of 8 bits × 4 is provided, and the image data after the image processing is grouped into 32 bits and the corresponding frame memory is provided. I am writing to 32. The 32-bit buffer 33 sequentially reads the 8-bit data transferred to the first to fourth latches as shown in FIG. 5, and outputs the 32-bit data having the same bus width as the frame memory 32 to the frame memory 32. Output. The control circuit 34 is a circuit that controls the image processing by the image processing circuit 31, and also controls the transfer of image data from the 32-bit buffer 33 to the frame memory 32 and the transfer of image data from the frame memory 32 to the display 10. is there.

In the liquid crystal projector in which such a controller is provided in the display device 10, the image data transferred to the controller in row / column order is input to the image processing circuit 31 as in the case of the first embodiment. Image processing such as gamma correction, contrast adjustment, and brightness adjustment is performed for each pixel, and the data of each color is separated and output to the 32-bit buffer 33 of the corresponding color by 8 bits. And
When 32-bit data is input to the 32-bit buffer 33, it is transferred to the corresponding frame memory 32,
It is written to a predetermined address. At this time, the frame memory 32 is written into the addresses in row / column order.

Since the image data stored in each frame memory 32 displays each color of each sub-frame, only the necessary data is read at a predetermined timing and transferred to the display unit 10. Here, since the frame memory 32 has a storage capacity capable of storing image data of two frames, the reading is performed after the writing of the image data of the frame is completed, and the image data of the next frame is read during the reading. Writing is performed in another storage area.

As described above, the image data of one color of one pixel is 8 bits, and the width of the output bus of the frame memory 32 is 32.
Since it is a bit, image data for four pixels is read out at one time and transferred. Further, since the image data is written in the addresses in the row / column order, the address where the image data of each frame is stored can be easily calculated as in the case of the first embodiment. . That is, if the head address of the image data of each row is obtained and the image data is read from the address obtained by adding the numerical values shown in Table 3 to each other, the continuous 4-pixel image data used for the display of the subframe is obtained. Can be read. Here, the first read of each row is performed from four addresses obtained by substituting n = 1, and n is set to 2,
Do as 3 and so on. The calculation of this address can be performed by the control circuit 34.

[0045]

[Table 3]

Then, in each sub-frame, the R image data of the sub-frame is read from the frame memory 32R and is input to the display 10 to display R, and then the G image data is read from the frame memory 32G. By displaying G, and similarly, by reading out the image data of B and displaying B, the display of each sub-frame can be performed field-sequentially. By performing this for four subframes, the display of one frame is completed.

According to such a liquid crystal projector, the bus width of the data output bus of the frame memory 32 is made equal to the bus width of the signal input bus of the display unit 10, so that the frame memory 32 is transferred to the display unit 10. Since the image data can be transferred at high speed, the access speed required for the frame memory 32 can be kept low. This can reduce the cost of the device, since the faster the access speed, the more expensive the memory. This point will be further described using a comparative example.

In order to confirm the effect of such a configuration, the inventors have provided the display 10 with a controller as shown in FIG. 4 as a comparative example (third comparative example), and the other points are the second. The same liquid crystal projector as that of the above embodiment was prototyped. The liquid crystal projector of the third comparative example uses, as the frame memory 32 ', the data input bus and the data output bus each having a bus width of 8 bits. Therefore, a 32-bit buffer is not provided between the image processing circuit 11. However, the frame memory 32 'and the display 1
A 32-bit buffer 33 is provided between 0s to match the number of bits of data with the data input bus of the display unit 10.

In the liquid crystal projector of the second embodiment described above, display is performed using the display device 10 having 640 × 480 pixels. And frame rate 60Hz
In the field sequential RGB display, each frame is composed of 4 sub-frames.
The image data of each color of each subframe is 1 / (3 × 4 ×
60) = must be transferred from the frame memory 32 to the display 10 within 1/720 seconds. Therefore, since the image data for one color of one pixel is 8 bits (= 1 byte), the transfer rate is 640 × 480 / (1/720) ≈2.
21.2 megabytes / second is required.

Therefore, since the width of the output bus of the frame memory 32 is 32 bits (= 4 bytes), the operating speed (reading speed) on the output side is 221.2 / 4 = 55.3.
Display can be performed when the access time is 18 MHz or less in the range of MHz or more. Since the input side may write the image data of one color of the next subframe to each frame memory 32 while displaying the image of three colors of one subframe, 18.43 MHz or more of 1/3 of the output side The operating speed (writing speed) and access time of 54 nanoseconds or less can be dealt with. In addition, field sequential color display could be actually performed using the frame memory 32 having such an operation speed.

On the other hand, in the liquid crystal projector of the third comparative example, since the width of the output bus of each frame memory 32 'is 8 bits (= 1 byte), 221.2 / 3≈ on the input side.
Operation speed of 73.7MHz or higher, access time 1
It is possible to deal with it in 3 nanoseconds or less, but the output side is 221.
An operating speed of 2 MHz or more and an access time of 4.5 nanoseconds or less are required. Since the amount of image data for one frame is about 3.5 megabytes, and creating a memory of such a capacity with an access speed of 4.5 nanoseconds would be very costly, the configuration of this comparative example requires field sequential color display. Realizing that was not realistic.

In the structure of the comparative example as well, a dichroic mirror or the like is provided in place of the rotary color filter 71 to spatially divide the light from the light source 61 into each color, and the display 10 is provided for each color. In the case of performing a space division type color display in which the light (image) modulated into the light is combined to display, the image data of each color may be input to the display device 10 in the time of one subframe. Is 73.7
If it was in MHz, it could be displayed. However, in such a space division type liquid crystal projector, the display device 10 for each color is required, and the scale of the control circuit becomes large, which leads to an increase in cost and size of the device. further,
Even in this case, since the required operation speed is 73.7 MHz, which is higher than that in the case of the second embodiment described above, the cost of the storage element also increases.

Therefore, as in the second embodiment described above, by making the bus width of the data output bus of the frame memory equal to the bus width of the signal input bus in the display device, an apparatus using an inexpensive memory is used. It can be seen that the device can be configured and the cost of the device can be reduced. Note that if the bus width is too wide, wiring on the board becomes difficult, so the bus width of 32 bits is most preferable.
Although the case of performing color display has been described here, it goes without saying that the configuration of this embodiment can be applied to the case of monochrome. In this case, of course, it is not necessary to provide the 32-bit buffer 33 and the frame memory 32 for each color.

[Third Embodiment: FIG. 6] Next, a liquid crystal projector which is a third embodiment of the display device of the present invention will be described. FIG. 6 is a block diagram showing the configuration of the controller of the display device in the liquid crystal projector.
This liquid crystal projector is the same as the liquid crystal projector of the first embodiment except for the configuration of the controller of the display device 10, so the description of other points will be omitted or simplified.

In this liquid crystal projector, as shown in FIG. 6, an image processing circuit 41, an address generation circuit 42, a control circuit 43, and an image data RAM 44 are provided in the controller of the display device 10, and the image processing means is constituted by these. I am configuring. Then, the image data transferred in synchronization with a predetermined clock by a main control unit (not shown) functioning as an input unit is temporarily stored in the image data RAM 44 sequentially. Then, an address in the image data RAM 44 is designated by the address signal generated by the address generation circuit 42 according to the second control signal from the control circuit 43, and the image data is read from the address and sequentially output to the image processing circuit 41. This image data contains
Image processing such as gamma correction, contrast adjustment, and brightness adjustment is performed by the image processing circuit 41 as in the case of the first embodiment, and is output to the display device 10 as it is.

Here, the address generating circuit 42 sequentially generates the addresses so that the image data is arranged in each sub-frame and is output in a state of being arranged in the row / column order in each sub-frame. As in the case of the first embodiment, the image data transferred by the main control unit is arranged in the row / column order. Therefore, if this is stored at the address of the input order of the image data RAM 44, it is easy. An address where the image data of each sub-frame is stored can be calculated, and by specifying the address, only the image data of the sub-frame can be read out in the row / column order and output to the image processing circuit 41.

According to such a liquid crystal projector, the image data for each frame after image processing is arranged in a plurality of sub-frames, and is output in a state of being arranged in a predetermined order within each sub-frame. By doing so, since it is not necessary to provide a frame memory, it is possible to reduce the cost of parts and eventually the cost of the entire apparatus. This point will be further described using a comparative example.

In order to confirm the effect of such a configuration, the inventors of the present invention prototyped a liquid crystal projector in which the liquid crystal projector of the third embodiment was modified as follows as a comparative example (fourth comparative example). did. That is, in the controller of the display device 10, the transferred image data is directly input to the image processing circuit 41 for image processing without providing the image data RAM 44 and the address generation circuit 42, and the processed image data is displayed. The frame memory provided for each subframe is divided into subframes and stored. Then, when displaying each sub-frame, the image data is read from the corresponding frame memory and displayed. The results of comparison between the liquid crystal projector of the third embodiment and the liquid crystal projector of the fourth comparative example described above are as shown in Table 4. In addition,
Each evaluation value in the table is shown as a relative value for the controller only, with the case of the third embodiment being 1.

[0059]

[Table 4]

As shown in the table, in the structure of the comparative example, the number of parts of the controller was small and the circuit scale could be reduced.
Since the frame memory is provided for each sub-frame in order to separate the image data for each sub-frame, the memory cost is 2.2 times that in the case of the third embodiment. It has been found that, in the present situation where the display has a large capacity and a high speed, the contribution of the memory to the component cost is high, and thus the configuration of this embodiment capable of reducing the memory cost is effective for the cost reduction.

Although a monochrome liquid crystal projector has been described here, the configuration of this embodiment can be applied to a color liquid crystal projector. In this case, the image data RAM 44 is designed so that the image data of each color can be stored at the same address, the image data for one pixel is read when reading, and only the data of the required color is selected and the image processing circuit 41 is selected. The image data of each color may be stored, or the image data of each color may be stored in different addresses so that only the image data of the necessary color is read.

[Fourth Embodiment] Next, a liquid crystal projector which is a fourth embodiment of the display device of the present invention will be described. This liquid crystal projector has a frame memory 1
Since the liquid crystal projector is the same as the liquid crystal projector of the first embodiment except for the control of reading the image data from the second embodiment,
Descriptions of other points will be omitted or simplified.
In this embodiment, the frame memory 12 is
An SRAM is used as a memory unit that inputs and outputs data by inputting an address.
It is composed of (static ram).

The image data is written to the frame memory 12 in the same manner as in the first embodiment, the image data output from the image processing circuit 11 in the order of rows / columns is input in the order of 0 to ascending order for each frame. To the address of. Therefore, each frame is sequentially stored from the start address of the storage area in correspondence with the addresses. On the other hand, reading is performed by obtaining the address of the image data of the subframe to be displayed from the subframe number indicating the order of each subframe, and sequentially reading the image data stored at that address in the frame memory 12.
Here, when one frame is composed of N subframes, a natural number from 1 to N is assigned to each subframe.

Since there are four subframes here,
The subframe number can be counted, for example, by providing the control circuit 13 with a 2-bit counter and counting up with a vertical synchronization signal indicating the completion of display of one subframe. Then, as the address storage means, the sub-frame number is stored in association with the address information including the start address where the image data of the sub-frame is stored in the frame memory 12 and the information of the increase pattern of the storage address. A control table is provided in the control circuit 13. As the increase pattern of the storage address, it is preferable to use the increment of the address for each reading or the number of times of reading.

In the case of this embodiment, for example, the image data of the second sub-frame is 1 as shown in FIG.
The rows are arranged every other row from the second column, and are not arranged in the second row. Therefore, the address of the first pixel is 0000
00H (H at the end indicates that the number is hexadecimal)
Since the number of columns of the image data of one frame is 1280, the address is incremented by 2 from the address 000001H and read 640 times, whereby the image data of the second sub-frame arranged in the first row is All can be read. Here, the address read out at the 640th time is 0004FFH. And the second line 0005
Skip the address from 00H to 0009FFH,
The address is incremented by 2 again from the address of 000A01H, which is the second pixel in the third row, and read 640 times. This is followed by the final address 12BFFFH on the 960th row.
It is possible to read all the image data of the second sub-frame by repeating the above process.

In order to perform such reading, as the address information when the subframe number is 2, for example, the start address 000001H, the increase pattern information 2H is repeated 639 times, and 502H is repeated once 479 times. It suffices to store a rule for repeating 2H 639 times in the table. By storing such information, it is possible to sequentially generate and read addresses to be read by a simple logic circuit without using a complicated arithmetic circuit. By storing the contents shown in Table 5 in a table in which the subframe numbers and the address information are associated and referring to this information according to the subframe numbers of the subframes to be displayed, the image data of each subframe can be obtained. Can be read out and output to the display 10 by a simple circuit as in the above case.

[0067]

[Table 5]

Alternatively, the contents as shown in Table 6 may be stored in the table, and the horizontal synchronizing signal of the display image may be used as the timing for each row to repeat the reading process in units of two rows. Table 6 shows the rules for the first and second rows, but the read address in each row can be obtained by adding 500H to the address for each row.

[0069]

[Table 6]

According to such a liquid crystal projector, the control of the process of decomposing image data into data for each subframe can be realized by an extremely simple circuit, so that the number of parts of the controller of the display device can be reduced and the cost can be reduced. And downsizing can be achieved. With respect to this point, a comparative example of the liquid crystal projector including a controller in which the inventors have provided a frame memory corresponding to each sub-frame and separately store image data after image processing for each sub-frame (fifth example) As a comparative example), a prototype was produced and compared with the case of this embodiment, the results were as shown in Table 7. Here, the component cost and the circuit scale are shown as relative values for the controller only, with the case of the fourth embodiment being 1.

[0071]

[Table 7]

In the comparative example, the storage capacity of the memory is required to be twice as large as that in this example, and the control circuit is also required to be complicated. Therefore, as shown in Table 7, the parts cost is 2.2 times and the circuit scale is large. It took 1.8 times. From this, this 4th
According to the configuration of the embodiment, it can be seen that cost reduction and size reduction can be realized.

[Fifth Embodiment: FIGS. 7 and 8] Next, a liquid crystal projector which is a fifth embodiment of the display device of the present invention will be described. FIG. 7 is a block diagram showing the configuration of a frame memory included in the controller of the display in the liquid crystal projector, and FIG. 8 is a diagram showing an example of the configuration in which the frame memory and its control circuit are configured by one chip. This liquid crystal projector is the same as the liquid crystal projector of the first embodiment except for the configuration of the controller of the display device 10, so the description of other points will be omitted or simplified.

In this liquid crystal projector, the frame memory 1 which is a storage means provided in the controller of the display device 10 is used.
2 uses a memory system having a FIFO (first in, first out) configuration. This memory system also includes a part of the control circuit 13 in the first embodiment. This memory system has the configuration shown in FIG.
It is performed for a specific position on the memory cell 57 designated by the pointer. The pointer is prepared for each of writing and reading, and is incremented by the input of the corresponding clock when writing and reading are permitted, respectively. If it is not permitted, it does not increment even if a clock is input. Then, it is reset to the head address by the pointer reset signal (write reset signal, read reset signal).

The memory cell 57 receives a read clock, a write clock, a read enable signal, a write enable signal, a read reset signal, a write reset signal, and an output enable signal from the control circuit 13 in this memory system. A timing controller 51 for controlling the reading and writing of data from and to is provided. By providing the timing controller 51 with the self-refresh function, the memory cell can be configured by an inexpensive DRAM, and the cost can be reduced. In this memory system, the write address register 53 is a register that stores the value of the write pointer (write address), and the read address register 54 is a register that stores the value of the read pointer (read address). The address selector 52 is a circuit that selects one of the values stored in these registers according to the write enable signal and the read enable signal and specifies the access position on the memory cell 57.

In this liquid crystal projector, since a liquid crystal panel having a 32-bit width signal input bus is used as the display unit 10, the bus width of the input data DIn and the output data DOut is also set to 32 bits. There is. Then, four 8-bit memory units are provided in parallel, and reading and writing to each of these memory units are performed by a common read clock, write clock, read enable signal, write enable signal, read reset signal, write reset signal, and By controlling with the output permission signal, reading and writing are always performed to a common address, and these are substantially operated as a 32-bit memory unit (hereinafter referred to as "memory array").

Further, the memory cell 57 is provided with four memory arrays as storage areas corresponding to the respective subframes,
A total of 16 8-bit memory units are used. The write address register 53 and the read address register 54 are provided for each memory array, but the write data register 55, the read data register 56, the input buffer 58, and the output buffer 59 are common to each memory array, and each memory array is used. By connecting the data input / output terminals having the same pin name to each other and connecting them to the same input / output bus, the circuit configuration is simplified and the number of parts is reduced. Therefore, this memory system can be driven by 32 signal lines for the data input terminal and the data output terminal, and 7 × 4 = 28 signal lines for the clock and control signals.

When writing to such a memory cell 57, the input data DIn is input to the input buffer 5.
8 to the write data register 55. At this time, if the write enable signal is enabled, the write data register 55 is written to the address specified by the write address register 53 in accordance with the write clock.
At the same time that the contents of is written, the write address register 53 is incremented. If the write enable signal is enabled even at the next write timing of the write clock, the content of the write data register 55 is written to the next address. Therefore, when continuously writing data, this Input buffer 58 by timing
From the write data register 55 to the next data.

Here, for example, when the image data of the first sub-frame is transferred, only the write enable signal to the memory array corresponding to the first sub-frame is enabled and the writing to the other memory array is performed. Disable the enable signal. By doing so, even if common data is input to each memory array, it is possible to write only to the necessary memory array. Image data is line /
The data should be stored in a column order.

Reading is performed when the read permission signal is enabled. When the read enable signal is enabled, the data stored at the address specified by the read address register 54 of the memory cell 57 is read according to the read clock and is stored in the read data register 56 and the read address register. 54 is incremented. If the output enable signal is enabled, the data stored in the memory cell read data register 56 is output as the output data DOut via the output buffer 59. The output permission signal is not provided and the read data is always output data D.
It may be output as Out. As long as the read enable signal is enabled, reading is performed while incrementing the address one after another.

Also in the case of reading, for example, when displaying the first sub-frame, only the read permission signal to the memory array corresponding to the first sub-frame is enabled, and the read permission to other memory arrays is permitted. Disable the signal. In this way, even if each memory array is connected to a common output bus, only the image data of the subframe to be displayed can be acquired in the row / column order and output to the display unit 10. At this time, each memory array or the memory unit constituting the memory array may be provided with means for fixing the output to high impedance when the read enable signal is disabled. By doing so, it is possible to stably acquire only the image data of the sub-frame to be displayed.

Therefore, by configuring the controller as described above, the image data after the image processing input from the image processing circuit 11 is stored for each subframe in the memory array corresponding to the subframe, The image data of a subframe can be read from the memory array corresponding to the subframe. The control circuit 13
Generates a read permission signal and a write permission signal according to the pixel position of the image data to be transferred and the subframe number of the subframe to be displayed, and functions as a switching unit. The subframe number can be counted by using a vertical synchronization signal indicating the completion of display of one subframe, as in the case of the fourth embodiment. According to such a memory system, the write address to the memory and the read address from the memory can be controlled by the clock signal to acquire the image data necessary for the display of each subframe. Can be controlled by an extremely simple circuit. Therefore, the scale of the control circuit in the controller of the display device can be reduced, and the size and cost can be reduced.

In the case of the configuration of this embodiment, assuming that the image data of 1 pixel is 8 bits, the data of 4 consecutive pixels in the subframe can be stored in the corresponding memory array by writing 32 bits once. It will be written in each memory unit. However, in the image data transferred in the row / column order, the image data of each sub-frame is included in every other pixel as shown in FIG. Therefore, the data is arranged so that the image data of each sub-frame is arranged in units of 4 pixels before being input to this memory system. However, for such alignment, for example, a 64-bit latch is provided, and image data for 8 pixels is stored and 1, 3,
This can be easily performed by an extremely simple circuit in which data of 32 bits in total of 5th and 7th pixels and data of 32 bits in total of 2, 4, 6 and 8 pixels are sequentially input to the memory unit. Therefore, there is no influence on the effect of the present invention of downsizing and cost reduction.

As a comparative example (sixth comparative example), in the memory system used in the fifth embodiment, instead of the memory array described above, the write and read addresses can be changed by directly inputting the address value. We made a prototype of a liquid crystal projector with a controller for the display using a specified memory. Also in this sixth comparative example, 32-bit data can be stored per address, but in order to set the address of the area for storing the image data of 640 × 480 pixels,
17 address lines are needed. Therefore, the wiring of the address line input to each memory unit becomes complicated, and the circuit scale and the number of parts of the control circuit are increased as a whole. On the other hand, in the case of the fifth embodiment, since the write and read addresses are controlled by the clock and a small number of control signals, the layout on the substrate is easy. Therefore, also from this comparison, it can be seen that with such a configuration, it is possible to realize the downsizing and cost reduction of the controller of the display, and thus the entire device.

Further, the memory system described in this embodiment, together with the circuit for performing the above-mentioned alignment and the part of the control circuit 13 that is involved in the control of the memory system, as shown in FIG. Can be created as a chip. In this state, at least the storage means and the disassembly means are formed on the same chip. Since this memory system is entirely configured at the logic level, it is suitable for one chip as compared with the case where the analog system is included. Image data (8 bits) after image processing by the image processing circuit 11 is input to this chip, and a control circuit on the chip controls the memory system in response to a display control signal and a display data control signal from a main control unit (not shown). By controlling the reading and writing of data, the image data required for display can be output in the order required for display through the output bus having a width of 32 bits. Here, the display control signal is a signal for controlling display start and sub-frames, and the display data control signal is a horizontal synchronization signal and a vertical synchronization signal.
By connecting the created chip to an external terminal and using it, the number of parts and the circuit scale can be further reduced, and the size can be reduced.

[Sixth Embodiment] Next, a liquid crystal projector which is a sixth embodiment of the display device of the present invention will be described. This liquid crystal projector is different from the liquid crystal projector of the fifth embodiment in that only one memory array is provided in the memory cell 57 and the image data is recorded by dividing the address area for each sub-frame. Except for this point and points related thereto, the explanation is the same as in the case of the fifth embodiment, so the explanation of other points will be simplified or omitted.

In this liquid crystal projector, in order to store the image data for each sub-frame by dividing the address area, the address is not simply incremented at the time of writing as in the case of the fifth embodiment, but writing is performed. Each time, the address is moved according to a predetermined rule (thus not a FIFO). For example, 1280 x 960
In the case of storing image data of 8 bits for each pixel, 32 bits of data are stored in one address, so that addresses from 00000H to 4AFFFH are required.

To store this in four subframes as shown in FIG. 10, the image data of the first subframe is 12C from 00000H to 12BFFH.
It is stored in the 00H address, and the second, third, fourth
The sub-frame data is stored in 12C00H addresses in ascending order. Further, the image data of each sub-frame is stored at the addresses in the row / column order. In order to perform such control, in this liquid crystal projector, the control circuit 1
3 is provided with a non-volatile rule storage means for storing the address transfer rule.

In the case of the above-mentioned 4 subframes, in the first row (odd row), the odd column is the first subframe,
Since the even-numbered columns are the second sub-frames, assuming that the image data are aligned and input as in the case of the fifth embodiment, first, the image data of the first sub-frame and the second sub-frame are input. Image data is alternately input 160 times (total of 1280 pixels). Then, in the second row (even row), the odd column is the fourth subframe,
Since the even-numbered column is the third sub-frame, the image data of the fourth sub-frame and the image data of the third sub-frame are alternately input 160 times (total of 1280 pixels). And this alternates 480 times (9
(60 lines) will be repeated.

Therefore, for example, the following rules for address movement may be stored. That is, first, the image data for the first set of four pixels of the first sub-frame is written to address 00000H, then 12C00H is added to write the first set of image data of the second sub-frame to address 12C00H,
Next, subtract 12BFFH to get the first address 00001H.
Write the second set of image data of the subframe of
・ Repeat the process of 160 times.

When the writing of the 160th set of image data of the second sub-frame is completed (the address is 12
C9FH) Add 25761H to this and address 384
Write the first set of image data for the fourth sub-frame to 00H, then subtract 12C00H to add address 25800
Write the first set of image data of the third sub-frame to H, then add 12C01H to write the second set of image data of the fourth sub-frame to address 38401H,
The process of ... is repeated 160 times. And the fourth
When the writing of the 160th set of image data of the sub-frame is completed (address is 3849FH), at this point, 2
Since writing of the image data for the line is completed, next 38
Subtract 3FFH and return to address 000A0H to write the first set of image data of the first sub-frame in the third row. And again, write two lines as above,
The process of ... is repeated 480 times.

By changing the address according to the write clock signal in accordance with such a rule, the image data for one frame can be divided into sub-frames and written into the addresses from 00000H to 4AFFFH of the memory cell 57 in the display order. it can. The process of changing the address according to such a rule can be performed by an extremely simple circuit. In this way, at the time of reading, the image data of each sub-frame is read in the row / column order and the display unit 10 can be read only by incrementing the address sequentially from 00000H according to the read clock.
Can be output to.

Further, by storing a plurality of movement rules in the above-mentioned rule storage means, it is possible to easily deal with the case where the number of subframes or the division method is changed. For example, considering a case where one frame is divided into two sub-frames, an odd-numbered row is used as a first sub-frame, and an even-numbered row is used as a second sub-frame, and display is performed by this liquid crystal projector.
The image data of one frame is 640 × 960 pixels. Then, the image data of the first sub-frame of the odd-numbered row is continuously input 160 times (for 640 pixels),
Next, the image data of the second sub-frame in the even-numbered row is 160
Since the process of continuously inputting, and so on, is repeated 480 times, the movement rule corresponding to this may be stored in the rule storage means as in the case described above.

Then, the movement rule corresponding to the sub-frame division method is read from the rule storage means, and when writing to the frame memory 12 (memory cell 57), the address is changed according to the rule by the write clock and writing is performed. Thus, even when the subframe division method changes, it can be easily dealt with. However,
In the case of the two sub-frames described above, it is not necessary to align the data at the time of input to the memory unit as in the case of the fifth embodiment. Therefore, the data alignment method is also stored in the rule storage means. The alignment may also be controlled by a method selected according to the subframe division method.

According to such a liquid crystal projector, the control of the process of decomposing the image data into data for each subframe can be realized by an extremely simple circuit, so that the number of parts of the controller of the display can be reduced and the cost can be reduced. And downsizing can be achieved. In addition, since the read control is particularly simple, the read-side processing, which requires particularly high speed, can be performed at high speed, so the operating speed required for each memory unit can be kept low and the cost can be reduced. can do. Note that the rule storage means is an EEPROM
By configuring a rewritable non-volatile storage means such as, it becomes possible to rewrite the movement rule, and by updating necessary data from the outside, it is possible to cope with a new division method.

[Modifications of Each Embodiment] In each of the embodiments described above, an example in which the image data is 8 bits (for each color) and the bus width of the data input bus of the display 10 is 32 bits has been described. Of course, it is not limited to. Further, in each embodiment, the example in which the image data is transferred to the controller in the order of rows / columns and the data input is required for the display on the display device 10 in that order has been described, but the order is not necessarily limited to such an order. Needless to say Even if the arrangement order required for display on the display unit 10 is different from the transfer order to the controller,
This can be dealt with by appropriately setting the write or read address movement rule or the like.

Further, although a monochrome liquid crystal projector has been described as an example except for the second embodiment, it can be applied to a color liquid crystal projector except for the third embodiment described in the description. . At this time, the second
A frame memory may be provided for each color as in the case of the above embodiment. Further, although the liquid crystal projector has been described here as an example, the present invention can be applied to a liquid crystal display other than the projection type and other display devices.

Here, another configuration example of a color liquid crystal projector which is a display device to which the present invention is applied is shown in FIG.
2 is used for the explanation. FIG. 12 is a diagram showing a schematic configuration of the liquid crystal projector. Note that FIG. 12 is a diagram showing a state in which the portions corresponding to FIGS. 9 and 11 are viewed from the upper side in these figures. This liquid crystal projector is shown in FIG.
2, the light source 61, the filter 62, the fly-eye lens 74, the first, second and third dichroic mirrors 81, 82 and 83, the first and second mirrors 84 and 85, and the first and second mirrors. , And third display devices 86, 87, 88, and a dichroic prism 89 for color combination, and each of these members constitutes display means together with a pixel shift element and a projection lens (not shown).

In this liquid crystal projector, the light source 6
An ultrahigh pressure mercury lamp of 120 W is used as 1, and ultraviolet rays and infrared rays unnecessary for display are cut off from the light emitted from the light source by the filter 62. Then, the fly-eye lenses 74 and 74, which are a uniformizing means, display the light 8 among the lights.
The illuminance distribution of the portions incident on 6, 87, 88 is made uniform. The red component light of the homogenized light is transmitted through the first dichroic mirror 81, is reflected by the first mirror 84, and is incident on the first display 86. The green component light is reflected by the first dichroic mirror 81 and
The light is also reflected by the dichroic mirror 82 and enters the second display 87. The blue component light is reflected by the first dichroic mirror 81, transmitted through the second dichroic mirror 82, reflected by the third dichroic mirror 83 and the second mirror 85, and incident on the third display 88. To do. Here, these first, second and third dichroic mirrors 81, 82 and 83 are separating means.

Each display 86, 87, 88 which is a modulation means
Is a liquid crystal panel corresponding to the display device 10 shown in FIGS. 9 and 11, but a transmissive type is used. And
The light of each color is modulated according to the image data of each color input. The lights of the respective colors respectively modulated by the respective display devices 86, 87, 88 are combined by a color combining dichroic prism 89 which is a combining means to form a full color display image. Although illustration is omitted, similarly to the case shown in FIG. 9, by shifting the position of this display image by the pixel shift element and then enlarging and projecting it on the screen by the projection lens which is the projecting means,
A color image based on image data can be displayed.

Also in this liquid crystal projector, pixel shifting is performed as in the case of the first embodiment, and by dividing an image of one frame into four sub-frames, a display unit 86 of 640 × 480 pixels is provided. , 87, 8
8 can be used to display a color image of 1280 × 960 pixels. Even when the present invention is applied to such a display device, the effects described in the respective embodiments can be obtained when compared with the conventional device.

[Modifications Providing Buffer Means: FIGS. 13 to 17] In each of the embodiments described above, except for the third embodiment, the image data transferred from the main control unit (not shown) is directly subjected to the image processing. The example of inputting to the circuit has been described. However, in such a configuration, the image processing circuit needs to perform image processing for each pixel. Therefore, when it is necessary to perform image processing using image data of a plurality of pixels or a plurality of lines in the image processing circuit, a buffer (buffer means) is provided in the preceding stage of the image processing circuit, and image data transferred from the main control unit Is temporarily stored here, and the image data may be input to the image processing circuit at a timing suitable for image processing.

Next, a modified example provided with such a buffer will be described. Here, an example in which this modification is applied to the liquid crystal projector of the first embodiment will be described, but this modification can be similarly applied to other embodiments except the third embodiment. The liquid crystal projector is almost the same as the liquid crystal projector of the first embodiment except for the configuration of the controller of the display device 10, and therefore the description of other points will be omitted or simplified.

FIG. 13 shows the configuration of the controller of the display device in this modification. In the liquid crystal projector of this modified example, the controller of the display 10 includes an image processing circuit 11, a frame memory 12, a control circuit 13, a data input unit 14, a buffer control circuit 15, and a buffer control circuit 15, as shown in FIG.
A buffer 16 is provided. Then, the image data transferred from the main control unit is input to the data input unit 14. At this time, although the description is omitted in the first embodiment,
Control signals such as a horizontal synchronizing signal and a vertical synchronizing signal are also input from the main control unit to the data input unit 14. In FIG. 13, the image data and the control signal are shown together as an image signal.

Then, the data input section 14 outputs the control signal of the image signal to the buffer control circuit 15 and the image data to the buffer 16. If necessary at this time, the signal used for transmission is + 5V used by the logic element or the like.
Or + 3.3V is converted to a logic signal in which High is set to 0V and Low is set to 0V, or image data is serial-parallel converted into parallel signals to reduce the operation clock. Here, if the operation clock is lowered to such an extent that there is no inconvenience to the subsequent processing, an inexpensive memory with a slow access speed can be used for the buffer 16, so that the cost of the device can be reduced.

The buffer control circuit 15 controls the reading and writing of image data in the buffer 16 based on the horizontal / vertical synchronizing signals transferred from the main control unit and input from the data input unit 14 and the control signal from the control circuit 13. Is. The buffer 16 is a buffer unit that temporarily stores the image data transferred from the main control unit so as to be input to the image processing circuit at a timing suitable for image processing, and can be configured by, for example, SRAM.

The buffer 16 has at least the image processing circuit 1
It suffices if there is a capacity that can store the image data only for the time required for the image processing in 1. However, from the viewpoint of the degree of freedom in the configuration of the image processing circuit, it is preferable that the storage area for the image data for two frames be prepared. In this way, the image data for one frame is stored in one of the storage areas, the image data of the next frame is stored in the other storage area, and the image data stored in each storage area can be read out. Since it can be performed while the image data is being written to the other storage area, while the image data for the next frame is being transferred, the image processing is performed while referring to the image data at any place in the frame. This is because it is possible. For example, when one frame is composed of image data of 640 × 480 pixels and 1 pixel of 8 bits, and when displaying at a frame rate of 60 Hz, the image data is transferred from the main control unit at 24 MHz of 8 bits. Data input section 1
When converted to a 12 MHz 16-bit signal at 4, the buffer 16 can be configured using an SRAM having an access time of 55 nanoseconds and a capacity of 256 kilowords × 2 (1 word 16 bits).

The buffer 16 is a multiport VR.
You may comprise using AM (video RAM). The multi-port VRAM has a signal input port and a signal output port individually, and can write and read data asynchronously. Therefore, the image data transferred from the main control unit can be transferred at a fixed timing. This is a suitable configuration for reading at a timing suitable for image processing in the image processing circuit 11 while writing. Even when using a memory whose ports are shared for input and output, data is written and read via a storage element such as a line buffer, and the input and output are asynchronously controlled. Writing can be realized. A circuit used for such control is, for example, an FPGA.
(Field Programmable Gate Array). The image processing circuit 11 performs image processing and stores the processed image data in the frame memory 12, and the control circuit 13 functions as a decomposing unit to display the image data of the subframe for each subframe from here.
The output to is similar to the case of the first embodiment.

Next, FIG. 14 shows an example of an image processing circuit in which this modification is effective. FIG. 14 shows a circuit for adjusting the brightness of an image. In this case, the image processing circuit 11
A maximum value / minimum value detection circuit 111, a calculation circuit 112, and a look-up table (LUT) 113 are provided in the above. Then, first, the image data in the range to be adjusted is input from the buffer 16 to the maximum value / minimum value detection circuit 111, and the maximum value and the minimum value of the pixel values indicated by the image data in this range are detected. Then, based on this value, the arithmetic circuit 112 calculates the correspondence between each value of the image data before correction and the value of the image data after correction, and stores it in the LUT 113. For example, the minimum value before correction may be 0 after correction, and the maximum value may be 255 after correction, and the values in between may be appropriately allocated between 0 and 255. After that, the image data is sent from the buffer 16 to the LUT 11
Input into 3 and refer to this to convert the value.

By performing image processing with such an image processing circuit, even if the image related to the image data before processing is too bright or too dark as a whole, it is possible to adjust the brightness and display an easily viewable image. it can. The image processing circuit 1 is provided with a buffer 16 for such image processing.
This is made possible by referring to the image data of the pixels other than the processing target in 1 and enabling the image processing. The image processing performed by the image processing circuit 11 is not limited to this, and of course, a plurality of processes may be performed successively. Here, another configuration example of the image processing circuit is shown in FIG. FIG. 15 shows a circuit for superimposing (overlapping) an operation instruction screen for performing screen setting or the like on a screen relating to image data from the main control unit in accordance with a user operation. is there.

In this case, the composite image storage section 116 of the image processing circuit 11 'stores in advance image data such as tables, characters and figures to be displayed according to this operation instruction. This composite image storage unit 116 is stored in an EEPROM or a flash ROM.
By using an electrically rewritable storage element such as the above, the contents can be easily updated without removing the element when it is necessary at the time of version upgrade.

The operation unit 1 of this liquid crystal projector
An operation instruction from the user is accepted at 20, and the contents are input to the image synthesizing unit 115 of the image processing circuit 11 ′. It is acquired from the composite image storage unit 116 and input to the image addition unit 114. On the other hand, the image addition unit 1
Image data to be processed read out from the buffer 16 is also input to 14, and arithmetic processing for superimposing is performed here. By the calculation method here, it is possible to perform display such that a semitransparent image is overlaid or completely overwritten on the original image. In the case of color display, it is possible to change the display color. Such a display is possible by performing image processing before the image data is decomposed into each sub-frame.

By providing the buffer 16, the cost of the memory and its control circuit is increased as compared with the case of the first embodiment, but the image processing in the image processing circuit is
Since it can be performed asynchronously with the input timing of the image data from the main control unit, the degree of freedom in designing the circuit is increased, and various image processing can be performed to perform high-quality display. Even in the modified examples described in the respective embodiments, the buffer 16 is still necessary to obtain the same effect, and when comparing the configurations capable of performing the equivalent image processing, the configuration according to the present invention shows the circuit scale and It can be said that the cost can be reduced.

In the first comparative example described with reference to FIG. 2, the frame memory is provided in front of the image processing circuit 21. Therefore, at first glance, various image processings as described above are possible. As you may think, since image processing is performed individually for each sub-frame, it is difficult to perform image processing that refers to image data over a plurality of sub-frames and image processing as described using FIG. Even if it is realized, the processing circuit becomes extremely complicated, and eventually the circuit scale and the cost increase.

Next, FIG. 16 shows a configuration suitable for the case where the above-mentioned buffer 16 is constituted by a memory such as SRAM which has a port for both input and output. 2 in buffer 16
As described above, it is preferable that the storage area for the image data for one frame be prepared, but it is preferable that each of the storage areas is configured by a memory unit having a capacity for storing one frame of image data. Figure 1
In the example shown in FIG. 6, this corresponds to the first memory 401 and the second memory 403, respectively.

Then, for each of these memories, a first switch 402 and a second switch 404 are provided as switchers for switching the connection destination according to the write / read operation state of the memory. Then, the control signal from the buffer control circuit 15 controls the write / read operation state of the memory and the target address. The input / output port of the memory is connected to the selector 405 when connected to the input and the memory performs the read operation. The selector 405 responds to each control signal from the buffer control circuit 15 by switching the first switching unit 4
02 or the output of the second switch 404 is selected and output to the image processing circuit 11.

Then, while the image data of the first frame is being input, the first memory 401 is set to the write state and the image data is written here via the first switch 402, and the image data of the next frame is written. While the is input, the second memory 403 is set to the writing state, and the second memory 403 is written in here via the second switch 404. And
While the second memory 403 is in the writing state,
The first memory 401 is set in the read state, and the first switch 402 causes the image processing circuit 11 to output image data via the selector 405. While the first memory 401 is in the write state, the second memory 403 is set in the read state and the second switch 404 outputs image data to the image processing circuit 11 via the selector 405. By causing the circuit shown in FIG. 16 to perform such an operation, writing and reading of image data are performed asynchronously and a wide range of images in the image processing circuit 11 is used even when a memory whose ports are commonly used for input and output is used. Processing can be enabled.

When the buffer 16 is provided with such two memory units, its reading and writing can be controlled also by the circuit shown in FIG. In this circuit, 501 and 503 are buffers, 502 and 504 are tri-state buffers whose output can be switched between the contents of the buffer and high impedance by High / Low of the signal input to the control terminal, and 505 is an inverter. In this circuit, the transfer direction of the image data can be switched by H / L of the control signal A. Therefore, if the read / write operation of the memory is controlled in synchronization with this, two memory units can be formed with a simple circuit configuration. It is possible to control the operation of the buffer 16 using.
Regarding this point, Table 8 shows the output state of each gate corresponding to the H / L of the control signal A.

[0119]

[Table 8]

That is, when the control signal A is High, the tri-state buffer 502 buffers the input image data and outputs it to the first memory, so that it can be written in the first memory. Since the input from the inverter 505 is LOW, the output from the AND gate 506 is LOW regardless of the content of the image data input from the buffer 501. On the other hand, the output of the tri-state buffer 504 becomes high impedance because Low is input to the control terminal, so image data is not input to the second memory. When the image data is read from the second memory, the image data is input to the AND gate 507 via the buffer 503, and the other input is High, so that it is output as it is and the output of the AND gate 506 is Low. Or gate 5
08 also passes through as it is and is output to the image processing circuit 11.

When the control signal A is Low, the output of the tri-state buffer 502 becomes high impedance, so the image data is not input to the first memory, and conversely, the tri-state buffer 504 buffers the image data. Then, since it is output to the second memory, it can be written in the second memory. And gate 507
The output of is low because one input is low, regardless of the content of the image data. On the other hand, when the image data is read from the first memory, the image data is input to the AND gate 506 via the buffer 501, and the other input is High, so that the image data is output as it is and also passes through the OR gate 508 as it is. It is output to the processing circuit 11.

Therefore, when the control signal A is High, the first
The write permission for the memory, the read permission for the second memory, the read permission for the first memory, and the write permission for the second memory when Low. Since one circuit shown in FIG. 17 can control one input / output pin of the memory,
Eight 8-bit SRAM, 16-bit SRA
If M, by providing 16 circuits in parallel, input / output of image data to / from each memory can be controlled.

Although the example in which the buffer 16 is provided in the preceding stage of the image processing circuit 11 has been described here, such a buffer may be provided as a subframe data buffer means for storing the image data decomposed into each subframe. Good. By inputting the image data of each sub-frame stored here to the display device 10 at a timing suitable for the display for each sub-frame, the image data can be input at the optimal timing for the display on the display device 10. .

[0124]

As described above, according to the display device of the present invention, the controller of the display device can be configured with a memory having a small storage capacity, and the processing circuit and control circuit provided therein can be simplified. The cost and size of the controller can be reduced, and the cost and size of the entire device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a controller of a display in a liquid crystal projector according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a controller of a display in the liquid crystal projector of the first comparative example.

FIG. 3 is a block diagram showing a configuration of a controller of a display device in the liquid crystal projector of the second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a controller of a display unit in a liquid crystal projector of a third comparative example.

5 is a diagram showing an operation timing of the 32-bit latch shown in FIGS. 3 and 4. FIG.

FIG. 6 is a block diagram showing a configuration of a controller of a display in a liquid crystal projector according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a frame memory included in a controller of a display device in a liquid crystal projector according to a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a configuration example when the frame memory and its control circuit are configured by one chip.

FIG. 9 is a diagram showing a schematic configuration of a liquid crystal projector according to a first embodiment of the present invention.

FIG. 10 is a diagram for explaining pixel shift and sub-frame configuration in the liquid crystal projector.

FIG. 11 is a diagram showing a schematic configuration of a liquid crystal projector according to a second embodiment of the present invention.

FIG. 12 is a diagram showing a schematic configuration of a liquid crystal projector of a modified example of the invention.

FIG. 13 is a block diagram showing a configuration of a controller of a display device in a liquid crystal projector of another modification of the present invention.

14 is a block diagram showing a configuration example of an image processing circuit in the controller shown in FIG.

FIG. 15 is a block diagram showing another configuration example thereof.

16 is a diagram showing a configuration example of the buffer shown in FIG.

17 is a diagram showing another configuration example of the image data input / output control circuit in the buffer shown in FIG. 13, which is different from FIG.

[Explanation of symbols]

10: Display 11, 11 ', 31, 41: Image processing circuit 12, 32, 32 ': Frame memory 13, 23, 34, 34 ', 43: Control circuit 14: Data input section 15: Buffer control circuit 16: buffer 24: signal switching circuit 33: 32-bit buffer 42: Address generation circuit 44: RAM for image data 51: Timing controller 52: Address selector 53: Write address register 54: Read address register 55: Write data register 56: Read data register 57: memory cell 58: input buffer 59: Output buffer 61: Light source 62: Filter 63: Lens 64: Integrator 65: Polarization conversion element 67: Polarizing beam splitter 68: Pixel shift element 69: Projection lens 70: Screen 71: Rotating color filter 72: Second lens 74: Fly-eye lens 81: First dichroic mirror 82: Second dichroic mirror 83: Third dichroic mirror 84: First mirror 85: Second mirror 86: First display 87: Second display 88: Third indicator 89: Dichroic prism for color synthesis

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G03B 21/00 G03B 21/00 E 5C080 G09G 3/20 631 G09G 3/20 631B 631D 632 632Z 641 641E 680 680C (72) Inventor Kenji Namie 1-3-6 Nakamagome, Ota-ku, Tokyo, Ricoh Co., Ltd. (72) Inventor Yasuyuki Takiguchi 1-3-3 Nakamagome, Ota-ku, Tokyo (72) Invention, Ricoh Co., Ltd. Kazuya Miyagaki 1-3-6 Nakamagome, Ota-ku, Tokyo (72) Inventor Takanobu Aisaka 1-3-3 Nakamagome, Ota-ku, Tokyo (72) Inventor, Ikuo Kato 1F, 3-6 Nakamagome, Ota-ku, Tokyo F-term in Ricoh Co., Ltd. (reference) 2H088 EA13 E A14 EA15 EA18 EA45 GA02 HA07 HA08 HA13 HA15 HA25 HA28 JA05 MA20 2H091 FA05X FA10Z FA11X FA26X FA26Z FA41Z FD24 GA12 GA13 HA07 LA11 MA07 2H093 NA16 NA65 NC13 NC14 NC29 NC04 NC05 NC02 NC05 NC02 NC05 NC05 NC02 NC05 NC05 NC05 NC05 NC02 NC16 NC43 NC43 NC43 NC43 NC43 NC43 BB11 BC16 BF02 BF24 BF26 BF28 EC11 FA51 FA56 5C080 AA10 CC03 DD07 DD27 EE32 FF09 GG12 JJ02 JJ03 JJ06 KK43

Claims (16)

[Claims] 1. Image processing means for performing image processing on input image data, and decomposing means for decomposing image data of each frame after the image processing by the means to obtain image data of a plurality of sub-frames. And a display unit for displaying an image by sequentially switching the display position for each subframe based on the image data of each subframe acquired by the unit. 2. Buffer means for storing input image data, image processing means for performing image processing on the image data, and image data stored in the buffer means at a timing suitable for the image processing. Means for inputting to the image processing means, decomposing means for decomposing the image data of each frame after the image processing by the image processing means to obtain image data of a plurality of subframes, and each subframe acquired by the means And a display means for displaying an image by sequentially switching the display position for each sub-frame based on the image data. 3. The display device according to claim 2, wherein the buffer means is constituted by a memory that performs writing and reading asynchronously. 4. The display device according to claim 2, wherein the buffer means is composed of two memories each having a storage capacity for storing image data for one frame, and one frame for each frame. Minute image data is stored in one of the memories, image data of the next frame is stored in the other of the memories, the image data stored in the memory is read out, and the image data is written in the other memory. A display device, which is characterized in that it is performed during a period in which the user goes out. 5. The display device according to claim 1, further comprising storage means for storing the image data after the image processing, wherein the decomposition means is stored in the storage means. A display device comprising means for acquiring image data of each sub-frame by reading out only data necessary for displaying each sub-frame from the image data. 6. The display device according to claim 5, wherein said storage means has a bus width equal to a width of a signal input bus of a display element constituting said display means on a data transfer side to said display means. A display device having a storage element provided with an output bus. 7. Image processing is performed on the input image data, and the image data for each frame after the image processing is arranged for each of a plurality of subframes and arranged in a predetermined order within each subframe. Image processing means for outputting the image in the state of being displayed, and display means for displaying an image by sequentially switching the display position for each subframe based on the image data of each subframe acquired by the means, and the predetermined order. Is a display device characterized by the order required for display by the display means. 8. The display device according to any one of claims 1 to 4, wherein the image data after the image processing is sequentially stored for each frame from a start address of a storage area in correspondence with an address. Storage means is provided, and the disassembling means obtains the address of the image data of the subframe to be displayed from the subframe number indicating the order of the subframes, and stores the address in the storage area of the storage means. A display device, which is a means for acquiring image data of each sub-frame by sequentially reading out image data stored therein. 9. The display device according to claim 8, wherein a subframe number of each subframe, a start address where image data of the subframe is stored in the storage area, and an increase pattern of the storage address. Address information consisting of the information of and the address storage means for storing in association with each other, the decomposing means generates an address to read the image data of each subframe from the subframe number and the address information, A display device, which is means for acquiring image data of each sub-frame by sequentially reading image data stored at the generated address of the storage area. 10. The display device according to claim 1, wherein the storage area corresponding to each of the subframes and the writing and reading of data in each storage area according to a predetermined signal are performed. Switching means for switching the storage area to be performed, and the image data after the image processing is written in the storage area corresponding to the sub-frame for each sub-frame in accordance with the switching by the switching means by a write address by a write clock signal. Storage means for storing while incrementing is provided, and the decomposing means reads each sub-frame while incrementing a read address by a read clock signal from a storage area corresponding to the sub-frame in accordance with the switching by the switching means. It is a means to acquire the image data of the frame Display device comprising the door. 11. The display device according to claim 1, wherein a storage area corresponding to each of the sub-frames and an output of each storage area are allowed to be read from the storage area. Means for fixing the image data after the image processing to the high-impedance according to the read permission signal, and incrementing the write address by the write clock signal according to the write permission signal for permitting the writing of the image data after the image processing. However, storage means is provided for storing each subframe in a storage area corresponding to the subframe, and the disassembling means is configured to store the subframe in accordance with the read permission signal for each storage area set according to the subframe number. For each time, the read address is incremented by the read clock signal from the storage area corresponding to the subframe. While bets to output image data, display and wherein the output from the storage area other than the storage area in which the corresponding is a means for acquiring image data of each sub-frame by fixed to high impedance. 12. The display device according to claim 1, wherein a rule storage unit that stores a rule of address movement and image data after the image processing are included in the sub-frame configuration. Storage means for storing in a storage area while moving a write address by a write clock signal in accordance with a rule selected from the rule storage means according to the rule, and the disassembling means stores the image data stored in the storage means in the sub memory. A display device comprising means for acquiring image data of each sub-frame by reading while incrementing a read address by a read clock signal for each frame. 13. The display device according to claim 10, wherein the storage unit and the disassembly unit are formed on the same chip. 14. The display device according to claim 1, wherein the subframe data buffer means stores image data of each subframe, and the subframe data buffer means stores the subframe data buffer means. Image data
A display device comprising: means for inputting to the display means at a timing suitable for display for each sub-frame, and the sub-frame buffer means is constituted by a memory for asynchronously writing and reading. 15. The display device according to claim 1, wherein the display unit has a light source, a uniformizing unit for uniformizing light from the light source, and a uniforming unit. Separation means for separating the subsequent light into light of a plurality of colors, modulation means for respectively modulating the light of each color separated by the means according to the input image data, and combining the light of each color after the modulation by the means A display device, comprising: a combining unit that performs the above-described combination, and a projection unit that projects the light combined by the unit. 16. The display device according to claim 1, wherein the display unit has a light source, a uniformizing unit for uniformizing light from the light source, and a uniformizing unit for uniformizing the light. Separation means for separating the following light into light of a plurality of colors in a time division manner, modulation means for respectively modulating the light of each color after separation by the means, and light after the modulation by the means. A display device having a projection means for projecting.